src/intel/compiler/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32 #include "brw_fs.h"
  33 #include "common/gen_debug.h"
  34
  35 namespace brw {
  36
  37 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  38                                    void *log_data,
  39                                    const struct brw_tcs_prog_key *key,
  40                                    struct brw_tcs_prog_data *prog_data,
  41                                    const nir_shader *nir,
  42                                    void *mem_ctx,
  43                                    int shader_time_index,
  44                                    const struct brw_vue_map *input_vue_map)
  45    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  46                   nir, mem_ctx, false, shader_time_index),
  47      input_vue_map(input_vue_map), key(key)
  48 {
  49 }
  50
  51
  52 void
  53 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  54 {
  55 }
  56
  57 dst_reg *
  58 vec4_tcs_visitor::make_reg_for_system_value(int location)
  59 {
  60    return NULL;
  61 }
  62
  63
  64 void
  65 vec4_tcs_visitor::setup_payload()
  66 {
  67    int reg = 0;
  68
  69    /* The payload always contains important data in r0, which contains
  70     * the URB handles that are passed on to the URB write at the end
  71     * of the thread.
  72     */
  73    reg++;
  74
  75    /* r1.0 - r4.7 may contain the input control point URB handles,
  76     * which we use to pull vertex data.
  77     */
  78    reg += 4;
  79
  80    /* Push constants may start at r5.0 */
  81    reg = setup_uniforms(reg);
  82
  83    this->first_non_payload_grf = reg;
  84 }
  85
  86
  87 void
  88 vec4_tcs_visitor::emit_prolog()
  89 {
  90    invocation_id = src_reg(this, glsl_type::uint_type);
  91    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
  92
  93    /* HS threads are dispatched with the dispatch mask set to 0xFF.
  94     * If there are an odd number of output vertices, then the final
  95     * HS instance dispatched will only have its bottom half doing real
  96     * work, and so we need to disable the upper half:
  97     */
  98    if (nir->info.tess.tcs_vertices_out % 2) {
  99       emit(CMP(dst_null_d(), invocation_id,
 100                brw_imm_ud(nir->info.tess.tcs_vertices_out),
 101                BRW_CONDITIONAL_L));
 102
 103       /* Matching ENDIF is in emit_thread_end() */
 104       emit(IF(BRW_PREDICATE_NORMAL));
 105    }
 106 }
 107
 108
 109 void
 110 vec4_tcs_visitor::emit_thread_end()
 111 {
 112    vec4_instruction *inst;
 113    current_annotation = "thread end";
 114
 115    if (nir->info.tess.tcs_vertices_out % 2) {
 116       emit(BRW_OPCODE_ENDIF);
 117    }
 118
 119    if (devinfo->gen == 7) {
 120       struct brw_tcs_prog_data *tcs_prog_data =
 121          (struct brw_tcs_prog_data *) prog_data;
 122
 123       current_annotation = "release input vertices";
 124
 125       /* Synchronize all threads, so we know that no one is still
 126        * using the input URB handles.
 127        */
 128       if (tcs_prog_data->instances > 1) {
 129          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 130          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 131          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 132       }
 133
 134       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 135        * We want to compare the bottom half of invocation_id with 0, but
 136        * use that truth value for the top half as well.  Unfortunately,
 137        * we don't have stride in the vec4 world, nor UV immediates in
 138        * align16, so we need an opcode to get invocation_id<0,4,0>.
 139        */
 140       set_condmod(BRW_CONDITIONAL_Z,
 141                   emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
 142                        invocation_id));
 143       emit(IF(BRW_PREDICATE_NORMAL));
 144       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 145          /* If we have an odd number of input vertices, the last will be
 146           * unpaired.  We don't want to use an interleaved URB write in
 147           * that case.
 148           */
 149          const bool is_unpaired = i == key->input_vertices - 1;
 150
 151          dst_reg header(this, glsl_type::uvec4_type);
 152          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 153               brw_imm_ud(is_unpaired));
 154       }
 155       emit(BRW_OPCODE_ENDIF);
 156    }
 157
 158    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 159       emit_shader_time_end();
 160
 161    inst = emit(TCS_OPCODE_THREAD_END);
 162    inst->base_mrf = 14;
 163    inst->mlen = 2;
 164 }
 165
 166
 167 void
 168 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 169                                       const src_reg &vertex_index,
 170                                       unsigned base_offset,
 171                                       unsigned first_component,
 172                                       const src_reg &indirect_offset)
 173 {
 174    vec4_instruction *inst;
 175    dst_reg temp(this, glsl_type::ivec4_type);
 176    temp.type = dst.type;
 177
 178    /* Set up the message header to reference the proper parts of the URB */
 179    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 180    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 181                indirect_offset);
 182    inst->force_writemask_all = true;
 183
 184    /* Read into a temporary, ignoring writemasking. */
 185    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 186    inst->offset = base_offset;
 187    inst->mlen = 1;
 188    inst->base_mrf = -1;
 189
 190    /* Copy the temporary to the destination to deal with writemasking.
 191     *
 192     * Also attempt to deal with gl_PointSize being in the .w component.
 193     */
 194    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 195       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 196    } else {
 197       src_reg src = src_reg(temp);
 198       src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 199       emit(MOV(dst, src));
 200    }
 201 }
 202
 203 void
 204 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 205                                        unsigned base_offset,
 206                                        unsigned first_component,
 207                                        const src_reg &indirect_offset)
 208 {
 209    vec4_instruction *inst;
 210
 211    /* Set up the message header to reference the proper parts of the URB */
 212    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 213    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 214                brw_imm_ud(dst.writemask << first_component), indirect_offset);
 215    inst->force_writemask_all = true;
 216
 217    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 218    read->offset = base_offset;
 219    read->mlen = 1;
 220    read->base_mrf = -1;
 221
 222    if (first_component) {
 223       /* Read into a temporary and copy with a swizzle and writemask. */
 224       read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type);
 225       emit(MOV(dst, swizzle(src_reg(read->dst),
 226                             BRW_SWZ_COMP_INPUT(first_component))));
 227    }
 228 }
 229
 230 void
 231 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 232                                  unsigned writemask,
 233                                  unsigned base_offset,
 234                                  const src_reg &indirect_offset)
 235 {
 236    if (writemask == 0)
 237       return;
 238
 239    src_reg message(this, glsl_type::uvec4_type, 2);
 240    vec4_instruction *inst;
 241
 242    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 243                brw_imm_ud(writemask), indirect_offset);
 244    inst->force_writemask_all = true;
 245    inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE),
 246                    value));
 247    inst->force_writemask_all = true;
 248
 249    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 250    inst->offset = base_offset;
 251    inst->mlen = 2;
 252    inst->base_mrf = -1;
 253 }
 254
 255 void
 256 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 257 {
 258    switch (instr->intrinsic) {
 259    case nir_intrinsic_load_invocation_id:
 260       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 261                invocation_id));
 262       break;
 263    case nir_intrinsic_load_primitive_id:
 264       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 265            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 266       break;
 267    case nir_intrinsic_load_patch_vertices_in:
 268       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 269                brw_imm_d(key->input_vertices)));
 270       break;
 271    case nir_intrinsic_load_per_vertex_input: {
 272       src_reg indirect_offset = get_indirect_offset(instr);
 273       unsigned imm_offset = instr->const_index[0];
 274
 275       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 276       src_reg vertex_index =
 277          vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
 278                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 279
 280       unsigned first_component = nir_intrinsic_component(instr);
 281       if (nir_dest_bit_size(instr->dest) == 64) {
 282          /* We need to emit up to two 32-bit URB reads, then shuffle
 283           * the result into a temporary, then move to the destination
 284           * honoring the writemask
 285           *
 286           * We don't need to divide first_component by 2 because
 287           * emit_input_urb_read takes a 32-bit type.
 288           */
 289          dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
 290          dst_reg tmp_d = retype(tmp, BRW_REGISTER_TYPE_D);
 291          emit_input_urb_read(tmp_d, vertex_index, imm_offset,
 292                              first_component, indirect_offset);
 293          if (instr->num_components > 2) {
 294             emit_input_urb_read(byte_offset(tmp_d, REG_SIZE), vertex_index,
 295                                 imm_offset + 1, 0, indirect_offset);
 296          }
 297
 298          src_reg tmp_src = retype(src_reg(tmp_d), BRW_REGISTER_TYPE_DF);
 299          dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
 300          shuffle_64bit_data(shuffled, tmp_src, false);
 301
 302          dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
 303          dst.writemask = brw_writemask_for_size(instr->num_components);
 304          emit(MOV(dst, src_reg(shuffled)));
 305       } else {
 306          dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 307          dst.writemask = brw_writemask_for_size(instr->num_components);
 308          emit_input_urb_read(dst, vertex_index, imm_offset,
 309                              first_component, indirect_offset);
 310       }
 311       break;
 312    }
 313    case nir_intrinsic_load_input:
 314       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 315       break;
 316    case nir_intrinsic_load_output:
 317    case nir_intrinsic_load_per_vertex_output: {
 318       src_reg indirect_offset = get_indirect_offset(instr);
 319       unsigned imm_offset = instr->const_index[0];
 320
 321       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 322       dst.writemask = brw_writemask_for_size(instr->num_components);
 323
 324       emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr),
 325                            indirect_offset);
 326       break;
 327    }
 328    case nir_intrinsic_store_output:
 329    case nir_intrinsic_store_per_vertex_output: {
 330       src_reg value = get_nir_src(instr->src[0]);
 331       unsigned mask = instr->const_index[1];
 332       unsigned swiz = BRW_SWIZZLE_XYZW;
 333
 334       src_reg indirect_offset = get_indirect_offset(instr);
 335       unsigned imm_offset = instr->const_index[0];
 336
 337       unsigned first_component = nir_intrinsic_component(instr);
 338       if (first_component) {
 339          if (nir_src_bit_size(instr->src[0]) == 64)
 340             first_component /= 2;
 341          assert(swiz == BRW_SWIZZLE_XYZW);
 342          swiz = BRW_SWZ_COMP_OUTPUT(first_component);
 343          mask = mask << first_component;
 344       }
 345
 346       if (nir_src_bit_size(instr->src[0]) == 64) {
 347          /* For 64-bit data we need to shuffle the data before we write and
 348           * emit two messages. Also, since each channel is twice as large we
 349           * need to fix the writemask in each 32-bit message to account for it.
 350           */
 351          value = swizzle(retype(value, BRW_REGISTER_TYPE_DF), swiz);
 352          dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
 353          shuffle_64bit_data(shuffled, value, true);
 354          src_reg shuffled_float = src_reg(retype(shuffled, BRW_REGISTER_TYPE_F));
 355
 356          for (int n = 0; n < 2; n++) {
 357             unsigned fixed_mask = 0;
 358             if (mask & WRITEMASK_X)
 359                fixed_mask |= WRITEMASK_XY;
 360             if (mask & WRITEMASK_Y)
 361                fixed_mask |= WRITEMASK_ZW;
 362             emit_urb_write(shuffled_float, fixed_mask,
 363                            imm_offset, indirect_offset);
 364
 365             shuffled_float = byte_offset(shuffled_float, REG_SIZE);
 366             mask >>= 2;
 367             imm_offset++;
 368          }
 369       } else {
 370          emit_urb_write(swizzle(value, swiz), mask,
 371                         imm_offset, indirect_offset);
 372       }
 373       break;
 374    }
 375
 376    case nir_intrinsic_barrier: {
 377       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 378       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 379       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 380       break;
 381    }
 382
 383    default:
 384       vec4_visitor::nir_emit_intrinsic(instr);
 385    }
 386 }
 387
 388
 389 extern "C" const unsigned *
 390 brw_compile_tcs(const struct brw_compiler *compiler,
 391                 void *log_data,
 392                 void *mem_ctx,
 393                 const struct brw_tcs_prog_key *key,
 394                 struct brw_tcs_prog_data *prog_data,
 395                 const nir_shader *src_shader,
 396                 int shader_time_index,
 397                 unsigned *final_assembly_size,
 398                 char **error_str)
 399 {
 400    const struct gen_device_info *devinfo = compiler->devinfo;
 401    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 402    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 403
 404    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 405    nir->info.outputs_written = key->outputs_written;
 406    nir->info.patch_outputs_written = key->patch_outputs_written;
 407
 408    struct brw_vue_map input_vue_map;
 409    brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read,
 410                        nir->info.separate_shader);
 411    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 412                             nir->info.outputs_written,
 413                             nir->info.patch_outputs_written);
 414
 415    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
 416    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 417    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
 418                              key->tes_primitive_mode);
 419    if (key->quads_workaround)
 420       brw_nir_apply_tcs_quads_workaround(nir);
 421
 422    nir = brw_postprocess_nir(nir, compiler, is_scalar);
 423
 424    if (is_scalar)
 425       prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 8);
 426    else
 427       prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 2);
 428
 429    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 430     * That divides up as follows:
 431     *
 432     *     32 bytes for the patch header (tessellation factors)
 433     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 434     *              gl_MaxTessPatchComponents = 120)
 435     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 436     *              gl_MaxPatchVertices = 32 and
 437     *              gl_MaxTessControlOutputComponents = 128)
 438     *
 439     *  15808 bytes left for varying packing overhead
 440     */
 441    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 442    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 443    unsigned output_size_bytes = 0;
 444    /* Note that the patch header is counted in num_per_patch_slots. */
 445    output_size_bytes += num_per_patch_slots * 16;
 446    output_size_bytes += nir->info.tess.tcs_vertices_out *
 447                         num_per_vertex_slots * 16;
 448
 449    assert(output_size_bytes >= 1);
 450    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 451       return NULL;
 452
 453    /* URB entry sizes are stored as a multiple of 64 bytes. */
 454    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 455
 456    /* HS does not use the usual payload pushing from URB to GRFs,
 457     * because we don't have enough registers for a full-size payload, and
 458     * the hardware is broken on Haswell anyway.
 459     */
 460    vue_prog_data->urb_read_length = 0;
 461
 462    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 463       fprintf(stderr, "TCS Input ");
 464       brw_print_vue_map(stderr, &input_vue_map);
 465       fprintf(stderr, "TCS Output ");
 466       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 467    }
 468
 469    if (is_scalar) {
 470       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
 471                    &prog_data->base.base, NULL, nir, 8,
 472                    shader_time_index, &input_vue_map);
 473       if (!v.run_tcs_single_patch()) {
 474          if (error_str)
 475             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 476          return NULL;
 477       }
 478
 479       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
 480       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
 481
 482       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
 483                      &prog_data->base.base, v.promoted_constants, false,
 484                      MESA_SHADER_TESS_CTRL);
 485       if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 486          g.enable_debug(ralloc_asprintf(mem_ctx,
 487                                         "%s tessellation control shader %s",
 488                                         nir->info.label ? nir->info.label
 489                                                         : "unnamed",
 490                                         nir->info.name));
 491       }
 492
 493       g.generate_code(v.cfg, 8);
 494
 495       return g.get_assembly(final_assembly_size);
 496    } else {
 497       vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 498                          nir, mem_ctx, shader_time_index, &input_vue_map);
 499       if (!v.run()) {
 500          if (error_str)
 501             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 502          return NULL;
 503       }
 504
 505       if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 506          v.dump_instructions();
 507
 508
 509       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 510                                         &prog_data->base, v.cfg,
 511                                         final_assembly_size);
 512    }
 513 }
 514
 515
 516 } /* namespace brw */