src/intel/compiler/brw_vec4_tes.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tes.cpp
  26  *
  27  * Tessellaton evaluation shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_vec4_tes.h"
  31 #include "brw_cfg.h"
  32 #include "dev/gen_debug.h"
  33
  34 namespace brw {
  35
  36 vec4_tes_visitor::vec4_tes_visitor(const struct brw_compiler *compiler,
  37                                   void *log_data,
  38                                   const struct brw_tes_prog_key *key,
  39                                   struct brw_tes_prog_data *prog_data,
  40                                   const nir_shader *shader,
  41                                   void *mem_ctx,
  42                                   int shader_time_index)
  43    : vec4_visitor(compiler, log_data, &key->base.tex, &prog_data->base,
  44                   shader, mem_ctx, false, shader_time_index)
  45 {
  46 }
  47
  48 void
  49 vec4_tes_visitor::setup_payload()
  50 {
  51    int reg = 0;
  52
  53    /* The payload always contains important data in r0 and r1, which contains
  54     * the URB handles that are passed on to the URB write at the end
  55     * of the thread.
  56     */
  57    reg += 2;
  58
  59    reg = setup_uniforms(reg);
  60
  61    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
  62       for (int i = 0; i < 3; i++) {
  63          if (inst->src[i].file != ATTR)
  64             continue;
  65
  66          unsigned slot = inst->src[i].nr + inst->src[i].offset / 16;
  67          struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2));
  68          grf = stride(grf, 0, 4, 1);
  69          grf.swizzle = inst->src[i].swizzle;
  70          grf.type = inst->src[i].type;
  71          grf.abs = inst->src[i].abs;
  72          grf.negate = inst->src[i].negate;
  73          inst->src[i] = grf;
  74       }
  75    }
  76
  77    reg += 8 * prog_data->urb_read_length;
  78
  79    this->first_non_payload_grf = reg;
  80 }
  81
  82
  83 void
  84 vec4_tes_visitor::emit_prolog()
  85 {
  86    input_read_header = src_reg(this, glsl_type::uvec4_type);
  87    emit(TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header));
  88
  89    this->current_annotation = NULL;
  90 }
  91
  92
  93 void
  94 vec4_tes_visitor::emit_urb_write_header(int mrf)
  95 {
  96    /* No need to do anything for DS; an implied write to this MRF will be
  97     * performed by VS_OPCODE_URB_WRITE.
  98     */
  99    (void) mrf;
 100 }
 101
 102
 103 vec4_instruction *
 104 vec4_tes_visitor::emit_urb_write_opcode(bool complete)
 105 {
 106    /* For DS, the URB writes end the thread. */
 107    if (complete) {
 108       if (INTEL_DEBUG & DEBUG_SHADER_TIME)
 109          emit_shader_time_end();
 110    }
 111
 112    vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
 113    inst->urb_write_flags = complete ?
 114       BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
 115
 116    return inst;
 117 }
 118
 119 void
 120 vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 121 {
 122    const struct brw_tes_prog_data *tes_prog_data =
 123       (const struct brw_tes_prog_data *) prog_data;
 124
 125    switch (instr->intrinsic) {
 126    case nir_intrinsic_load_tess_coord:
 127       /* gl_TessCoord is part of the payload in g1 channels 0-2 and 4-6. */
 128       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
 129                src_reg(brw_vec8_grf(1, 0))));
 130       break;
 131    case nir_intrinsic_load_tess_level_outer:
 132       if (tes_prog_data->domain == BRW_TESS_DOMAIN_ISOLINE) {
 133          emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
 134                   swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
 135                           BRW_SWIZZLE_ZWZW)));
 136       } else {
 137          emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
 138                   swizzle(src_reg(ATTR, 1, glsl_type::vec4_type),
 139                           BRW_SWIZZLE_WZYX)));
 140       }
 141       break;
 142    case nir_intrinsic_load_tess_level_inner:
 143       if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) {
 144          emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
 145                   swizzle(src_reg(ATTR, 0, glsl_type::vec4_type),
 146                           BRW_SWIZZLE_WZYX)));
 147       } else {
 148          emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
 149                   src_reg(ATTR, 1, glsl_type::float_type)));
 150       }
 151       break;
 152    case nir_intrinsic_load_primitive_id:
 153       emit(TES_OPCODE_GET_PRIMITIVE_ID,
 154            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 155       break;
 156
 157    case nir_intrinsic_load_input:
 158    case nir_intrinsic_load_per_vertex_input: {
 159       assert(nir_dest_bit_size(instr->dest) == 32);
 160       src_reg indirect_offset = get_indirect_offset(instr);
 161       unsigned imm_offset = instr->const_index[0];
 162       src_reg header = input_read_header;
 163       unsigned first_component = nir_intrinsic_component(instr);
 164
 165       if (indirect_offset.file != BAD_FILE) {
 166          src_reg clamped_indirect_offset = src_reg(this, glsl_type::uvec4_type);
 167
 168          /* Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the
 169           * valid range of the offset is [0, 0FFFFFFFh].
 170           */
 171          emit_minmax(BRW_CONDITIONAL_L,
 172                      dst_reg(clamped_indirect_offset),
 173                      retype(indirect_offset, BRW_REGISTER_TYPE_UD),
 174                      brw_imm_ud(0x0fffffffu));
 175
 176          header = src_reg(this, glsl_type::uvec4_type);
 177          emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
 178               input_read_header, clamped_indirect_offset);
 179       } else {
 180          /* Arbitrarily only push up to 24 vec4 slots worth of data,
 181           * which is 12 registers (since each holds 2 vec4 slots).
 182           */
 183          const unsigned max_push_slots = 24;
 184          if (imm_offset < max_push_slots) {
 185             src_reg src = src_reg(ATTR, imm_offset, glsl_type::ivec4_type);
 186             src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 187
 188             emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D), src));
 189
 190             prog_data->urb_read_length =
 191                MAX2(prog_data->urb_read_length,
 192                     DIV_ROUND_UP(imm_offset + 1, 2));
 193             break;
 194          }
 195       }
 196
 197       dst_reg temp(this, glsl_type::ivec4_type);
 198       vec4_instruction *read =
 199          emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 200       read->offset = imm_offset;
 201       read->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
 202
 203       src_reg src = src_reg(temp);
 204       src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 205
 206       /* Copy to target.  We might end up with some funky writemasks landing
 207        * in here, but we really don't want them in the above pseudo-ops.
 208        */
 209       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 210       dst.writemask = brw_writemask_for_size(instr->num_components);
 211       emit(MOV(dst, src));
 212       break;
 213    }
 214    default:
 215       vec4_visitor::nir_emit_intrinsic(instr);
 216    }
 217 }
 218
 219
 220 void
 221 vec4_tes_visitor::emit_thread_end()
 222 {
 223    /* For DS, we always end the thread by emitting a single vertex.
 224     * emit_urb_write_opcode() will take care of setting the eot flag on the
 225     * SEND instruction.
 226     */
 227    emit_vertex();
 228 }
 229
 230 } /* namespace brw */