src/intel/compiler/brw_wm_iz.cpp

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_fs.h"
  34
  35
  36 #undef P                        /* prompted depth */
  37 #undef C                        /* computed */
  38 #undef N                        /* non-promoted? */
  39
  40 #define P 0
  41 #define C 1
  42 #define N 2
  43
  44 static const struct {
  45    GLuint mode:2;
  46    GLuint sd_present:1;
  47    GLuint sd_to_rt:1;
  48    GLuint dd_present:1;
  49    GLuint ds_present:1;
  50 } wm_iz_table[BRW_WM_IZ_BIT_MAX] =
  51 {
  52  { P, 0, 0, 0, 0 },
  53  { P, 0, 0, 0, 0 },
  54  { P, 0, 0, 0, 0 },
  55  { P, 0, 0, 0, 0 },
  56  { P, 0, 0, 0, 0 },
  57  { N, 1, 1, 0, 0 },
  58  { N, 0, 1, 0, 0 },
  59  { N, 0, 1, 0, 0 },
  60  { P, 0, 0, 0, 0 },
  61  { P, 0, 0, 0, 0 },
  62  { C, 0, 1, 1, 0 },
  63  { C, 0, 1, 1, 0 },
  64  { P, 0, 0, 0, 0 },
  65  { N, 1, 1, 0, 0 },
  66  { C, 0, 1, 1, 0 },
  67  { C, 0, 1, 1, 0 },
  68  { P, 0, 0, 0, 0 },
  69  { P, 0, 0, 0, 0 },
  70  { P, 0, 0, 0, 0 },
  71  { P, 0, 0, 0, 0 },
  72  { P, 0, 0, 0, 0 },
  73  { N, 1, 1, 0, 0 },
  74  { N, 0, 1, 0, 0 },
  75  { N, 0, 1, 0, 0 },
  76  { P, 0, 0, 0, 0 },
  77  { P, 0, 0, 0, 0 },
  78  { C, 0, 1, 1, 0 },
  79  { C, 0, 1, 1, 0 },
  80  { P, 0, 0, 0, 0 },
  81  { N, 1, 1, 0, 0 },
  82  { C, 0, 1, 1, 0 },
  83  { C, 0, 1, 1, 0 },
  84  { P, 0, 0, 0, 0 },
  85  { P, 0, 0, 0, 0 },
  86  { P, 0, 0, 0, 0 },
  87  { P, 0, 0, 0, 0 },
  88  { P, 0, 0, 0, 0 },
  89  { N, 1, 1, 0, 1 },
  90  { N, 0, 1, 0, 1 },
  91  { N, 0, 1, 0, 1 },
  92  { P, 0, 0, 0, 0 },
  93  { P, 0, 0, 0, 0 },
  94  { C, 0, 1, 1, 1 },
  95  { C, 0, 1, 1, 1 },
  96  { P, 0, 0, 0, 0 },
  97  { N, 1, 1, 0, 1 },
  98  { C, 0, 1, 1, 1 },
  99  { C, 0, 1, 1, 1 },
 100  { P, 0, 0, 0, 0 },
 101  { C, 0, 0, 0, 1 },
 102  { P, 0, 0, 0, 0 },
 103  { C, 0, 1, 0, 1 },
 104  { P, 0, 0, 0, 0 },
 105  { C, 1, 1, 0, 1 },
 106  { C, 0, 1, 0, 1 },
 107  { C, 0, 1, 0, 1 },
 108  { P, 0, 0, 0, 0 },
 109  { C, 1, 1, 1, 1 },
 110  { C, 0, 1, 1, 1 },
 111  { C, 0, 1, 1, 1 },
 112  { P, 0, 0, 0, 0 },
 113  { C, 1, 1, 1, 1 },
 114  { C, 0, 1, 1, 1 },
 115  { C, 0, 1, 1, 1 }
 116 };
 117
 118 /**
 119  * \param line_aa  BRW_WM_AA_NEVER, BRW_WM_AA_ALWAYS or BRW_WM_AA_SOMETIMES
 120  * \param lookup  bitmask of BRW_WM_IZ_* flags
 121  */
 122 void fs_visitor::setup_fs_payload_gen4()
 123 {
 124    assert(stage == MESA_SHADER_FRAGMENT);
 125    assert(dispatch_width <= 16);
 126    struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
 127    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
 128    GLuint reg = 1;
 129    bool kill_stats_promoted_workaround = false;
 130    int lookup = key->iz_lookup;
 131
 132    assert(lookup < BRW_WM_IZ_BIT_MAX);
 133
 134    /* Crazy workaround in the windowizer, which we need to track in
 135     * our register allocation and render target writes.  See the "If
 136     * statistics are enabled..." paragraph of 11.5.3.2: Early Depth
 137     * Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec.
 138     */
 139    if (key->stats_wm &&
 140        (lookup & BRW_WM_IZ_PS_KILL_ALPHATEST_BIT) &&
 141        wm_iz_table[lookup].mode == P) {
 142       kill_stats_promoted_workaround = true;
 143    }
 144
 145    payload.subspan_coord_reg[0] = reg++;
 146
 147    if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
 148        kill_stats_promoted_workaround) {
 149       payload.source_depth_reg[0] = reg;
 150       reg += 2;
 151    }
 152
 153    if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
 154       source_depth_to_render_target = true;
 155
 156    if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_WM_AA_NEVER) {
 157       payload.aa_dest_stencil_reg[0] = reg;
 158       runtime_check_aads_emit =
 159          !wm_iz_table[lookup].ds_present && key->line_aa == BRW_WM_AA_SOMETIMES;
 160       reg++;
 161    }
 162
 163    if (wm_iz_table[lookup].dd_present) {
 164       payload.dest_depth_reg[0] = reg;
 165       reg+=2;
 166    }
 167
 168    payload.num_regs = reg;
 169 }