2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
36 #include "drm-uapi/i915_drm.h"
67 * Get the PCI ID for the device name.
69 * Returns -1 if the device is not known.
72 gen_device_name_to_pci_device_id(const char *name
)
74 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
75 if (!strcmp(name_map
[i
].name
, name
))
76 return name_map
[i
].pci_id
;
82 static const struct gen_device_info gen_device_info_i965
= {
84 .has_negative_rhw_bug
= true,
86 .num_subslices
= { 1, },
87 .num_eu_per_subslice
= 8,
88 .num_thread_per_eu
= 4,
91 .max_wm_threads
= 8 * 4,
95 .timestamp_frequency
= 12500000,
99 static const struct gen_device_info gen_device_info_g4x
= {
103 .has_surface_tile_offset
= true,
106 .num_subslices
= { 1, },
107 .num_eu_per_subslice
= 10,
108 .num_thread_per_eu
= 5,
109 .max_vs_threads
= 32,
111 .max_wm_threads
= 10 * 5,
115 .timestamp_frequency
= 12500000,
119 static const struct gen_device_info gen_device_info_ilk
= {
123 .has_surface_tile_offset
= true,
125 .num_subslices
= { 1, },
126 .num_eu_per_subslice
= 12,
127 .num_thread_per_eu
= 6,
128 .max_vs_threads
= 72,
129 .max_gs_threads
= 32,
130 .max_wm_threads
= 12 * 6,
134 .timestamp_frequency
= 12500000,
138 static const struct gen_device_info gen_device_info_snb_gt1
= {
141 .has_hiz_and_separate_stencil
= true,
144 .has_surface_tile_offset
= true,
145 .needs_unlit_centroid_workaround
= true,
147 .num_subslices
= { 1, },
148 .num_eu_per_subslice
= 6,
149 .num_thread_per_eu
= 6, /* Not confirmed */
150 .max_vs_threads
= 24,
151 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
152 .max_wm_threads
= 40,
156 [MESA_SHADER_VERTEX
] = 24,
159 [MESA_SHADER_VERTEX
] = 256,
160 [MESA_SHADER_GEOMETRY
] = 256,
163 .timestamp_frequency
= 12500000,
167 static const struct gen_device_info gen_device_info_snb_gt2
= {
170 .has_hiz_and_separate_stencil
= true,
173 .has_surface_tile_offset
= true,
174 .needs_unlit_centroid_workaround
= true,
176 .num_subslices
= { 1, },
177 .num_eu_per_subslice
= 12,
178 .num_thread_per_eu
= 6, /* Not confirmed */
179 .max_vs_threads
= 60,
180 .max_gs_threads
= 60,
181 .max_wm_threads
= 80,
185 [MESA_SHADER_VERTEX
] = 24,
188 [MESA_SHADER_VERTEX
] = 256,
189 [MESA_SHADER_GEOMETRY
] = 256,
192 .timestamp_frequency
= 12500000,
196 #define GEN7_FEATURES \
198 .has_hiz_and_separate_stencil = true, \
199 .must_use_separate_stencil = true, \
202 .has_64bit_float = true, \
203 .has_surface_tile_offset = true, \
204 .timestamp_frequency = 12500000
206 static const struct gen_device_info gen_device_info_ivb_gt1
= {
207 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
209 .num_subslices
= { 1, },
210 .num_eu_per_subslice
= 6,
211 .num_thread_per_eu
= 6,
213 .max_vs_threads
= 36,
214 .max_tcs_threads
= 36,
215 .max_tes_threads
= 36,
216 .max_gs_threads
= 36,
217 .max_wm_threads
= 48,
218 .max_cs_threads
= 36,
222 [MESA_SHADER_VERTEX
] = 32,
223 [MESA_SHADER_TESS_EVAL
] = 10,
226 [MESA_SHADER_VERTEX
] = 512,
227 [MESA_SHADER_TESS_CTRL
] = 32,
228 [MESA_SHADER_TESS_EVAL
] = 288,
229 [MESA_SHADER_GEOMETRY
] = 192,
235 static const struct gen_device_info gen_device_info_ivb_gt2
= {
236 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
238 .num_subslices
= { 1, },
239 .num_eu_per_subslice
= 12,
240 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
241 * @max_wm_threads ... */
243 .max_vs_threads
= 128,
244 .max_tcs_threads
= 128,
245 .max_tes_threads
= 128,
246 .max_gs_threads
= 128,
247 .max_wm_threads
= 172,
248 .max_cs_threads
= 64,
252 [MESA_SHADER_VERTEX
] = 32,
253 [MESA_SHADER_TESS_EVAL
] = 10,
256 [MESA_SHADER_VERTEX
] = 704,
257 [MESA_SHADER_TESS_CTRL
] = 64,
258 [MESA_SHADER_TESS_EVAL
] = 448,
259 [MESA_SHADER_GEOMETRY
] = 320,
265 static const struct gen_device_info gen_device_info_byt
= {
266 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
268 .num_subslices
= { 1, },
269 .num_eu_per_subslice
= 4,
270 .num_thread_per_eu
= 8,
273 .max_vs_threads
= 36,
274 .max_tcs_threads
= 36,
275 .max_tes_threads
= 36,
276 .max_gs_threads
= 36,
277 .max_wm_threads
= 48,
278 .max_cs_threads
= 32,
282 [MESA_SHADER_VERTEX
] = 32,
283 [MESA_SHADER_TESS_EVAL
] = 10,
286 [MESA_SHADER_VERTEX
] = 512,
287 [MESA_SHADER_TESS_CTRL
] = 32,
288 [MESA_SHADER_TESS_EVAL
] = 288,
289 [MESA_SHADER_GEOMETRY
] = 192,
295 #define HSW_FEATURES \
297 .is_haswell = true, \
298 .supports_simd16_3src = true, \
299 .has_resource_streamer = true
301 static const struct gen_device_info gen_device_info_hsw_gt1
= {
302 HSW_FEATURES
, .gt
= 1,
304 .num_subslices
= { 1, },
305 .num_eu_per_subslice
= 10,
306 .num_thread_per_eu
= 7,
308 .max_vs_threads
= 70,
309 .max_tcs_threads
= 70,
310 .max_tes_threads
= 70,
311 .max_gs_threads
= 70,
312 .max_wm_threads
= 102,
313 .max_cs_threads
= 70,
317 [MESA_SHADER_VERTEX
] = 32,
318 [MESA_SHADER_TESS_EVAL
] = 10,
321 [MESA_SHADER_VERTEX
] = 640,
322 [MESA_SHADER_TESS_CTRL
] = 64,
323 [MESA_SHADER_TESS_EVAL
] = 384,
324 [MESA_SHADER_GEOMETRY
] = 256,
330 static const struct gen_device_info gen_device_info_hsw_gt2
= {
331 HSW_FEATURES
, .gt
= 2,
333 .num_subslices
= { 2, },
334 .num_eu_per_subslice
= 10,
335 .num_thread_per_eu
= 7,
337 .max_vs_threads
= 280,
338 .max_tcs_threads
= 256,
339 .max_tes_threads
= 280,
340 .max_gs_threads
= 256,
341 .max_wm_threads
= 204,
342 .max_cs_threads
= 70,
346 [MESA_SHADER_VERTEX
] = 64,
347 [MESA_SHADER_TESS_EVAL
] = 10,
350 [MESA_SHADER_VERTEX
] = 1664,
351 [MESA_SHADER_TESS_CTRL
] = 128,
352 [MESA_SHADER_TESS_EVAL
] = 960,
353 [MESA_SHADER_GEOMETRY
] = 640,
359 static const struct gen_device_info gen_device_info_hsw_gt3
= {
360 HSW_FEATURES
, .gt
= 3,
362 .num_subslices
= { 2, },
363 .num_eu_per_subslice
= 10,
364 .num_thread_per_eu
= 7,
366 .max_vs_threads
= 280,
367 .max_tcs_threads
= 256,
368 .max_tes_threads
= 280,
369 .max_gs_threads
= 256,
370 .max_wm_threads
= 408,
371 .max_cs_threads
= 70,
375 [MESA_SHADER_VERTEX
] = 64,
376 [MESA_SHADER_TESS_EVAL
] = 10,
379 [MESA_SHADER_VERTEX
] = 1664,
380 [MESA_SHADER_TESS_CTRL
] = 128,
381 [MESA_SHADER_TESS_EVAL
] = 960,
382 [MESA_SHADER_GEOMETRY
] = 640,
388 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
389 * so keep things conservative for now and set has_sample_with_hiz = false.
391 #define GEN8_FEATURES \
393 .has_hiz_and_separate_stencil = true, \
394 .has_resource_streamer = true, \
395 .must_use_separate_stencil = true, \
397 .has_sample_with_hiz = false, \
399 .has_integer_dword_mul = true, \
400 .has_64bit_float = true, \
401 .has_64bit_int = true, \
402 .supports_simd16_3src = true, \
403 .has_surface_tile_offset = true, \
404 .num_thread_per_eu = 7, \
405 .max_vs_threads = 504, \
406 .max_tcs_threads = 504, \
407 .max_tes_threads = 504, \
408 .max_gs_threads = 504, \
409 .max_wm_threads = 384, \
410 .timestamp_frequency = 12500000
412 static const struct gen_device_info gen_device_info_bdw_gt1
= {
413 GEN8_FEATURES
, .gt
= 1,
414 .is_broadwell
= true,
416 .num_subslices
= { 2, },
417 .num_eu_per_subslice
= 6,
419 .max_cs_threads
= 42,
423 [MESA_SHADER_VERTEX
] = 64,
424 [MESA_SHADER_TESS_EVAL
] = 34,
427 [MESA_SHADER_VERTEX
] = 2560,
428 [MESA_SHADER_TESS_CTRL
] = 504,
429 [MESA_SHADER_TESS_EVAL
] = 1536,
430 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
431 [MESA_SHADER_GEOMETRY
] = 690,
437 static const struct gen_device_info gen_device_info_bdw_gt2
= {
438 GEN8_FEATURES
, .gt
= 2,
439 .is_broadwell
= true,
441 .num_subslices
= { 3, },
442 .num_eu_per_subslice
= 8,
444 .max_cs_threads
= 56,
448 [MESA_SHADER_VERTEX
] = 64,
449 [MESA_SHADER_TESS_EVAL
] = 34,
452 [MESA_SHADER_VERTEX
] = 2560,
453 [MESA_SHADER_TESS_CTRL
] = 504,
454 [MESA_SHADER_TESS_EVAL
] = 1536,
455 [MESA_SHADER_GEOMETRY
] = 960,
461 static const struct gen_device_info gen_device_info_bdw_gt3
= {
462 GEN8_FEATURES
, .gt
= 3,
463 .is_broadwell
= true,
465 .num_subslices
= { 3, 3, },
466 .num_eu_per_subslice
= 8,
468 .max_cs_threads
= 56,
472 [MESA_SHADER_VERTEX
] = 64,
473 [MESA_SHADER_TESS_EVAL
] = 34,
476 [MESA_SHADER_VERTEX
] = 2560,
477 [MESA_SHADER_TESS_CTRL
] = 504,
478 [MESA_SHADER_TESS_EVAL
] = 1536,
479 [MESA_SHADER_GEOMETRY
] = 960,
485 static const struct gen_device_info gen_device_info_chv
= {
486 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
488 .has_integer_dword_mul
= false,
490 .num_subslices
= { 2, },
491 .num_eu_per_subslice
= 8,
493 .max_vs_threads
= 80,
494 .max_tcs_threads
= 80,
495 .max_tes_threads
= 80,
496 .max_gs_threads
= 80,
497 .max_wm_threads
= 128,
498 .max_cs_threads
= 6 * 7,
502 [MESA_SHADER_VERTEX
] = 34,
503 [MESA_SHADER_TESS_EVAL
] = 34,
506 [MESA_SHADER_VERTEX
] = 640,
507 [MESA_SHADER_TESS_CTRL
] = 80,
508 [MESA_SHADER_TESS_EVAL
] = 384,
509 [MESA_SHADER_GEOMETRY
] = 256,
515 #define GEN9_HW_INFO \
517 .max_vs_threads = 336, \
518 .max_gs_threads = 336, \
519 .max_tcs_threads = 336, \
520 .max_tes_threads = 336, \
521 .max_cs_threads = 56, \
522 .timestamp_frequency = 12000000, \
526 [MESA_SHADER_VERTEX] = 64, \
527 [MESA_SHADER_TESS_EVAL] = 34, \
530 [MESA_SHADER_VERTEX] = 1856, \
531 [MESA_SHADER_TESS_CTRL] = 672, \
532 [MESA_SHADER_TESS_EVAL] = 1120, \
533 [MESA_SHADER_GEOMETRY] = 640, \
537 #define GEN9_LP_FEATURES \
540 .has_integer_dword_mul = false, \
543 .has_sample_with_hiz = true, \
545 .num_thread_per_eu = 6, \
546 .max_vs_threads = 112, \
547 .max_tcs_threads = 112, \
548 .max_tes_threads = 112, \
549 .max_gs_threads = 112, \
550 .max_cs_threads = 6 * 6, \
551 .timestamp_frequency = 19200000, \
555 [MESA_SHADER_VERTEX] = 34, \
556 [MESA_SHADER_TESS_EVAL] = 34, \
559 [MESA_SHADER_VERTEX] = 704, \
560 [MESA_SHADER_TESS_CTRL] = 256, \
561 [MESA_SHADER_TESS_EVAL] = 416, \
562 [MESA_SHADER_GEOMETRY] = 256, \
566 #define GEN9_LP_FEATURES_3X6 \
568 .num_subslices = { 3, }, \
569 .num_eu_per_subslice = 6
571 #define GEN9_LP_FEATURES_2X6 \
573 .num_subslices = { 2, }, \
574 .num_eu_per_subslice = 6, \
575 .max_vs_threads = 56, \
576 .max_tcs_threads = 56, \
577 .max_tes_threads = 56, \
578 .max_gs_threads = 56, \
579 .max_cs_threads = 6 * 6, \
583 [MESA_SHADER_VERTEX] = 34, \
584 [MESA_SHADER_TESS_EVAL] = 34, \
587 [MESA_SHADER_VERTEX] = 352, \
588 [MESA_SHADER_TESS_CTRL] = 128, \
589 [MESA_SHADER_TESS_EVAL] = 208, \
590 [MESA_SHADER_GEOMETRY] = 128, \
594 #define GEN9_FEATURES \
597 .has_sample_with_hiz = true
599 static const struct gen_device_info gen_device_info_skl_gt1
= {
600 GEN9_FEATURES
, .gt
= 1,
603 .num_subslices
= { 2, },
604 .num_eu_per_subslice
= 6,
607 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
608 * leading to some vertices to go missing if we use too much URB.
610 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
614 static const struct gen_device_info gen_device_info_skl_gt2
= {
615 GEN9_FEATURES
, .gt
= 2,
618 .num_subslices
= { 3, },
619 .num_eu_per_subslice
= 8,
624 static const struct gen_device_info gen_device_info_skl_gt3
= {
625 GEN9_FEATURES
, .gt
= 3,
628 .num_subslices
= { 3, 3, },
629 .num_eu_per_subslice
= 8,
634 static const struct gen_device_info gen_device_info_skl_gt4
= {
635 GEN9_FEATURES
, .gt
= 4,
638 .num_subslices
= { 3, 3, 3, },
639 .num_eu_per_subslice
= 8,
641 /* From the "L3 Allocation and Programming" documentation:
643 * "URB is limited to 1008KB due to programming restrictions. This is not a
644 * restriction of the L3 implementation, but of the FF and other clients.
645 * Therefore, in a GT4 implementation it is possible for the programmed
646 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
647 * only 1008KB of this will be used."
649 .urb
.size
= 1008 / 3,
653 static const struct gen_device_info gen_device_info_bxt
= {
654 GEN9_LP_FEATURES_3X6
,
660 static const struct gen_device_info gen_device_info_bxt_2x6
= {
661 GEN9_LP_FEATURES_2X6
,
667 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
668 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
671 static const struct gen_device_info gen_device_info_kbl_gt1
= {
676 .max_cs_threads
= 7 * 6,
679 .num_subslices
= { 2, },
680 .num_eu_per_subslice
= 6,
682 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
683 * leading to some vertices to go missing if we use too much URB.
685 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
689 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
694 .max_cs_threads
= 7 * 6,
696 .num_subslices
= { 3, },
697 .num_eu_per_subslice
= 6,
702 static const struct gen_device_info gen_device_info_kbl_gt2
= {
708 .num_subslices
= { 3, },
709 .num_eu_per_subslice
= 8,
714 static const struct gen_device_info gen_device_info_kbl_gt3
= {
720 .num_subslices
= { 3, 3, },
721 .num_eu_per_subslice
= 8,
726 static const struct gen_device_info gen_device_info_kbl_gt4
= {
732 * From the "L3 Allocation and Programming" documentation:
734 * "URB is limited to 1008KB due to programming restrictions. This
735 * is not a restriction of the L3 implementation, but of the FF and
736 * other clients. Therefore, in a GT4 implementation it is
737 * possible for the programmed allocation of the L3 data array to
738 * provide 3*384KB=1152KB for URB, but only 1008KB of this
741 .urb
.size
= 1008 / 3,
743 .num_subslices
= { 3, 3, 3, },
744 .num_eu_per_subslice
= 8,
749 static const struct gen_device_info gen_device_info_glk
= {
750 GEN9_LP_FEATURES_3X6
,
751 .is_geminilake
= true,
756 static const struct gen_device_info gen_device_info_glk_2x6
= {
757 GEN9_LP_FEATURES_2X6
,
758 .is_geminilake
= true,
763 static const struct gen_device_info gen_device_info_cfl_gt1
= {
765 .is_coffeelake
= true,
769 .num_subslices
= { 2, },
770 .num_eu_per_subslice
= 6,
773 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
774 * leading to some vertices to go missing if we use too much URB.
776 .urb
.max_entries
[MESA_SHADER_VERTEX
] = 928,
779 static const struct gen_device_info gen_device_info_cfl_gt2
= {
781 .is_coffeelake
= true,
785 .num_subslices
= { 3, },
786 .num_eu_per_subslice
= 8,
791 static const struct gen_device_info gen_device_info_cfl_gt3
= {
793 .is_coffeelake
= true,
797 .num_subslices
= { 3, 3, },
798 .num_eu_per_subslice
= 8,
803 #define GEN10_HW_INFO \
805 .num_thread_per_eu = 7, \
806 .max_vs_threads = 728, \
807 .max_gs_threads = 432, \
808 .max_tcs_threads = 432, \
809 .max_tes_threads = 624, \
810 .max_cs_threads = 56, \
811 .timestamp_frequency = 19200000, \
815 [MESA_SHADER_VERTEX] = 64, \
816 [MESA_SHADER_TESS_EVAL] = 34, \
819 [MESA_SHADER_VERTEX] = 3936, \
820 [MESA_SHADER_TESS_CTRL] = 896, \
821 [MESA_SHADER_TESS_EVAL] = 2064, \
822 [MESA_SHADER_GEOMETRY] = 832, \
826 #define subslices(args...) { args, }
828 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
831 .has_sample_with_hiz = true, \
833 .num_slices = _slices, \
834 .num_subslices = _subslices, \
835 .num_eu_per_subslice = 8, \
838 static const struct gen_device_info gen_device_info_cnl_gt0_5
= {
840 GEN10_FEATURES(1, 1, subslices(2), 2),
841 .is_cannonlake
= true,
845 static const struct gen_device_info gen_device_info_cnl_gt1
= {
847 GEN10_FEATURES(1, 1, subslices(3), 3),
848 .is_cannonlake
= true,
852 static const struct gen_device_info gen_device_info_cnl_gt1_5
= {
854 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
855 .is_cannonlake
= true,
859 static const struct gen_device_info gen_device_info_cnl_gt2
= {
861 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
862 .is_cannonlake
= true,
866 #define GEN11_HW_INFO \
869 .max_vs_threads = 364, \
870 .max_gs_threads = 224, \
871 .max_tcs_threads = 224, \
872 .max_tes_threads = 364, \
875 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
878 .has_64bit_float = false, \
879 .has_64bit_int = false, \
880 .has_integer_dword_mul = false, \
881 .has_sample_with_hiz = false, \
882 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
883 .num_subslices = _subslices, \
884 .num_eu_per_subslice = 8
886 #define GEN11_URB_MIN_MAX_ENTRIES \
888 [MESA_SHADER_VERTEX] = 64, \
889 [MESA_SHADER_TESS_EVAL] = 34, \
892 [MESA_SHADER_VERTEX] = 2384, \
893 [MESA_SHADER_TESS_CTRL] = 1032, \
894 [MESA_SHADER_TESS_EVAL] = 2384, \
895 [MESA_SHADER_GEOMETRY] = 1032, \
898 static const struct gen_device_info gen_device_info_icl_gt2
= {
899 GEN11_FEATURES(2, 1, subslices(8), 8),
902 GEN11_URB_MIN_MAX_ENTRIES
,
907 static const struct gen_device_info gen_device_info_icl_gt1_5
= {
908 GEN11_FEATURES(1, 1, subslices(6), 6),
911 GEN11_URB_MIN_MAX_ENTRIES
,
916 static const struct gen_device_info gen_device_info_icl_gt1
= {
917 GEN11_FEATURES(1, 1, subslices(4), 6),
920 GEN11_URB_MIN_MAX_ENTRIES
,
925 static const struct gen_device_info gen_device_info_icl_gt0_5
= {
926 GEN11_FEATURES(1, 1, subslices(1), 6),
929 GEN11_URB_MIN_MAX_ENTRIES
,
934 static const struct gen_device_info gen_device_info_ehl_7
= {
935 GEN11_FEATURES(1, 1, subslices(4), 4),
936 .is_elkhartlake
= true,
940 [MESA_SHADER_VERTEX
] = 64,
941 [MESA_SHADER_TESS_EVAL
] = 34,
944 [MESA_SHADER_VERTEX
] = 2384,
945 [MESA_SHADER_TESS_CTRL
] = 1032,
946 [MESA_SHADER_TESS_EVAL
] = 2384,
947 [MESA_SHADER_GEOMETRY
] = 1032,
950 .disable_ccs_repack
= true,
954 static const struct gen_device_info gen_device_info_ehl_6
= {
955 GEN11_FEATURES(1, 1, subslices(4), 4),
956 .is_elkhartlake
= true,
960 [MESA_SHADER_VERTEX
] = 64,
961 [MESA_SHADER_TESS_EVAL
] = 34,
964 [MESA_SHADER_VERTEX
] = 2384,
965 [MESA_SHADER_TESS_CTRL
] = 1032,
966 [MESA_SHADER_TESS_EVAL
] = 2384,
967 [MESA_SHADER_GEOMETRY
] = 1032,
970 .disable_ccs_repack
= true,
971 .num_eu_per_subslice
= 6,
975 static const struct gen_device_info gen_device_info_ehl_5
= {
976 GEN11_FEATURES(1, 1, subslices(4), 4),
977 .is_elkhartlake
= true,
981 [MESA_SHADER_VERTEX
] = 64,
982 [MESA_SHADER_TESS_EVAL
] = 34,
985 [MESA_SHADER_VERTEX
] = 2384,
986 [MESA_SHADER_TESS_CTRL
] = 1032,
987 [MESA_SHADER_TESS_EVAL
] = 2384,
988 [MESA_SHADER_GEOMETRY
] = 1032,
991 .disable_ccs_repack
= true,
992 .num_eu_per_subslice
= 4,
996 static const struct gen_device_info gen_device_info_ehl_4
= {
997 GEN11_FEATURES(1, 1, subslices(2), 4),
998 .is_elkhartlake
= true,
1002 [MESA_SHADER_VERTEX
] = 64,
1003 [MESA_SHADER_TESS_EVAL
] = 34,
1006 [MESA_SHADER_VERTEX
] = 2384,
1007 [MESA_SHADER_TESS_CTRL
] = 1032,
1008 [MESA_SHADER_TESS_EVAL
] = 2384,
1009 [MESA_SHADER_GEOMETRY
] = 1032,
1012 .disable_ccs_repack
= true,
1013 .num_eu_per_subslice
=4,
1017 #define GEN12_URB_MIN_MAX_ENTRIES \
1019 [MESA_SHADER_VERTEX] = 64, \
1020 [MESA_SHADER_TESS_EVAL] = 34, \
1023 [MESA_SHADER_VERTEX] = 3576, \
1024 [MESA_SHADER_TESS_CTRL] = 1548, \
1025 [MESA_SHADER_TESS_EVAL] = 3576, \
1026 [MESA_SHADER_GEOMETRY] = 1548, \
1029 #define GEN12_HW_INFO \
1032 .has_sample_with_hiz = false, \
1033 .has_aux_map = true, \
1034 .max_vs_threads = 546, \
1035 .max_gs_threads = 336, \
1036 .max_tcs_threads = 336, \
1037 .max_tes_threads = 546, \
1038 .max_cs_threads = 112, /* threads per DSS */ \
1040 GEN12_URB_MIN_MAX_ENTRIES, \
1043 #define GEN12_FEATURES(_gt, _slices, _l3) \
1046 .has_64bit_float = false, \
1047 .has_64bit_int = false, \
1048 .has_integer_dword_mul = false, \
1049 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1050 .simulator_id = 22, \
1051 .urb.size = (_gt) == 1 ? 512 : 1024, \
1052 .num_eu_per_subslice = 16
1054 #define dual_subslices(args...) { args, }
1056 #define GEN12_GT_FEATURES(_gt) \
1057 GEN12_FEATURES(1, 1, _gt == 1 ? 4 : 8), \
1058 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1060 static const struct gen_device_info gen_device_info_tgl_gt1
= {
1061 GEN12_GT_FEATURES(1),
1064 static const struct gen_device_info gen_device_info_tgl_gt2
= {
1065 GEN12_GT_FEATURES(2),
1069 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
1074 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
1075 subslice
* devinfo
->eu_subslice_stride
;
1077 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
1078 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
1079 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
1083 /* Generate slice/subslice/eu masks from number of
1084 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1087 * These can be overridden with values reported by the kernel either from
1088 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1089 * through the i915 query uapi.
1092 fill_masks(struct gen_device_info
*devinfo
)
1094 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
1096 /* Subslice masks */
1097 unsigned max_subslices
= 0;
1098 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
1099 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
1100 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
1102 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1103 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
1104 (1U << devinfo
->num_subslices
[s
]) - 1;
1108 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
1109 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
1111 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
1112 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
1113 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
1114 (1U << devinfo
->num_eu_per_subslice
) - 1);
1120 reset_masks(struct gen_device_info
*devinfo
)
1122 devinfo
->subslice_slice_stride
= 0;
1123 devinfo
->eu_subslice_stride
= 0;
1124 devinfo
->eu_slice_stride
= 0;
1126 devinfo
->num_slices
= 0;
1127 devinfo
->num_eu_per_subslice
= 0;
1128 memset(devinfo
->num_subslices
, 0, sizeof(devinfo
->num_subslices
));
1130 memset(&devinfo
->slice_masks
, 0, sizeof(devinfo
->slice_masks
));
1131 memset(devinfo
->subslice_masks
, 0, sizeof(devinfo
->subslice_masks
));
1132 memset(devinfo
->eu_masks
, 0, sizeof(devinfo
->eu_masks
));
1133 memset(devinfo
->ppipe_subslices
, 0, sizeof(devinfo
->ppipe_subslices
));
1137 update_from_topology(struct gen_device_info
*devinfo
,
1138 const struct drm_i915_query_topology_info
*topology
)
1140 reset_masks(devinfo
);
1142 devinfo
->subslice_slice_stride
= topology
->subslice_stride
;
1144 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(topology
->max_eus_per_subslice
, 8);
1145 devinfo
->eu_slice_stride
= topology
->max_subslices
* devinfo
->eu_subslice_stride
;
1147 assert(sizeof(devinfo
->slice_masks
) >= DIV_ROUND_UP(topology
->max_slices
, 8));
1148 memcpy(&devinfo
->slice_masks
, topology
->data
, DIV_ROUND_UP(topology
->max_slices
, 8));
1149 devinfo
->num_slices
= __builtin_popcount(devinfo
->slice_masks
);
1151 uint32_t subslice_mask_len
=
1152 topology
->max_slices
* topology
->subslice_stride
;
1153 assert(sizeof(devinfo
->subslice_masks
) >= subslice_mask_len
);
1154 memcpy(devinfo
->subslice_masks
, &topology
->data
[topology
->subslice_offset
],
1157 uint32_t n_subslices
= 0;
1158 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1159 if ((devinfo
->slice_masks
& (1 << s
)) == 0)
1162 for (int b
= 0; b
< devinfo
->subslice_slice_stride
; b
++) {
1163 devinfo
->num_subslices
[s
] +=
1164 __builtin_popcount(devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
+ b
]);
1166 n_subslices
+= devinfo
->num_subslices
[s
];
1168 assert(n_subslices
> 0);
1170 if (devinfo
->gen
== 11) {
1171 /* On ICL we only have one slice */
1172 assert(devinfo
->slice_masks
== 1);
1174 /* Count the number of subslices on each pixel pipe. Assume that
1175 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1177 unsigned subslices
= devinfo
->subslice_masks
[0];
1179 while (subslices
> 0) {
1181 devinfo
->ppipe_subslices
[ss
>= 4 ? 1 : 0] += 1;
1187 if (devinfo
->gen
== 12 && devinfo
->num_slices
== 1) {
1188 if (n_subslices
>= 6) {
1189 assert(n_subslices
== 6);
1190 devinfo
->l3_banks
= 8;
1191 } else if (n_subslices
> 2) {
1192 devinfo
->l3_banks
= 6;
1194 devinfo
->l3_banks
= 4;
1198 uint32_t eu_mask_len
=
1199 topology
->eu_stride
* topology
->max_subslices
* topology
->max_slices
;
1200 assert(sizeof(devinfo
->eu_masks
) >= eu_mask_len
);
1201 memcpy(devinfo
->eu_masks
, &topology
->data
[topology
->eu_offset
], eu_mask_len
);
1204 for (int b
= 0; b
< eu_mask_len
; b
++)
1205 n_eus
+= __builtin_popcount(devinfo
->eu_masks
[b
]);
1207 devinfo
->num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1211 update_from_masks(struct gen_device_info
*devinfo
, uint32_t slice_mask
,
1212 uint32_t subslice_mask
, uint32_t n_eus
)
1214 struct drm_i915_query_topology_info
*topology
;
1216 assert((slice_mask
& 0xff) == slice_mask
);
1218 size_t data_length
= 100;
1220 topology
= calloc(1, sizeof(*topology
) + data_length
);
1224 topology
->max_slices
= util_last_bit(slice_mask
);
1225 topology
->max_subslices
= util_last_bit(subslice_mask
);
1227 topology
->subslice_offset
= DIV_ROUND_UP(topology
->max_slices
, 8);
1228 topology
->subslice_stride
= DIV_ROUND_UP(topology
->max_subslices
, 8);
1230 uint32_t n_subslices
= __builtin_popcount(slice_mask
) *
1231 __builtin_popcount(subslice_mask
);
1232 uint32_t num_eu_per_subslice
= DIV_ROUND_UP(n_eus
, n_subslices
);
1233 uint32_t eu_mask
= (1U << num_eu_per_subslice
) - 1;
1235 topology
->eu_offset
= topology
->subslice_offset
+
1236 DIV_ROUND_UP(topology
->max_subslices
, 8);
1237 topology
->eu_stride
= DIV_ROUND_UP(num_eu_per_subslice
, 8);
1239 /* Set slice mask in topology */
1240 for (int b
= 0; b
< topology
->subslice_offset
; b
++)
1241 topology
->data
[b
] = (slice_mask
>> (b
* 8)) & 0xff;
1243 for (int s
= 0; s
< topology
->max_slices
; s
++) {
1245 /* Set subslice mask in topology */
1246 for (int b
= 0; b
< topology
->subslice_stride
; b
++) {
1247 int subslice_offset
= topology
->subslice_offset
+
1248 s
* topology
->subslice_stride
+ b
;
1250 topology
->data
[subslice_offset
] = (subslice_mask
>> (b
* 8)) & 0xff;
1253 /* Set eu mask in topology */
1254 for (int ss
= 0; ss
< topology
->max_subslices
; ss
++) {
1255 for (int b
= 0; b
< topology
->eu_stride
; b
++) {
1256 int eu_offset
= topology
->eu_offset
+
1257 (s
* topology
->max_subslices
+ ss
) * topology
->eu_stride
+ b
;
1259 topology
->data
[eu_offset
] = (eu_mask
>> (b
* 8)) & 0xff;
1264 update_from_topology(devinfo
, topology
);
1271 getparam(int fd
, uint32_t param
, int *value
)
1275 struct drm_i915_getparam gp
= {
1280 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
1289 gen_get_device_info_from_pci_id(int pci_id
,
1290 struct gen_device_info
*devinfo
)
1294 #define CHIPSET(id, family, fam_str, name) \
1295 case id: *devinfo = gen_device_info_##family; break;
1296 #include "pci_ids/i965_pci_ids.h"
1297 #include "pci_ids/iris_pci_ids.h"
1299 fprintf(stderr
, "Driver does not support the 0x%x PCI ID.\n", pci_id
);
1303 fill_masks(devinfo
);
1305 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1307 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1308 * allocate scratch space enough so that each slice has 4 slices allowed."
1310 * The equivalent internal documentation says that this programming note
1311 * applies to all Gen9+ platforms.
1313 * The hardware typically calculates the scratch space pointer by taking
1314 * the base address, and adding per-thread-scratch-space * thread ID.
1315 * Extra padding can be necessary depending how the thread IDs are
1316 * calculated for a particular shader stage.
1319 switch(devinfo
->gen
) {
1322 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
1323 * devinfo
->num_slices
1324 * 4; /* effective subslices per slice */
1328 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
1329 * devinfo
->num_slices
1330 * 8; /* subslices per slice */
1333 assert(devinfo
->gen
< 9);
1337 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
1339 devinfo
->chipset_id
= pci_id
;
1344 gen_get_device_name(int devid
)
1348 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1349 #include "pci_ids/i965_pci_ids.h"
1350 #include "pci_ids/iris_pci_ids.h"
1357 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1361 getparam_topology(struct gen_device_info
*devinfo
, int fd
)
1364 if (!getparam(fd
, I915_PARAM_SLICE_MASK
, &slice_mask
))
1368 if (!getparam(fd
, I915_PARAM_EU_TOTAL
, &n_eus
))
1371 int subslice_mask
= 0;
1372 if (!getparam(fd
, I915_PARAM_SUBSLICE_MASK
, &subslice_mask
))
1375 return update_from_masks(devinfo
, slice_mask
, subslice_mask
, n_eus
);
1379 * preferred API for updating the topology in devinfo (kernel 4.17+)
1382 query_topology(struct gen_device_info
*devinfo
, int fd
)
1384 struct drm_i915_query_item item
= {
1385 .query_id
= DRM_I915_QUERY_TOPOLOGY_INFO
,
1387 struct drm_i915_query query
= {
1389 .items_ptr
= (uintptr_t) &item
,
1392 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
))
1395 if (item
.length
< 0)
1398 struct drm_i915_query_topology_info
*topo_info
=
1399 (struct drm_i915_query_topology_info
*) calloc(1, item
.length
);
1400 item
.data_ptr
= (uintptr_t) topo_info
;
1402 if (gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &query
) ||
1406 update_from_topology(devinfo
, topo_info
);
1415 gen_get_device_info_from_fd(int fd
, struct gen_device_info
*devinfo
)
1419 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1420 if (devid_override
&& strlen(devid_override
) > 0) {
1421 if (geteuid() == getuid()) {
1422 devid
= gen_device_name_to_pci_device_id(devid_override
);
1423 /* Fallback to PCI ID. */
1425 devid
= strtol(devid_override
, NULL
, 0);
1427 fprintf(stderr
, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1428 "Use a valid numeric PCI ID or one of the supported "
1429 "platform names: %s", devid_override
, name_map
[0].name
);
1430 for (unsigned i
= 1; i
< ARRAY_SIZE(name_map
); i
++)
1431 fprintf(stderr
, ", %s", name_map
[i
].name
);
1432 fprintf(stderr
, "\n");
1436 fprintf(stderr
, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1437 "real and effective user ID don't match.\n", devid_override
);
1442 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1444 devinfo
->no_hw
= true;
1446 /* query the device id */
1447 if (!getparam(fd
, I915_PARAM_CHIPSET_ID
, &devid
))
1449 if (!gen_get_device_info_from_pci_id(devid
, devinfo
))
1451 devinfo
->no_hw
= false;
1454 /* remaining initializion queries the kernel for device info */
1458 int timestamp_frequency
;
1459 if (getparam(fd
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1460 ×tamp_frequency
))
1461 devinfo
->timestamp_frequency
= timestamp_frequency
;
1462 else if (devinfo
->gen
>= 10)
1463 /* gen10 and later requires the timestamp_frequency to be updated */
1466 if (!getparam(fd
, I915_PARAM_REVISION
, &devinfo
->revision
))
1467 devinfo
->revision
= 0;
1469 if (!query_topology(devinfo
, fd
)) {
1470 if (devinfo
->gen
>= 10) {
1471 /* topology uAPI required for CNL+ (kernel 4.17+) */
1475 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1476 * will be wrong, affecting GPU metrics. In this case, fail silently.
1478 getparam_topology(devinfo
, fd
);