src/intel/dev/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <stdio.h>
  27 #include <stdlib.h>
  28 #include <string.h>
  29 #include <unistd.h>
  30 #include "gen_device_info.h"
  31 #include "compiler/shader_enums.h"
  32 #include "intel/common/gen_gem.h"
  33 #include "util/bitscan.h"
  34 #include "util/macros.h"
  35
  36 #include "drm-uapi/i915_drm.h"
  37
  38 /**
  39  * Get the PCI ID for the device name.
  40  *
  41  * Returns -1 if the device is not known.
  42  */
  43 int
  44 gen_device_name_to_pci_device_id(const char *name)
  45 {
  46    static const struct {
  47       const char *name;
  48       int pci_id;
  49    } name_map[] = {
  50       { "brw", 0x2a02 },
  51       { "g4x", 0x2a42 },
  52       { "ilk", 0x0042 },
  53       { "snb", 0x0126 },
  54       { "ivb", 0x016a },
  55       { "hsw", 0x0d2e },
  56       { "byt", 0x0f33 },
  57       { "bdw", 0x162e },
  58       { "chv", 0x22B3 },
  59       { "skl", 0x1912 },
  60       { "bxt", 0x5A85 },
  61       { "kbl", 0x5912 },
  62       { "aml", 0x591C },
  63       { "glk", 0x3185 },
  64       { "cfl", 0x3E9B },
  65       { "whl", 0x3EA1 },
  66       { "cml", 0x9b41 },
  67       { "cnl", 0x5a52 },
  68       { "icl", 0x8a52 },
  69       { "ehl", 0x4500 },
  70       { "jsl", 0x4E71 },
  71       { "tgl", 0x9a49 },
  72    };
  73
  74    for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
  75       if (!strcmp(name_map[i].name, name))
  76          return name_map[i].pci_id;
  77    }
  78
  79    return -1;
  80 }
  81
  82 /**
  83  * Get the overridden PCI ID for the device. This is set with the
  84  * INTEL_DEVID_OVERRIDE environment variable.
  85  *
  86  * Returns -1 if the override is not set.
  87  */
  88 static int
  89 get_pci_device_id_override(void)
  90 {
  91    if (geteuid() == getuid()) {
  92       const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
  93       if (devid_override) {
  94          const int id = gen_device_name_to_pci_device_id(devid_override);
  95          return id >= 0 ? id : strtol(devid_override, NULL, 0);
  96       }
  97    }
  98
  99    return -1;
 100 }
 101
 102 static const struct gen_device_info gen_device_info_i965 = {
 103    .gen = 4,
 104    .has_negative_rhw_bug = true,
 105    .num_slices = 1,
 106    .num_subslices = { 1, },
 107    .num_eu_per_subslice = 8,
 108    .num_thread_per_eu = 4,
 109    .max_vs_threads = 16,
 110    .max_gs_threads = 2,
 111    .max_wm_threads = 8 * 4,
 112    .urb = {
 113       .size = 256,
 114    },
 115    .timestamp_frequency = 12500000,
 116    .simulator_id = -1,
 117 };
 118
 119 static const struct gen_device_info gen_device_info_g4x = {
 120    .gen = 4,
 121    .has_pln = true,
 122    .has_compr4 = true,
 123    .has_surface_tile_offset = true,
 124    .is_g4x = true,
 125    .num_slices = 1,
 126    .num_subslices = { 1, },
 127    .num_eu_per_subslice = 10,
 128    .num_thread_per_eu = 5,
 129    .max_vs_threads = 32,
 130    .max_gs_threads = 2,
 131    .max_wm_threads = 10 * 5,
 132    .urb = {
 133       .size = 384,
 134    },
 135    .timestamp_frequency = 12500000,
 136    .simulator_id = -1,
 137 };
 138
 139 static const struct gen_device_info gen_device_info_ilk = {
 140    .gen = 5,
 141    .has_pln = true,
 142    .has_compr4 = true,
 143    .has_surface_tile_offset = true,
 144    .num_slices = 1,
 145    .num_subslices = { 1, },
 146    .num_eu_per_subslice = 12,
 147    .num_thread_per_eu = 6,
 148    .max_vs_threads = 72,
 149    .max_gs_threads = 32,
 150    .max_wm_threads = 12 * 6,
 151    .urb = {
 152       .size = 1024,
 153    },
 154    .timestamp_frequency = 12500000,
 155    .simulator_id = -1,
 156 };
 157
 158 static const struct gen_device_info gen_device_info_snb_gt1 = {
 159    .gen = 6,
 160    .gt = 1,
 161    .has_hiz_and_separate_stencil = true,
 162    .has_llc = true,
 163    .has_pln = true,
 164    .has_surface_tile_offset = true,
 165    .needs_unlit_centroid_workaround = true,
 166    .num_slices = 1,
 167    .num_subslices = { 1, },
 168    .num_eu_per_subslice = 6,
 169    .num_thread_per_eu = 6, /* Not confirmed */
 170    .max_vs_threads = 24,
 171    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
 172    .max_wm_threads = 40,
 173    .urb = {
 174       .size = 32,
 175       .min_entries = {
 176          [MESA_SHADER_VERTEX]   = 24,
 177       },
 178       .max_entries = {
 179          [MESA_SHADER_VERTEX]   = 256,
 180          [MESA_SHADER_GEOMETRY] = 256,
 181       },
 182    },
 183    .timestamp_frequency = 12500000,
 184    .simulator_id = -1,
 185 };
 186
 187 static const struct gen_device_info gen_device_info_snb_gt2 = {
 188    .gen = 6,
 189    .gt = 2,
 190    .has_hiz_and_separate_stencil = true,
 191    .has_llc = true,
 192    .has_pln = true,
 193    .has_surface_tile_offset = true,
 194    .needs_unlit_centroid_workaround = true,
 195    .num_slices = 1,
 196    .num_subslices = { 1, },
 197    .num_eu_per_subslice = 12,
 198    .num_thread_per_eu = 6, /* Not confirmed */
 199    .max_vs_threads = 60,
 200    .max_gs_threads = 60,
 201    .max_wm_threads = 80,
 202    .urb = {
 203       .size = 64,
 204       .min_entries = {
 205          [MESA_SHADER_VERTEX]   = 24,
 206       },
 207       .max_entries = {
 208          [MESA_SHADER_VERTEX]   = 256,
 209          [MESA_SHADER_GEOMETRY] = 256,
 210       },
 211    },
 212    .timestamp_frequency = 12500000,
 213    .simulator_id = -1,
 214 };
 215
 216 #define GEN7_FEATURES                               \
 217    .gen = 7,                                        \
 218    .has_hiz_and_separate_stencil = true,            \
 219    .must_use_separate_stencil = true,               \
 220    .has_llc = true,                                 \
 221    .has_pln = true,                                 \
 222    .has_64bit_types = true,                         \
 223    .has_surface_tile_offset = true,                 \
 224    .timestamp_frequency = 12500000
 225
 226 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 227    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 228    .num_slices = 1,
 229    .num_subslices = { 1, },
 230    .num_eu_per_subslice = 6,
 231    .num_thread_per_eu = 6,
 232    .l3_banks = 2,
 233    .max_vs_threads = 36,
 234    .max_tcs_threads = 36,
 235    .max_tes_threads = 36,
 236    .max_gs_threads = 36,
 237    .max_wm_threads = 48,
 238    .max_cs_threads = 36,
 239    .urb = {
 240       .size = 128,
 241       .min_entries = {
 242          [MESA_SHADER_VERTEX]    = 32,
 243          [MESA_SHADER_TESS_EVAL] = 10,
 244       },
 245       .max_entries = {
 246          [MESA_SHADER_VERTEX]    = 512,
 247          [MESA_SHADER_TESS_CTRL] = 32,
 248          [MESA_SHADER_TESS_EVAL] = 288,
 249          [MESA_SHADER_GEOMETRY]  = 192,
 250       },
 251    },
 252    .simulator_id = 7,
 253 };
 254
 255 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 256    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 257    .num_slices = 1,
 258    .num_subslices = { 1, },
 259    .num_eu_per_subslice = 12,
 260    .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
 261                             * @max_wm_threads ... */
 262    .l3_banks = 4,
 263    .max_vs_threads = 128,
 264    .max_tcs_threads = 128,
 265    .max_tes_threads = 128,
 266    .max_gs_threads = 128,
 267    .max_wm_threads = 172,
 268    .max_cs_threads = 64,
 269    .urb = {
 270       .size = 256,
 271       .min_entries = {
 272          [MESA_SHADER_VERTEX]    = 32,
 273          [MESA_SHADER_TESS_EVAL] = 10,
 274       },
 275       .max_entries = {
 276          [MESA_SHADER_VERTEX]    = 704,
 277          [MESA_SHADER_TESS_CTRL] = 64,
 278          [MESA_SHADER_TESS_EVAL] = 448,
 279          [MESA_SHADER_GEOMETRY]  = 320,
 280       },
 281    },
 282    .simulator_id = 7,
 283 };
 284
 285 static const struct gen_device_info gen_device_info_byt = {
 286    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 287    .num_slices = 1,
 288    .num_subslices = { 1, },
 289    .num_eu_per_subslice = 4,
 290    .num_thread_per_eu = 8,
 291    .l3_banks = 1,
 292    .has_llc = false,
 293    .max_vs_threads = 36,
 294    .max_tcs_threads = 36,
 295    .max_tes_threads = 36,
 296    .max_gs_threads = 36,
 297    .max_wm_threads = 48,
 298    .max_cs_threads = 32,
 299    .urb = {
 300       .size = 128,
 301       .min_entries = {
 302          [MESA_SHADER_VERTEX]    = 32,
 303          [MESA_SHADER_TESS_EVAL] = 10,
 304       },
 305       .max_entries = {
 306          [MESA_SHADER_VERTEX]    = 512,
 307          [MESA_SHADER_TESS_CTRL] = 32,
 308          [MESA_SHADER_TESS_EVAL] = 288,
 309          [MESA_SHADER_GEOMETRY]  = 192,
 310       },
 311    },
 312    .simulator_id = 10,
 313 };
 314
 315 #define HSW_FEATURES             \
 316    GEN7_FEATURES,                \
 317    .is_haswell = true,           \
 318    .supports_simd16_3src = true, \
 319    .has_resource_streamer = true
 320
 321 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 322    HSW_FEATURES, .gt = 1,
 323    .num_slices = 1,
 324    .num_subslices = { 1, },
 325    .num_eu_per_subslice = 10,
 326    .num_thread_per_eu = 7,
 327    .l3_banks = 2,
 328    .max_vs_threads = 70,
 329    .max_tcs_threads = 70,
 330    .max_tes_threads = 70,
 331    .max_gs_threads = 70,
 332    .max_wm_threads = 102,
 333    .max_cs_threads = 70,
 334    .urb = {
 335       .size = 128,
 336       .min_entries = {
 337          [MESA_SHADER_VERTEX]    = 32,
 338          [MESA_SHADER_TESS_EVAL] = 10,
 339       },
 340       .max_entries = {
 341          [MESA_SHADER_VERTEX]    = 640,
 342          [MESA_SHADER_TESS_CTRL] = 64,
 343          [MESA_SHADER_TESS_EVAL] = 384,
 344          [MESA_SHADER_GEOMETRY]  = 256,
 345       },
 346    },
 347    .simulator_id = 9,
 348 };
 349
 350 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 351    HSW_FEATURES, .gt = 2,
 352    .num_slices = 1,
 353    .num_subslices = { 2, },
 354    .num_eu_per_subslice = 10,
 355    .num_thread_per_eu = 7,
 356    .l3_banks = 4,
 357    .max_vs_threads = 280,
 358    .max_tcs_threads = 256,
 359    .max_tes_threads = 280,
 360    .max_gs_threads = 256,
 361    .max_wm_threads = 204,
 362    .max_cs_threads = 70,
 363    .urb = {
 364       .size = 256,
 365       .min_entries = {
 366          [MESA_SHADER_VERTEX]    = 64,
 367          [MESA_SHADER_TESS_EVAL] = 10,
 368       },
 369       .max_entries = {
 370          [MESA_SHADER_VERTEX]    = 1664,
 371          [MESA_SHADER_TESS_CTRL] = 128,
 372          [MESA_SHADER_TESS_EVAL] = 960,
 373          [MESA_SHADER_GEOMETRY]  = 640,
 374       },
 375    },
 376    .simulator_id = 9,
 377 };
 378
 379 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 380    HSW_FEATURES, .gt = 3,
 381    .num_slices = 2,
 382    .num_subslices = { 2, },
 383    .num_eu_per_subslice = 10,
 384    .num_thread_per_eu = 7,
 385    .l3_banks = 8,
 386    .max_vs_threads = 280,
 387    .max_tcs_threads = 256,
 388    .max_tes_threads = 280,
 389    .max_gs_threads = 256,
 390    .max_wm_threads = 408,
 391    .max_cs_threads = 70,
 392    .urb = {
 393       .size = 512,
 394       .min_entries = {
 395          [MESA_SHADER_VERTEX]    = 64,
 396          [MESA_SHADER_TESS_EVAL] = 10,
 397       },
 398       .max_entries = {
 399          [MESA_SHADER_VERTEX]    = 1664,
 400          [MESA_SHADER_TESS_CTRL] = 128,
 401          [MESA_SHADER_TESS_EVAL] = 960,
 402          [MESA_SHADER_GEOMETRY]  = 640,
 403       },
 404    },
 405    .simulator_id = 9,
 406 };
 407
 408 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
 409  * so keep things conservative for now and set has_sample_with_hiz = false.
 410  */
 411 #define GEN8_FEATURES                               \
 412    .gen = 8,                                        \
 413    .has_hiz_and_separate_stencil = true,            \
 414    .has_resource_streamer = true,                   \
 415    .must_use_separate_stencil = true,               \
 416    .has_llc = true,                                 \
 417    .has_sample_with_hiz = false,                    \
 418    .has_pln = true,                                 \
 419    .has_integer_dword_mul = true,                   \
 420    .has_64bit_types = true,                         \
 421    .supports_simd16_3src = true,                    \
 422    .has_surface_tile_offset = true,                 \
 423    .num_thread_per_eu = 7,                          \
 424    .max_vs_threads = 504,                           \
 425    .max_tcs_threads = 504,                          \
 426    .max_tes_threads = 504,                          \
 427    .max_gs_threads = 504,                           \
 428    .max_wm_threads = 384,                           \
 429    .timestamp_frequency = 12500000
 430
 431 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 432    GEN8_FEATURES, .gt = 1,
 433    .is_broadwell = true,
 434    .num_slices = 1,
 435    .num_subslices = { 2, },
 436    .num_eu_per_subslice = 8,
 437    .l3_banks = 2,
 438    .max_cs_threads = 42,
 439    .urb = {
 440       .size = 192,
 441       .min_entries = {
 442          [MESA_SHADER_VERTEX]    = 64,
 443          [MESA_SHADER_TESS_EVAL] = 34,
 444       },
 445       .max_entries = {
 446          [MESA_SHADER_VERTEX]    = 2560,
 447          [MESA_SHADER_TESS_CTRL] = 504,
 448          [MESA_SHADER_TESS_EVAL] = 1536,
 449          /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
 450          [MESA_SHADER_GEOMETRY]  = 690,
 451       },
 452    },
 453    .simulator_id = 11,
 454 };
 455
 456 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 457    GEN8_FEATURES, .gt = 2,
 458    .is_broadwell = true,
 459    .num_slices = 1,
 460    .num_subslices = { 3, },
 461    .num_eu_per_subslice = 8,
 462    .l3_banks = 4,
 463    .max_cs_threads = 56,
 464    .urb = {
 465       .size = 384,
 466       .min_entries = {
 467          [MESA_SHADER_VERTEX]    = 64,
 468          [MESA_SHADER_TESS_EVAL] = 34,
 469       },
 470       .max_entries = {
 471          [MESA_SHADER_VERTEX]    = 2560,
 472          [MESA_SHADER_TESS_CTRL] = 504,
 473          [MESA_SHADER_TESS_EVAL] = 1536,
 474          [MESA_SHADER_GEOMETRY]  = 960,
 475       },
 476    },
 477    .simulator_id = 11,
 478 };
 479
 480 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 481    GEN8_FEATURES, .gt = 3,
 482    .is_broadwell = true,
 483    .num_slices = 2,
 484    .num_subslices = { 3, 3, },
 485    .num_eu_per_subslice = 8,
 486    .l3_banks = 8,
 487    .max_cs_threads = 56,
 488    .urb = {
 489       .size = 384,
 490       .min_entries = {
 491          [MESA_SHADER_VERTEX]    = 64,
 492          [MESA_SHADER_TESS_EVAL] = 34,
 493       },
 494       .max_entries = {
 495          [MESA_SHADER_VERTEX]    = 2560,
 496          [MESA_SHADER_TESS_CTRL] = 504,
 497          [MESA_SHADER_TESS_EVAL] = 1536,
 498          [MESA_SHADER_GEOMETRY]  = 960,
 499       },
 500    },
 501    .simulator_id = 11,
 502 };
 503
 504 static const struct gen_device_info gen_device_info_chv = {
 505    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 506    .has_llc = false,
 507    .has_integer_dword_mul = false,
 508    .num_slices = 1,
 509    .num_subslices = { 2, },
 510    .num_eu_per_subslice = 8,
 511    .l3_banks = 2,
 512    .max_vs_threads = 80,
 513    .max_tcs_threads = 80,
 514    .max_tes_threads = 80,
 515    .max_gs_threads = 80,
 516    .max_wm_threads = 128,
 517    .max_cs_threads = 6 * 7,
 518    .urb = {
 519       .size = 192,
 520       .min_entries = {
 521          [MESA_SHADER_VERTEX]    = 34,
 522          [MESA_SHADER_TESS_EVAL] = 34,
 523       },
 524       .max_entries = {
 525          [MESA_SHADER_VERTEX]    = 640,
 526          [MESA_SHADER_TESS_CTRL] = 80,
 527          [MESA_SHADER_TESS_EVAL] = 384,
 528          [MESA_SHADER_GEOMETRY]  = 256,
 529       },
 530    },
 531    .simulator_id = 13,
 532 };
 533
 534 #define GEN9_HW_INFO                                \
 535    .gen = 9,                                        \
 536    .max_vs_threads = 336,                           \
 537    .max_gs_threads = 336,                           \
 538    .max_tcs_threads = 336,                          \
 539    .max_tes_threads = 336,                          \
 540    .max_cs_threads = 56,                            \
 541    .timestamp_frequency = 12000000,                 \
 542    .urb = {                                         \
 543       .size = 384,                                  \
 544       .min_entries = {                              \
 545          [MESA_SHADER_VERTEX]    = 64,              \
 546          [MESA_SHADER_TESS_EVAL] = 34,              \
 547       },                                            \
 548       .max_entries = {                              \
 549          [MESA_SHADER_VERTEX]    = 1856,            \
 550          [MESA_SHADER_TESS_CTRL] = 672,             \
 551          [MESA_SHADER_TESS_EVAL] = 1120,            \
 552          [MESA_SHADER_GEOMETRY]  = 640,             \
 553       },                                            \
 554    }
 555
 556 #define GEN9_LP_FEATURES                           \
 557    GEN8_FEATURES,                                  \
 558    GEN9_HW_INFO,                                   \
 559    .has_integer_dword_mul = false,                 \
 560    .gt = 1,                                        \
 561    .has_llc = false,                               \
 562    .has_sample_with_hiz = true,                    \
 563    .num_slices = 1,                                \
 564    .num_thread_per_eu = 6,                         \
 565    .max_vs_threads = 112,                          \
 566    .max_tcs_threads = 112,                         \
 567    .max_tes_threads = 112,                         \
 568    .max_gs_threads = 112,                          \
 569    .max_cs_threads = 6 * 6,                        \
 570    .timestamp_frequency = 19200000,                \
 571    .urb = {                                        \
 572       .size = 192,                                 \
 573       .min_entries = {                             \
 574          [MESA_SHADER_VERTEX]    = 34,             \
 575          [MESA_SHADER_TESS_EVAL] = 34,             \
 576       },                                           \
 577       .max_entries = {                             \
 578          [MESA_SHADER_VERTEX]    = 704,            \
 579          [MESA_SHADER_TESS_CTRL] = 256,            \
 580          [MESA_SHADER_TESS_EVAL] = 416,            \
 581          [MESA_SHADER_GEOMETRY]  = 256,            \
 582       },                                           \
 583    }
 584
 585 #define GEN9_LP_FEATURES_3X6                       \
 586    GEN9_LP_FEATURES,                               \
 587    .num_subslices = { 3, },                        \
 588    .num_eu_per_subslice = 6
 589
 590 #define GEN9_LP_FEATURES_2X6                       \
 591    GEN9_LP_FEATURES,                               \
 592    .num_subslices = { 2, },                        \
 593    .num_eu_per_subslice = 6,                       \
 594    .max_vs_threads = 56,                           \
 595    .max_tcs_threads = 56,                          \
 596    .max_tes_threads = 56,                          \
 597    .max_gs_threads = 56,                           \
 598    .max_cs_threads = 6 * 6,                        \
 599    .urb = {                                        \
 600       .size = 128,                                 \
 601       .min_entries = {                             \
 602          [MESA_SHADER_VERTEX]    = 34,             \
 603          [MESA_SHADER_TESS_EVAL] = 34,             \
 604       },                                           \
 605       .max_entries = {                             \
 606          [MESA_SHADER_VERTEX]    = 352,            \
 607          [MESA_SHADER_TESS_CTRL] = 128,            \
 608          [MESA_SHADER_TESS_EVAL] = 208,            \
 609          [MESA_SHADER_GEOMETRY]  = 128,            \
 610       },                                           \
 611    }
 612
 613 #define GEN9_FEATURES                               \
 614    GEN8_FEATURES,                                   \
 615    GEN9_HW_INFO,                                    \
 616    .has_sample_with_hiz = true
 617
 618 static const struct gen_device_info gen_device_info_skl_gt1 = {
 619    GEN9_FEATURES, .gt = 1,
 620    .is_skylake = true,
 621    .num_slices = 1,
 622    .num_subslices = { 2, },
 623    .num_eu_per_subslice = 6,
 624    .l3_banks = 2,
 625    .urb.size = 192,
 626    /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
 627     * leading to some vertices to go missing if we use too much URB.
 628     */
 629    .urb.max_entries[MESA_SHADER_VERTEX] = 928,
 630    .simulator_id = 12,
 631 };
 632
 633 static const struct gen_device_info gen_device_info_skl_gt2 = {
 634    GEN9_FEATURES, .gt = 2,
 635    .is_skylake = true,
 636    .num_slices = 1,
 637    .num_subslices = { 3, },
 638    .num_eu_per_subslice = 8,
 639    .l3_banks = 4,
 640    .simulator_id = 12,
 641 };
 642
 643 static const struct gen_device_info gen_device_info_skl_gt3 = {
 644    GEN9_FEATURES, .gt = 3,
 645    .is_skylake = true,
 646    .num_slices = 2,
 647    .num_subslices = { 3, 3, },
 648    .num_eu_per_subslice = 8,
 649    .l3_banks = 8,
 650    .simulator_id = 12,
 651 };
 652
 653 static const struct gen_device_info gen_device_info_skl_gt4 = {
 654    GEN9_FEATURES, .gt = 4,
 655    .is_skylake = true,
 656    .num_slices = 3,
 657    .num_subslices = { 3, 3, 3, },
 658    .num_eu_per_subslice = 8,
 659    .l3_banks = 12,
 660    /* From the "L3 Allocation and Programming" documentation:
 661     *
 662     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 663     * restriction of the L3 implementation, but of the FF and other clients.
 664     * Therefore, in a GT4 implementation it is possible for the programmed
 665     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 666     * only 1008KB of this will be used."
 667     */
 668    .urb.size = 1008 / 3,
 669    .simulator_id = 12,
 670 };
 671
 672 static const struct gen_device_info gen_device_info_bxt = {
 673    GEN9_LP_FEATURES_3X6,
 674    .is_broxton = true,
 675    .l3_banks = 2,
 676    .simulator_id = 14,
 677 };
 678
 679 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 680    GEN9_LP_FEATURES_2X6,
 681    .is_broxton = true,
 682    .l3_banks = 1,
 683    .simulator_id = 14,
 684 };
 685 /*
 686  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 687  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 688  */
 689
 690 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 691    GEN9_FEATURES,
 692    .is_kabylake = true,
 693    .gt = 1,
 694
 695    .max_cs_threads = 7 * 6,
 696    .urb.size = 192,
 697    .num_slices = 1,
 698    .num_subslices = { 2, },
 699    .num_eu_per_subslice = 6,
 700    .l3_banks = 2,
 701    /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
 702     * leading to some vertices to go missing if we use too much URB.
 703     */
 704    .urb.max_entries[MESA_SHADER_VERTEX] = 928,
 705    .simulator_id = 16,
 706 };
 707
 708 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 709    GEN9_FEATURES,
 710    .is_kabylake = true,
 711    .gt = 1,
 712
 713    .max_cs_threads = 7 * 6,
 714    .num_slices = 1,
 715    .num_subslices = { 3, },
 716    .num_eu_per_subslice = 6,
 717    .l3_banks = 4,
 718    .simulator_id = 16,
 719 };
 720
 721 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 722    GEN9_FEATURES,
 723    .is_kabylake = true,
 724    .gt = 2,
 725
 726    .num_slices = 1,
 727    .num_subslices = { 3, },
 728    .num_eu_per_subslice = 8,
 729    .l3_banks = 4,
 730    .simulator_id = 16,
 731 };
 732
 733 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 734    GEN9_FEATURES,
 735    .is_kabylake = true,
 736    .gt = 3,
 737
 738    .num_slices = 2,
 739    .num_subslices = { 3, 3, },
 740    .num_eu_per_subslice = 8,
 741    .l3_banks = 8,
 742    .simulator_id = 16,
 743 };
 744
 745 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 746    GEN9_FEATURES,
 747    .is_kabylake = true,
 748    .gt = 4,
 749
 750    /*
 751     * From the "L3 Allocation and Programming" documentation:
 752     *
 753     * "URB is limited to 1008KB due to programming restrictions.  This
 754     *  is not a restriction of the L3 implementation, but of the FF and
 755     *  other clients.  Therefore, in a GT4 implementation it is
 756     *  possible for the programmed allocation of the L3 data array to
 757     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 758     *  will be used."
 759     */
 760    .urb.size = 1008 / 3,
 761    .num_slices = 3,
 762    .num_subslices = { 3, 3, 3, },
 763    .num_eu_per_subslice = 8,
 764    .l3_banks = 12,
 765    .simulator_id = 16,
 766 };
 767
 768 static const struct gen_device_info gen_device_info_glk = {
 769    GEN9_LP_FEATURES_3X6,
 770    .is_geminilake = true,
 771    .l3_banks = 2,
 772    .simulator_id = 17,
 773 };
 774
 775 static const struct gen_device_info gen_device_info_glk_2x6 = {
 776    GEN9_LP_FEATURES_2X6,
 777    .is_geminilake = true,
 778    .l3_banks = 2,
 779    .simulator_id = 17,
 780 };
 781
 782 static const struct gen_device_info gen_device_info_cfl_gt1 = {
 783    GEN9_FEATURES,
 784    .is_coffeelake = true,
 785    .gt = 1,
 786
 787    .num_slices = 1,
 788    .num_subslices = { 2, },
 789    .num_eu_per_subslice = 6,
 790    .l3_banks = 2,
 791    .urb.size = 192,
 792    /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
 793     * leading to some vertices to go missing if we use too much URB.
 794     */
 795    .urb.max_entries[MESA_SHADER_VERTEX] = 928,
 796    .simulator_id = 24,
 797 };
 798 static const struct gen_device_info gen_device_info_cfl_gt2 = {
 799    GEN9_FEATURES,
 800    .is_coffeelake = true,
 801    .gt = 2,
 802
 803    .num_slices = 1,
 804    .num_subslices = { 3, },
 805    .num_eu_per_subslice = 8,
 806    .l3_banks = 4,
 807    .simulator_id = 24,
 808 };
 809
 810 static const struct gen_device_info gen_device_info_cfl_gt3 = {
 811    GEN9_FEATURES,
 812    .is_coffeelake = true,
 813    .gt = 3,
 814
 815    .num_slices = 2,
 816    .num_subslices = { 3, 3, },
 817    .num_eu_per_subslice = 8,
 818    .l3_banks = 8,
 819    .simulator_id = 24,
 820 };
 821
 822 #define GEN10_HW_INFO                               \
 823    .gen = 10,                                       \
 824    .num_thread_per_eu = 7,                          \
 825    .max_vs_threads = 728,                           \
 826    .max_gs_threads = 432,                           \
 827    .max_tcs_threads = 432,                          \
 828    .max_tes_threads = 624,                          \
 829    .max_cs_threads = 56,                            \
 830    .timestamp_frequency = 19200000,                 \
 831    .urb = {                                         \
 832       .size = 256,                                  \
 833       .min_entries = {                              \
 834          [MESA_SHADER_VERTEX]    = 64,              \
 835          [MESA_SHADER_TESS_EVAL] = 34,              \
 836       },                                            \
 837       .max_entries = {                              \
 838       [MESA_SHADER_VERTEX]       = 3936,            \
 839       [MESA_SHADER_TESS_CTRL]    = 896,             \
 840       [MESA_SHADER_TESS_EVAL]    = 2064,            \
 841       [MESA_SHADER_GEOMETRY]     = 832,             \
 842       },                                            \
 843    }
 844
 845 #define subslices(args...) { args, }
 846
 847 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
 848    GEN8_FEATURES,                                   \
 849    GEN10_HW_INFO,                                   \
 850    .has_sample_with_hiz = true,                     \
 851    .gt = _gt,                                       \
 852    .num_slices = _slices,                           \
 853    .num_subslices = _subslices,                     \
 854    .num_eu_per_subslice = 8,                        \
 855    .l3_banks = _l3
 856
 857 static const struct gen_device_info gen_device_info_cnl_gt0_5 = {
 858    /* GT0.5 */
 859    GEN10_FEATURES(1, 1, subslices(2), 2),
 860    .is_cannonlake = true,
 861    .simulator_id = 15,
 862 };
 863
 864 static const struct gen_device_info gen_device_info_cnl_gt1 = {
 865    /* GT1 */
 866    GEN10_FEATURES(1, 1, subslices(3), 3),
 867    .is_cannonlake = true,
 868    .simulator_id = 15,
 869 };
 870
 871 static const struct gen_device_info gen_device_info_cnl_gt1_5 = {
 872    /* GT 1.5 */
 873    GEN10_FEATURES(1, 2, subslices(2, 2), 6),
 874    .is_cannonlake = true,
 875    .simulator_id = 15,
 876 };
 877
 878 static const struct gen_device_info gen_device_info_cnl_gt2 = {
 879    /* GT2 */
 880    GEN10_FEATURES(2, 2, subslices(3, 2), 6),
 881    .is_cannonlake = true,
 882    .simulator_id = 15,
 883 };
 884
 885 #define GEN11_HW_INFO                               \
 886    .gen = 11,                                       \
 887    .has_pln = false,                                \
 888    .max_vs_threads = 364,                           \
 889    .max_gs_threads = 224,                           \
 890    .max_tcs_threads = 224,                          \
 891    .max_tes_threads = 364,                          \
 892    .max_cs_threads = 56
 893
 894 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
 895    GEN8_FEATURES,                                     \
 896    GEN11_HW_INFO,                                     \
 897    .has_64bit_types = false,                          \
 898    .has_integer_dword_mul = false,                    \
 899    .has_sample_with_hiz = false,                      \
 900    .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
 901    .num_subslices = _subslices,                       \
 902    .num_eu_per_subslice = 8
 903
 904 #define GEN11_URB_MIN_MAX_ENTRIES                     \
 905    .min_entries = {                                   \
 906       [MESA_SHADER_VERTEX]    = 64,                   \
 907       [MESA_SHADER_TESS_EVAL] = 34,                   \
 908    },                                                 \
 909    .max_entries = {                                   \
 910       [MESA_SHADER_VERTEX]    = 2384,                 \
 911       [MESA_SHADER_TESS_CTRL] = 1032,                 \
 912       [MESA_SHADER_TESS_EVAL] = 2384,                 \
 913       [MESA_SHADER_GEOMETRY]  = 1032,                 \
 914    }
 915
 916 static const struct gen_device_info gen_device_info_icl_gt2 = {
 917    GEN11_FEATURES(2, 1, subslices(8), 8),
 918    .urb = {
 919       .size = 1024,
 920       GEN11_URB_MIN_MAX_ENTRIES,
 921    },
 922    .simulator_id = 19,
 923 };
 924
 925 static const struct gen_device_info gen_device_info_icl_gt1_5 = {
 926    GEN11_FEATURES(1, 1, subslices(6), 6),
 927    .urb = {
 928       .size = 768,
 929       GEN11_URB_MIN_MAX_ENTRIES,
 930    },
 931    .simulator_id = 19,
 932 };
 933
 934 static const struct gen_device_info gen_device_info_icl_gt1 = {
 935    GEN11_FEATURES(1, 1, subslices(4), 6),
 936    .urb = {
 937       .size = 768,
 938       GEN11_URB_MIN_MAX_ENTRIES,
 939    },
 940    .simulator_id = 19,
 941 };
 942
 943 static const struct gen_device_info gen_device_info_icl_gt0_5 = {
 944    GEN11_FEATURES(1, 1, subslices(1), 6),
 945    .urb = {
 946       .size = 768,
 947       GEN11_URB_MIN_MAX_ENTRIES,
 948    },
 949    .simulator_id = 19,
 950 };
 951
 952 static const struct gen_device_info gen_device_info_ehl_7 = {
 953    GEN11_FEATURES(1, 1, subslices(4), 4),
 954    .is_elkhartlake = true,
 955    .urb = {
 956       .size = 512,
 957       .min_entries = {
 958          [MESA_SHADER_VERTEX]    = 64,
 959          [MESA_SHADER_TESS_EVAL] = 34,
 960       },
 961       .max_entries = {
 962          [MESA_SHADER_VERTEX]    = 2384,
 963          [MESA_SHADER_TESS_CTRL] = 1032,
 964          [MESA_SHADER_TESS_EVAL] = 2384,
 965          [MESA_SHADER_GEOMETRY]  = 1032,
 966       },
 967    },
 968    .disable_ccs_repack = true,
 969    .simulator_id = 28,
 970 };
 971
 972 static const struct gen_device_info gen_device_info_ehl_6 = {
 973    GEN11_FEATURES(1, 1, subslices(4), 4),
 974    .is_elkhartlake = true,
 975    .urb = {
 976       .size = 512,
 977       .min_entries = {
 978          [MESA_SHADER_VERTEX]    = 64,
 979          [MESA_SHADER_TESS_EVAL] = 34,
 980       },
 981       .max_entries = {
 982          [MESA_SHADER_VERTEX]    = 2384,
 983          [MESA_SHADER_TESS_CTRL] = 1032,
 984          [MESA_SHADER_TESS_EVAL] = 2384,
 985          [MESA_SHADER_GEOMETRY]  = 1032,
 986       },
 987    },
 988    .disable_ccs_repack = true,
 989    .num_eu_per_subslice = 6,
 990    .simulator_id = 28,
 991 };
 992
 993 static const struct gen_device_info gen_device_info_ehl_5 = {
 994    GEN11_FEATURES(1, 1, subslices(4), 4),
 995    .is_elkhartlake = true,
 996    .urb = {
 997       .size = 512,
 998       .min_entries = {
 999          [MESA_SHADER_VERTEX]    = 64,
1000          [MESA_SHADER_TESS_EVAL] = 34,
1001       },
1002       .max_entries = {
1003          [MESA_SHADER_VERTEX]    = 2384,
1004          [MESA_SHADER_TESS_CTRL] = 1032,
1005          [MESA_SHADER_TESS_EVAL] = 2384,
1006          [MESA_SHADER_GEOMETRY]  = 1032,
1007       },
1008    },
1009    .disable_ccs_repack = true,
1010    .num_eu_per_subslice = 4,
1011    .simulator_id = 28,
1012 };
1013
1014 static const struct gen_device_info gen_device_info_ehl_4 = {
1015    GEN11_FEATURES(1, 1, subslices(2), 4),
1016    .is_elkhartlake = true,
1017    .urb = {
1018       .size = 512,
1019       .min_entries = {
1020          [MESA_SHADER_VERTEX]    = 64,
1021          [MESA_SHADER_TESS_EVAL] = 34,
1022       },
1023       .max_entries = {
1024          [MESA_SHADER_VERTEX]    = 2384,
1025          [MESA_SHADER_TESS_CTRL] = 1032,
1026          [MESA_SHADER_TESS_EVAL] = 2384,
1027          [MESA_SHADER_GEOMETRY]  = 1032,
1028       },
1029    },
1030    .disable_ccs_repack = true,
1031    .num_eu_per_subslice =4,
1032    .simulator_id = 28,
1033 };
1034
1035 #define GEN12_URB_MIN_MAX_ENTRIES                   \
1036    .min_entries = {                                 \
1037       [MESA_SHADER_VERTEX]    = 64,                 \
1038       [MESA_SHADER_TESS_EVAL] = 34,                 \
1039    },                                               \
1040    .max_entries = {                                 \
1041       [MESA_SHADER_VERTEX]    = 3576,               \
1042       [MESA_SHADER_TESS_CTRL] = 1548,               \
1043       [MESA_SHADER_TESS_EVAL] = 3576,               \
1044       [MESA_SHADER_GEOMETRY]  = 1548,               \
1045    }
1046
1047 #define GEN12_HW_INFO                               \
1048    .gen = 12,                                       \
1049    .has_pln = false,                                \
1050    .has_sample_with_hiz = false,                    \
1051    .has_aux_map = true,                             \
1052    .max_vs_threads = 546,                           \
1053    .max_gs_threads = 336,                           \
1054    .max_tcs_threads = 336,                          \
1055    .max_tes_threads = 546,                          \
1056    .max_cs_threads = 112, /* threads per DSS */     \
1057    .urb = {                                         \
1058       GEN12_URB_MIN_MAX_ENTRIES,                    \
1059    }
1060
1061 #define GEN12_FEATURES(_gt, _slices, _dual_subslices, _l3)      \
1062    GEN8_FEATURES,                                               \
1063    GEN12_HW_INFO,                                               \
1064    .has_64bit_types = false,                                    \
1065    .has_integer_dword_mul = false,                              \
1066    .gt = _gt, .num_slices = _slices, .l3_banks = _l3,           \
1067    .simulator_id = 22,                                          \
1068    .urb.size = (_gt) == 1 ? 512 : 1024,                         \
1069    .num_subslices = _dual_subslices,                            \
1070    .num_eu_per_subslice = 16
1071
1072 #define dual_subslices(args...) { args, }
1073
1074 static const struct gen_device_info gen_device_info_tgl_gt1 = {
1075    GEN12_FEATURES(1, 1, dual_subslices(2), 8),
1076 };
1077
1078 static const struct gen_device_info gen_device_info_tgl_gt2 = {
1079    GEN12_FEATURES(2, 1, dual_subslices(6), 8),
1080 };
1081
1082 static void
1083 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1084                             unsigned slice,
1085                             unsigned subslice,
1086                             unsigned eu_mask)
1087 {
1088    unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1089       subslice * devinfo->eu_subslice_stride;
1090
1091    for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1092       devinfo->eu_masks[subslice_offset + b_eu] =
1093          (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1094    }
1095 }
1096
1097 /* Generate slice/subslice/eu masks from number of
1098  * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1099  * structure.
1100  *
1101  * These can be overridden with values reported by the kernel either from
1102  * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1103  * through the i915 query uapi.
1104  */
1105 static void
1106 fill_masks(struct gen_device_info *devinfo)
1107 {
1108    devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1109
1110    /* Subslice masks */
1111    unsigned max_subslices = 0;
1112    for (int s = 0; s < devinfo->num_slices; s++)
1113       max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1114    devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1115
1116    for (int s = 0; s < devinfo->num_slices; s++) {
1117       devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1118          (1U << devinfo->num_subslices[s]) - 1;
1119    }
1120
1121    /* EU masks */
1122    devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1123    devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1124
1125    for (int s = 0; s < devinfo->num_slices; s++) {
1126       for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1127          gen_device_info_set_eu_mask(devinfo, s, ss,
1128                                      (1U << devinfo->num_eu_per_subslice) - 1);
1129       }
1130    }
1131 }
1132
1133 static void
1134 reset_masks(struct gen_device_info *devinfo)
1135 {
1136    devinfo->subslice_slice_stride = 0;
1137    devinfo->eu_subslice_stride = 0;
1138    devinfo->eu_slice_stride = 0;
1139
1140    devinfo->num_slices = 0;
1141    devinfo->num_eu_per_subslice = 0;
1142    memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1143
1144    memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1145    memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1146    memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1147    memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1148 }
1149
1150 static void
1151 update_from_topology(struct gen_device_info *devinfo,
1152                      const struct drm_i915_query_topology_info *topology)
1153 {
1154    reset_masks(devinfo);
1155
1156    devinfo->subslice_slice_stride = topology->subslice_stride;
1157
1158    devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1159    devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1160
1161    assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1162    memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1163    devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1164
1165    uint32_t subslice_mask_len =
1166       topology->max_slices * topology->subslice_stride;
1167    assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1168    memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1169           subslice_mask_len);
1170
1171    uint32_t n_subslices = 0;
1172    for (int s = 0; s < topology->max_slices; s++) {
1173       if ((devinfo->slice_masks & (1 << s)) == 0)
1174          continue;
1175
1176       for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1177          devinfo->num_subslices[s] +=
1178             __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1179       }
1180       n_subslices += devinfo->num_subslices[s];
1181    }
1182    assert(n_subslices > 0);
1183
1184    if (devinfo->gen == 11) {
1185       /* On ICL we only have one slice */
1186       assert(devinfo->slice_masks == 1);
1187
1188       /* Count the number of subslices on each pixel pipe. Assume that
1189        * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1190        */
1191       unsigned subslices = devinfo->subslice_masks[0];
1192       unsigned ss = 0;
1193       while (subslices > 0) {
1194          if (subslices & 1)
1195             devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
1196          subslices >>= 1;
1197          ss++;
1198       }
1199    }
1200
1201    uint32_t eu_mask_len =
1202       topology->eu_stride * topology->max_subslices * topology->max_slices;
1203    assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1204    memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1205
1206    uint32_t n_eus = 0;
1207    for (int b = 0; b < eu_mask_len; b++)
1208       n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1209
1210    devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1211 }
1212
1213 static bool
1214 update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask,
1215                   uint32_t subslice_mask, uint32_t n_eus)
1216 {
1217    struct drm_i915_query_topology_info *topology;
1218
1219    assert((slice_mask & 0xff) == slice_mask);
1220
1221    size_t data_length = 100;
1222
1223    topology = calloc(1, sizeof(*topology) + data_length);
1224    if (!topology)
1225       return false;
1226
1227    topology->max_slices = util_last_bit(slice_mask);
1228    topology->max_subslices = util_last_bit(subslice_mask);
1229
1230    topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1231    topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1232
1233    uint32_t n_subslices = __builtin_popcount(slice_mask) *
1234       __builtin_popcount(subslice_mask);
1235    uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1236    uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1237
1238    topology->eu_offset = topology->subslice_offset +
1239       DIV_ROUND_UP(topology->max_subslices, 8);
1240    topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1241
1242    /* Set slice mask in topology */
1243    for (int b = 0; b < topology->subslice_offset; b++)
1244       topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1245
1246    for (int s = 0; s < topology->max_slices; s++) {
1247
1248       /* Set subslice mask in topology */
1249       for (int b = 0; b < topology->subslice_stride; b++) {
1250          int subslice_offset = topology->subslice_offset +
1251             s * topology->subslice_stride + b;
1252
1253          topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1254       }
1255
1256       /* Set eu mask in topology */
1257       for (int ss = 0; ss < topology->max_subslices; ss++) {
1258          for (int b = 0; b < topology->eu_stride; b++) {
1259             int eu_offset = topology->eu_offset +
1260                (s * topology->max_subslices + ss) * topology->eu_stride + b;
1261
1262             topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1263          }
1264       }
1265    }
1266
1267    update_from_topology(devinfo, topology);
1268    free(topology);
1269
1270    return true;
1271 }
1272
1273 static bool
1274 getparam(int fd, uint32_t param, int *value)
1275 {
1276    int tmp;
1277
1278    struct drm_i915_getparam gp = {
1279       .param = param,
1280       .value = &tmp,
1281    };
1282
1283    int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
1284    if (ret != 0)
1285       return false;
1286
1287    *value = tmp;
1288    return true;
1289 }
1290
1291 bool
1292 gen_get_device_info_from_pci_id(int pci_id,
1293                                 struct gen_device_info *devinfo)
1294 {
1295    switch (pci_id) {
1296 #undef CHIPSET
1297 #define CHIPSET(id, family, fam_str, name) \
1298       case id: *devinfo = gen_device_info_##family; break;
1299 #include "pci_ids/i965_pci_ids.h"
1300 #include "pci_ids/iris_pci_ids.h"
1301    default:
1302       fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id);
1303       return false;
1304    }
1305
1306    fill_masks(devinfo);
1307
1308    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1309     *
1310     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
1311     *  allocate scratch space enough so that each slice has 4 slices allowed."
1312     *
1313     * The equivalent internal documentation says that this programming note
1314     * applies to all Gen9+ platforms.
1315     *
1316     * The hardware typically calculates the scratch space pointer by taking
1317     * the base address, and adding per-thread-scratch-space * thread ID.
1318     * Extra padding can be necessary depending how the thread IDs are
1319     * calculated for a particular shader stage.
1320     */
1321
1322    switch(devinfo->gen) {
1323    case 9:
1324    case 10:
1325       devinfo->max_wm_threads = 64 /* threads-per-PSD */
1326                               * devinfo->num_slices
1327                               * 4; /* effective subslices per slice */
1328       break;
1329    case 11:
1330    case 12:
1331       devinfo->max_wm_threads = 128 /* threads-per-PSD */
1332                               * devinfo->num_slices
1333                               * 8; /* subslices per slice */
1334       break;
1335    default:
1336       assert(devinfo->gen < 9);
1337       break;
1338    }
1339
1340    assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1341
1342    devinfo->chipset_id = pci_id;
1343    return true;
1344 }
1345
1346 const char *
1347 gen_get_device_name(int devid)
1348 {
1349    switch (devid) {
1350 #undef CHIPSET
1351 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1352 #include "pci_ids/i965_pci_ids.h"
1353 #include "pci_ids/iris_pci_ids.h"
1354    default:
1355       return NULL;
1356    }
1357 }
1358
1359 /**
1360  * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1361  * (kernel 4.13+)
1362  */
1363 static bool
1364 getparam_topology(struct gen_device_info *devinfo, int fd)
1365 {
1366    int slice_mask = 0;
1367    if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
1368       return false;
1369
1370    int n_eus;
1371    if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
1372       return false;
1373
1374    int subslice_mask = 0;
1375    if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
1376       return false;
1377
1378    return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1379 }
1380
1381 /**
1382  * preferred API for updating the topology in devinfo (kernel 4.17+)
1383  */
1384 static bool
1385 query_topology(struct gen_device_info *devinfo, int fd)
1386 {
1387    struct drm_i915_query_item item = {
1388       .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
1389    };
1390    struct drm_i915_query query = {
1391       .num_items = 1,
1392       .items_ptr = (uintptr_t) &item,
1393    };
1394
1395    if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
1396       return false;
1397
1398    if (item.length < 0)
1399       return false;
1400
1401    struct drm_i915_query_topology_info *topo_info =
1402       (struct drm_i915_query_topology_info *) calloc(1, item.length);
1403    item.data_ptr = (uintptr_t) topo_info;
1404
1405    if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
1406        item.length <= 0)
1407       return false;
1408
1409    update_from_topology(devinfo, topo_info);
1410
1411    free(topo_info);
1412
1413    return true;
1414
1415 }
1416
1417 bool
1418 gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
1419 {
1420    int devid = get_pci_device_id_override();
1421    if (devid > 0) {
1422       if (!gen_get_device_info_from_pci_id(devid, devinfo))
1423          return false;
1424       devinfo->no_hw = true;
1425    } else {
1426       /* query the device id */
1427       if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
1428          return false;
1429       if (!gen_get_device_info_from_pci_id(devid, devinfo))
1430          return false;
1431       devinfo->no_hw = false;
1432    }
1433
1434    /* remaining initializion queries the kernel for device info */
1435    if (devinfo->no_hw)
1436       return true;
1437
1438    int timestamp_frequency;
1439    if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1440                 &timestamp_frequency))
1441       devinfo->timestamp_frequency = timestamp_frequency;
1442    else if (devinfo->gen >= 10)
1443       /* gen10 and later requires the timestamp_frequency to be updated */
1444       return false;
1445
1446    if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
1447        return false;
1448
1449    if (!query_topology(devinfo, fd)) {
1450       if (devinfo->gen >= 10) {
1451          /* topology uAPI required for CNL+ (kernel 4.17+) */
1452          return false;
1453       }
1454
1455       /* else use the kernel 4.13+ api for gen8+.  For older kernels, topology
1456        * will be wrong, affecting GPU metrics. In this case, fail silently.
1457        */
1458       getparam_topology(devinfo, fd);
1459    }
1460
1461    return true;
1462 }