src/intel/dev/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdbool.h>
  26 #include <stdio.h>
  27 #include <stdlib.h>
  28 #include <string.h>
  29 #include <unistd.h>
  30 #include "gen_device_info.h"
  31 #include "compiler/shader_enums.h"
  32 #include "intel/common/gen_gem.h"
  33 #include "util/bitscan.h"
  34 #include "util/macros.h"
  35
  36 #include "drm-uapi/i915_drm.h"
  37
  38 /**
  39  * Get the PCI ID for the device name.
  40  *
  41  * Returns -1 if the device is not known.
  42  */
  43 int
  44 gen_device_name_to_pci_device_id(const char *name)
  45 {
  46    static const struct {
  47       const char *name;
  48       int pci_id;
  49    } name_map[] = {
  50       { "brw", 0x2a02 },
  51       { "g4x", 0x2a42 },
  52       { "ilk", 0x0042 },
  53       { "snb", 0x0126 },
  54       { "ivb", 0x016a },
  55       { "hsw", 0x0d2e },
  56       { "byt", 0x0f33 },
  57       { "bdw", 0x162e },
  58       { "chv", 0x22B3 },
  59       { "skl", 0x1912 },
  60       { "bxt", 0x5A85 },
  61       { "kbl", 0x5912 },
  62       { "aml", 0x591C },
  63       { "glk", 0x3185 },
  64       { "cfl", 0x3E9B },
  65       { "whl", 0x3EA1 },
  66       { "cml", 0x9b41 },
  67       { "cnl", 0x5a52 },
  68       { "icl", 0x8a52 },
  69    };
  70
  71    for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
  72       if (!strcmp(name_map[i].name, name))
  73          return name_map[i].pci_id;
  74    }
  75
  76    return -1;
  77 }
  78
  79 /**
  80  * Get the overridden PCI ID for the device. This is set with the
  81  * INTEL_DEVID_OVERRIDE environment variable.
  82  *
  83  * Returns -1 if the override is not set.
  84  */
  85 static int
  86 get_pci_device_id_override(void)
  87 {
  88    if (geteuid() == getuid()) {
  89       const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
  90       if (devid_override) {
  91          const int id = gen_device_name_to_pci_device_id(devid_override);
  92          return id >= 0 ? id : strtol(devid_override, NULL, 0);
  93       }
  94    }
  95
  96    return -1;
  97 }
  98
  99 static const struct gen_device_info gen_device_info_i965 = {
 100    .gen = 4,
 101    .has_negative_rhw_bug = true,
 102    .num_slices = 1,
 103    .num_subslices = { 1, },
 104    .num_eu_per_subslice = 8,
 105    .num_thread_per_eu = 4,
 106    .max_vs_threads = 16,
 107    .max_gs_threads = 2,
 108    .max_wm_threads = 8 * 4,
 109    .urb = {
 110       .size = 256,
 111    },
 112    .timestamp_frequency = 12500000,
 113    .simulator_id = -1,
 114 };
 115
 116 static const struct gen_device_info gen_device_info_g4x = {
 117    .gen = 4,
 118    .has_pln = true,
 119    .has_compr4 = true,
 120    .has_surface_tile_offset = true,
 121    .is_g4x = true,
 122    .num_slices = 1,
 123    .num_subslices = { 1, },
 124    .num_eu_per_subslice = 10,
 125    .num_thread_per_eu = 5,
 126    .max_vs_threads = 32,
 127    .max_gs_threads = 2,
 128    .max_wm_threads = 10 * 5,
 129    .urb = {
 130       .size = 384,
 131    },
 132    .timestamp_frequency = 12500000,
 133    .simulator_id = -1,
 134 };
 135
 136 static const struct gen_device_info gen_device_info_ilk = {
 137    .gen = 5,
 138    .has_pln = true,
 139    .has_compr4 = true,
 140    .has_surface_tile_offset = true,
 141    .num_slices = 1,
 142    .num_subslices = { 1, },
 143    .num_eu_per_subslice = 12,
 144    .num_thread_per_eu = 6,
 145    .max_vs_threads = 72,
 146    .max_gs_threads = 32,
 147    .max_wm_threads = 12 * 6,
 148    .urb = {
 149       .size = 1024,
 150    },
 151    .timestamp_frequency = 12500000,
 152    .simulator_id = -1,
 153 };
 154
 155 static const struct gen_device_info gen_device_info_snb_gt1 = {
 156    .gen = 6,
 157    .gt = 1,
 158    .has_hiz_and_separate_stencil = true,
 159    .has_llc = true,
 160    .has_pln = true,
 161    .has_surface_tile_offset = true,
 162    .needs_unlit_centroid_workaround = true,
 163    .num_slices = 1,
 164    .num_subslices = { 1, },
 165    .num_eu_per_subslice = 6,
 166    .num_thread_per_eu = 6, /* Not confirmed */
 167    .max_vs_threads = 24,
 168    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
 169    .max_wm_threads = 40,
 170    .urb = {
 171       .size = 32,
 172       .min_entries = {
 173          [MESA_SHADER_VERTEX]   = 24,
 174       },
 175       .max_entries = {
 176          [MESA_SHADER_VERTEX]   = 256,
 177          [MESA_SHADER_GEOMETRY] = 256,
 178       },
 179    },
 180    .timestamp_frequency = 12500000,
 181    .simulator_id = -1,
 182 };
 183
 184 static const struct gen_device_info gen_device_info_snb_gt2 = {
 185    .gen = 6,
 186    .gt = 2,
 187    .has_hiz_and_separate_stencil = true,
 188    .has_llc = true,
 189    .has_pln = true,
 190    .has_surface_tile_offset = true,
 191    .needs_unlit_centroid_workaround = true,
 192    .num_slices = 1,
 193    .num_subslices = { 1, },
 194    .num_eu_per_subslice = 12,
 195    .num_thread_per_eu = 6, /* Not confirmed */
 196    .max_vs_threads = 60,
 197    .max_gs_threads = 60,
 198    .max_wm_threads = 80,
 199    .urb = {
 200       .size = 64,
 201       .min_entries = {
 202          [MESA_SHADER_VERTEX]   = 24,
 203       },
 204       .max_entries = {
 205          [MESA_SHADER_VERTEX]   = 256,
 206          [MESA_SHADER_GEOMETRY] = 256,
 207       },
 208    },
 209    .timestamp_frequency = 12500000,
 210    .simulator_id = -1,
 211 };
 212
 213 #define GEN7_FEATURES                               \
 214    .gen = 7,                                        \
 215    .has_hiz_and_separate_stencil = true,            \
 216    .must_use_separate_stencil = true,               \
 217    .has_llc = true,                                 \
 218    .has_pln = true,                                 \
 219    .has_64bit_types = true,                         \
 220    .has_surface_tile_offset = true,                 \
 221    .timestamp_frequency = 12500000
 222
 223 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 224    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 225    .num_slices = 1,
 226    .num_subslices = { 1, },
 227    .num_eu_per_subslice = 6,
 228    .num_thread_per_eu = 6,
 229    .l3_banks = 2,
 230    .max_vs_threads = 36,
 231    .max_tcs_threads = 36,
 232    .max_tes_threads = 36,
 233    .max_gs_threads = 36,
 234    .max_wm_threads = 48,
 235    .max_cs_threads = 36,
 236    .urb = {
 237       .size = 128,
 238       .min_entries = {
 239          [MESA_SHADER_VERTEX]    = 32,
 240          [MESA_SHADER_TESS_EVAL] = 10,
 241       },
 242       .max_entries = {
 243          [MESA_SHADER_VERTEX]    = 512,
 244          [MESA_SHADER_TESS_CTRL] = 32,
 245          [MESA_SHADER_TESS_EVAL] = 288,
 246          [MESA_SHADER_GEOMETRY]  = 192,
 247       },
 248    },
 249    .simulator_id = 7,
 250 };
 251
 252 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 253    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 254    .num_slices = 1,
 255    .num_subslices = { 1, },
 256    .num_eu_per_subslice = 12,
 257    .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
 258                             * @max_wm_threads ... */
 259    .l3_banks = 4,
 260    .max_vs_threads = 128,
 261    .max_tcs_threads = 128,
 262    .max_tes_threads = 128,
 263    .max_gs_threads = 128,
 264    .max_wm_threads = 172,
 265    .max_cs_threads = 64,
 266    .urb = {
 267       .size = 256,
 268       .min_entries = {
 269          [MESA_SHADER_VERTEX]    = 32,
 270          [MESA_SHADER_TESS_EVAL] = 10,
 271       },
 272       .max_entries = {
 273          [MESA_SHADER_VERTEX]    = 704,
 274          [MESA_SHADER_TESS_CTRL] = 64,
 275          [MESA_SHADER_TESS_EVAL] = 448,
 276          [MESA_SHADER_GEOMETRY]  = 320,
 277       },
 278    },
 279    .simulator_id = 7,
 280 };
 281
 282 static const struct gen_device_info gen_device_info_byt = {
 283    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 284    .num_slices = 1,
 285    .num_subslices = { 1, },
 286    .num_eu_per_subslice = 4,
 287    .num_thread_per_eu = 8,
 288    .l3_banks = 1,
 289    .has_llc = false,
 290    .max_vs_threads = 36,
 291    .max_tcs_threads = 36,
 292    .max_tes_threads = 36,
 293    .max_gs_threads = 36,
 294    .max_wm_threads = 48,
 295    .max_cs_threads = 32,
 296    .urb = {
 297       .size = 128,
 298       .min_entries = {
 299          [MESA_SHADER_VERTEX]    = 32,
 300          [MESA_SHADER_TESS_EVAL] = 10,
 301       },
 302       .max_entries = {
 303          [MESA_SHADER_VERTEX]    = 512,
 304          [MESA_SHADER_TESS_CTRL] = 32,
 305          [MESA_SHADER_TESS_EVAL] = 288,
 306          [MESA_SHADER_GEOMETRY]  = 192,
 307       },
 308    },
 309    .simulator_id = 10,
 310 };
 311
 312 #define HSW_FEATURES             \
 313    GEN7_FEATURES,                \
 314    .is_haswell = true,           \
 315    .supports_simd16_3src = true, \
 316    .has_resource_streamer = true
 317
 318 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 319    HSW_FEATURES, .gt = 1,
 320    .num_slices = 1,
 321    .num_subslices = { 1, },
 322    .num_eu_per_subslice = 10,
 323    .num_thread_per_eu = 7,
 324    .l3_banks = 2,
 325    .max_vs_threads = 70,
 326    .max_tcs_threads = 70,
 327    .max_tes_threads = 70,
 328    .max_gs_threads = 70,
 329    .max_wm_threads = 102,
 330    .max_cs_threads = 70,
 331    .urb = {
 332       .size = 128,
 333       .min_entries = {
 334          [MESA_SHADER_VERTEX]    = 32,
 335          [MESA_SHADER_TESS_EVAL] = 10,
 336       },
 337       .max_entries = {
 338          [MESA_SHADER_VERTEX]    = 640,
 339          [MESA_SHADER_TESS_CTRL] = 64,
 340          [MESA_SHADER_TESS_EVAL] = 384,
 341          [MESA_SHADER_GEOMETRY]  = 256,
 342       },
 343    },
 344    .simulator_id = 9,
 345 };
 346
 347 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 348    HSW_FEATURES, .gt = 2,
 349    .num_slices = 1,
 350    .num_subslices = { 2, },
 351    .num_eu_per_subslice = 10,
 352    .num_thread_per_eu = 7,
 353    .l3_banks = 4,
 354    .max_vs_threads = 280,
 355    .max_tcs_threads = 256,
 356    .max_tes_threads = 280,
 357    .max_gs_threads = 256,
 358    .max_wm_threads = 204,
 359    .max_cs_threads = 70,
 360    .urb = {
 361       .size = 256,
 362       .min_entries = {
 363          [MESA_SHADER_VERTEX]    = 64,
 364          [MESA_SHADER_TESS_EVAL] = 10,
 365       },
 366       .max_entries = {
 367          [MESA_SHADER_VERTEX]    = 1664,
 368          [MESA_SHADER_TESS_CTRL] = 128,
 369          [MESA_SHADER_TESS_EVAL] = 960,
 370          [MESA_SHADER_GEOMETRY]  = 640,
 371       },
 372    },
 373    .simulator_id = 9,
 374 };
 375
 376 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 377    HSW_FEATURES, .gt = 3,
 378    .num_slices = 2,
 379    .num_subslices = { 2, },
 380    .num_eu_per_subslice = 10,
 381    .num_thread_per_eu = 7,
 382    .l3_banks = 8,
 383    .max_vs_threads = 280,
 384    .max_tcs_threads = 256,
 385    .max_tes_threads = 280,
 386    .max_gs_threads = 256,
 387    .max_wm_threads = 408,
 388    .max_cs_threads = 70,
 389    .urb = {
 390       .size = 512,
 391       .min_entries = {
 392          [MESA_SHADER_VERTEX]    = 64,
 393          [MESA_SHADER_TESS_EVAL] = 10,
 394       },
 395       .max_entries = {
 396          [MESA_SHADER_VERTEX]    = 1664,
 397          [MESA_SHADER_TESS_CTRL] = 128,
 398          [MESA_SHADER_TESS_EVAL] = 960,
 399          [MESA_SHADER_GEOMETRY]  = 640,
 400       },
 401    },
 402    .simulator_id = 9,
 403 };
 404
 405 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
 406  * so keep things conservative for now and set has_sample_with_hiz = false.
 407  */
 408 #define GEN8_FEATURES                               \
 409    .gen = 8,                                        \
 410    .has_hiz_and_separate_stencil = true,            \
 411    .has_resource_streamer = true,                   \
 412    .must_use_separate_stencil = true,               \
 413    .has_llc = true,                                 \
 414    .has_sample_with_hiz = false,                    \
 415    .has_pln = true,                                 \
 416    .has_integer_dword_mul = true,                   \
 417    .has_64bit_types = true,                         \
 418    .supports_simd16_3src = true,                    \
 419    .has_surface_tile_offset = true,                 \
 420    .num_thread_per_eu = 7,                          \
 421    .max_vs_threads = 504,                           \
 422    .max_tcs_threads = 504,                          \
 423    .max_tes_threads = 504,                          \
 424    .max_gs_threads = 504,                           \
 425    .max_wm_threads = 384,                           \
 426    .timestamp_frequency = 12500000
 427
 428 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 429    GEN8_FEATURES, .gt = 1,
 430    .is_broadwell = true,
 431    .num_slices = 1,
 432    .num_subslices = { 2, },
 433    .num_eu_per_subslice = 8,
 434    .l3_banks = 2,
 435    .max_cs_threads = 42,
 436    .urb = {
 437       .size = 192,
 438       .min_entries = {
 439          [MESA_SHADER_VERTEX]    = 64,
 440          [MESA_SHADER_TESS_EVAL] = 34,
 441       },
 442       .max_entries = {
 443          [MESA_SHADER_VERTEX]    = 2560,
 444          [MESA_SHADER_TESS_CTRL] = 504,
 445          [MESA_SHADER_TESS_EVAL] = 1536,
 446          [MESA_SHADER_GEOMETRY]  = 960,
 447       },
 448    },
 449    .simulator_id = 11,
 450 };
 451
 452 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 453    GEN8_FEATURES, .gt = 2,
 454    .is_broadwell = true,
 455    .num_slices = 1,
 456    .num_subslices = { 3, },
 457    .num_eu_per_subslice = 8,
 458    .l3_banks = 4,
 459    .max_cs_threads = 56,
 460    .urb = {
 461       .size = 384,
 462       .min_entries = {
 463          [MESA_SHADER_VERTEX]    = 64,
 464          [MESA_SHADER_TESS_EVAL] = 34,
 465       },
 466       .max_entries = {
 467          [MESA_SHADER_VERTEX]    = 2560,
 468          [MESA_SHADER_TESS_CTRL] = 504,
 469          [MESA_SHADER_TESS_EVAL] = 1536,
 470          [MESA_SHADER_GEOMETRY]  = 960,
 471       },
 472    },
 473    .simulator_id = 11,
 474 };
 475
 476 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 477    GEN8_FEATURES, .gt = 3,
 478    .is_broadwell = true,
 479    .num_slices = 2,
 480    .num_subslices = { 3, 3, },
 481    .num_eu_per_subslice = 8,
 482    .l3_banks = 8,
 483    .max_cs_threads = 56,
 484    .urb = {
 485       .size = 384,
 486       .min_entries = {
 487          [MESA_SHADER_VERTEX]    = 64,
 488          [MESA_SHADER_TESS_EVAL] = 34,
 489       },
 490       .max_entries = {
 491          [MESA_SHADER_VERTEX]    = 2560,
 492          [MESA_SHADER_TESS_CTRL] = 504,
 493          [MESA_SHADER_TESS_EVAL] = 1536,
 494          [MESA_SHADER_GEOMETRY]  = 960,
 495       },
 496    },
 497    .simulator_id = 11,
 498 };
 499
 500 static const struct gen_device_info gen_device_info_chv = {
 501    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 502    .has_llc = false,
 503    .has_integer_dword_mul = false,
 504    .num_slices = 1,
 505    .num_subslices = { 2, },
 506    .num_eu_per_subslice = 8,
 507    .l3_banks = 2,
 508    .max_vs_threads = 80,
 509    .max_tcs_threads = 80,
 510    .max_tes_threads = 80,
 511    .max_gs_threads = 80,
 512    .max_wm_threads = 128,
 513    .max_cs_threads = 6 * 7,
 514    .urb = {
 515       .size = 192,
 516       .min_entries = {
 517          [MESA_SHADER_VERTEX]    = 34,
 518          [MESA_SHADER_TESS_EVAL] = 34,
 519       },
 520       .max_entries = {
 521          [MESA_SHADER_VERTEX]    = 640,
 522          [MESA_SHADER_TESS_CTRL] = 80,
 523          [MESA_SHADER_TESS_EVAL] = 384,
 524          [MESA_SHADER_GEOMETRY]  = 256,
 525       },
 526    },
 527    .simulator_id = 13,
 528 };
 529
 530 #define GEN9_HW_INFO                                \
 531    .gen = 9,                                        \
 532    .max_vs_threads = 336,                           \
 533    .max_gs_threads = 336,                           \
 534    .max_tcs_threads = 336,                          \
 535    .max_tes_threads = 336,                          \
 536    .max_cs_threads = 56,                            \
 537    .timestamp_frequency = 12000000,                 \
 538    .urb = {                                         \
 539       .size = 384,                                  \
 540       .min_entries = {                              \
 541          [MESA_SHADER_VERTEX]    = 64,              \
 542          [MESA_SHADER_TESS_EVAL] = 34,              \
 543       },                                            \
 544       .max_entries = {                              \
 545          [MESA_SHADER_VERTEX]    = 1856,            \
 546          [MESA_SHADER_TESS_CTRL] = 672,             \
 547          [MESA_SHADER_TESS_EVAL] = 1120,            \
 548          [MESA_SHADER_GEOMETRY]  = 640,             \
 549       },                                            \
 550    }
 551
 552 #define GEN9_LP_FEATURES                           \
 553    GEN8_FEATURES,                                  \
 554    GEN9_HW_INFO,                                   \
 555    .has_integer_dword_mul = false,                 \
 556    .gt = 1,                                        \
 557    .has_llc = false,                               \
 558    .has_sample_with_hiz = true,                    \
 559    .num_slices = 1,                                \
 560    .num_thread_per_eu = 6,                         \
 561    .max_vs_threads = 112,                          \
 562    .max_tcs_threads = 112,                         \
 563    .max_tes_threads = 112,                         \
 564    .max_gs_threads = 112,                          \
 565    .max_cs_threads = 6 * 6,                        \
 566    .timestamp_frequency = 19200000,                \
 567    .urb = {                                        \
 568       .size = 192,                                 \
 569       .min_entries = {                             \
 570          [MESA_SHADER_VERTEX]    = 34,             \
 571          [MESA_SHADER_TESS_EVAL] = 34,             \
 572       },                                           \
 573       .max_entries = {                             \
 574          [MESA_SHADER_VERTEX]    = 704,            \
 575          [MESA_SHADER_TESS_CTRL] = 256,            \
 576          [MESA_SHADER_TESS_EVAL] = 416,            \
 577          [MESA_SHADER_GEOMETRY]  = 256,            \
 578       },                                           \
 579    }
 580
 581 #define GEN9_LP_FEATURES_3X6                       \
 582    GEN9_LP_FEATURES,                               \
 583    .num_subslices = { 3, },                        \
 584    .num_eu_per_subslice = 6
 585
 586 #define GEN9_LP_FEATURES_2X6                       \
 587    GEN9_LP_FEATURES,                               \
 588    .num_subslices = { 2, },                        \
 589    .num_eu_per_subslice = 6,                       \
 590    .max_vs_threads = 56,                           \
 591    .max_tcs_threads = 56,                          \
 592    .max_tes_threads = 56,                          \
 593    .max_gs_threads = 56,                           \
 594    .max_cs_threads = 6 * 6,                        \
 595    .urb = {                                        \
 596       .size = 128,                                 \
 597       .min_entries = {                             \
 598          [MESA_SHADER_VERTEX]    = 34,             \
 599          [MESA_SHADER_TESS_EVAL] = 34,             \
 600       },                                           \
 601       .max_entries = {                             \
 602          [MESA_SHADER_VERTEX]    = 352,            \
 603          [MESA_SHADER_TESS_CTRL] = 128,            \
 604          [MESA_SHADER_TESS_EVAL] = 208,            \
 605          [MESA_SHADER_GEOMETRY]  = 128,            \
 606       },                                           \
 607    }
 608
 609 #define GEN9_FEATURES                               \
 610    GEN8_FEATURES,                                   \
 611    GEN9_HW_INFO,                                    \
 612    .has_sample_with_hiz = true
 613
 614 static const struct gen_device_info gen_device_info_skl_gt1 = {
 615    GEN9_FEATURES, .gt = 1,
 616    .is_skylake = true,
 617    .num_slices = 1,
 618    .num_subslices = { 2, },
 619    .num_eu_per_subslice = 6,
 620    .l3_banks = 2,
 621    .urb.size = 192,
 622    /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
 623     * leading to some vertices to go missing if we use too much URB.
 624     */
 625    .urb.max_entries[MESA_SHADER_VERTEX] = 928,
 626    .simulator_id = 12,
 627 };
 628
 629 static const struct gen_device_info gen_device_info_skl_gt2 = {
 630    GEN9_FEATURES, .gt = 2,
 631    .is_skylake = true,
 632    .num_slices = 1,
 633    .num_subslices = { 3, },
 634    .num_eu_per_subslice = 8,
 635    .l3_banks = 4,
 636    .simulator_id = 12,
 637 };
 638
 639 static const struct gen_device_info gen_device_info_skl_gt3 = {
 640    GEN9_FEATURES, .gt = 3,
 641    .is_skylake = true,
 642    .num_slices = 2,
 643    .num_subslices = { 3, 3, },
 644    .num_eu_per_subslice = 8,
 645    .l3_banks = 8,
 646    .simulator_id = 12,
 647 };
 648
 649 static const struct gen_device_info gen_device_info_skl_gt4 = {
 650    GEN9_FEATURES, .gt = 4,
 651    .is_skylake = true,
 652    .num_slices = 3,
 653    .num_subslices = { 3, 3, 3, },
 654    .num_eu_per_subslice = 8,
 655    .l3_banks = 12,
 656    /* From the "L3 Allocation and Programming" documentation:
 657     *
 658     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 659     * restriction of the L3 implementation, but of the FF and other clients.
 660     * Therefore, in a GT4 implementation it is possible for the programmed
 661     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 662     * only 1008KB of this will be used."
 663     */
 664    .urb.size = 1008 / 3,
 665    .simulator_id = 12,
 666 };
 667
 668 static const struct gen_device_info gen_device_info_bxt = {
 669    GEN9_LP_FEATURES_3X6,
 670    .is_broxton = true,
 671    .l3_banks = 2,
 672    .simulator_id = 14,
 673 };
 674
 675 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 676    GEN9_LP_FEATURES_2X6,
 677    .is_broxton = true,
 678    .l3_banks = 1,
 679    .simulator_id = 14,
 680 };
 681 /*
 682  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 683  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 684  */
 685
 686 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 687    GEN9_FEATURES,
 688    .is_kabylake = true,
 689    .gt = 1,
 690
 691    .max_cs_threads = 7 * 6,
 692    .urb.size = 192,
 693    .num_slices = 1,
 694    .num_subslices = { 2, },
 695    .num_eu_per_subslice = 6,
 696    .l3_banks = 2,
 697    /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
 698     * leading to some vertices to go missing if we use too much URB.
 699     */
 700    .urb.max_entries[MESA_SHADER_VERTEX] = 928,
 701    .simulator_id = 16,
 702 };
 703
 704 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 705    GEN9_FEATURES,
 706    .is_kabylake = true,
 707    .gt = 1,
 708
 709    .max_cs_threads = 7 * 6,
 710    .num_slices = 1,
 711    .num_subslices = { 3, },
 712    .num_eu_per_subslice = 6,
 713    .l3_banks = 4,
 714    .simulator_id = 16,
 715 };
 716
 717 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 718    GEN9_FEATURES,
 719    .is_kabylake = true,
 720    .gt = 2,
 721
 722    .num_slices = 1,
 723    .num_subslices = { 3, },
 724    .num_eu_per_subslice = 8,
 725    .l3_banks = 4,
 726    .simulator_id = 16,
 727 };
 728
 729 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 730    GEN9_FEATURES,
 731    .is_kabylake = true,
 732    .gt = 3,
 733
 734    .num_slices = 2,
 735    .num_subslices = { 3, 3, },
 736    .num_eu_per_subslice = 8,
 737    .l3_banks = 8,
 738    .simulator_id = 16,
 739 };
 740
 741 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 742    GEN9_FEATURES,
 743    .is_kabylake = true,
 744    .gt = 4,
 745
 746    /*
 747     * From the "L3 Allocation and Programming" documentation:
 748     *
 749     * "URB is limited to 1008KB due to programming restrictions.  This
 750     *  is not a restriction of the L3 implementation, but of the FF and
 751     *  other clients.  Therefore, in a GT4 implementation it is
 752     *  possible for the programmed allocation of the L3 data array to
 753     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 754     *  will be used."
 755     */
 756    .urb.size = 1008 / 3,
 757    .num_slices = 3,
 758    .num_subslices = { 3, 3, 3, },
 759    .num_eu_per_subslice = 8,
 760    .l3_banks = 12,
 761    .simulator_id = 16,
 762 };
 763
 764 static const struct gen_device_info gen_device_info_glk = {
 765    GEN9_LP_FEATURES_3X6,
 766    .is_geminilake = true,
 767    .l3_banks = 2,
 768    .simulator_id = 17,
 769 };
 770
 771 static const struct gen_device_info gen_device_info_glk_2x6 = {
 772    GEN9_LP_FEATURES_2X6,
 773    .is_geminilake = true,
 774    .l3_banks = 2,
 775    .simulator_id = 17,
 776 };
 777
 778 static const struct gen_device_info gen_device_info_cfl_gt1 = {
 779    GEN9_FEATURES,
 780    .is_coffeelake = true,
 781    .gt = 1,
 782
 783    .num_slices = 1,
 784    .num_subslices = { 2, },
 785    .num_eu_per_subslice = 6,
 786    .l3_banks = 2,
 787    .urb.size = 192,
 788    /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
 789     * leading to some vertices to go missing if we use too much URB.
 790     */
 791    .urb.max_entries[MESA_SHADER_VERTEX] = 928,
 792    .simulator_id = 24,
 793 };
 794 static const struct gen_device_info gen_device_info_cfl_gt2 = {
 795    GEN9_FEATURES,
 796    .is_coffeelake = true,
 797    .gt = 2,
 798
 799    .num_slices = 1,
 800    .num_subslices = { 3, },
 801    .num_eu_per_subslice = 8,
 802    .l3_banks = 4,
 803    .simulator_id = 24,
 804 };
 805
 806 static const struct gen_device_info gen_device_info_cfl_gt3 = {
 807    GEN9_FEATURES,
 808    .is_coffeelake = true,
 809    .gt = 3,
 810
 811    .num_slices = 2,
 812    .num_subslices = { 3, 3, },
 813    .num_eu_per_subslice = 8,
 814    .l3_banks = 8,
 815    .simulator_id = 24,
 816 };
 817
 818 #define GEN10_HW_INFO                               \
 819    .gen = 10,                                       \
 820    .num_thread_per_eu = 7,                          \
 821    .max_vs_threads = 728,                           \
 822    .max_gs_threads = 432,                           \
 823    .max_tcs_threads = 432,                          \
 824    .max_tes_threads = 624,                          \
 825    .max_cs_threads = 56,                            \
 826    .timestamp_frequency = 19200000,                 \
 827    .urb = {                                         \
 828       .size = 256,                                  \
 829       .min_entries = {                              \
 830          [MESA_SHADER_VERTEX]    = 64,              \
 831          [MESA_SHADER_TESS_EVAL] = 34,              \
 832       },                                            \
 833       .max_entries = {                              \
 834       [MESA_SHADER_VERTEX]       = 3936,            \
 835       [MESA_SHADER_TESS_CTRL]    = 896,             \
 836       [MESA_SHADER_TESS_EVAL]    = 2064,            \
 837       [MESA_SHADER_GEOMETRY]     = 832,             \
 838       },                                            \
 839    }
 840
 841 #define subslices(args...) { args, }
 842
 843 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
 844    GEN8_FEATURES,                                   \
 845    GEN10_HW_INFO,                                   \
 846    .has_sample_with_hiz = true,                     \
 847    .gt = _gt,                                       \
 848    .num_slices = _slices,                           \
 849    .num_subslices = _subslices,                     \
 850    .num_eu_per_subslice = 8,                        \
 851    .l3_banks = _l3
 852
 853 static const struct gen_device_info gen_device_info_cnl_2x8 = {
 854    /* GT0.5 */
 855    GEN10_FEATURES(1, 1, subslices(2), 2),
 856    .is_cannonlake = true,
 857    .simulator_id = 15,
 858 };
 859
 860 static const struct gen_device_info gen_device_info_cnl_3x8 = {
 861    /* GT1 */
 862    GEN10_FEATURES(1, 1, subslices(3), 3),
 863    .is_cannonlake = true,
 864    .simulator_id = 15,
 865 };
 866
 867 static const struct gen_device_info gen_device_info_cnl_4x8 = {
 868    /* GT 1.5 */
 869    GEN10_FEATURES(1, 2, subslices(2, 2), 6),
 870    .is_cannonlake = true,
 871    .simulator_id = 15,
 872 };
 873
 874 static const struct gen_device_info gen_device_info_cnl_5x8 = {
 875    /* GT2 */
 876    GEN10_FEATURES(2, 2, subslices(3, 2), 6),
 877    .is_cannonlake = true,
 878    .simulator_id = 15,
 879 };
 880
 881 #define GEN11_HW_INFO                               \
 882    .gen = 11,                                       \
 883    .has_pln = false,                                \
 884    .max_vs_threads = 364,                           \
 885    .max_gs_threads = 224,                           \
 886    .max_tcs_threads = 224,                          \
 887    .max_tes_threads = 364,                          \
 888    .max_cs_threads = 56
 889
 890 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
 891    GEN8_FEATURES,                                     \
 892    GEN11_HW_INFO,                                     \
 893    .has_64bit_types = false,                          \
 894    .has_integer_dword_mul = false,                    \
 895    .has_sample_with_hiz = false,                      \
 896    .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
 897    .num_subslices = _subslices,                       \
 898    .num_eu_per_subslice = 8
 899
 900 #define GEN11_URB_MIN_MAX_ENTRIES                     \
 901    .min_entries = {                                   \
 902       [MESA_SHADER_VERTEX]    = 64,                   \
 903       [MESA_SHADER_TESS_EVAL] = 34,                   \
 904    },                                                 \
 905    .max_entries = {                                   \
 906       [MESA_SHADER_VERTEX]    = 2384,                 \
 907       [MESA_SHADER_TESS_CTRL] = 1032,                 \
 908       [MESA_SHADER_TESS_EVAL] = 2384,                 \
 909       [MESA_SHADER_GEOMETRY]  = 1032,                 \
 910    }
 911
 912 static const struct gen_device_info gen_device_info_icl_8x8 = {
 913    GEN11_FEATURES(2, 1, subslices(8), 8),
 914    .urb = {
 915       .size = 1024,
 916       GEN11_URB_MIN_MAX_ENTRIES,
 917    },
 918    .simulator_id = 19,
 919 };
 920
 921 static const struct gen_device_info gen_device_info_icl_6x8 = {
 922    GEN11_FEATURES(1, 1, subslices(6), 6),
 923    .urb = {
 924       .size = 768,
 925       GEN11_URB_MIN_MAX_ENTRIES,
 926    },
 927    .simulator_id = 19,
 928 };
 929
 930 static const struct gen_device_info gen_device_info_icl_4x8 = {
 931    GEN11_FEATURES(1, 1, subslices(4), 6),
 932    .urb = {
 933       .size = 768,
 934       GEN11_URB_MIN_MAX_ENTRIES,
 935    },
 936    .simulator_id = 19,
 937 };
 938
 939 static const struct gen_device_info gen_device_info_icl_1x8 = {
 940    GEN11_FEATURES(1, 1, subslices(1), 6),
 941    .urb = {
 942       .size = 768,
 943       GEN11_URB_MIN_MAX_ENTRIES,
 944    },
 945    .simulator_id = 19,
 946 };
 947
 948 static const struct gen_device_info gen_device_info_ehl_4x8 = {
 949    GEN11_FEATURES(1, 1, subslices(4), 4),
 950    .urb = {
 951       .size = 512,
 952       .min_entries = {
 953          [MESA_SHADER_VERTEX]    = 64,
 954          [MESA_SHADER_TESS_EVAL] = 34,
 955       },
 956       .max_entries = {
 957          [MESA_SHADER_VERTEX]    = 2384,
 958          [MESA_SHADER_TESS_CTRL] = 1032,
 959          [MESA_SHADER_TESS_EVAL] = 2384,
 960          [MESA_SHADER_GEOMETRY]  = 1032,
 961       },
 962    },
 963    .disable_ccs_repack = true,
 964    .simulator_id = 28,
 965 };
 966
 967 /* FIXME: Verfiy below entries when more information is available for this SKU.
 968  */
 969 static const struct gen_device_info gen_device_info_ehl_4x4 = {
 970    GEN11_FEATURES(1, 1, subslices(4), 4),
 971    .urb = {
 972       .size = 512,
 973       .min_entries = {
 974          [MESA_SHADER_VERTEX]    = 64,
 975          [MESA_SHADER_TESS_EVAL] = 34,
 976       },
 977       .max_entries = {
 978          [MESA_SHADER_VERTEX]    = 2384,
 979          [MESA_SHADER_TESS_CTRL] = 1032,
 980          [MESA_SHADER_TESS_EVAL] = 2384,
 981          [MESA_SHADER_GEOMETRY]  = 1032,
 982       },
 983    },
 984    .disable_ccs_repack = true,
 985    .num_eu_per_subslice = 4,
 986    .simulator_id = 28,
 987 };
 988
 989 /* FIXME: Verfiy below entries when more information is available for this SKU.
 990  */
 991 static const struct gen_device_info gen_device_info_ehl_2x4 = {
 992    GEN11_FEATURES(1, 1, subslices(2), 4),
 993    .urb = {
 994       .size = 512,
 995       .min_entries = {
 996          [MESA_SHADER_VERTEX]    = 64,
 997          [MESA_SHADER_TESS_EVAL] = 34,
 998       },
 999       .max_entries = {
1000          [MESA_SHADER_VERTEX]    = 2384,
1001          [MESA_SHADER_TESS_CTRL] = 1032,
1002          [MESA_SHADER_TESS_EVAL] = 2384,
1003          [MESA_SHADER_GEOMETRY]  = 1032,
1004       },
1005    },
1006    .disable_ccs_repack = true,
1007    .num_eu_per_subslice =4,
1008    .simulator_id = 28,
1009 };
1010
1011 static void
1012 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1013                             unsigned slice,
1014                             unsigned subslice,
1015                             unsigned eu_mask)
1016 {
1017    unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1018       subslice * devinfo->eu_subslice_stride;
1019
1020    for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1021       devinfo->eu_masks[subslice_offset + b_eu] =
1022          (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1023    }
1024 }
1025
1026 /* Generate slice/subslice/eu masks from number of
1027  * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1028  * structure.
1029  *
1030  * These can be overridden with values reported by the kernel either from
1031  * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1032  * through the i915 query uapi.
1033  */
1034 static void
1035 fill_masks(struct gen_device_info *devinfo)
1036 {
1037    devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1038
1039    /* Subslice masks */
1040    unsigned max_subslices = 0;
1041    for (int s = 0; s < devinfo->num_slices; s++)
1042       max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1043    devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1044
1045    for (int s = 0; s < devinfo->num_slices; s++) {
1046       devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1047          (1U << devinfo->num_subslices[s]) - 1;
1048    }
1049
1050    /* EU masks */
1051    devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1052    devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1053
1054    for (int s = 0; s < devinfo->num_slices; s++) {
1055       for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1056          gen_device_info_set_eu_mask(devinfo, s, ss,
1057                                      (1U << devinfo->num_eu_per_subslice) - 1);
1058       }
1059    }
1060 }
1061
1062 static void
1063 reset_masks(struct gen_device_info *devinfo)
1064 {
1065    devinfo->subslice_slice_stride = 0;
1066    devinfo->eu_subslice_stride = 0;
1067    devinfo->eu_slice_stride = 0;
1068
1069    devinfo->num_slices = 0;
1070    devinfo->num_eu_per_subslice = 0;
1071    memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1072
1073    memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1074    memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1075    memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1076    memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1077 }
1078
1079 static void
1080 update_from_topology(struct gen_device_info *devinfo,
1081                      const struct drm_i915_query_topology_info *topology)
1082 {
1083    reset_masks(devinfo);
1084
1085    devinfo->subslice_slice_stride = topology->subslice_stride;
1086
1087    devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1088    devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1089
1090    assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1091    memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1092    devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1093
1094    uint32_t subslice_mask_len =
1095       topology->max_slices * topology->subslice_stride;
1096    assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1097    memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1098           subslice_mask_len);
1099
1100    uint32_t n_subslices = 0;
1101    for (int s = 0; s < topology->max_slices; s++) {
1102       if ((devinfo->slice_masks & (1 << s)) == 0)
1103          continue;
1104
1105       for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1106          devinfo->num_subslices[s] +=
1107             __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1108       }
1109       n_subslices += devinfo->num_subslices[s];
1110    }
1111    assert(n_subslices > 0);
1112
1113    if (devinfo->gen == 11) {
1114       /* On ICL we only have one slice */
1115       assert(devinfo->slice_masks == 1);
1116
1117       /* Count the number of subslices on each pixel pipe. Assume that
1118        * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1119        */
1120       unsigned subslices = devinfo->subslice_masks[0];
1121       unsigned ss = 0;
1122       while (subslices > 0) {
1123          if (subslices & 1)
1124             devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
1125          subslices >>= 1;
1126          ss++;
1127       }
1128    }
1129
1130    uint32_t eu_mask_len =
1131       topology->eu_stride * topology->max_subslices * topology->max_slices;
1132    assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1133    memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1134
1135    uint32_t n_eus = 0;
1136    for (int b = 0; b < eu_mask_len; b++)
1137       n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1138
1139    devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1140 }
1141
1142 static bool
1143 update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask,
1144                   uint32_t subslice_mask, uint32_t n_eus)
1145 {
1146    struct drm_i915_query_topology_info *topology;
1147
1148    assert((slice_mask & 0xff) == slice_mask);
1149
1150    size_t data_length = 100;
1151
1152    topology = calloc(1, sizeof(*topology) + data_length);
1153    if (!topology)
1154       return false;
1155
1156    topology->max_slices = util_last_bit(slice_mask);
1157    topology->max_subslices = util_last_bit(subslice_mask);
1158
1159    topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1160    topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1161
1162    uint32_t n_subslices = __builtin_popcount(slice_mask) *
1163       __builtin_popcount(subslice_mask);
1164    uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1165    uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1166
1167    topology->eu_offset = topology->subslice_offset +
1168       DIV_ROUND_UP(topology->max_subslices, 8);
1169    topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1170
1171    /* Set slice mask in topology */
1172    for (int b = 0; b < topology->subslice_offset; b++)
1173       topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1174
1175    for (int s = 0; s < topology->max_slices; s++) {
1176
1177       /* Set subslice mask in topology */
1178       for (int b = 0; b < topology->subslice_stride; b++) {
1179          int subslice_offset = topology->subslice_offset +
1180             s * topology->subslice_stride + b;
1181
1182          topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1183       }
1184
1185       /* Set eu mask in topology */
1186       for (int ss = 0; ss < topology->max_subslices; ss++) {
1187          for (int b = 0; b < topology->eu_stride; b++) {
1188             int eu_offset = topology->eu_offset +
1189                (s * topology->max_subslices + ss) * topology->eu_stride + b;
1190
1191             topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1192          }
1193       }
1194    }
1195
1196    update_from_topology(devinfo, topology);
1197    free(topology);
1198
1199    return true;
1200 }
1201
1202 static bool
1203 getparam(int fd, uint32_t param, int *value)
1204 {
1205    int tmp;
1206
1207    struct drm_i915_getparam gp = {
1208       .param = param,
1209       .value = &tmp,
1210    };
1211
1212    int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
1213    if (ret != 0)
1214       return false;
1215
1216    *value = tmp;
1217    return true;
1218 }
1219
1220 bool
1221 gen_get_device_info_from_pci_id(int pci_id,
1222                                 struct gen_device_info *devinfo)
1223 {
1224    switch (pci_id) {
1225 #undef CHIPSET
1226 #define CHIPSET(id, family, name) \
1227       case id: *devinfo = gen_device_info_##family; break;
1228 #include "pci_ids/i965_pci_ids.h"
1229 #include "pci_ids/iris_pci_ids.h"
1230    default:
1231       fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id);
1232       return false;
1233    }
1234
1235    fill_masks(devinfo);
1236
1237    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1238     *
1239     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
1240     *  allocate scratch space enough so that each slice has 4 slices allowed."
1241     *
1242     * The equivalent internal documentation says that this programming note
1243     * applies to all Gen9+ platforms.
1244     *
1245     * The hardware typically calculates the scratch space pointer by taking
1246     * the base address, and adding per-thread-scratch-space * thread ID.
1247     * Extra padding can be necessary depending how the thread IDs are
1248     * calculated for a particular shader stage.
1249     */
1250
1251    switch(devinfo->gen) {
1252    case 9:
1253    case 10:
1254       devinfo->max_wm_threads = 64 /* threads-per-PSD */
1255                               * devinfo->num_slices
1256                               * 4; /* effective subslices per slice */
1257       break;
1258    case 11:
1259       devinfo->max_wm_threads = 128 /* threads-per-PSD */
1260                               * devinfo->num_slices
1261                               * 8; /* subslices per slice */
1262       break;
1263    default:
1264       break;
1265    }
1266
1267    assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1268
1269    devinfo->chipset_id = pci_id;
1270    return true;
1271 }
1272
1273 const char *
1274 gen_get_device_name(int devid)
1275 {
1276    switch (devid) {
1277 #undef CHIPSET
1278 #define CHIPSET(id, family, name) case id: return name;
1279 #include "pci_ids/i965_pci_ids.h"
1280 #include "pci_ids/iris_pci_ids.h"
1281    default:
1282       return NULL;
1283    }
1284 }
1285
1286 /**
1287  * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1288  * (kernel 4.13+)
1289  */
1290 static bool
1291 getparam_topology(struct gen_device_info *devinfo, int fd)
1292 {
1293    int slice_mask = 0;
1294    if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
1295       return false;
1296
1297    int n_eus;
1298    if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
1299       return false;
1300
1301    int subslice_mask = 0;
1302    if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
1303       return false;
1304
1305    return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1306 }
1307
1308 /**
1309  * preferred API for updating the topology in devinfo (kernel 4.17+)
1310  */
1311 static bool
1312 query_topology(struct gen_device_info *devinfo, int fd)
1313 {
1314    struct drm_i915_query_item item = {
1315       .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
1316    };
1317    struct drm_i915_query query = {
1318       .num_items = 1,
1319       .items_ptr = (uintptr_t) &item,
1320    };
1321
1322    if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
1323       return false;
1324
1325    if (item.length < 0)
1326       return false;
1327
1328    struct drm_i915_query_topology_info *topo_info =
1329       (struct drm_i915_query_topology_info *) calloc(1, item.length);
1330    item.data_ptr = (uintptr_t) topo_info;
1331
1332    if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
1333        item.length <= 0)
1334       return false;
1335
1336    update_from_topology(devinfo, topo_info);
1337
1338    free(topo_info);
1339
1340    return true;
1341
1342 }
1343
1344 bool
1345 gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
1346 {
1347    int devid = get_pci_device_id_override();
1348    if (devid > 0) {
1349       if (!gen_get_device_info_from_pci_id(devid, devinfo))
1350          return false;
1351       devinfo->no_hw = true;
1352    } else {
1353       /* query the device id */
1354       if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
1355          return false;
1356       if (!gen_get_device_info_from_pci_id(devid, devinfo))
1357          return false;
1358       devinfo->no_hw = false;
1359    }
1360
1361    /* remaining initializion queries the kernel for device info */
1362    if (devinfo->no_hw)
1363       return true;
1364
1365    int timestamp_frequency;
1366    if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1367                 &timestamp_frequency))
1368       devinfo->timestamp_frequency = timestamp_frequency;
1369    else if (devinfo->gen >= 10)
1370       /* gen10 and later requires the timestamp_frequency to be updated */
1371       return false;
1372
1373    if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
1374        return false;
1375
1376    if (!query_topology(devinfo, fd)) {
1377       if (devinfo->gen >= 10) {
1378          /* topology uAPI required for CNL+ (kernel 4.17+) */
1379          return false;
1380       }
1381
1382       /* else use the kernel 4.13+ api for gen8+.  For older kernels, topology
1383        * will be wrong, affecting GPU metrics. In this case, fail silently.
1384        */
1385       getparam_topology(devinfo, fd);
1386    }
1387
1388    return true;
1389 }