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intel: Add pci-ids for Jasper Lake
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
35
36 #include "drm-uapi/i915_drm.h"
37
38 /**
39 * Get the PCI ID for the device name.
40 *
41 * Returns -1 if the device is not known.
42 */
43 int
44 gen_device_name_to_pci_device_id(const char *name)
45 {
46 static const struct {
47 const char *name;
48 int pci_id;
49 } name_map[] = {
50 { "brw", 0x2a02 },
51 { "g4x", 0x2a42 },
52 { "ilk", 0x0042 },
53 { "snb", 0x0126 },
54 { "ivb", 0x016a },
55 { "hsw", 0x0d2e },
56 { "byt", 0x0f33 },
57 { "bdw", 0x162e },
58 { "chv", 0x22B3 },
59 { "skl", 0x1912 },
60 { "bxt", 0x5A85 },
61 { "kbl", 0x5912 },
62 { "aml", 0x591C },
63 { "glk", 0x3185 },
64 { "cfl", 0x3E9B },
65 { "whl", 0x3EA1 },
66 { "cml", 0x9b41 },
67 { "cnl", 0x5a52 },
68 { "icl", 0x8a52 },
69 { "ehl", 0x4500 },
70 { "jsl", 0x4E71 },
71 { "tgl", 0x9a49 },
72 };
73
74 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
75 if (!strcmp(name_map[i].name, name))
76 return name_map[i].pci_id;
77 }
78
79 return -1;
80 }
81
82 /**
83 * Get the overridden PCI ID for the device. This is set with the
84 * INTEL_DEVID_OVERRIDE environment variable.
85 *
86 * Returns -1 if the override is not set.
87 */
88 static int
89 get_pci_device_id_override(void)
90 {
91 if (geteuid() == getuid()) {
92 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
93 if (devid_override) {
94 const int id = gen_device_name_to_pci_device_id(devid_override);
95 return id >= 0 ? id : strtol(devid_override, NULL, 0);
96 }
97 }
98
99 return -1;
100 }
101
102 static const struct gen_device_info gen_device_info_i965 = {
103 .gen = 4,
104 .has_negative_rhw_bug = true,
105 .num_slices = 1,
106 .num_subslices = { 1, },
107 .num_eu_per_subslice = 8,
108 .num_thread_per_eu = 4,
109 .max_vs_threads = 16,
110 .max_gs_threads = 2,
111 .max_wm_threads = 8 * 4,
112 .urb = {
113 .size = 256,
114 },
115 .timestamp_frequency = 12500000,
116 .simulator_id = -1,
117 };
118
119 static const struct gen_device_info gen_device_info_g4x = {
120 .gen = 4,
121 .has_pln = true,
122 .has_compr4 = true,
123 .has_surface_tile_offset = true,
124 .is_g4x = true,
125 .num_slices = 1,
126 .num_subslices = { 1, },
127 .num_eu_per_subslice = 10,
128 .num_thread_per_eu = 5,
129 .max_vs_threads = 32,
130 .max_gs_threads = 2,
131 .max_wm_threads = 10 * 5,
132 .urb = {
133 .size = 384,
134 },
135 .timestamp_frequency = 12500000,
136 .simulator_id = -1,
137 };
138
139 static const struct gen_device_info gen_device_info_ilk = {
140 .gen = 5,
141 .has_pln = true,
142 .has_compr4 = true,
143 .has_surface_tile_offset = true,
144 .num_slices = 1,
145 .num_subslices = { 1, },
146 .num_eu_per_subslice = 12,
147 .num_thread_per_eu = 6,
148 .max_vs_threads = 72,
149 .max_gs_threads = 32,
150 .max_wm_threads = 12 * 6,
151 .urb = {
152 .size = 1024,
153 },
154 .timestamp_frequency = 12500000,
155 .simulator_id = -1,
156 };
157
158 static const struct gen_device_info gen_device_info_snb_gt1 = {
159 .gen = 6,
160 .gt = 1,
161 .has_hiz_and_separate_stencil = true,
162 .has_llc = true,
163 .has_pln = true,
164 .has_surface_tile_offset = true,
165 .needs_unlit_centroid_workaround = true,
166 .num_slices = 1,
167 .num_subslices = { 1, },
168 .num_eu_per_subslice = 6,
169 .num_thread_per_eu = 6, /* Not confirmed */
170 .max_vs_threads = 24,
171 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
172 .max_wm_threads = 40,
173 .urb = {
174 .size = 32,
175 .min_entries = {
176 [MESA_SHADER_VERTEX] = 24,
177 },
178 .max_entries = {
179 [MESA_SHADER_VERTEX] = 256,
180 [MESA_SHADER_GEOMETRY] = 256,
181 },
182 },
183 .timestamp_frequency = 12500000,
184 .simulator_id = -1,
185 };
186
187 static const struct gen_device_info gen_device_info_snb_gt2 = {
188 .gen = 6,
189 .gt = 2,
190 .has_hiz_and_separate_stencil = true,
191 .has_llc = true,
192 .has_pln = true,
193 .has_surface_tile_offset = true,
194 .needs_unlit_centroid_workaround = true,
195 .num_slices = 1,
196 .num_subslices = { 1, },
197 .num_eu_per_subslice = 12,
198 .num_thread_per_eu = 6, /* Not confirmed */
199 .max_vs_threads = 60,
200 .max_gs_threads = 60,
201 .max_wm_threads = 80,
202 .urb = {
203 .size = 64,
204 .min_entries = {
205 [MESA_SHADER_VERTEX] = 24,
206 },
207 .max_entries = {
208 [MESA_SHADER_VERTEX] = 256,
209 [MESA_SHADER_GEOMETRY] = 256,
210 },
211 },
212 .timestamp_frequency = 12500000,
213 .simulator_id = -1,
214 };
215
216 #define GEN7_FEATURES \
217 .gen = 7, \
218 .has_hiz_and_separate_stencil = true, \
219 .must_use_separate_stencil = true, \
220 .has_llc = true, \
221 .has_pln = true, \
222 .has_64bit_types = true, \
223 .has_surface_tile_offset = true, \
224 .timestamp_frequency = 12500000
225
226 static const struct gen_device_info gen_device_info_ivb_gt1 = {
227 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
228 .num_slices = 1,
229 .num_subslices = { 1, },
230 .num_eu_per_subslice = 6,
231 .num_thread_per_eu = 6,
232 .l3_banks = 2,
233 .max_vs_threads = 36,
234 .max_tcs_threads = 36,
235 .max_tes_threads = 36,
236 .max_gs_threads = 36,
237 .max_wm_threads = 48,
238 .max_cs_threads = 36,
239 .urb = {
240 .size = 128,
241 .min_entries = {
242 [MESA_SHADER_VERTEX] = 32,
243 [MESA_SHADER_TESS_EVAL] = 10,
244 },
245 .max_entries = {
246 [MESA_SHADER_VERTEX] = 512,
247 [MESA_SHADER_TESS_CTRL] = 32,
248 [MESA_SHADER_TESS_EVAL] = 288,
249 [MESA_SHADER_GEOMETRY] = 192,
250 },
251 },
252 .simulator_id = 7,
253 };
254
255 static const struct gen_device_info gen_device_info_ivb_gt2 = {
256 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
257 .num_slices = 1,
258 .num_subslices = { 1, },
259 .num_eu_per_subslice = 12,
260 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
261 * @max_wm_threads ... */
262 .l3_banks = 4,
263 .max_vs_threads = 128,
264 .max_tcs_threads = 128,
265 .max_tes_threads = 128,
266 .max_gs_threads = 128,
267 .max_wm_threads = 172,
268 .max_cs_threads = 64,
269 .urb = {
270 .size = 256,
271 .min_entries = {
272 [MESA_SHADER_VERTEX] = 32,
273 [MESA_SHADER_TESS_EVAL] = 10,
274 },
275 .max_entries = {
276 [MESA_SHADER_VERTEX] = 704,
277 [MESA_SHADER_TESS_CTRL] = 64,
278 [MESA_SHADER_TESS_EVAL] = 448,
279 [MESA_SHADER_GEOMETRY] = 320,
280 },
281 },
282 .simulator_id = 7,
283 };
284
285 static const struct gen_device_info gen_device_info_byt = {
286 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
287 .num_slices = 1,
288 .num_subslices = { 1, },
289 .num_eu_per_subslice = 4,
290 .num_thread_per_eu = 8,
291 .l3_banks = 1,
292 .has_llc = false,
293 .max_vs_threads = 36,
294 .max_tcs_threads = 36,
295 .max_tes_threads = 36,
296 .max_gs_threads = 36,
297 .max_wm_threads = 48,
298 .max_cs_threads = 32,
299 .urb = {
300 .size = 128,
301 .min_entries = {
302 [MESA_SHADER_VERTEX] = 32,
303 [MESA_SHADER_TESS_EVAL] = 10,
304 },
305 .max_entries = {
306 [MESA_SHADER_VERTEX] = 512,
307 [MESA_SHADER_TESS_CTRL] = 32,
308 [MESA_SHADER_TESS_EVAL] = 288,
309 [MESA_SHADER_GEOMETRY] = 192,
310 },
311 },
312 .simulator_id = 10,
313 };
314
315 #define HSW_FEATURES \
316 GEN7_FEATURES, \
317 .is_haswell = true, \
318 .supports_simd16_3src = true, \
319 .has_resource_streamer = true
320
321 static const struct gen_device_info gen_device_info_hsw_gt1 = {
322 HSW_FEATURES, .gt = 1,
323 .num_slices = 1,
324 .num_subslices = { 1, },
325 .num_eu_per_subslice = 10,
326 .num_thread_per_eu = 7,
327 .l3_banks = 2,
328 .max_vs_threads = 70,
329 .max_tcs_threads = 70,
330 .max_tes_threads = 70,
331 .max_gs_threads = 70,
332 .max_wm_threads = 102,
333 .max_cs_threads = 70,
334 .urb = {
335 .size = 128,
336 .min_entries = {
337 [MESA_SHADER_VERTEX] = 32,
338 [MESA_SHADER_TESS_EVAL] = 10,
339 },
340 .max_entries = {
341 [MESA_SHADER_VERTEX] = 640,
342 [MESA_SHADER_TESS_CTRL] = 64,
343 [MESA_SHADER_TESS_EVAL] = 384,
344 [MESA_SHADER_GEOMETRY] = 256,
345 },
346 },
347 .simulator_id = 9,
348 };
349
350 static const struct gen_device_info gen_device_info_hsw_gt2 = {
351 HSW_FEATURES, .gt = 2,
352 .num_slices = 1,
353 .num_subslices = { 2, },
354 .num_eu_per_subslice = 10,
355 .num_thread_per_eu = 7,
356 .l3_banks = 4,
357 .max_vs_threads = 280,
358 .max_tcs_threads = 256,
359 .max_tes_threads = 280,
360 .max_gs_threads = 256,
361 .max_wm_threads = 204,
362 .max_cs_threads = 70,
363 .urb = {
364 .size = 256,
365 .min_entries = {
366 [MESA_SHADER_VERTEX] = 64,
367 [MESA_SHADER_TESS_EVAL] = 10,
368 },
369 .max_entries = {
370 [MESA_SHADER_VERTEX] = 1664,
371 [MESA_SHADER_TESS_CTRL] = 128,
372 [MESA_SHADER_TESS_EVAL] = 960,
373 [MESA_SHADER_GEOMETRY] = 640,
374 },
375 },
376 .simulator_id = 9,
377 };
378
379 static const struct gen_device_info gen_device_info_hsw_gt3 = {
380 HSW_FEATURES, .gt = 3,
381 .num_slices = 2,
382 .num_subslices = { 2, },
383 .num_eu_per_subslice = 10,
384 .num_thread_per_eu = 7,
385 .l3_banks = 8,
386 .max_vs_threads = 280,
387 .max_tcs_threads = 256,
388 .max_tes_threads = 280,
389 .max_gs_threads = 256,
390 .max_wm_threads = 408,
391 .max_cs_threads = 70,
392 .urb = {
393 .size = 512,
394 .min_entries = {
395 [MESA_SHADER_VERTEX] = 64,
396 [MESA_SHADER_TESS_EVAL] = 10,
397 },
398 .max_entries = {
399 [MESA_SHADER_VERTEX] = 1664,
400 [MESA_SHADER_TESS_CTRL] = 128,
401 [MESA_SHADER_TESS_EVAL] = 960,
402 [MESA_SHADER_GEOMETRY] = 640,
403 },
404 },
405 .simulator_id = 9,
406 };
407
408 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
409 * so keep things conservative for now and set has_sample_with_hiz = false.
410 */
411 #define GEN8_FEATURES \
412 .gen = 8, \
413 .has_hiz_and_separate_stencil = true, \
414 .has_resource_streamer = true, \
415 .must_use_separate_stencil = true, \
416 .has_llc = true, \
417 .has_sample_with_hiz = false, \
418 .has_pln = true, \
419 .has_integer_dword_mul = true, \
420 .has_64bit_types = true, \
421 .supports_simd16_3src = true, \
422 .has_surface_tile_offset = true, \
423 .num_thread_per_eu = 7, \
424 .max_vs_threads = 504, \
425 .max_tcs_threads = 504, \
426 .max_tes_threads = 504, \
427 .max_gs_threads = 504, \
428 .max_wm_threads = 384, \
429 .timestamp_frequency = 12500000
430
431 static const struct gen_device_info gen_device_info_bdw_gt1 = {
432 GEN8_FEATURES, .gt = 1,
433 .is_broadwell = true,
434 .num_slices = 1,
435 .num_subslices = { 2, },
436 .num_eu_per_subslice = 8,
437 .l3_banks = 2,
438 .max_cs_threads = 42,
439 .urb = {
440 .size = 192,
441 .min_entries = {
442 [MESA_SHADER_VERTEX] = 64,
443 [MESA_SHADER_TESS_EVAL] = 34,
444 },
445 .max_entries = {
446 [MESA_SHADER_VERTEX] = 2560,
447 [MESA_SHADER_TESS_CTRL] = 504,
448 [MESA_SHADER_TESS_EVAL] = 1536,
449 [MESA_SHADER_GEOMETRY] = 960,
450 },
451 },
452 .simulator_id = 11,
453 };
454
455 static const struct gen_device_info gen_device_info_bdw_gt2 = {
456 GEN8_FEATURES, .gt = 2,
457 .is_broadwell = true,
458 .num_slices = 1,
459 .num_subslices = { 3, },
460 .num_eu_per_subslice = 8,
461 .l3_banks = 4,
462 .max_cs_threads = 56,
463 .urb = {
464 .size = 384,
465 .min_entries = {
466 [MESA_SHADER_VERTEX] = 64,
467 [MESA_SHADER_TESS_EVAL] = 34,
468 },
469 .max_entries = {
470 [MESA_SHADER_VERTEX] = 2560,
471 [MESA_SHADER_TESS_CTRL] = 504,
472 [MESA_SHADER_TESS_EVAL] = 1536,
473 [MESA_SHADER_GEOMETRY] = 960,
474 },
475 },
476 .simulator_id = 11,
477 };
478
479 static const struct gen_device_info gen_device_info_bdw_gt3 = {
480 GEN8_FEATURES, .gt = 3,
481 .is_broadwell = true,
482 .num_slices = 2,
483 .num_subslices = { 3, 3, },
484 .num_eu_per_subslice = 8,
485 .l3_banks = 8,
486 .max_cs_threads = 56,
487 .urb = {
488 .size = 384,
489 .min_entries = {
490 [MESA_SHADER_VERTEX] = 64,
491 [MESA_SHADER_TESS_EVAL] = 34,
492 },
493 .max_entries = {
494 [MESA_SHADER_VERTEX] = 2560,
495 [MESA_SHADER_TESS_CTRL] = 504,
496 [MESA_SHADER_TESS_EVAL] = 1536,
497 [MESA_SHADER_GEOMETRY] = 960,
498 },
499 },
500 .simulator_id = 11,
501 };
502
503 static const struct gen_device_info gen_device_info_chv = {
504 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
505 .has_llc = false,
506 .has_integer_dword_mul = false,
507 .num_slices = 1,
508 .num_subslices = { 2, },
509 .num_eu_per_subslice = 8,
510 .l3_banks = 2,
511 .max_vs_threads = 80,
512 .max_tcs_threads = 80,
513 .max_tes_threads = 80,
514 .max_gs_threads = 80,
515 .max_wm_threads = 128,
516 .max_cs_threads = 6 * 7,
517 .urb = {
518 .size = 192,
519 .min_entries = {
520 [MESA_SHADER_VERTEX] = 34,
521 [MESA_SHADER_TESS_EVAL] = 34,
522 },
523 .max_entries = {
524 [MESA_SHADER_VERTEX] = 640,
525 [MESA_SHADER_TESS_CTRL] = 80,
526 [MESA_SHADER_TESS_EVAL] = 384,
527 [MESA_SHADER_GEOMETRY] = 256,
528 },
529 },
530 .simulator_id = 13,
531 };
532
533 #define GEN9_HW_INFO \
534 .gen = 9, \
535 .max_vs_threads = 336, \
536 .max_gs_threads = 336, \
537 .max_tcs_threads = 336, \
538 .max_tes_threads = 336, \
539 .max_cs_threads = 56, \
540 .timestamp_frequency = 12000000, \
541 .urb = { \
542 .size = 384, \
543 .min_entries = { \
544 [MESA_SHADER_VERTEX] = 64, \
545 [MESA_SHADER_TESS_EVAL] = 34, \
546 }, \
547 .max_entries = { \
548 [MESA_SHADER_VERTEX] = 1856, \
549 [MESA_SHADER_TESS_CTRL] = 672, \
550 [MESA_SHADER_TESS_EVAL] = 1120, \
551 [MESA_SHADER_GEOMETRY] = 640, \
552 }, \
553 }
554
555 #define GEN9_LP_FEATURES \
556 GEN8_FEATURES, \
557 GEN9_HW_INFO, \
558 .has_integer_dword_mul = false, \
559 .gt = 1, \
560 .has_llc = false, \
561 .has_sample_with_hiz = true, \
562 .num_slices = 1, \
563 .num_thread_per_eu = 6, \
564 .max_vs_threads = 112, \
565 .max_tcs_threads = 112, \
566 .max_tes_threads = 112, \
567 .max_gs_threads = 112, \
568 .max_cs_threads = 6 * 6, \
569 .timestamp_frequency = 19200000, \
570 .urb = { \
571 .size = 192, \
572 .min_entries = { \
573 [MESA_SHADER_VERTEX] = 34, \
574 [MESA_SHADER_TESS_EVAL] = 34, \
575 }, \
576 .max_entries = { \
577 [MESA_SHADER_VERTEX] = 704, \
578 [MESA_SHADER_TESS_CTRL] = 256, \
579 [MESA_SHADER_TESS_EVAL] = 416, \
580 [MESA_SHADER_GEOMETRY] = 256, \
581 }, \
582 }
583
584 #define GEN9_LP_FEATURES_3X6 \
585 GEN9_LP_FEATURES, \
586 .num_subslices = { 3, }, \
587 .num_eu_per_subslice = 6
588
589 #define GEN9_LP_FEATURES_2X6 \
590 GEN9_LP_FEATURES, \
591 .num_subslices = { 2, }, \
592 .num_eu_per_subslice = 6, \
593 .max_vs_threads = 56, \
594 .max_tcs_threads = 56, \
595 .max_tes_threads = 56, \
596 .max_gs_threads = 56, \
597 .max_cs_threads = 6 * 6, \
598 .urb = { \
599 .size = 128, \
600 .min_entries = { \
601 [MESA_SHADER_VERTEX] = 34, \
602 [MESA_SHADER_TESS_EVAL] = 34, \
603 }, \
604 .max_entries = { \
605 [MESA_SHADER_VERTEX] = 352, \
606 [MESA_SHADER_TESS_CTRL] = 128, \
607 [MESA_SHADER_TESS_EVAL] = 208, \
608 [MESA_SHADER_GEOMETRY] = 128, \
609 }, \
610 }
611
612 #define GEN9_FEATURES \
613 GEN8_FEATURES, \
614 GEN9_HW_INFO, \
615 .has_sample_with_hiz = true
616
617 static const struct gen_device_info gen_device_info_skl_gt1 = {
618 GEN9_FEATURES, .gt = 1,
619 .is_skylake = true,
620 .num_slices = 1,
621 .num_subslices = { 2, },
622 .num_eu_per_subslice = 6,
623 .l3_banks = 2,
624 .urb.size = 192,
625 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
626 * leading to some vertices to go missing if we use too much URB.
627 */
628 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
629 .simulator_id = 12,
630 };
631
632 static const struct gen_device_info gen_device_info_skl_gt2 = {
633 GEN9_FEATURES, .gt = 2,
634 .is_skylake = true,
635 .num_slices = 1,
636 .num_subslices = { 3, },
637 .num_eu_per_subslice = 8,
638 .l3_banks = 4,
639 .simulator_id = 12,
640 };
641
642 static const struct gen_device_info gen_device_info_skl_gt3 = {
643 GEN9_FEATURES, .gt = 3,
644 .is_skylake = true,
645 .num_slices = 2,
646 .num_subslices = { 3, 3, },
647 .num_eu_per_subslice = 8,
648 .l3_banks = 8,
649 .simulator_id = 12,
650 };
651
652 static const struct gen_device_info gen_device_info_skl_gt4 = {
653 GEN9_FEATURES, .gt = 4,
654 .is_skylake = true,
655 .num_slices = 3,
656 .num_subslices = { 3, 3, 3, },
657 .num_eu_per_subslice = 8,
658 .l3_banks = 12,
659 /* From the "L3 Allocation and Programming" documentation:
660 *
661 * "URB is limited to 1008KB due to programming restrictions. This is not a
662 * restriction of the L3 implementation, but of the FF and other clients.
663 * Therefore, in a GT4 implementation it is possible for the programmed
664 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
665 * only 1008KB of this will be used."
666 */
667 .urb.size = 1008 / 3,
668 .simulator_id = 12,
669 };
670
671 static const struct gen_device_info gen_device_info_bxt = {
672 GEN9_LP_FEATURES_3X6,
673 .is_broxton = true,
674 .l3_banks = 2,
675 .simulator_id = 14,
676 };
677
678 static const struct gen_device_info gen_device_info_bxt_2x6 = {
679 GEN9_LP_FEATURES_2X6,
680 .is_broxton = true,
681 .l3_banks = 1,
682 .simulator_id = 14,
683 };
684 /*
685 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
686 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
687 */
688
689 static const struct gen_device_info gen_device_info_kbl_gt1 = {
690 GEN9_FEATURES,
691 .is_kabylake = true,
692 .gt = 1,
693
694 .max_cs_threads = 7 * 6,
695 .urb.size = 192,
696 .num_slices = 1,
697 .num_subslices = { 2, },
698 .num_eu_per_subslice = 6,
699 .l3_banks = 2,
700 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
701 * leading to some vertices to go missing if we use too much URB.
702 */
703 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
704 .simulator_id = 16,
705 };
706
707 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
708 GEN9_FEATURES,
709 .is_kabylake = true,
710 .gt = 1,
711
712 .max_cs_threads = 7 * 6,
713 .num_slices = 1,
714 .num_subslices = { 3, },
715 .num_eu_per_subslice = 6,
716 .l3_banks = 4,
717 .simulator_id = 16,
718 };
719
720 static const struct gen_device_info gen_device_info_kbl_gt2 = {
721 GEN9_FEATURES,
722 .is_kabylake = true,
723 .gt = 2,
724
725 .num_slices = 1,
726 .num_subslices = { 3, },
727 .num_eu_per_subslice = 8,
728 .l3_banks = 4,
729 .simulator_id = 16,
730 };
731
732 static const struct gen_device_info gen_device_info_kbl_gt3 = {
733 GEN9_FEATURES,
734 .is_kabylake = true,
735 .gt = 3,
736
737 .num_slices = 2,
738 .num_subslices = { 3, 3, },
739 .num_eu_per_subslice = 8,
740 .l3_banks = 8,
741 .simulator_id = 16,
742 };
743
744 static const struct gen_device_info gen_device_info_kbl_gt4 = {
745 GEN9_FEATURES,
746 .is_kabylake = true,
747 .gt = 4,
748
749 /*
750 * From the "L3 Allocation and Programming" documentation:
751 *
752 * "URB is limited to 1008KB due to programming restrictions. This
753 * is not a restriction of the L3 implementation, but of the FF and
754 * other clients. Therefore, in a GT4 implementation it is
755 * possible for the programmed allocation of the L3 data array to
756 * provide 3*384KB=1152KB for URB, but only 1008KB of this
757 * will be used."
758 */
759 .urb.size = 1008 / 3,
760 .num_slices = 3,
761 .num_subslices = { 3, 3, 3, },
762 .num_eu_per_subslice = 8,
763 .l3_banks = 12,
764 .simulator_id = 16,
765 };
766
767 static const struct gen_device_info gen_device_info_glk = {
768 GEN9_LP_FEATURES_3X6,
769 .is_geminilake = true,
770 .l3_banks = 2,
771 .simulator_id = 17,
772 };
773
774 static const struct gen_device_info gen_device_info_glk_2x6 = {
775 GEN9_LP_FEATURES_2X6,
776 .is_geminilake = true,
777 .l3_banks = 2,
778 .simulator_id = 17,
779 };
780
781 static const struct gen_device_info gen_device_info_cfl_gt1 = {
782 GEN9_FEATURES,
783 .is_coffeelake = true,
784 .gt = 1,
785
786 .num_slices = 1,
787 .num_subslices = { 2, },
788 .num_eu_per_subslice = 6,
789 .l3_banks = 2,
790 .urb.size = 192,
791 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
792 * leading to some vertices to go missing if we use too much URB.
793 */
794 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
795 .simulator_id = 24,
796 };
797 static const struct gen_device_info gen_device_info_cfl_gt2 = {
798 GEN9_FEATURES,
799 .is_coffeelake = true,
800 .gt = 2,
801
802 .num_slices = 1,
803 .num_subslices = { 3, },
804 .num_eu_per_subslice = 8,
805 .l3_banks = 4,
806 .simulator_id = 24,
807 };
808
809 static const struct gen_device_info gen_device_info_cfl_gt3 = {
810 GEN9_FEATURES,
811 .is_coffeelake = true,
812 .gt = 3,
813
814 .num_slices = 2,
815 .num_subslices = { 3, 3, },
816 .num_eu_per_subslice = 8,
817 .l3_banks = 8,
818 .simulator_id = 24,
819 };
820
821 #define GEN10_HW_INFO \
822 .gen = 10, \
823 .num_thread_per_eu = 7, \
824 .max_vs_threads = 728, \
825 .max_gs_threads = 432, \
826 .max_tcs_threads = 432, \
827 .max_tes_threads = 624, \
828 .max_cs_threads = 56, \
829 .timestamp_frequency = 19200000, \
830 .urb = { \
831 .size = 256, \
832 .min_entries = { \
833 [MESA_SHADER_VERTEX] = 64, \
834 [MESA_SHADER_TESS_EVAL] = 34, \
835 }, \
836 .max_entries = { \
837 [MESA_SHADER_VERTEX] = 3936, \
838 [MESA_SHADER_TESS_CTRL] = 896, \
839 [MESA_SHADER_TESS_EVAL] = 2064, \
840 [MESA_SHADER_GEOMETRY] = 832, \
841 }, \
842 }
843
844 #define subslices(args...) { args, }
845
846 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
847 GEN8_FEATURES, \
848 GEN10_HW_INFO, \
849 .has_sample_with_hiz = true, \
850 .gt = _gt, \
851 .num_slices = _slices, \
852 .num_subslices = _subslices, \
853 .num_eu_per_subslice = 8, \
854 .l3_banks = _l3
855
856 static const struct gen_device_info gen_device_info_cnl_2x8 = {
857 /* GT0.5 */
858 GEN10_FEATURES(1, 1, subslices(2), 2),
859 .is_cannonlake = true,
860 .simulator_id = 15,
861 };
862
863 static const struct gen_device_info gen_device_info_cnl_3x8 = {
864 /* GT1 */
865 GEN10_FEATURES(1, 1, subslices(3), 3),
866 .is_cannonlake = true,
867 .simulator_id = 15,
868 };
869
870 static const struct gen_device_info gen_device_info_cnl_4x8 = {
871 /* GT 1.5 */
872 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
873 .is_cannonlake = true,
874 .simulator_id = 15,
875 };
876
877 static const struct gen_device_info gen_device_info_cnl_5x8 = {
878 /* GT2 */
879 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
880 .is_cannonlake = true,
881 .simulator_id = 15,
882 };
883
884 #define GEN11_HW_INFO \
885 .gen = 11, \
886 .has_pln = false, \
887 .max_vs_threads = 364, \
888 .max_gs_threads = 224, \
889 .max_tcs_threads = 224, \
890 .max_tes_threads = 364, \
891 .max_cs_threads = 56
892
893 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
894 GEN8_FEATURES, \
895 GEN11_HW_INFO, \
896 .has_64bit_types = false, \
897 .has_integer_dword_mul = false, \
898 .has_sample_with_hiz = false, \
899 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
900 .num_subslices = _subslices, \
901 .num_eu_per_subslice = 8
902
903 #define GEN11_URB_MIN_MAX_ENTRIES \
904 .min_entries = { \
905 [MESA_SHADER_VERTEX] = 64, \
906 [MESA_SHADER_TESS_EVAL] = 34, \
907 }, \
908 .max_entries = { \
909 [MESA_SHADER_VERTEX] = 2384, \
910 [MESA_SHADER_TESS_CTRL] = 1032, \
911 [MESA_SHADER_TESS_EVAL] = 2384, \
912 [MESA_SHADER_GEOMETRY] = 1032, \
913 }
914
915 static const struct gen_device_info gen_device_info_icl_8x8 = {
916 GEN11_FEATURES(2, 1, subslices(8), 8),
917 .urb = {
918 .size = 1024,
919 GEN11_URB_MIN_MAX_ENTRIES,
920 },
921 .simulator_id = 19,
922 };
923
924 static const struct gen_device_info gen_device_info_icl_6x8 = {
925 GEN11_FEATURES(1, 1, subslices(6), 6),
926 .urb = {
927 .size = 768,
928 GEN11_URB_MIN_MAX_ENTRIES,
929 },
930 .simulator_id = 19,
931 };
932
933 static const struct gen_device_info gen_device_info_icl_4x8 = {
934 GEN11_FEATURES(1, 1, subslices(4), 6),
935 .urb = {
936 .size = 768,
937 GEN11_URB_MIN_MAX_ENTRIES,
938 },
939 .simulator_id = 19,
940 };
941
942 static const struct gen_device_info gen_device_info_icl_1x8 = {
943 GEN11_FEATURES(1, 1, subslices(1), 6),
944 .urb = {
945 .size = 768,
946 GEN11_URB_MIN_MAX_ENTRIES,
947 },
948 .simulator_id = 19,
949 };
950
951 static const struct gen_device_info gen_device_info_ehl_4x8 = {
952 GEN11_FEATURES(1, 1, subslices(4), 4),
953 .is_elkhartlake = true,
954 .urb = {
955 .size = 512,
956 .min_entries = {
957 [MESA_SHADER_VERTEX] = 64,
958 [MESA_SHADER_TESS_EVAL] = 34,
959 },
960 .max_entries = {
961 [MESA_SHADER_VERTEX] = 2384,
962 [MESA_SHADER_TESS_CTRL] = 1032,
963 [MESA_SHADER_TESS_EVAL] = 2384,
964 [MESA_SHADER_GEOMETRY] = 1032,
965 },
966 },
967 .disable_ccs_repack = true,
968 .simulator_id = 28,
969 };
970
971 static const struct gen_device_info gen_device_info_ehl_4x6 = {
972 GEN11_FEATURES(1, 1, subslices(4), 4),
973 .is_elkhartlake = true,
974 .urb = {
975 .size = 512,
976 .min_entries = {
977 [MESA_SHADER_VERTEX] = 64,
978 [MESA_SHADER_TESS_EVAL] = 34,
979 },
980 .max_entries = {
981 [MESA_SHADER_VERTEX] = 2384,
982 [MESA_SHADER_TESS_CTRL] = 1032,
983 [MESA_SHADER_TESS_EVAL] = 2384,
984 [MESA_SHADER_GEOMETRY] = 1032,
985 },
986 },
987 .disable_ccs_repack = true,
988 .num_eu_per_subslice = 6,
989 .simulator_id = 28,
990 };
991
992 static const struct gen_device_info gen_device_info_ehl_4x4 = {
993 GEN11_FEATURES(1, 1, subslices(4), 4),
994 .is_elkhartlake = true,
995 .urb = {
996 .size = 512,
997 .min_entries = {
998 [MESA_SHADER_VERTEX] = 64,
999 [MESA_SHADER_TESS_EVAL] = 34,
1000 },
1001 .max_entries = {
1002 [MESA_SHADER_VERTEX] = 2384,
1003 [MESA_SHADER_TESS_CTRL] = 1032,
1004 [MESA_SHADER_TESS_EVAL] = 2384,
1005 [MESA_SHADER_GEOMETRY] = 1032,
1006 },
1007 },
1008 .disable_ccs_repack = true,
1009 .num_eu_per_subslice = 4,
1010 .simulator_id = 28,
1011 };
1012
1013 static const struct gen_device_info gen_device_info_ehl_2x4 = {
1014 GEN11_FEATURES(1, 1, subslices(2), 4),
1015 .is_elkhartlake = true,
1016 .urb = {
1017 .size = 512,
1018 .min_entries = {
1019 [MESA_SHADER_VERTEX] = 64,
1020 [MESA_SHADER_TESS_EVAL] = 34,
1021 },
1022 .max_entries = {
1023 [MESA_SHADER_VERTEX] = 2384,
1024 [MESA_SHADER_TESS_CTRL] = 1032,
1025 [MESA_SHADER_TESS_EVAL] = 2384,
1026 [MESA_SHADER_GEOMETRY] = 1032,
1027 },
1028 },
1029 .disable_ccs_repack = true,
1030 .num_eu_per_subslice =4,
1031 .simulator_id = 28,
1032 };
1033
1034 #define GEN12_URB_MIN_MAX_ENTRIES \
1035 .min_entries = { \
1036 [MESA_SHADER_VERTEX] = 64, \
1037 [MESA_SHADER_TESS_EVAL] = 34, \
1038 }, \
1039 .max_entries = { \
1040 [MESA_SHADER_VERTEX] = 3576, \
1041 [MESA_SHADER_TESS_CTRL] = 1548, \
1042 [MESA_SHADER_TESS_EVAL] = 3576, \
1043 [MESA_SHADER_GEOMETRY] = 1548, \
1044 }
1045
1046 #define GEN12_HW_INFO \
1047 .gen = 12, \
1048 .has_pln = false, \
1049 .has_sample_with_hiz = false, \
1050 .has_aux_map = true, \
1051 .max_vs_threads = 546, \
1052 .max_gs_threads = 336, \
1053 .max_tcs_threads = 336, \
1054 .max_tes_threads = 546, \
1055 .max_cs_threads = 112, /* threads per DSS */ \
1056 .urb = { \
1057 GEN12_URB_MIN_MAX_ENTRIES, \
1058 }
1059
1060 #define GEN12_FEATURES(_gt, _slices, _dual_subslices, _l3) \
1061 GEN8_FEATURES, \
1062 GEN12_HW_INFO, \
1063 .has_64bit_types = false, \
1064 .has_integer_dword_mul = false, \
1065 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1066 .simulator_id = 22, \
1067 .urb.size = (_gt) == 1 ? 512 : 1024, \
1068 .num_subslices = _dual_subslices, \
1069 .num_eu_per_subslice = 16
1070
1071 #define dual_subslices(args...) { args, }
1072
1073 static const struct gen_device_info gen_device_info_tgl_1x2x16 = {
1074 GEN12_FEATURES(1, 1, dual_subslices(2), 8),
1075 };
1076
1077 static const struct gen_device_info gen_device_info_tgl_1x6x16 = {
1078 GEN12_FEATURES(2, 1, dual_subslices(6), 8),
1079 };
1080
1081 static void
1082 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1083 unsigned slice,
1084 unsigned subslice,
1085 unsigned eu_mask)
1086 {
1087 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1088 subslice * devinfo->eu_subslice_stride;
1089
1090 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1091 devinfo->eu_masks[subslice_offset + b_eu] =
1092 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1093 }
1094 }
1095
1096 /* Generate slice/subslice/eu masks from number of
1097 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1098 * structure.
1099 *
1100 * These can be overridden with values reported by the kernel either from
1101 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1102 * through the i915 query uapi.
1103 */
1104 static void
1105 fill_masks(struct gen_device_info *devinfo)
1106 {
1107 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1108
1109 /* Subslice masks */
1110 unsigned max_subslices = 0;
1111 for (int s = 0; s < devinfo->num_slices; s++)
1112 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1113 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1114
1115 for (int s = 0; s < devinfo->num_slices; s++) {
1116 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1117 (1U << devinfo->num_subslices[s]) - 1;
1118 }
1119
1120 /* EU masks */
1121 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1122 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1123
1124 for (int s = 0; s < devinfo->num_slices; s++) {
1125 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1126 gen_device_info_set_eu_mask(devinfo, s, ss,
1127 (1U << devinfo->num_eu_per_subslice) - 1);
1128 }
1129 }
1130 }
1131
1132 static void
1133 reset_masks(struct gen_device_info *devinfo)
1134 {
1135 devinfo->subslice_slice_stride = 0;
1136 devinfo->eu_subslice_stride = 0;
1137 devinfo->eu_slice_stride = 0;
1138
1139 devinfo->num_slices = 0;
1140 devinfo->num_eu_per_subslice = 0;
1141 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1142
1143 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1144 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1145 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1146 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1147 }
1148
1149 static void
1150 update_from_topology(struct gen_device_info *devinfo,
1151 const struct drm_i915_query_topology_info *topology)
1152 {
1153 reset_masks(devinfo);
1154
1155 devinfo->subslice_slice_stride = topology->subslice_stride;
1156
1157 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1158 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1159
1160 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1161 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1162 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1163
1164 uint32_t subslice_mask_len =
1165 topology->max_slices * topology->subslice_stride;
1166 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1167 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1168 subslice_mask_len);
1169
1170 uint32_t n_subslices = 0;
1171 for (int s = 0; s < topology->max_slices; s++) {
1172 if ((devinfo->slice_masks & (1 << s)) == 0)
1173 continue;
1174
1175 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1176 devinfo->num_subslices[s] +=
1177 __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1178 }
1179 n_subslices += devinfo->num_subslices[s];
1180 }
1181 assert(n_subslices > 0);
1182
1183 if (devinfo->gen == 11) {
1184 /* On ICL we only have one slice */
1185 assert(devinfo->slice_masks == 1);
1186
1187 /* Count the number of subslices on each pixel pipe. Assume that
1188 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1189 */
1190 unsigned subslices = devinfo->subslice_masks[0];
1191 unsigned ss = 0;
1192 while (subslices > 0) {
1193 if (subslices & 1)
1194 devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
1195 subslices >>= 1;
1196 ss++;
1197 }
1198 }
1199
1200 uint32_t eu_mask_len =
1201 topology->eu_stride * topology->max_subslices * topology->max_slices;
1202 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1203 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1204
1205 uint32_t n_eus = 0;
1206 for (int b = 0; b < eu_mask_len; b++)
1207 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1208
1209 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1210 }
1211
1212 static bool
1213 update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask,
1214 uint32_t subslice_mask, uint32_t n_eus)
1215 {
1216 struct drm_i915_query_topology_info *topology;
1217
1218 assert((slice_mask & 0xff) == slice_mask);
1219
1220 size_t data_length = 100;
1221
1222 topology = calloc(1, sizeof(*topology) + data_length);
1223 if (!topology)
1224 return false;
1225
1226 topology->max_slices = util_last_bit(slice_mask);
1227 topology->max_subslices = util_last_bit(subslice_mask);
1228
1229 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1230 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1231
1232 uint32_t n_subslices = __builtin_popcount(slice_mask) *
1233 __builtin_popcount(subslice_mask);
1234 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1235 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1236
1237 topology->eu_offset = topology->subslice_offset +
1238 DIV_ROUND_UP(topology->max_subslices, 8);
1239 topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1240
1241 /* Set slice mask in topology */
1242 for (int b = 0; b < topology->subslice_offset; b++)
1243 topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1244
1245 for (int s = 0; s < topology->max_slices; s++) {
1246
1247 /* Set subslice mask in topology */
1248 for (int b = 0; b < topology->subslice_stride; b++) {
1249 int subslice_offset = topology->subslice_offset +
1250 s * topology->subslice_stride + b;
1251
1252 topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1253 }
1254
1255 /* Set eu mask in topology */
1256 for (int ss = 0; ss < topology->max_subslices; ss++) {
1257 for (int b = 0; b < topology->eu_stride; b++) {
1258 int eu_offset = topology->eu_offset +
1259 (s * topology->max_subslices + ss) * topology->eu_stride + b;
1260
1261 topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1262 }
1263 }
1264 }
1265
1266 update_from_topology(devinfo, topology);
1267 free(topology);
1268
1269 return true;
1270 }
1271
1272 static bool
1273 getparam(int fd, uint32_t param, int *value)
1274 {
1275 int tmp;
1276
1277 struct drm_i915_getparam gp = {
1278 .param = param,
1279 .value = &tmp,
1280 };
1281
1282 int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
1283 if (ret != 0)
1284 return false;
1285
1286 *value = tmp;
1287 return true;
1288 }
1289
1290 bool
1291 gen_get_device_info_from_pci_id(int pci_id,
1292 struct gen_device_info *devinfo)
1293 {
1294 switch (pci_id) {
1295 #undef CHIPSET
1296 #define CHIPSET(id, family, name) \
1297 case id: *devinfo = gen_device_info_##family; break;
1298 #include "pci_ids/i965_pci_ids.h"
1299 #include "pci_ids/iris_pci_ids.h"
1300 default:
1301 fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id);
1302 return false;
1303 }
1304
1305 fill_masks(devinfo);
1306
1307 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1308 *
1309 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1310 * allocate scratch space enough so that each slice has 4 slices allowed."
1311 *
1312 * The equivalent internal documentation says that this programming note
1313 * applies to all Gen9+ platforms.
1314 *
1315 * The hardware typically calculates the scratch space pointer by taking
1316 * the base address, and adding per-thread-scratch-space * thread ID.
1317 * Extra padding can be necessary depending how the thread IDs are
1318 * calculated for a particular shader stage.
1319 */
1320
1321 switch(devinfo->gen) {
1322 case 9:
1323 case 10:
1324 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1325 * devinfo->num_slices
1326 * 4; /* effective subslices per slice */
1327 break;
1328 case 11:
1329 case 12:
1330 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1331 * devinfo->num_slices
1332 * 8; /* subslices per slice */
1333 break;
1334 default:
1335 assert(devinfo->gen < 9);
1336 break;
1337 }
1338
1339 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1340
1341 devinfo->chipset_id = pci_id;
1342 return true;
1343 }
1344
1345 const char *
1346 gen_get_device_name(int devid)
1347 {
1348 switch (devid) {
1349 #undef CHIPSET
1350 #define CHIPSET(id, family, name) case id: return name;
1351 #include "pci_ids/i965_pci_ids.h"
1352 #include "pci_ids/iris_pci_ids.h"
1353 default:
1354 return NULL;
1355 }
1356 }
1357
1358 /**
1359 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1360 * (kernel 4.13+)
1361 */
1362 static bool
1363 getparam_topology(struct gen_device_info *devinfo, int fd)
1364 {
1365 int slice_mask = 0;
1366 if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
1367 return false;
1368
1369 int n_eus;
1370 if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
1371 return false;
1372
1373 int subslice_mask = 0;
1374 if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
1375 return false;
1376
1377 return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1378 }
1379
1380 /**
1381 * preferred API for updating the topology in devinfo (kernel 4.17+)
1382 */
1383 static bool
1384 query_topology(struct gen_device_info *devinfo, int fd)
1385 {
1386 struct drm_i915_query_item item = {
1387 .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
1388 };
1389 struct drm_i915_query query = {
1390 .num_items = 1,
1391 .items_ptr = (uintptr_t) &item,
1392 };
1393
1394 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
1395 return false;
1396
1397 if (item.length < 0)
1398 return false;
1399
1400 struct drm_i915_query_topology_info *topo_info =
1401 (struct drm_i915_query_topology_info *) calloc(1, item.length);
1402 item.data_ptr = (uintptr_t) topo_info;
1403
1404 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
1405 item.length <= 0)
1406 return false;
1407
1408 update_from_topology(devinfo, topo_info);
1409
1410 free(topo_info);
1411
1412 return true;
1413
1414 }
1415
1416 bool
1417 gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
1418 {
1419 int devid = get_pci_device_id_override();
1420 if (devid > 0) {
1421 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1422 return false;
1423 devinfo->no_hw = true;
1424 } else {
1425 /* query the device id */
1426 if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
1427 return false;
1428 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1429 return false;
1430 devinfo->no_hw = false;
1431 }
1432
1433 /* remaining initializion queries the kernel for device info */
1434 if (devinfo->no_hw)
1435 return true;
1436
1437 int timestamp_frequency;
1438 if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1439 &timestamp_frequency))
1440 devinfo->timestamp_frequency = timestamp_frequency;
1441 else if (devinfo->gen >= 10)
1442 /* gen10 and later requires the timestamp_frequency to be updated */
1443 return false;
1444
1445 if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
1446 return false;
1447
1448 if (!query_topology(devinfo, fd)) {
1449 if (devinfo->gen >= 10) {
1450 /* topology uAPI required for CNL+ (kernel 4.17+) */
1451 return false;
1452 }
1453
1454 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1455 * will be wrong, affecting GPU metrics. In this case, fail silently.
1456 */
1457 getparam_topology(devinfo, fd);
1458 }
1459
1460 return true;
1461 }