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intel: devinfo: fix assertion on devices with odd number of EUs
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <unistd.h>
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/bitscan.h"
32 #include "util/macros.h"
33
34 #include <i915_drm.h>
35
36 /**
37 * Get the PCI ID for the device name.
38 *
39 * Returns -1 if the device is not known.
40 */
41 int
42 gen_device_name_to_pci_device_id(const char *name)
43 {
44 static const struct {
45 const char *name;
46 int pci_id;
47 } name_map[] = {
48 { "brw", 0x2a02 },
49 { "g4x", 0x2a42 },
50 { "ilk", 0x0042 },
51 { "snb", 0x0126 },
52 { "ivb", 0x016a },
53 { "hsw", 0x0d2e },
54 { "byt", 0x0f33 },
55 { "bdw", 0x162e },
56 { "chv", 0x22B3 },
57 { "skl", 0x1912 },
58 { "bxt", 0x5A85 },
59 { "kbl", 0x5912 },
60 { "glk", 0x3185 },
61 { "cfl", 0x3E9B },
62 { "cnl", 0x5a52 },
63 { "icl", 0x8a52 },
64 };
65
66 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
67 if (!strcmp(name_map[i].name, name))
68 return name_map[i].pci_id;
69 }
70
71 return -1;
72 }
73
74 /**
75 * Get the overridden PCI ID for the device. This is set with the
76 * INTEL_DEVID_OVERRIDE environment variable.
77 *
78 * Returns -1 if the override is not set.
79 */
80 int
81 gen_get_pci_device_id_override(void)
82 {
83 if (geteuid() == getuid()) {
84 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
85 if (devid_override) {
86 const int id = gen_device_name_to_pci_device_id(devid_override);
87 return id >= 0 ? id : strtol(devid_override, NULL, 0);
88 }
89 }
90
91 return -1;
92 }
93
94 static const struct gen_device_info gen_device_info_i965 = {
95 .gen = 4,
96 .has_negative_rhw_bug = true,
97 .num_slices = 1,
98 .num_subslices = { 1, },
99 .num_eu_per_subslice = 8,
100 .num_thread_per_eu = 4,
101 .max_vs_threads = 16,
102 .max_gs_threads = 2,
103 .max_wm_threads = 8 * 4,
104 .urb = {
105 .size = 256,
106 },
107 .timestamp_frequency = 12500000,
108 };
109
110 static const struct gen_device_info gen_device_info_g4x = {
111 .gen = 4,
112 .has_pln = true,
113 .has_compr4 = true,
114 .has_surface_tile_offset = true,
115 .is_g4x = true,
116 .num_slices = 1,
117 .num_subslices = { 1, },
118 .num_eu_per_subslice = 10,
119 .num_thread_per_eu = 5,
120 .max_vs_threads = 32,
121 .max_gs_threads = 2,
122 .max_wm_threads = 10 * 5,
123 .urb = {
124 .size = 384,
125 },
126 .timestamp_frequency = 12500000,
127 };
128
129 static const struct gen_device_info gen_device_info_ilk = {
130 .gen = 5,
131 .has_pln = true,
132 .has_compr4 = true,
133 .has_surface_tile_offset = true,
134 .num_slices = 1,
135 .num_subslices = { 1, },
136 .num_eu_per_subslice = 12,
137 .num_thread_per_eu = 6,
138 .max_vs_threads = 72,
139 .max_gs_threads = 32,
140 .max_wm_threads = 12 * 6,
141 .urb = {
142 .size = 1024,
143 },
144 .timestamp_frequency = 12500000,
145 };
146
147 static const struct gen_device_info gen_device_info_snb_gt1 = {
148 .gen = 6,
149 .gt = 1,
150 .has_hiz_and_separate_stencil = true,
151 .has_llc = true,
152 .has_pln = true,
153 .has_surface_tile_offset = true,
154 .needs_unlit_centroid_workaround = true,
155 .num_slices = 1,
156 .num_subslices = { 1, },
157 .num_eu_per_subslice = 6,
158 .num_thread_per_eu = 6, /* Not confirmed */
159 .max_vs_threads = 24,
160 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
161 .max_wm_threads = 40,
162 .urb = {
163 .size = 32,
164 .min_entries = {
165 [MESA_SHADER_VERTEX] = 24,
166 },
167 .max_entries = {
168 [MESA_SHADER_VERTEX] = 256,
169 [MESA_SHADER_GEOMETRY] = 256,
170 },
171 },
172 .timestamp_frequency = 12500000,
173 };
174
175 static const struct gen_device_info gen_device_info_snb_gt2 = {
176 .gen = 6,
177 .gt = 2,
178 .has_hiz_and_separate_stencil = true,
179 .has_llc = true,
180 .has_pln = true,
181 .has_surface_tile_offset = true,
182 .needs_unlit_centroid_workaround = true,
183 .num_slices = 1,
184 .num_subslices = { 1, },
185 .num_eu_per_subslice = 12,
186 .num_thread_per_eu = 6, /* Not confirmed */
187 .max_vs_threads = 60,
188 .max_gs_threads = 60,
189 .max_wm_threads = 80,
190 .urb = {
191 .size = 64,
192 .min_entries = {
193 [MESA_SHADER_VERTEX] = 24,
194 },
195 .max_entries = {
196 [MESA_SHADER_VERTEX] = 256,
197 [MESA_SHADER_GEOMETRY] = 256,
198 },
199 },
200 .timestamp_frequency = 12500000,
201 };
202
203 #define GEN7_FEATURES \
204 .gen = 7, \
205 .has_hiz_and_separate_stencil = true, \
206 .must_use_separate_stencil = true, \
207 .has_llc = true, \
208 .has_pln = true, \
209 .has_64bit_types = true, \
210 .has_surface_tile_offset = true, \
211 .timestamp_frequency = 12500000
212
213 static const struct gen_device_info gen_device_info_ivb_gt1 = {
214 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
215 .num_slices = 1,
216 .num_subslices = { 1, },
217 .num_eu_per_subslice = 6,
218 .num_thread_per_eu = 6,
219 .l3_banks = 2,
220 .max_vs_threads = 36,
221 .max_tcs_threads = 36,
222 .max_tes_threads = 36,
223 .max_gs_threads = 36,
224 .max_wm_threads = 48,
225 .max_cs_threads = 36,
226 .urb = {
227 .size = 128,
228 .min_entries = {
229 [MESA_SHADER_VERTEX] = 32,
230 [MESA_SHADER_TESS_EVAL] = 10,
231 },
232 .max_entries = {
233 [MESA_SHADER_VERTEX] = 512,
234 [MESA_SHADER_TESS_CTRL] = 32,
235 [MESA_SHADER_TESS_EVAL] = 288,
236 [MESA_SHADER_GEOMETRY] = 192,
237 },
238 },
239 };
240
241 static const struct gen_device_info gen_device_info_ivb_gt2 = {
242 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
243 .num_slices = 1,
244 .num_subslices = { 1, },
245 .num_eu_per_subslice = 12,
246 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
247 * @max_wm_threads ... */
248 .l3_banks = 4,
249 .max_vs_threads = 128,
250 .max_tcs_threads = 128,
251 .max_tes_threads = 128,
252 .max_gs_threads = 128,
253 .max_wm_threads = 172,
254 .max_cs_threads = 64,
255 .urb = {
256 .size = 256,
257 .min_entries = {
258 [MESA_SHADER_VERTEX] = 32,
259 [MESA_SHADER_TESS_EVAL] = 10,
260 },
261 .max_entries = {
262 [MESA_SHADER_VERTEX] = 704,
263 [MESA_SHADER_TESS_CTRL] = 64,
264 [MESA_SHADER_TESS_EVAL] = 448,
265 [MESA_SHADER_GEOMETRY] = 320,
266 },
267 },
268 };
269
270 static const struct gen_device_info gen_device_info_byt = {
271 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
272 .num_slices = 1,
273 .num_subslices = { 1, },
274 .num_eu_per_subslice = 4,
275 .num_thread_per_eu = 8,
276 .l3_banks = 1,
277 .has_llc = false,
278 .max_vs_threads = 36,
279 .max_tcs_threads = 36,
280 .max_tes_threads = 36,
281 .max_gs_threads = 36,
282 .max_wm_threads = 48,
283 .max_cs_threads = 32,
284 .urb = {
285 .size = 128,
286 .min_entries = {
287 [MESA_SHADER_VERTEX] = 32,
288 [MESA_SHADER_TESS_EVAL] = 10,
289 },
290 .max_entries = {
291 [MESA_SHADER_VERTEX] = 512,
292 [MESA_SHADER_TESS_CTRL] = 32,
293 [MESA_SHADER_TESS_EVAL] = 288,
294 [MESA_SHADER_GEOMETRY] = 192,
295 },
296 },
297 };
298
299 #define HSW_FEATURES \
300 GEN7_FEATURES, \
301 .is_haswell = true, \
302 .supports_simd16_3src = true, \
303 .has_resource_streamer = true
304
305 static const struct gen_device_info gen_device_info_hsw_gt1 = {
306 HSW_FEATURES, .gt = 1,
307 .num_slices = 1,
308 .num_subslices = { 1, },
309 .num_eu_per_subslice = 10,
310 .num_thread_per_eu = 7,
311 .l3_banks = 2,
312 .max_vs_threads = 70,
313 .max_tcs_threads = 70,
314 .max_tes_threads = 70,
315 .max_gs_threads = 70,
316 .max_wm_threads = 102,
317 .max_cs_threads = 70,
318 .urb = {
319 .size = 128,
320 .min_entries = {
321 [MESA_SHADER_VERTEX] = 32,
322 [MESA_SHADER_TESS_EVAL] = 10,
323 },
324 .max_entries = {
325 [MESA_SHADER_VERTEX] = 640,
326 [MESA_SHADER_TESS_CTRL] = 64,
327 [MESA_SHADER_TESS_EVAL] = 384,
328 [MESA_SHADER_GEOMETRY] = 256,
329 },
330 },
331 };
332
333 static const struct gen_device_info gen_device_info_hsw_gt2 = {
334 HSW_FEATURES, .gt = 2,
335 .num_slices = 1,
336 .num_subslices = { 2, },
337 .num_eu_per_subslice = 10,
338 .num_thread_per_eu = 7,
339 .l3_banks = 4,
340 .max_vs_threads = 280,
341 .max_tcs_threads = 256,
342 .max_tes_threads = 280,
343 .max_gs_threads = 256,
344 .max_wm_threads = 204,
345 .max_cs_threads = 70,
346 .urb = {
347 .size = 256,
348 .min_entries = {
349 [MESA_SHADER_VERTEX] = 64,
350 [MESA_SHADER_TESS_EVAL] = 10,
351 },
352 .max_entries = {
353 [MESA_SHADER_VERTEX] = 1664,
354 [MESA_SHADER_TESS_CTRL] = 128,
355 [MESA_SHADER_TESS_EVAL] = 960,
356 [MESA_SHADER_GEOMETRY] = 640,
357 },
358 },
359 };
360
361 static const struct gen_device_info gen_device_info_hsw_gt3 = {
362 HSW_FEATURES, .gt = 3,
363 .num_slices = 2,
364 .num_subslices = { 2, },
365 .num_eu_per_subslice = 10,
366 .num_thread_per_eu = 7,
367 .l3_banks = 8,
368 .max_vs_threads = 280,
369 .max_tcs_threads = 256,
370 .max_tes_threads = 280,
371 .max_gs_threads = 256,
372 .max_wm_threads = 408,
373 .max_cs_threads = 70,
374 .urb = {
375 .size = 512,
376 .min_entries = {
377 [MESA_SHADER_VERTEX] = 64,
378 [MESA_SHADER_TESS_EVAL] = 10,
379 },
380 .max_entries = {
381 [MESA_SHADER_VERTEX] = 1664,
382 [MESA_SHADER_TESS_CTRL] = 128,
383 [MESA_SHADER_TESS_EVAL] = 960,
384 [MESA_SHADER_GEOMETRY] = 640,
385 },
386 },
387 };
388
389 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
390 * so keep things conservative for now and set has_sample_with_hiz = false.
391 */
392 #define GEN8_FEATURES \
393 .gen = 8, \
394 .has_hiz_and_separate_stencil = true, \
395 .has_resource_streamer = true, \
396 .must_use_separate_stencil = true, \
397 .has_llc = true, \
398 .has_sample_with_hiz = false, \
399 .has_pln = true, \
400 .has_integer_dword_mul = true, \
401 .has_64bit_types = true, \
402 .supports_simd16_3src = true, \
403 .has_surface_tile_offset = true, \
404 .max_vs_threads = 504, \
405 .max_tcs_threads = 504, \
406 .max_tes_threads = 504, \
407 .max_gs_threads = 504, \
408 .max_wm_threads = 384, \
409 .timestamp_frequency = 12500000
410
411 static const struct gen_device_info gen_device_info_bdw_gt1 = {
412 GEN8_FEATURES, .gt = 1,
413 .is_broadwell = true,
414 .num_slices = 1,
415 .num_subslices = { 2, },
416 .num_eu_per_subslice = 8,
417 .num_thread_per_eu = 7,
418 .l3_banks = 2,
419 .max_cs_threads = 42,
420 .urb = {
421 .size = 192,
422 .min_entries = {
423 [MESA_SHADER_VERTEX] = 64,
424 [MESA_SHADER_TESS_EVAL] = 34,
425 },
426 .max_entries = {
427 [MESA_SHADER_VERTEX] = 2560,
428 [MESA_SHADER_TESS_CTRL] = 504,
429 [MESA_SHADER_TESS_EVAL] = 1536,
430 [MESA_SHADER_GEOMETRY] = 960,
431 },
432 }
433 };
434
435 static const struct gen_device_info gen_device_info_bdw_gt2 = {
436 GEN8_FEATURES, .gt = 2,
437 .is_broadwell = true,
438 .num_slices = 1,
439 .num_subslices = { 3, },
440 .num_eu_per_subslice = 8,
441 .num_thread_per_eu = 7,
442 .l3_banks = 4,
443 .max_cs_threads = 56,
444 .urb = {
445 .size = 384,
446 .min_entries = {
447 [MESA_SHADER_VERTEX] = 64,
448 [MESA_SHADER_TESS_EVAL] = 34,
449 },
450 .max_entries = {
451 [MESA_SHADER_VERTEX] = 2560,
452 [MESA_SHADER_TESS_CTRL] = 504,
453 [MESA_SHADER_TESS_EVAL] = 1536,
454 [MESA_SHADER_GEOMETRY] = 960,
455 },
456 }
457 };
458
459 static const struct gen_device_info gen_device_info_bdw_gt3 = {
460 GEN8_FEATURES, .gt = 3,
461 .is_broadwell = true,
462 .num_slices = 2,
463 .num_subslices = { 3, 3, },
464 .num_eu_per_subslice = 8,
465 .num_thread_per_eu = 7,
466 .l3_banks = 8,
467 .max_cs_threads = 56,
468 .urb = {
469 .size = 384,
470 .min_entries = {
471 [MESA_SHADER_VERTEX] = 64,
472 [MESA_SHADER_TESS_EVAL] = 34,
473 },
474 .max_entries = {
475 [MESA_SHADER_VERTEX] = 2560,
476 [MESA_SHADER_TESS_CTRL] = 504,
477 [MESA_SHADER_TESS_EVAL] = 1536,
478 [MESA_SHADER_GEOMETRY] = 960,
479 },
480 }
481 };
482
483 static const struct gen_device_info gen_device_info_chv = {
484 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
485 .has_llc = false,
486 .has_integer_dword_mul = false,
487 .num_slices = 1,
488 .num_subslices = { 2, },
489 .num_eu_per_subslice = 8,
490 .num_thread_per_eu = 7,
491 .l3_banks = 2,
492 .max_vs_threads = 80,
493 .max_tcs_threads = 80,
494 .max_tes_threads = 80,
495 .max_gs_threads = 80,
496 .max_wm_threads = 128,
497 .max_cs_threads = 6 * 7,
498 .urb = {
499 .size = 192,
500 .min_entries = {
501 [MESA_SHADER_VERTEX] = 34,
502 [MESA_SHADER_TESS_EVAL] = 34,
503 },
504 .max_entries = {
505 [MESA_SHADER_VERTEX] = 640,
506 [MESA_SHADER_TESS_CTRL] = 80,
507 [MESA_SHADER_TESS_EVAL] = 384,
508 [MESA_SHADER_GEOMETRY] = 256,
509 },
510 }
511 };
512
513 #define GEN9_HW_INFO \
514 .gen = 9, \
515 .max_vs_threads = 336, \
516 .max_gs_threads = 336, \
517 .max_tcs_threads = 336, \
518 .max_tes_threads = 336, \
519 .max_cs_threads = 56, \
520 .timestamp_frequency = 12000000, \
521 .urb = { \
522 .size = 384, \
523 .min_entries = { \
524 [MESA_SHADER_VERTEX] = 64, \
525 [MESA_SHADER_TESS_EVAL] = 34, \
526 }, \
527 .max_entries = { \
528 [MESA_SHADER_VERTEX] = 1856, \
529 [MESA_SHADER_TESS_CTRL] = 672, \
530 [MESA_SHADER_TESS_EVAL] = 1120, \
531 [MESA_SHADER_GEOMETRY] = 640, \
532 }, \
533 }
534
535 #define GEN9_LP_FEATURES \
536 GEN8_FEATURES, \
537 GEN9_HW_INFO, \
538 .has_integer_dword_mul = false, \
539 .gt = 1, \
540 .has_llc = false, \
541 .has_sample_with_hiz = true, \
542 .num_slices = 1, \
543 .num_thread_per_eu = 6, \
544 .max_vs_threads = 112, \
545 .max_tcs_threads = 112, \
546 .max_tes_threads = 112, \
547 .max_gs_threads = 112, \
548 .max_cs_threads = 6 * 6, \
549 .timestamp_frequency = 19200000, \
550 .urb = { \
551 .size = 192, \
552 .min_entries = { \
553 [MESA_SHADER_VERTEX] = 34, \
554 [MESA_SHADER_TESS_EVAL] = 34, \
555 }, \
556 .max_entries = { \
557 [MESA_SHADER_VERTEX] = 704, \
558 [MESA_SHADER_TESS_CTRL] = 256, \
559 [MESA_SHADER_TESS_EVAL] = 416, \
560 [MESA_SHADER_GEOMETRY] = 256, \
561 }, \
562 }
563
564 #define GEN9_LP_FEATURES_3X6 \
565 GEN9_LP_FEATURES, \
566 .num_subslices = { 3, }, \
567 .num_eu_per_subslice = 6
568
569 #define GEN9_LP_FEATURES_2X6 \
570 GEN9_LP_FEATURES, \
571 .num_subslices = { 2, }, \
572 .num_eu_per_subslice = 6, \
573 .max_vs_threads = 56, \
574 .max_tcs_threads = 56, \
575 .max_tes_threads = 56, \
576 .max_gs_threads = 56, \
577 .max_cs_threads = 6 * 6, \
578 .urb = { \
579 .size = 128, \
580 .min_entries = { \
581 [MESA_SHADER_VERTEX] = 34, \
582 [MESA_SHADER_TESS_EVAL] = 34, \
583 }, \
584 .max_entries = { \
585 [MESA_SHADER_VERTEX] = 352, \
586 [MESA_SHADER_TESS_CTRL] = 128, \
587 [MESA_SHADER_TESS_EVAL] = 208, \
588 [MESA_SHADER_GEOMETRY] = 128, \
589 }, \
590 }
591
592 #define GEN9_FEATURES \
593 GEN8_FEATURES, \
594 GEN9_HW_INFO, \
595 .has_sample_with_hiz = true, \
596 .num_thread_per_eu = 7
597
598 static const struct gen_device_info gen_device_info_skl_gt1 = {
599 GEN9_FEATURES, .gt = 1,
600 .is_skylake = true,
601 .num_slices = 1,
602 .num_subslices = { 2, },
603 .num_eu_per_subslice = 6,
604 .l3_banks = 2,
605 .urb.size = 192,
606 };
607
608 static const struct gen_device_info gen_device_info_skl_gt2 = {
609 GEN9_FEATURES, .gt = 2,
610 .is_skylake = true,
611 .num_slices = 1,
612 .num_subslices = { 3, },
613 .num_eu_per_subslice = 8,
614 .l3_banks = 4,
615 };
616
617 static const struct gen_device_info gen_device_info_skl_gt3 = {
618 GEN9_FEATURES, .gt = 3,
619 .is_skylake = true,
620 .num_slices = 2,
621 .num_subslices = { 3, 3, },
622 .num_eu_per_subslice = 8,
623 .l3_banks = 8,
624 };
625
626 static const struct gen_device_info gen_device_info_skl_gt4 = {
627 GEN9_FEATURES, .gt = 4,
628 .is_skylake = true,
629 .num_slices = 3,
630 .num_subslices = { 3, 3, 3, },
631 .num_eu_per_subslice = 8,
632 .l3_banks = 12,
633 /* From the "L3 Allocation and Programming" documentation:
634 *
635 * "URB is limited to 1008KB due to programming restrictions. This is not a
636 * restriction of the L3 implementation, but of the FF and other clients.
637 * Therefore, in a GT4 implementation it is possible for the programmed
638 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
639 * only 1008KB of this will be used."
640 */
641 .urb.size = 1008 / 3,
642 };
643
644 static const struct gen_device_info gen_device_info_bxt = {
645 GEN9_LP_FEATURES_3X6,
646 .is_broxton = true,
647 .l3_banks = 2,
648 };
649
650 static const struct gen_device_info gen_device_info_bxt_2x6 = {
651 GEN9_LP_FEATURES_2X6,
652 .is_broxton = true,
653 .l3_banks = 1,
654 };
655 /*
656 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
657 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
658 */
659
660 static const struct gen_device_info gen_device_info_kbl_gt1 = {
661 GEN9_FEATURES,
662 .is_kabylake = true,
663 .gt = 1,
664
665 .max_cs_threads = 7 * 6,
666 .urb.size = 192,
667 .num_slices = 1,
668 .num_subslices = { 2, },
669 .num_eu_per_subslice = 6,
670 .l3_banks = 2,
671 };
672
673 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
674 GEN9_FEATURES,
675 .is_kabylake = true,
676 .gt = 1,
677
678 .max_cs_threads = 7 * 6,
679 .num_slices = 1,
680 .num_subslices = { 3, },
681 .num_eu_per_subslice = 6,
682 .l3_banks = 4,
683 };
684
685 static const struct gen_device_info gen_device_info_kbl_gt2 = {
686 GEN9_FEATURES,
687 .is_kabylake = true,
688 .gt = 2,
689
690 .num_slices = 1,
691 .num_subslices = { 3, },
692 .num_eu_per_subslice = 8,
693 .l3_banks = 4,
694 };
695
696 static const struct gen_device_info gen_device_info_kbl_gt3 = {
697 GEN9_FEATURES,
698 .is_kabylake = true,
699 .gt = 3,
700
701 .num_slices = 2,
702 .num_subslices = { 3, 3, },
703 .num_eu_per_subslice = 8,
704 .l3_banks = 8,
705 };
706
707 static const struct gen_device_info gen_device_info_kbl_gt4 = {
708 GEN9_FEATURES,
709 .is_kabylake = true,
710 .gt = 4,
711
712 /*
713 * From the "L3 Allocation and Programming" documentation:
714 *
715 * "URB is limited to 1008KB due to programming restrictions. This
716 * is not a restriction of the L3 implementation, but of the FF and
717 * other clients. Therefore, in a GT4 implementation it is
718 * possible for the programmed allocation of the L3 data array to
719 * provide 3*384KB=1152KB for URB, but only 1008KB of this
720 * will be used."
721 */
722 .urb.size = 1008 / 3,
723 .num_slices = 3,
724 .num_subslices = { 3, 3, 3, },
725 .num_eu_per_subslice = 8,
726 .l3_banks = 12,
727 };
728
729 static const struct gen_device_info gen_device_info_glk = {
730 GEN9_LP_FEATURES_3X6,
731 .is_geminilake = true,
732 .l3_banks = 2,
733 };
734
735 /*TODO: Initialize l3_banks when we know the number. */
736 static const struct gen_device_info gen_device_info_glk_2x6 = {
737 GEN9_LP_FEATURES_2X6,
738 .is_geminilake = true,
739 };
740
741 static const struct gen_device_info gen_device_info_cfl_gt1 = {
742 GEN9_FEATURES,
743 .is_coffeelake = true,
744 .gt = 1,
745
746 .num_slices = 1,
747 .num_subslices = { 2, },
748 .num_eu_per_subslice = 6,
749 .l3_banks = 2,
750 };
751 static const struct gen_device_info gen_device_info_cfl_gt2 = {
752 GEN9_FEATURES,
753 .is_coffeelake = true,
754 .gt = 2,
755
756 .num_slices = 1,
757 .num_subslices = { 3, },
758 .num_eu_per_subslice = 8,
759 .l3_banks = 4,
760 };
761
762 static const struct gen_device_info gen_device_info_cfl_gt3 = {
763 GEN9_FEATURES,
764 .is_coffeelake = true,
765 .gt = 3,
766
767 .num_slices = 2,
768 .num_subslices = { 3, 3, },
769 .num_eu_per_subslice = 8,
770 .l3_banks = 8,
771 };
772
773 #define GEN10_HW_INFO \
774 .gen = 10, \
775 .num_thread_per_eu = 7, \
776 .max_vs_threads = 728, \
777 .max_gs_threads = 432, \
778 .max_tcs_threads = 432, \
779 .max_tes_threads = 624, \
780 .max_cs_threads = 56, \
781 .timestamp_frequency = 19200000, \
782 .urb = { \
783 .size = 256, \
784 .min_entries = { \
785 [MESA_SHADER_VERTEX] = 64, \
786 [MESA_SHADER_TESS_EVAL] = 34, \
787 }, \
788 .max_entries = { \
789 [MESA_SHADER_VERTEX] = 3936, \
790 [MESA_SHADER_TESS_CTRL] = 896, \
791 [MESA_SHADER_TESS_EVAL] = 2064, \
792 [MESA_SHADER_GEOMETRY] = 832, \
793 }, \
794 }
795
796 #define subslices(args...) { args, }
797
798 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
799 GEN8_FEATURES, \
800 GEN10_HW_INFO, \
801 .has_sample_with_hiz = true, \
802 .gt = _gt, \
803 .num_slices = _slices, \
804 .num_subslices = _subslices, \
805 .num_eu_per_subslice = 8, \
806 .l3_banks = _l3
807
808 static const struct gen_device_info gen_device_info_cnl_2x8 = {
809 /* GT0.5 */
810 GEN10_FEATURES(1, 1, subslices(2), 2),
811 .is_cannonlake = true,
812 };
813
814 static const struct gen_device_info gen_device_info_cnl_3x8 = {
815 /* GT1 */
816 GEN10_FEATURES(1, 1, subslices(3), 3),
817 .is_cannonlake = true,
818 };
819
820 static const struct gen_device_info gen_device_info_cnl_4x8 = {
821 /* GT 1.5 */
822 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
823 .is_cannonlake = true,
824 };
825
826 static const struct gen_device_info gen_device_info_cnl_5x8 = {
827 /* GT2 */
828 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
829 .is_cannonlake = true,
830 };
831
832 #define GEN11_HW_INFO \
833 .gen = 11, \
834 .has_pln = false, \
835 .max_vs_threads = 364, \
836 .max_gs_threads = 224, \
837 .max_tcs_threads = 224, \
838 .max_tes_threads = 364, \
839 .max_cs_threads = 56, \
840 .urb = { \
841 .size = 1024, \
842 .min_entries = { \
843 [MESA_SHADER_VERTEX] = 64, \
844 [MESA_SHADER_TESS_EVAL] = 34, \
845 }, \
846 .max_entries = { \
847 [MESA_SHADER_VERTEX] = 2384, \
848 [MESA_SHADER_TESS_CTRL] = 1032, \
849 [MESA_SHADER_TESS_EVAL] = 2384, \
850 [MESA_SHADER_GEOMETRY] = 1032, \
851 }, \
852 }
853
854 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
855 GEN8_FEATURES, \
856 GEN11_HW_INFO, \
857 .has_64bit_types = false, \
858 .has_integer_dword_mul = false, \
859 .has_sample_with_hiz = false, \
860 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
861 .num_subslices = _subslices, \
862 .num_eu_per_subslice = 8
863
864 static const struct gen_device_info gen_device_info_icl_8x8 = {
865 GEN11_FEATURES(2, 1, subslices(8), 8),
866 };
867
868 static const struct gen_device_info gen_device_info_icl_6x8 = {
869 GEN11_FEATURES(1, 1, subslices(6), 6),
870 };
871
872 static const struct gen_device_info gen_device_info_icl_4x8 = {
873 GEN11_FEATURES(1, 1, subslices(4), 6),
874 };
875
876 static const struct gen_device_info gen_device_info_icl_1x8 = {
877 GEN11_FEATURES(1, 1, subslices(1), 6),
878 };
879
880 static void
881 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
882 unsigned slice,
883 unsigned subslice,
884 unsigned eu_mask)
885 {
886 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
887 subslice * devinfo->eu_subslice_stride;
888
889 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
890 devinfo->eu_masks[subslice_offset + b_eu] =
891 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
892 }
893 }
894
895 /* Generate slice/subslice/eu masks from number of
896 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
897 * structure.
898 *
899 * These can be overridden with values reported by the kernel either from
900 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
901 * through the i915 query uapi.
902 */
903 static void
904 fill_masks(struct gen_device_info *devinfo)
905 {
906 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
907
908 /* Subslice masks */
909 unsigned max_subslices = 0;
910 for (int s = 0; s < devinfo->num_slices; s++)
911 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
912 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
913
914 for (int s = 0; s < devinfo->num_slices; s++) {
915 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
916 (1U << devinfo->num_subslices[s]) - 1;
917 }
918
919 /* EU masks */
920 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
921 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
922
923 for (int s = 0; s < devinfo->num_slices; s++) {
924 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
925 gen_device_info_set_eu_mask(devinfo, s, ss,
926 (1U << devinfo->num_eu_per_subslice) - 1);
927 }
928 }
929 }
930
931 void
932 gen_device_info_update_from_masks(struct gen_device_info *devinfo,
933 uint32_t slice_mask,
934 uint32_t subslice_mask,
935 uint32_t n_eus)
936 {
937 struct {
938 struct drm_i915_query_topology_info base;
939 uint8_t data[100];
940 } topology;
941
942 assert((slice_mask & 0xff) == slice_mask);
943
944 memset(&topology, 0, sizeof(topology));
945
946 topology.base.max_slices = util_last_bit(slice_mask);
947 topology.base.max_subslices = util_last_bit(subslice_mask);
948
949 topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
950 topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices, 8);
951
952 uint32_t n_subslices = __builtin_popcount(slice_mask) *
953 __builtin_popcount(subslice_mask);
954 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
955 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
956
957 topology.base.eu_offset = topology.base.subslice_offset +
958 DIV_ROUND_UP(topology.base.max_subslices, 8);
959 topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
960
961 /* Set slice mask in topology */
962 for (int b = 0; b < topology.base.subslice_offset; b++)
963 topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
964
965 for (int s = 0; s < topology.base.max_slices; s++) {
966
967 /* Set subslice mask in topology */
968 for (int b = 0; b < topology.base.subslice_stride; b++) {
969 int subslice_offset = topology.base.subslice_offset +
970 s * topology.base.subslice_stride + b;
971
972 topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
973 }
974
975 /* Set eu mask in topology */
976 for (int ss = 0; ss < topology.base.max_subslices; ss++) {
977 for (int b = 0; b < topology.base.eu_stride; b++) {
978 int eu_offset = topology.base.eu_offset +
979 (s * topology.base.max_subslices + ss) * topology.base.eu_stride + b;
980
981 topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
982 }
983 }
984 }
985
986 gen_device_info_update_from_topology(devinfo, &topology.base);
987 }
988
989 static void
990 reset_masks(struct gen_device_info *devinfo)
991 {
992 devinfo->subslice_slice_stride = 0;
993 devinfo->eu_subslice_stride = 0;
994 devinfo->eu_slice_stride = 0;
995
996 devinfo->num_slices = 0;
997 devinfo->num_eu_per_subslice = 0;
998 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
999
1000 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1001 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1002 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1003 }
1004
1005 void
1006 gen_device_info_update_from_topology(struct gen_device_info *devinfo,
1007 const struct drm_i915_query_topology_info *topology)
1008 {
1009 reset_masks(devinfo);
1010
1011 devinfo->subslice_slice_stride = topology->subslice_stride;
1012
1013 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1014 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1015
1016 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1017 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1018 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1019
1020 uint32_t subslice_mask_len =
1021 topology->max_slices * topology->subslice_stride;
1022 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1023 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1024 subslice_mask_len);
1025
1026 uint32_t n_subslices = 0;
1027 for (int s = 0; s < topology->max_slices; s++) {
1028 if ((devinfo->slice_masks & (1UL << s)) == 0)
1029 continue;
1030
1031 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1032 devinfo->num_subslices[s] +=
1033 __builtin_popcount(devinfo->subslice_masks[b]);
1034 }
1035 n_subslices += devinfo->num_subslices[s];
1036 }
1037
1038 uint32_t eu_mask_len =
1039 topology->eu_stride * topology->max_subslices * topology->max_slices;
1040 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1041 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1042
1043 uint32_t n_eus = 0;
1044 for (int b = 0; b < eu_mask_len; b++)
1045 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1046
1047 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1048 }
1049
1050 bool
1051 gen_get_device_info(int devid, struct gen_device_info *devinfo)
1052 {
1053 switch (devid) {
1054 #undef CHIPSET
1055 #define CHIPSET(id, family, name) \
1056 case id: *devinfo = gen_device_info_##family; break;
1057 #include "pci_ids/i965_pci_ids.h"
1058 default:
1059 fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
1060 return false;
1061 }
1062
1063 fill_masks(devinfo);
1064
1065 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1066 *
1067 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1068 * allocate scratch space enough so that each slice has 4 slices allowed."
1069 *
1070 * The equivalent internal documentation says that this programming note
1071 * applies to all Gen9+ platforms.
1072 *
1073 * The hardware typically calculates the scratch space pointer by taking
1074 * the base address, and adding per-thread-scratch-space * thread ID.
1075 * Extra padding can be necessary depending how the thread IDs are
1076 * calculated for a particular shader stage.
1077 */
1078
1079 switch(devinfo->gen) {
1080 case 9:
1081 case 10:
1082 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1083 * devinfo->num_slices
1084 * 4; /* effective subslices per slice */
1085 break;
1086 case 11:
1087 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1088 * devinfo->num_slices
1089 * 8; /* subslices per slice */
1090 break;
1091 default:
1092 break;
1093 }
1094
1095 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1096
1097 return true;
1098 }
1099
1100 const char *
1101 gen_get_device_name(int devid)
1102 {
1103 switch (devid) {
1104 #undef CHIPSET
1105 #define CHIPSET(id, family, name) case id: return name;
1106 #include "pci_ids/i965_pci_ids.h"
1107 default:
1108 return NULL;
1109 }
1110 }