projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
intel/dev: Split .num_subslices out of GEN12_FEATURES macro
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
35
36 #include "drm-uapi/i915_drm.h"
37
38 static const struct {
39 const char *name;
40 int pci_id;
41 } name_map[] = {
42 { "brw", 0x2a02 },
43 { "g4x", 0x2a42 },
44 { "ilk", 0x0042 },
45 { "snb", 0x0126 },
46 { "ivb", 0x016a },
47 { "hsw", 0x0d2e },
48 { "byt", 0x0f33 },
49 { "bdw", 0x162e },
50 { "chv", 0x22B3 },
51 { "skl", 0x1912 },
52 { "bxt", 0x5A85 },
53 { "kbl", 0x5912 },
54 { "aml", 0x591C },
55 { "glk", 0x3185 },
56 { "cfl", 0x3E9B },
57 { "whl", 0x3EA1 },
58 { "cml", 0x9b41 },
59 { "cnl", 0x5a52 },
60 { "icl", 0x8a52 },
61 { "ehl", 0x4500 },
62 { "jsl", 0x4E71 },
63 { "tgl", 0x9a49 },
64 };
65
66 /**
67 * Get the PCI ID for the device name.
68 *
69 * Returns -1 if the device is not known.
70 */
71 int
72 gen_device_name_to_pci_device_id(const char *name)
73 {
74 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
75 if (!strcmp(name_map[i].name, name))
76 return name_map[i].pci_id;
77 }
78
79 return -1;
80 }
81
82 static const struct gen_device_info gen_device_info_i965 = {
83 .gen = 4,
84 .has_negative_rhw_bug = true,
85 .num_slices = 1,
86 .num_subslices = { 1, },
87 .num_eu_per_subslice = 8,
88 .num_thread_per_eu = 4,
89 .max_vs_threads = 16,
90 .max_gs_threads = 2,
91 .max_wm_threads = 8 * 4,
92 .urb = {
93 .size = 256,
94 },
95 .timestamp_frequency = 12500000,
96 .simulator_id = -1,
97 };
98
99 static const struct gen_device_info gen_device_info_g4x = {
100 .gen = 4,
101 .has_pln = true,
102 .has_compr4 = true,
103 .has_surface_tile_offset = true,
104 .is_g4x = true,
105 .num_slices = 1,
106 .num_subslices = { 1, },
107 .num_eu_per_subslice = 10,
108 .num_thread_per_eu = 5,
109 .max_vs_threads = 32,
110 .max_gs_threads = 2,
111 .max_wm_threads = 10 * 5,
112 .urb = {
113 .size = 384,
114 },
115 .timestamp_frequency = 12500000,
116 .simulator_id = -1,
117 };
118
119 static const struct gen_device_info gen_device_info_ilk = {
120 .gen = 5,
121 .has_pln = true,
122 .has_compr4 = true,
123 .has_surface_tile_offset = true,
124 .num_slices = 1,
125 .num_subslices = { 1, },
126 .num_eu_per_subslice = 12,
127 .num_thread_per_eu = 6,
128 .max_vs_threads = 72,
129 .max_gs_threads = 32,
130 .max_wm_threads = 12 * 6,
131 .urb = {
132 .size = 1024,
133 },
134 .timestamp_frequency = 12500000,
135 .simulator_id = -1,
136 };
137
138 static const struct gen_device_info gen_device_info_snb_gt1 = {
139 .gen = 6,
140 .gt = 1,
141 .has_hiz_and_separate_stencil = true,
142 .has_llc = true,
143 .has_pln = true,
144 .has_surface_tile_offset = true,
145 .needs_unlit_centroid_workaround = true,
146 .num_slices = 1,
147 .num_subslices = { 1, },
148 .num_eu_per_subslice = 6,
149 .num_thread_per_eu = 6, /* Not confirmed */
150 .max_vs_threads = 24,
151 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
152 .max_wm_threads = 40,
153 .urb = {
154 .size = 32,
155 .min_entries = {
156 [MESA_SHADER_VERTEX] = 24,
157 },
158 .max_entries = {
159 [MESA_SHADER_VERTEX] = 256,
160 [MESA_SHADER_GEOMETRY] = 256,
161 },
162 },
163 .timestamp_frequency = 12500000,
164 .simulator_id = -1,
165 };
166
167 static const struct gen_device_info gen_device_info_snb_gt2 = {
168 .gen = 6,
169 .gt = 2,
170 .has_hiz_and_separate_stencil = true,
171 .has_llc = true,
172 .has_pln = true,
173 .has_surface_tile_offset = true,
174 .needs_unlit_centroid_workaround = true,
175 .num_slices = 1,
176 .num_subslices = { 1, },
177 .num_eu_per_subslice = 12,
178 .num_thread_per_eu = 6, /* Not confirmed */
179 .max_vs_threads = 60,
180 .max_gs_threads = 60,
181 .max_wm_threads = 80,
182 .urb = {
183 .size = 64,
184 .min_entries = {
185 [MESA_SHADER_VERTEX] = 24,
186 },
187 .max_entries = {
188 [MESA_SHADER_VERTEX] = 256,
189 [MESA_SHADER_GEOMETRY] = 256,
190 },
191 },
192 .timestamp_frequency = 12500000,
193 .simulator_id = -1,
194 };
195
196 #define GEN7_FEATURES \
197 .gen = 7, \
198 .has_hiz_and_separate_stencil = true, \
199 .must_use_separate_stencil = true, \
200 .has_llc = true, \
201 .has_pln = true, \
202 .has_64bit_float = true, \
203 .has_surface_tile_offset = true, \
204 .timestamp_frequency = 12500000
205
206 static const struct gen_device_info gen_device_info_ivb_gt1 = {
207 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
208 .num_slices = 1,
209 .num_subslices = { 1, },
210 .num_eu_per_subslice = 6,
211 .num_thread_per_eu = 6,
212 .l3_banks = 2,
213 .max_vs_threads = 36,
214 .max_tcs_threads = 36,
215 .max_tes_threads = 36,
216 .max_gs_threads = 36,
217 .max_wm_threads = 48,
218 .max_cs_threads = 36,
219 .urb = {
220 .size = 128,
221 .min_entries = {
222 [MESA_SHADER_VERTEX] = 32,
223 [MESA_SHADER_TESS_EVAL] = 10,
224 },
225 .max_entries = {
226 [MESA_SHADER_VERTEX] = 512,
227 [MESA_SHADER_TESS_CTRL] = 32,
228 [MESA_SHADER_TESS_EVAL] = 288,
229 [MESA_SHADER_GEOMETRY] = 192,
230 },
231 },
232 .simulator_id = 7,
233 };
234
235 static const struct gen_device_info gen_device_info_ivb_gt2 = {
236 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
237 .num_slices = 1,
238 .num_subslices = { 1, },
239 .num_eu_per_subslice = 12,
240 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
241 * @max_wm_threads ... */
242 .l3_banks = 4,
243 .max_vs_threads = 128,
244 .max_tcs_threads = 128,
245 .max_tes_threads = 128,
246 .max_gs_threads = 128,
247 .max_wm_threads = 172,
248 .max_cs_threads = 64,
249 .urb = {
250 .size = 256,
251 .min_entries = {
252 [MESA_SHADER_VERTEX] = 32,
253 [MESA_SHADER_TESS_EVAL] = 10,
254 },
255 .max_entries = {
256 [MESA_SHADER_VERTEX] = 704,
257 [MESA_SHADER_TESS_CTRL] = 64,
258 [MESA_SHADER_TESS_EVAL] = 448,
259 [MESA_SHADER_GEOMETRY] = 320,
260 },
261 },
262 .simulator_id = 7,
263 };
264
265 static const struct gen_device_info gen_device_info_byt = {
266 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
267 .num_slices = 1,
268 .num_subslices = { 1, },
269 .num_eu_per_subslice = 4,
270 .num_thread_per_eu = 8,
271 .l3_banks = 1,
272 .has_llc = false,
273 .max_vs_threads = 36,
274 .max_tcs_threads = 36,
275 .max_tes_threads = 36,
276 .max_gs_threads = 36,
277 .max_wm_threads = 48,
278 .max_cs_threads = 32,
279 .urb = {
280 .size = 128,
281 .min_entries = {
282 [MESA_SHADER_VERTEX] = 32,
283 [MESA_SHADER_TESS_EVAL] = 10,
284 },
285 .max_entries = {
286 [MESA_SHADER_VERTEX] = 512,
287 [MESA_SHADER_TESS_CTRL] = 32,
288 [MESA_SHADER_TESS_EVAL] = 288,
289 [MESA_SHADER_GEOMETRY] = 192,
290 },
291 },
292 .simulator_id = 10,
293 };
294
295 #define HSW_FEATURES \
296 GEN7_FEATURES, \
297 .is_haswell = true, \
298 .supports_simd16_3src = true, \
299 .has_resource_streamer = true
300
301 static const struct gen_device_info gen_device_info_hsw_gt1 = {
302 HSW_FEATURES, .gt = 1,
303 .num_slices = 1,
304 .num_subslices = { 1, },
305 .num_eu_per_subslice = 10,
306 .num_thread_per_eu = 7,
307 .l3_banks = 2,
308 .max_vs_threads = 70,
309 .max_tcs_threads = 70,
310 .max_tes_threads = 70,
311 .max_gs_threads = 70,
312 .max_wm_threads = 102,
313 .max_cs_threads = 70,
314 .urb = {
315 .size = 128,
316 .min_entries = {
317 [MESA_SHADER_VERTEX] = 32,
318 [MESA_SHADER_TESS_EVAL] = 10,
319 },
320 .max_entries = {
321 [MESA_SHADER_VERTEX] = 640,
322 [MESA_SHADER_TESS_CTRL] = 64,
323 [MESA_SHADER_TESS_EVAL] = 384,
324 [MESA_SHADER_GEOMETRY] = 256,
325 },
326 },
327 .simulator_id = 9,
328 };
329
330 static const struct gen_device_info gen_device_info_hsw_gt2 = {
331 HSW_FEATURES, .gt = 2,
332 .num_slices = 1,
333 .num_subslices = { 2, },
334 .num_eu_per_subslice = 10,
335 .num_thread_per_eu = 7,
336 .l3_banks = 4,
337 .max_vs_threads = 280,
338 .max_tcs_threads = 256,
339 .max_tes_threads = 280,
340 .max_gs_threads = 256,
341 .max_wm_threads = 204,
342 .max_cs_threads = 70,
343 .urb = {
344 .size = 256,
345 .min_entries = {
346 [MESA_SHADER_VERTEX] = 64,
347 [MESA_SHADER_TESS_EVAL] = 10,
348 },
349 .max_entries = {
350 [MESA_SHADER_VERTEX] = 1664,
351 [MESA_SHADER_TESS_CTRL] = 128,
352 [MESA_SHADER_TESS_EVAL] = 960,
353 [MESA_SHADER_GEOMETRY] = 640,
354 },
355 },
356 .simulator_id = 9,
357 };
358
359 static const struct gen_device_info gen_device_info_hsw_gt3 = {
360 HSW_FEATURES, .gt = 3,
361 .num_slices = 2,
362 .num_subslices = { 2, },
363 .num_eu_per_subslice = 10,
364 .num_thread_per_eu = 7,
365 .l3_banks = 8,
366 .max_vs_threads = 280,
367 .max_tcs_threads = 256,
368 .max_tes_threads = 280,
369 .max_gs_threads = 256,
370 .max_wm_threads = 408,
371 .max_cs_threads = 70,
372 .urb = {
373 .size = 512,
374 .min_entries = {
375 [MESA_SHADER_VERTEX] = 64,
376 [MESA_SHADER_TESS_EVAL] = 10,
377 },
378 .max_entries = {
379 [MESA_SHADER_VERTEX] = 1664,
380 [MESA_SHADER_TESS_CTRL] = 128,
381 [MESA_SHADER_TESS_EVAL] = 960,
382 [MESA_SHADER_GEOMETRY] = 640,
383 },
384 },
385 .simulator_id = 9,
386 };
387
388 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
389 * so keep things conservative for now and set has_sample_with_hiz = false.
390 */
391 #define GEN8_FEATURES \
392 .gen = 8, \
393 .has_hiz_and_separate_stencil = true, \
394 .has_resource_streamer = true, \
395 .must_use_separate_stencil = true, \
396 .has_llc = true, \
397 .has_sample_with_hiz = false, \
398 .has_pln = true, \
399 .has_integer_dword_mul = true, \
400 .has_64bit_float = true, \
401 .has_64bit_int = true, \
402 .supports_simd16_3src = true, \
403 .has_surface_tile_offset = true, \
404 .num_thread_per_eu = 7, \
405 .max_vs_threads = 504, \
406 .max_tcs_threads = 504, \
407 .max_tes_threads = 504, \
408 .max_gs_threads = 504, \
409 .max_wm_threads = 384, \
410 .timestamp_frequency = 12500000
411
412 static const struct gen_device_info gen_device_info_bdw_gt1 = {
413 GEN8_FEATURES, .gt = 1,
414 .is_broadwell = true,
415 .num_slices = 1,
416 .num_subslices = { 2, },
417 .num_eu_per_subslice = 6,
418 .l3_banks = 2,
419 .max_cs_threads = 42,
420 .urb = {
421 .size = 192,
422 .min_entries = {
423 [MESA_SHADER_VERTEX] = 64,
424 [MESA_SHADER_TESS_EVAL] = 34,
425 },
426 .max_entries = {
427 [MESA_SHADER_VERTEX] = 2560,
428 [MESA_SHADER_TESS_CTRL] = 504,
429 [MESA_SHADER_TESS_EVAL] = 1536,
430 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
431 [MESA_SHADER_GEOMETRY] = 690,
432 },
433 },
434 .simulator_id = 11,
435 };
436
437 static const struct gen_device_info gen_device_info_bdw_gt2 = {
438 GEN8_FEATURES, .gt = 2,
439 .is_broadwell = true,
440 .num_slices = 1,
441 .num_subslices = { 3, },
442 .num_eu_per_subslice = 8,
443 .l3_banks = 4,
444 .max_cs_threads = 56,
445 .urb = {
446 .size = 384,
447 .min_entries = {
448 [MESA_SHADER_VERTEX] = 64,
449 [MESA_SHADER_TESS_EVAL] = 34,
450 },
451 .max_entries = {
452 [MESA_SHADER_VERTEX] = 2560,
453 [MESA_SHADER_TESS_CTRL] = 504,
454 [MESA_SHADER_TESS_EVAL] = 1536,
455 [MESA_SHADER_GEOMETRY] = 960,
456 },
457 },
458 .simulator_id = 11,
459 };
460
461 static const struct gen_device_info gen_device_info_bdw_gt3 = {
462 GEN8_FEATURES, .gt = 3,
463 .is_broadwell = true,
464 .num_slices = 2,
465 .num_subslices = { 3, 3, },
466 .num_eu_per_subslice = 8,
467 .l3_banks = 8,
468 .max_cs_threads = 56,
469 .urb = {
470 .size = 384,
471 .min_entries = {
472 [MESA_SHADER_VERTEX] = 64,
473 [MESA_SHADER_TESS_EVAL] = 34,
474 },
475 .max_entries = {
476 [MESA_SHADER_VERTEX] = 2560,
477 [MESA_SHADER_TESS_CTRL] = 504,
478 [MESA_SHADER_TESS_EVAL] = 1536,
479 [MESA_SHADER_GEOMETRY] = 960,
480 },
481 },
482 .simulator_id = 11,
483 };
484
485 static const struct gen_device_info gen_device_info_chv = {
486 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
487 .has_llc = false,
488 .has_integer_dword_mul = false,
489 .num_slices = 1,
490 .num_subslices = { 2, },
491 .num_eu_per_subslice = 8,
492 .l3_banks = 2,
493 .max_vs_threads = 80,
494 .max_tcs_threads = 80,
495 .max_tes_threads = 80,
496 .max_gs_threads = 80,
497 .max_wm_threads = 128,
498 .max_cs_threads = 6 * 7,
499 .urb = {
500 .size = 192,
501 .min_entries = {
502 [MESA_SHADER_VERTEX] = 34,
503 [MESA_SHADER_TESS_EVAL] = 34,
504 },
505 .max_entries = {
506 [MESA_SHADER_VERTEX] = 640,
507 [MESA_SHADER_TESS_CTRL] = 80,
508 [MESA_SHADER_TESS_EVAL] = 384,
509 [MESA_SHADER_GEOMETRY] = 256,
510 },
511 },
512 .simulator_id = 13,
513 };
514
515 #define GEN9_HW_INFO \
516 .gen = 9, \
517 .max_vs_threads = 336, \
518 .max_gs_threads = 336, \
519 .max_tcs_threads = 336, \
520 .max_tes_threads = 336, \
521 .max_cs_threads = 56, \
522 .timestamp_frequency = 12000000, \
523 .urb = { \
524 .size = 384, \
525 .min_entries = { \
526 [MESA_SHADER_VERTEX] = 64, \
527 [MESA_SHADER_TESS_EVAL] = 34, \
528 }, \
529 .max_entries = { \
530 [MESA_SHADER_VERTEX] = 1856, \
531 [MESA_SHADER_TESS_CTRL] = 672, \
532 [MESA_SHADER_TESS_EVAL] = 1120, \
533 [MESA_SHADER_GEOMETRY] = 640, \
534 }, \
535 }
536
537 #define GEN9_LP_FEATURES \
538 GEN8_FEATURES, \
539 GEN9_HW_INFO, \
540 .has_integer_dword_mul = false, \
541 .gt = 1, \
542 .has_llc = false, \
543 .has_sample_with_hiz = true, \
544 .num_slices = 1, \
545 .num_thread_per_eu = 6, \
546 .max_vs_threads = 112, \
547 .max_tcs_threads = 112, \
548 .max_tes_threads = 112, \
549 .max_gs_threads = 112, \
550 .max_cs_threads = 6 * 6, \
551 .timestamp_frequency = 19200000, \
552 .urb = { \
553 .size = 192, \
554 .min_entries = { \
555 [MESA_SHADER_VERTEX] = 34, \
556 [MESA_SHADER_TESS_EVAL] = 34, \
557 }, \
558 .max_entries = { \
559 [MESA_SHADER_VERTEX] = 704, \
560 [MESA_SHADER_TESS_CTRL] = 256, \
561 [MESA_SHADER_TESS_EVAL] = 416, \
562 [MESA_SHADER_GEOMETRY] = 256, \
563 }, \
564 }
565
566 #define GEN9_LP_FEATURES_3X6 \
567 GEN9_LP_FEATURES, \
568 .num_subslices = { 3, }, \
569 .num_eu_per_subslice = 6
570
571 #define GEN9_LP_FEATURES_2X6 \
572 GEN9_LP_FEATURES, \
573 .num_subslices = { 2, }, \
574 .num_eu_per_subslice = 6, \
575 .max_vs_threads = 56, \
576 .max_tcs_threads = 56, \
577 .max_tes_threads = 56, \
578 .max_gs_threads = 56, \
579 .max_cs_threads = 6 * 6, \
580 .urb = { \
581 .size = 128, \
582 .min_entries = { \
583 [MESA_SHADER_VERTEX] = 34, \
584 [MESA_SHADER_TESS_EVAL] = 34, \
585 }, \
586 .max_entries = { \
587 [MESA_SHADER_VERTEX] = 352, \
588 [MESA_SHADER_TESS_CTRL] = 128, \
589 [MESA_SHADER_TESS_EVAL] = 208, \
590 [MESA_SHADER_GEOMETRY] = 128, \
591 }, \
592 }
593
594 #define GEN9_FEATURES \
595 GEN8_FEATURES, \
596 GEN9_HW_INFO, \
597 .has_sample_with_hiz = true
598
599 static const struct gen_device_info gen_device_info_skl_gt1 = {
600 GEN9_FEATURES, .gt = 1,
601 .is_skylake = true,
602 .num_slices = 1,
603 .num_subslices = { 2, },
604 .num_eu_per_subslice = 6,
605 .l3_banks = 2,
606 .urb.size = 192,
607 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
608 * leading to some vertices to go missing if we use too much URB.
609 */
610 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
611 .simulator_id = 12,
612 };
613
614 static const struct gen_device_info gen_device_info_skl_gt2 = {
615 GEN9_FEATURES, .gt = 2,
616 .is_skylake = true,
617 .num_slices = 1,
618 .num_subslices = { 3, },
619 .num_eu_per_subslice = 8,
620 .l3_banks = 4,
621 .simulator_id = 12,
622 };
623
624 static const struct gen_device_info gen_device_info_skl_gt3 = {
625 GEN9_FEATURES, .gt = 3,
626 .is_skylake = true,
627 .num_slices = 2,
628 .num_subslices = { 3, 3, },
629 .num_eu_per_subslice = 8,
630 .l3_banks = 8,
631 .simulator_id = 12,
632 };
633
634 static const struct gen_device_info gen_device_info_skl_gt4 = {
635 GEN9_FEATURES, .gt = 4,
636 .is_skylake = true,
637 .num_slices = 3,
638 .num_subslices = { 3, 3, 3, },
639 .num_eu_per_subslice = 8,
640 .l3_banks = 12,
641 /* From the "L3 Allocation and Programming" documentation:
642 *
643 * "URB is limited to 1008KB due to programming restrictions. This is not a
644 * restriction of the L3 implementation, but of the FF and other clients.
645 * Therefore, in a GT4 implementation it is possible for the programmed
646 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
647 * only 1008KB of this will be used."
648 */
649 .urb.size = 1008 / 3,
650 .simulator_id = 12,
651 };
652
653 static const struct gen_device_info gen_device_info_bxt = {
654 GEN9_LP_FEATURES_3X6,
655 .is_broxton = true,
656 .l3_banks = 2,
657 .simulator_id = 14,
658 };
659
660 static const struct gen_device_info gen_device_info_bxt_2x6 = {
661 GEN9_LP_FEATURES_2X6,
662 .is_broxton = true,
663 .l3_banks = 1,
664 .simulator_id = 14,
665 };
666 /*
667 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
668 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
669 */
670
671 static const struct gen_device_info gen_device_info_kbl_gt1 = {
672 GEN9_FEATURES,
673 .is_kabylake = true,
674 .gt = 1,
675
676 .max_cs_threads = 7 * 6,
677 .urb.size = 192,
678 .num_slices = 1,
679 .num_subslices = { 2, },
680 .num_eu_per_subslice = 6,
681 .l3_banks = 2,
682 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
683 * leading to some vertices to go missing if we use too much URB.
684 */
685 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
686 .simulator_id = 16,
687 };
688
689 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
690 GEN9_FEATURES,
691 .is_kabylake = true,
692 .gt = 1,
693
694 .max_cs_threads = 7 * 6,
695 .num_slices = 1,
696 .num_subslices = { 3, },
697 .num_eu_per_subslice = 6,
698 .l3_banks = 4,
699 .simulator_id = 16,
700 };
701
702 static const struct gen_device_info gen_device_info_kbl_gt2 = {
703 GEN9_FEATURES,
704 .is_kabylake = true,
705 .gt = 2,
706
707 .num_slices = 1,
708 .num_subslices = { 3, },
709 .num_eu_per_subslice = 8,
710 .l3_banks = 4,
711 .simulator_id = 16,
712 };
713
714 static const struct gen_device_info gen_device_info_kbl_gt3 = {
715 GEN9_FEATURES,
716 .is_kabylake = true,
717 .gt = 3,
718
719 .num_slices = 2,
720 .num_subslices = { 3, 3, },
721 .num_eu_per_subslice = 8,
722 .l3_banks = 8,
723 .simulator_id = 16,
724 };
725
726 static const struct gen_device_info gen_device_info_kbl_gt4 = {
727 GEN9_FEATURES,
728 .is_kabylake = true,
729 .gt = 4,
730
731 /*
732 * From the "L3 Allocation and Programming" documentation:
733 *
734 * "URB is limited to 1008KB due to programming restrictions. This
735 * is not a restriction of the L3 implementation, but of the FF and
736 * other clients. Therefore, in a GT4 implementation it is
737 * possible for the programmed allocation of the L3 data array to
738 * provide 3*384KB=1152KB for URB, but only 1008KB of this
739 * will be used."
740 */
741 .urb.size = 1008 / 3,
742 .num_slices = 3,
743 .num_subslices = { 3, 3, 3, },
744 .num_eu_per_subslice = 8,
745 .l3_banks = 12,
746 .simulator_id = 16,
747 };
748
749 static const struct gen_device_info gen_device_info_glk = {
750 GEN9_LP_FEATURES_3X6,
751 .is_geminilake = true,
752 .l3_banks = 2,
753 .simulator_id = 17,
754 };
755
756 static const struct gen_device_info gen_device_info_glk_2x6 = {
757 GEN9_LP_FEATURES_2X6,
758 .is_geminilake = true,
759 .l3_banks = 2,
760 .simulator_id = 17,
761 };
762
763 static const struct gen_device_info gen_device_info_cfl_gt1 = {
764 GEN9_FEATURES,
765 .is_coffeelake = true,
766 .gt = 1,
767
768 .num_slices = 1,
769 .num_subslices = { 2, },
770 .num_eu_per_subslice = 6,
771 .l3_banks = 2,
772 .urb.size = 192,
773 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
774 * leading to some vertices to go missing if we use too much URB.
775 */
776 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
777 .simulator_id = 24,
778 };
779 static const struct gen_device_info gen_device_info_cfl_gt2 = {
780 GEN9_FEATURES,
781 .is_coffeelake = true,
782 .gt = 2,
783
784 .num_slices = 1,
785 .num_subslices = { 3, },
786 .num_eu_per_subslice = 8,
787 .l3_banks = 4,
788 .simulator_id = 24,
789 };
790
791 static const struct gen_device_info gen_device_info_cfl_gt3 = {
792 GEN9_FEATURES,
793 .is_coffeelake = true,
794 .gt = 3,
795
796 .num_slices = 2,
797 .num_subslices = { 3, 3, },
798 .num_eu_per_subslice = 8,
799 .l3_banks = 8,
800 .simulator_id = 24,
801 };
802
803 #define GEN10_HW_INFO \
804 .gen = 10, \
805 .num_thread_per_eu = 7, \
806 .max_vs_threads = 728, \
807 .max_gs_threads = 432, \
808 .max_tcs_threads = 432, \
809 .max_tes_threads = 624, \
810 .max_cs_threads = 56, \
811 .timestamp_frequency = 19200000, \
812 .urb = { \
813 .size = 256, \
814 .min_entries = { \
815 [MESA_SHADER_VERTEX] = 64, \
816 [MESA_SHADER_TESS_EVAL] = 34, \
817 }, \
818 .max_entries = { \
819 [MESA_SHADER_VERTEX] = 3936, \
820 [MESA_SHADER_TESS_CTRL] = 896, \
821 [MESA_SHADER_TESS_EVAL] = 2064, \
822 [MESA_SHADER_GEOMETRY] = 832, \
823 }, \
824 }
825
826 #define subslices(args...) { args, }
827
828 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
829 GEN8_FEATURES, \
830 GEN10_HW_INFO, \
831 .has_sample_with_hiz = true, \
832 .gt = _gt, \
833 .num_slices = _slices, \
834 .num_subslices = _subslices, \
835 .num_eu_per_subslice = 8, \
836 .l3_banks = _l3
837
838 static const struct gen_device_info gen_device_info_cnl_gt0_5 = {
839 /* GT0.5 */
840 GEN10_FEATURES(1, 1, subslices(2), 2),
841 .is_cannonlake = true,
842 .simulator_id = 15,
843 };
844
845 static const struct gen_device_info gen_device_info_cnl_gt1 = {
846 /* GT1 */
847 GEN10_FEATURES(1, 1, subslices(3), 3),
848 .is_cannonlake = true,
849 .simulator_id = 15,
850 };
851
852 static const struct gen_device_info gen_device_info_cnl_gt1_5 = {
853 /* GT 1.5 */
854 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
855 .is_cannonlake = true,
856 .simulator_id = 15,
857 };
858
859 static const struct gen_device_info gen_device_info_cnl_gt2 = {
860 /* GT2 */
861 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
862 .is_cannonlake = true,
863 .simulator_id = 15,
864 };
865
866 #define GEN11_HW_INFO \
867 .gen = 11, \
868 .has_pln = false, \
869 .max_vs_threads = 364, \
870 .max_gs_threads = 224, \
871 .max_tcs_threads = 224, \
872 .max_tes_threads = 364, \
873 .max_cs_threads = 56
874
875 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
876 GEN8_FEATURES, \
877 GEN11_HW_INFO, \
878 .has_64bit_float = false, \
879 .has_64bit_int = false, \
880 .has_integer_dword_mul = false, \
881 .has_sample_with_hiz = false, \
882 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
883 .num_subslices = _subslices, \
884 .num_eu_per_subslice = 8
885
886 #define GEN11_URB_MIN_MAX_ENTRIES \
887 .min_entries = { \
888 [MESA_SHADER_VERTEX] = 64, \
889 [MESA_SHADER_TESS_EVAL] = 34, \
890 }, \
891 .max_entries = { \
892 [MESA_SHADER_VERTEX] = 2384, \
893 [MESA_SHADER_TESS_CTRL] = 1032, \
894 [MESA_SHADER_TESS_EVAL] = 2384, \
895 [MESA_SHADER_GEOMETRY] = 1032, \
896 }
897
898 static const struct gen_device_info gen_device_info_icl_gt2 = {
899 GEN11_FEATURES(2, 1, subslices(8), 8),
900 .urb = {
901 .size = 1024,
902 GEN11_URB_MIN_MAX_ENTRIES,
903 },
904 .simulator_id = 19,
905 };
906
907 static const struct gen_device_info gen_device_info_icl_gt1_5 = {
908 GEN11_FEATURES(1, 1, subslices(6), 6),
909 .urb = {
910 .size = 768,
911 GEN11_URB_MIN_MAX_ENTRIES,
912 },
913 .simulator_id = 19,
914 };
915
916 static const struct gen_device_info gen_device_info_icl_gt1 = {
917 GEN11_FEATURES(1, 1, subslices(4), 6),
918 .urb = {
919 .size = 768,
920 GEN11_URB_MIN_MAX_ENTRIES,
921 },
922 .simulator_id = 19,
923 };
924
925 static const struct gen_device_info gen_device_info_icl_gt0_5 = {
926 GEN11_FEATURES(1, 1, subslices(1), 6),
927 .urb = {
928 .size = 768,
929 GEN11_URB_MIN_MAX_ENTRIES,
930 },
931 .simulator_id = 19,
932 };
933
934 static const struct gen_device_info gen_device_info_ehl_7 = {
935 GEN11_FEATURES(1, 1, subslices(4), 4),
936 .is_elkhartlake = true,
937 .urb = {
938 .size = 512,
939 .min_entries = {
940 [MESA_SHADER_VERTEX] = 64,
941 [MESA_SHADER_TESS_EVAL] = 34,
942 },
943 .max_entries = {
944 [MESA_SHADER_VERTEX] = 2384,
945 [MESA_SHADER_TESS_CTRL] = 1032,
946 [MESA_SHADER_TESS_EVAL] = 2384,
947 [MESA_SHADER_GEOMETRY] = 1032,
948 },
949 },
950 .disable_ccs_repack = true,
951 .simulator_id = 28,
952 };
953
954 static const struct gen_device_info gen_device_info_ehl_6 = {
955 GEN11_FEATURES(1, 1, subslices(4), 4),
956 .is_elkhartlake = true,
957 .urb = {
958 .size = 512,
959 .min_entries = {
960 [MESA_SHADER_VERTEX] = 64,
961 [MESA_SHADER_TESS_EVAL] = 34,
962 },
963 .max_entries = {
964 [MESA_SHADER_VERTEX] = 2384,
965 [MESA_SHADER_TESS_CTRL] = 1032,
966 [MESA_SHADER_TESS_EVAL] = 2384,
967 [MESA_SHADER_GEOMETRY] = 1032,
968 },
969 },
970 .disable_ccs_repack = true,
971 .num_eu_per_subslice = 6,
972 .simulator_id = 28,
973 };
974
975 static const struct gen_device_info gen_device_info_ehl_5 = {
976 GEN11_FEATURES(1, 1, subslices(4), 4),
977 .is_elkhartlake = true,
978 .urb = {
979 .size = 512,
980 .min_entries = {
981 [MESA_SHADER_VERTEX] = 64,
982 [MESA_SHADER_TESS_EVAL] = 34,
983 },
984 .max_entries = {
985 [MESA_SHADER_VERTEX] = 2384,
986 [MESA_SHADER_TESS_CTRL] = 1032,
987 [MESA_SHADER_TESS_EVAL] = 2384,
988 [MESA_SHADER_GEOMETRY] = 1032,
989 },
990 },
991 .disable_ccs_repack = true,
992 .num_eu_per_subslice = 4,
993 .simulator_id = 28,
994 };
995
996 static const struct gen_device_info gen_device_info_ehl_4 = {
997 GEN11_FEATURES(1, 1, subslices(2), 4),
998 .is_elkhartlake = true,
999 .urb = {
1000 .size = 512,
1001 .min_entries = {
1002 [MESA_SHADER_VERTEX] = 64,
1003 [MESA_SHADER_TESS_EVAL] = 34,
1004 },
1005 .max_entries = {
1006 [MESA_SHADER_VERTEX] = 2384,
1007 [MESA_SHADER_TESS_CTRL] = 1032,
1008 [MESA_SHADER_TESS_EVAL] = 2384,
1009 [MESA_SHADER_GEOMETRY] = 1032,
1010 },
1011 },
1012 .disable_ccs_repack = true,
1013 .num_eu_per_subslice =4,
1014 .simulator_id = 28,
1015 };
1016
1017 #define GEN12_URB_MIN_MAX_ENTRIES \
1018 .min_entries = { \
1019 [MESA_SHADER_VERTEX] = 64, \
1020 [MESA_SHADER_TESS_EVAL] = 34, \
1021 }, \
1022 .max_entries = { \
1023 [MESA_SHADER_VERTEX] = 3576, \
1024 [MESA_SHADER_TESS_CTRL] = 1548, \
1025 [MESA_SHADER_TESS_EVAL] = 3576, \
1026 [MESA_SHADER_GEOMETRY] = 1548, \
1027 }
1028
1029 #define GEN12_HW_INFO \
1030 .gen = 12, \
1031 .has_pln = false, \
1032 .has_sample_with_hiz = false, \
1033 .has_aux_map = true, \
1034 .max_vs_threads = 546, \
1035 .max_gs_threads = 336, \
1036 .max_tcs_threads = 336, \
1037 .max_tes_threads = 546, \
1038 .max_cs_threads = 112, /* threads per DSS */ \
1039 .urb = { \
1040 GEN12_URB_MIN_MAX_ENTRIES, \
1041 }
1042
1043 #define GEN12_FEATURES(_gt, _slices, _l3) \
1044 GEN8_FEATURES, \
1045 GEN12_HW_INFO, \
1046 .has_64bit_float = false, \
1047 .has_64bit_int = false, \
1048 .has_integer_dword_mul = false, \
1049 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1050 .simulator_id = 22, \
1051 .urb.size = (_gt) == 1 ? 512 : 1024, \
1052 .num_eu_per_subslice = 16
1053
1054 #define dual_subslices(args...) { args, }
1055
1056 #define GEN12_GT_FEATURES(_gt) \
1057 GEN12_FEATURES(1, 1, _gt == 1 ? 4 : 8), \
1058 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1059
1060 static const struct gen_device_info gen_device_info_tgl_gt1 = {
1061 GEN12_GT_FEATURES(1),
1062 };
1063
1064 static const struct gen_device_info gen_device_info_tgl_gt2 = {
1065 GEN12_GT_FEATURES(2),
1066 };
1067
1068 static void
1069 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1070 unsigned slice,
1071 unsigned subslice,
1072 unsigned eu_mask)
1073 {
1074 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1075 subslice * devinfo->eu_subslice_stride;
1076
1077 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1078 devinfo->eu_masks[subslice_offset + b_eu] =
1079 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1080 }
1081 }
1082
1083 /* Generate slice/subslice/eu masks from number of
1084 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1085 * structure.
1086 *
1087 * These can be overridden with values reported by the kernel either from
1088 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1089 * through the i915 query uapi.
1090 */
1091 static void
1092 fill_masks(struct gen_device_info *devinfo)
1093 {
1094 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1095
1096 /* Subslice masks */
1097 unsigned max_subslices = 0;
1098 for (int s = 0; s < devinfo->num_slices; s++)
1099 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1100 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1101
1102 for (int s = 0; s < devinfo->num_slices; s++) {
1103 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1104 (1U << devinfo->num_subslices[s]) - 1;
1105 }
1106
1107 /* EU masks */
1108 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1109 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1110
1111 for (int s = 0; s < devinfo->num_slices; s++) {
1112 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1113 gen_device_info_set_eu_mask(devinfo, s, ss,
1114 (1U << devinfo->num_eu_per_subslice) - 1);
1115 }
1116 }
1117 }
1118
1119 static void
1120 reset_masks(struct gen_device_info *devinfo)
1121 {
1122 devinfo->subslice_slice_stride = 0;
1123 devinfo->eu_subslice_stride = 0;
1124 devinfo->eu_slice_stride = 0;
1125
1126 devinfo->num_slices = 0;
1127 devinfo->num_eu_per_subslice = 0;
1128 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1129
1130 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1131 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1132 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1133 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1134 }
1135
1136 static void
1137 update_from_topology(struct gen_device_info *devinfo,
1138 const struct drm_i915_query_topology_info *topology)
1139 {
1140 reset_masks(devinfo);
1141
1142 devinfo->subslice_slice_stride = topology->subslice_stride;
1143
1144 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1145 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1146
1147 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1148 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1149 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1150
1151 uint32_t subslice_mask_len =
1152 topology->max_slices * topology->subslice_stride;
1153 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1154 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1155 subslice_mask_len);
1156
1157 uint32_t n_subslices = 0;
1158 for (int s = 0; s < topology->max_slices; s++) {
1159 if ((devinfo->slice_masks & (1 << s)) == 0)
1160 continue;
1161
1162 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1163 devinfo->num_subslices[s] +=
1164 __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1165 }
1166 n_subslices += devinfo->num_subslices[s];
1167 }
1168 assert(n_subslices > 0);
1169
1170 if (devinfo->gen == 11) {
1171 /* On ICL we only have one slice */
1172 assert(devinfo->slice_masks == 1);
1173
1174 /* Count the number of subslices on each pixel pipe. Assume that
1175 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1176 */
1177 unsigned subslices = devinfo->subslice_masks[0];
1178 unsigned ss = 0;
1179 while (subslices > 0) {
1180 if (subslices & 1)
1181 devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
1182 subslices >>= 1;
1183 ss++;
1184 }
1185 }
1186
1187 if (devinfo->gen == 12 && devinfo->num_slices == 1) {
1188 if (n_subslices >= 6) {
1189 assert(n_subslices == 6);
1190 devinfo->l3_banks = 8;
1191 } else if (n_subslices > 2) {
1192 devinfo->l3_banks = 6;
1193 } else {
1194 devinfo->l3_banks = 4;
1195 }
1196 }
1197
1198 uint32_t eu_mask_len =
1199 topology->eu_stride * topology->max_subslices * topology->max_slices;
1200 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1201 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1202
1203 uint32_t n_eus = 0;
1204 for (int b = 0; b < eu_mask_len; b++)
1205 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1206
1207 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1208 }
1209
1210 static bool
1211 update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask,
1212 uint32_t subslice_mask, uint32_t n_eus)
1213 {
1214 struct drm_i915_query_topology_info *topology;
1215
1216 assert((slice_mask & 0xff) == slice_mask);
1217
1218 size_t data_length = 100;
1219
1220 topology = calloc(1, sizeof(*topology) + data_length);
1221 if (!topology)
1222 return false;
1223
1224 topology->max_slices = util_last_bit(slice_mask);
1225 topology->max_subslices = util_last_bit(subslice_mask);
1226
1227 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1228 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1229
1230 uint32_t n_subslices = __builtin_popcount(slice_mask) *
1231 __builtin_popcount(subslice_mask);
1232 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1233 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1234
1235 topology->eu_offset = topology->subslice_offset +
1236 DIV_ROUND_UP(topology->max_subslices, 8);
1237 topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1238
1239 /* Set slice mask in topology */
1240 for (int b = 0; b < topology->subslice_offset; b++)
1241 topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1242
1243 for (int s = 0; s < topology->max_slices; s++) {
1244
1245 /* Set subslice mask in topology */
1246 for (int b = 0; b < topology->subslice_stride; b++) {
1247 int subslice_offset = topology->subslice_offset +
1248 s * topology->subslice_stride + b;
1249
1250 topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1251 }
1252
1253 /* Set eu mask in topology */
1254 for (int ss = 0; ss < topology->max_subslices; ss++) {
1255 for (int b = 0; b < topology->eu_stride; b++) {
1256 int eu_offset = topology->eu_offset +
1257 (s * topology->max_subslices + ss) * topology->eu_stride + b;
1258
1259 topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1260 }
1261 }
1262 }
1263
1264 update_from_topology(devinfo, topology);
1265 free(topology);
1266
1267 return true;
1268 }
1269
1270 static bool
1271 getparam(int fd, uint32_t param, int *value)
1272 {
1273 int tmp;
1274
1275 struct drm_i915_getparam gp = {
1276 .param = param,
1277 .value = &tmp,
1278 };
1279
1280 int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
1281 if (ret != 0)
1282 return false;
1283
1284 *value = tmp;
1285 return true;
1286 }
1287
1288 bool
1289 gen_get_device_info_from_pci_id(int pci_id,
1290 struct gen_device_info *devinfo)
1291 {
1292 switch (pci_id) {
1293 #undef CHIPSET
1294 #define CHIPSET(id, family, fam_str, name) \
1295 case id: *devinfo = gen_device_info_##family; break;
1296 #include "pci_ids/i965_pci_ids.h"
1297 #include "pci_ids/iris_pci_ids.h"
1298 default:
1299 fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id);
1300 return false;
1301 }
1302
1303 fill_masks(devinfo);
1304
1305 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1306 *
1307 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1308 * allocate scratch space enough so that each slice has 4 slices allowed."
1309 *
1310 * The equivalent internal documentation says that this programming note
1311 * applies to all Gen9+ platforms.
1312 *
1313 * The hardware typically calculates the scratch space pointer by taking
1314 * the base address, and adding per-thread-scratch-space * thread ID.
1315 * Extra padding can be necessary depending how the thread IDs are
1316 * calculated for a particular shader stage.
1317 */
1318
1319 switch(devinfo->gen) {
1320 case 9:
1321 case 10:
1322 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1323 * devinfo->num_slices
1324 * 4; /* effective subslices per slice */
1325 break;
1326 case 11:
1327 case 12:
1328 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1329 * devinfo->num_slices
1330 * 8; /* subslices per slice */
1331 break;
1332 default:
1333 assert(devinfo->gen < 9);
1334 break;
1335 }
1336
1337 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1338
1339 devinfo->chipset_id = pci_id;
1340 return true;
1341 }
1342
1343 const char *
1344 gen_get_device_name(int devid)
1345 {
1346 switch (devid) {
1347 #undef CHIPSET
1348 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1349 #include "pci_ids/i965_pci_ids.h"
1350 #include "pci_ids/iris_pci_ids.h"
1351 default:
1352 return NULL;
1353 }
1354 }
1355
1356 /**
1357 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1358 * (kernel 4.13+)
1359 */
1360 static bool
1361 getparam_topology(struct gen_device_info *devinfo, int fd)
1362 {
1363 int slice_mask = 0;
1364 if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
1365 return false;
1366
1367 int n_eus;
1368 if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
1369 return false;
1370
1371 int subslice_mask = 0;
1372 if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
1373 return false;
1374
1375 return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1376 }
1377
1378 /**
1379 * preferred API for updating the topology in devinfo (kernel 4.17+)
1380 */
1381 static bool
1382 query_topology(struct gen_device_info *devinfo, int fd)
1383 {
1384 struct drm_i915_query_item item = {
1385 .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
1386 };
1387 struct drm_i915_query query = {
1388 .num_items = 1,
1389 .items_ptr = (uintptr_t) &item,
1390 };
1391
1392 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
1393 return false;
1394
1395 if (item.length < 0)
1396 return false;
1397
1398 struct drm_i915_query_topology_info *topo_info =
1399 (struct drm_i915_query_topology_info *) calloc(1, item.length);
1400 item.data_ptr = (uintptr_t) topo_info;
1401
1402 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
1403 item.length <= 0)
1404 return false;
1405
1406 update_from_topology(devinfo, topo_info);
1407
1408 free(topo_info);
1409
1410 return true;
1411
1412 }
1413
1414 bool
1415 gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
1416 {
1417 int devid = 0;
1418
1419 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
1420 if (devid_override && strlen(devid_override) > 0) {
1421 if (geteuid() == getuid()) {
1422 devid = gen_device_name_to_pci_device_id(devid_override);
1423 /* Fallback to PCI ID. */
1424 if (devid <= 0)
1425 devid = strtol(devid_override, NULL, 0);
1426 if (devid <= 0) {
1427 fprintf(stderr, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1428 "Use a valid numeric PCI ID or one of the supported "
1429 "platform names: %s", devid_override, name_map[0].name);
1430 for (unsigned i = 1; i < ARRAY_SIZE(name_map); i++)
1431 fprintf(stderr, ", %s", name_map[i].name);
1432 fprintf(stderr, "\n");
1433 return false;
1434 }
1435 } else {
1436 fprintf(stderr, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1437 "real and effective user ID don't match.\n", devid_override);
1438 }
1439 }
1440
1441 if (devid > 0) {
1442 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1443 return false;
1444 devinfo->no_hw = true;
1445 } else {
1446 /* query the device id */
1447 if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
1448 return false;
1449 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1450 return false;
1451 devinfo->no_hw = false;
1452 }
1453
1454 /* remaining initializion queries the kernel for device info */
1455 if (devinfo->no_hw)
1456 return true;
1457
1458 int timestamp_frequency;
1459 if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1460 &timestamp_frequency))
1461 devinfo->timestamp_frequency = timestamp_frequency;
1462 else if (devinfo->gen >= 10)
1463 /* gen10 and later requires the timestamp_frequency to be updated */
1464 return false;
1465
1466 if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
1467 devinfo->revision = 0;
1468
1469 if (!query_topology(devinfo, fd)) {
1470 if (devinfo->gen >= 10) {
1471 /* topology uAPI required for CNL+ (kernel 4.17+) */
1472 return false;
1473 }
1474
1475 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1476 * will be wrong, affecting GPU metrics. In this case, fail silently.
1477 */
1478 getparam_topology(devinfo, fd);
1479 }
1480
1481 return true;
1482 }