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intel/dev: Don't consider all TGL SKUs as GT1 only
[mesa.git] / src / intel / dev / gen_device_info.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <stdio.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include "gen_device_info.h"
31 #include "compiler/shader_enums.h"
32 #include "intel/common/gen_gem.h"
33 #include "util/bitscan.h"
34 #include "util/macros.h"
35
36 #include "drm-uapi/i915_drm.h"
37
38 static const struct {
39 const char *name;
40 int pci_id;
41 } name_map[] = {
42 { "brw", 0x2a02 },
43 { "g4x", 0x2a42 },
44 { "ilk", 0x0042 },
45 { "snb", 0x0126 },
46 { "ivb", 0x016a },
47 { "hsw", 0x0d2e },
48 { "byt", 0x0f33 },
49 { "bdw", 0x162e },
50 { "chv", 0x22B3 },
51 { "skl", 0x1912 },
52 { "bxt", 0x5A85 },
53 { "kbl", 0x5912 },
54 { "aml", 0x591C },
55 { "glk", 0x3185 },
56 { "cfl", 0x3E9B },
57 { "whl", 0x3EA1 },
58 { "cml", 0x9b41 },
59 { "cnl", 0x5a52 },
60 { "icl", 0x8a52 },
61 { "ehl", 0x4500 },
62 { "jsl", 0x4E71 },
63 { "tgl", 0x9a49 },
64 { "rkl", 0x4c8a },
65 };
66
67 /**
68 * Get the PCI ID for the device name.
69 *
70 * Returns -1 if the device is not known.
71 */
72 int
73 gen_device_name_to_pci_device_id(const char *name)
74 {
75 for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
76 if (!strcmp(name_map[i].name, name))
77 return name_map[i].pci_id;
78 }
79
80 return -1;
81 }
82
83 static const struct gen_device_info gen_device_info_i965 = {
84 .gen = 4,
85 .has_negative_rhw_bug = true,
86 .num_slices = 1,
87 .num_subslices = { 1, },
88 .num_eu_per_subslice = 8,
89 .num_thread_per_eu = 4,
90 .max_vs_threads = 16,
91 .max_gs_threads = 2,
92 .max_wm_threads = 8 * 4,
93 .urb = {
94 .size = 256,
95 },
96 .timestamp_frequency = 12500000,
97 .simulator_id = -1,
98 };
99
100 static const struct gen_device_info gen_device_info_g4x = {
101 .gen = 4,
102 .has_pln = true,
103 .has_compr4 = true,
104 .has_surface_tile_offset = true,
105 .is_g4x = true,
106 .num_slices = 1,
107 .num_subslices = { 1, },
108 .num_eu_per_subslice = 10,
109 .num_thread_per_eu = 5,
110 .max_vs_threads = 32,
111 .max_gs_threads = 2,
112 .max_wm_threads = 10 * 5,
113 .urb = {
114 .size = 384,
115 },
116 .timestamp_frequency = 12500000,
117 .simulator_id = -1,
118 };
119
120 static const struct gen_device_info gen_device_info_ilk = {
121 .gen = 5,
122 .has_pln = true,
123 .has_compr4 = true,
124 .has_surface_tile_offset = true,
125 .num_slices = 1,
126 .num_subslices = { 1, },
127 .num_eu_per_subslice = 12,
128 .num_thread_per_eu = 6,
129 .max_vs_threads = 72,
130 .max_gs_threads = 32,
131 .max_wm_threads = 12 * 6,
132 .urb = {
133 .size = 1024,
134 },
135 .timestamp_frequency = 12500000,
136 .simulator_id = -1,
137 };
138
139 static const struct gen_device_info gen_device_info_snb_gt1 = {
140 .gen = 6,
141 .gt = 1,
142 .has_hiz_and_separate_stencil = true,
143 .has_llc = true,
144 .has_pln = true,
145 .has_surface_tile_offset = true,
146 .needs_unlit_centroid_workaround = true,
147 .num_slices = 1,
148 .num_subslices = { 1, },
149 .num_eu_per_subslice = 6,
150 .num_thread_per_eu = 6, /* Not confirmed */
151 .max_vs_threads = 24,
152 .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
153 .max_wm_threads = 40,
154 .urb = {
155 .size = 32,
156 .min_entries = {
157 [MESA_SHADER_VERTEX] = 24,
158 },
159 .max_entries = {
160 [MESA_SHADER_VERTEX] = 256,
161 [MESA_SHADER_GEOMETRY] = 256,
162 },
163 },
164 .timestamp_frequency = 12500000,
165 .simulator_id = -1,
166 };
167
168 static const struct gen_device_info gen_device_info_snb_gt2 = {
169 .gen = 6,
170 .gt = 2,
171 .has_hiz_and_separate_stencil = true,
172 .has_llc = true,
173 .has_pln = true,
174 .has_surface_tile_offset = true,
175 .needs_unlit_centroid_workaround = true,
176 .num_slices = 1,
177 .num_subslices = { 1, },
178 .num_eu_per_subslice = 12,
179 .num_thread_per_eu = 6, /* Not confirmed */
180 .max_vs_threads = 60,
181 .max_gs_threads = 60,
182 .max_wm_threads = 80,
183 .urb = {
184 .size = 64,
185 .min_entries = {
186 [MESA_SHADER_VERTEX] = 24,
187 },
188 .max_entries = {
189 [MESA_SHADER_VERTEX] = 256,
190 [MESA_SHADER_GEOMETRY] = 256,
191 },
192 },
193 .timestamp_frequency = 12500000,
194 .simulator_id = -1,
195 };
196
197 #define GEN7_FEATURES \
198 .gen = 7, \
199 .has_hiz_and_separate_stencil = true, \
200 .must_use_separate_stencil = true, \
201 .has_llc = true, \
202 .has_pln = true, \
203 .has_64bit_float = true, \
204 .has_surface_tile_offset = true, \
205 .timestamp_frequency = 12500000
206
207 static const struct gen_device_info gen_device_info_ivb_gt1 = {
208 GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
209 .num_slices = 1,
210 .num_subslices = { 1, },
211 .num_eu_per_subslice = 6,
212 .num_thread_per_eu = 6,
213 .l3_banks = 2,
214 .max_vs_threads = 36,
215 .max_tcs_threads = 36,
216 .max_tes_threads = 36,
217 .max_gs_threads = 36,
218 .max_wm_threads = 48,
219 .max_cs_threads = 36,
220 .urb = {
221 .min_entries = {
222 [MESA_SHADER_VERTEX] = 32,
223 [MESA_SHADER_TESS_EVAL] = 10,
224 },
225 .max_entries = {
226 [MESA_SHADER_VERTEX] = 512,
227 [MESA_SHADER_TESS_CTRL] = 32,
228 [MESA_SHADER_TESS_EVAL] = 288,
229 [MESA_SHADER_GEOMETRY] = 192,
230 },
231 },
232 .simulator_id = 7,
233 };
234
235 static const struct gen_device_info gen_device_info_ivb_gt2 = {
236 GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
237 .num_slices = 1,
238 .num_subslices = { 1, },
239 .num_eu_per_subslice = 12,
240 .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
241 * @max_wm_threads ... */
242 .l3_banks = 4,
243 .max_vs_threads = 128,
244 .max_tcs_threads = 128,
245 .max_tes_threads = 128,
246 .max_gs_threads = 128,
247 .max_wm_threads = 172,
248 .max_cs_threads = 64,
249 .urb = {
250 .min_entries = {
251 [MESA_SHADER_VERTEX] = 32,
252 [MESA_SHADER_TESS_EVAL] = 10,
253 },
254 .max_entries = {
255 [MESA_SHADER_VERTEX] = 704,
256 [MESA_SHADER_TESS_CTRL] = 64,
257 [MESA_SHADER_TESS_EVAL] = 448,
258 [MESA_SHADER_GEOMETRY] = 320,
259 },
260 },
261 .simulator_id = 7,
262 };
263
264 static const struct gen_device_info gen_device_info_byt = {
265 GEN7_FEATURES, .is_baytrail = true, .gt = 1,
266 .num_slices = 1,
267 .num_subslices = { 1, },
268 .num_eu_per_subslice = 4,
269 .num_thread_per_eu = 8,
270 .l3_banks = 1,
271 .has_llc = false,
272 .max_vs_threads = 36,
273 .max_tcs_threads = 36,
274 .max_tes_threads = 36,
275 .max_gs_threads = 36,
276 .max_wm_threads = 48,
277 .max_cs_threads = 32,
278 .urb = {
279 .min_entries = {
280 [MESA_SHADER_VERTEX] = 32,
281 [MESA_SHADER_TESS_EVAL] = 10,
282 },
283 .max_entries = {
284 [MESA_SHADER_VERTEX] = 512,
285 [MESA_SHADER_TESS_CTRL] = 32,
286 [MESA_SHADER_TESS_EVAL] = 288,
287 [MESA_SHADER_GEOMETRY] = 192,
288 },
289 },
290 .simulator_id = 10,
291 };
292
293 #define HSW_FEATURES \
294 GEN7_FEATURES, \
295 .is_haswell = true, \
296 .supports_simd16_3src = true, \
297 .has_resource_streamer = true
298
299 static const struct gen_device_info gen_device_info_hsw_gt1 = {
300 HSW_FEATURES, .gt = 1,
301 .num_slices = 1,
302 .num_subslices = { 1, },
303 .num_eu_per_subslice = 10,
304 .num_thread_per_eu = 7,
305 .l3_banks = 2,
306 .max_vs_threads = 70,
307 .max_tcs_threads = 70,
308 .max_tes_threads = 70,
309 .max_gs_threads = 70,
310 .max_wm_threads = 102,
311 .max_cs_threads = 70,
312 .urb = {
313 .min_entries = {
314 [MESA_SHADER_VERTEX] = 32,
315 [MESA_SHADER_TESS_EVAL] = 10,
316 },
317 .max_entries = {
318 [MESA_SHADER_VERTEX] = 640,
319 [MESA_SHADER_TESS_CTRL] = 64,
320 [MESA_SHADER_TESS_EVAL] = 384,
321 [MESA_SHADER_GEOMETRY] = 256,
322 },
323 },
324 .simulator_id = 9,
325 };
326
327 static const struct gen_device_info gen_device_info_hsw_gt2 = {
328 HSW_FEATURES, .gt = 2,
329 .num_slices = 1,
330 .num_subslices = { 2, },
331 .num_eu_per_subslice = 10,
332 .num_thread_per_eu = 7,
333 .l3_banks = 4,
334 .max_vs_threads = 280,
335 .max_tcs_threads = 256,
336 .max_tes_threads = 280,
337 .max_gs_threads = 256,
338 .max_wm_threads = 204,
339 .max_cs_threads = 70,
340 .urb = {
341 .min_entries = {
342 [MESA_SHADER_VERTEX] = 64,
343 [MESA_SHADER_TESS_EVAL] = 10,
344 },
345 .max_entries = {
346 [MESA_SHADER_VERTEX] = 1664,
347 [MESA_SHADER_TESS_CTRL] = 128,
348 [MESA_SHADER_TESS_EVAL] = 960,
349 [MESA_SHADER_GEOMETRY] = 640,
350 },
351 },
352 .simulator_id = 9,
353 };
354
355 static const struct gen_device_info gen_device_info_hsw_gt3 = {
356 HSW_FEATURES, .gt = 3,
357 .num_slices = 2,
358 .num_subslices = { 2, },
359 .num_eu_per_subslice = 10,
360 .num_thread_per_eu = 7,
361 .l3_banks = 8,
362 .max_vs_threads = 280,
363 .max_tcs_threads = 256,
364 .max_tes_threads = 280,
365 .max_gs_threads = 256,
366 .max_wm_threads = 408,
367 .max_cs_threads = 70,
368 .urb = {
369 .min_entries = {
370 [MESA_SHADER_VERTEX] = 64,
371 [MESA_SHADER_TESS_EVAL] = 10,
372 },
373 .max_entries = {
374 [MESA_SHADER_VERTEX] = 1664,
375 [MESA_SHADER_TESS_CTRL] = 128,
376 [MESA_SHADER_TESS_EVAL] = 960,
377 [MESA_SHADER_GEOMETRY] = 640,
378 },
379 },
380 .simulator_id = 9,
381 };
382
383 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
384 * so keep things conservative for now and set has_sample_with_hiz = false.
385 */
386 #define GEN8_FEATURES \
387 .gen = 8, \
388 .has_hiz_and_separate_stencil = true, \
389 .has_resource_streamer = true, \
390 .must_use_separate_stencil = true, \
391 .has_llc = true, \
392 .has_sample_with_hiz = false, \
393 .has_pln = true, \
394 .has_integer_dword_mul = true, \
395 .has_64bit_float = true, \
396 .has_64bit_int = true, \
397 .supports_simd16_3src = true, \
398 .has_surface_tile_offset = true, \
399 .num_thread_per_eu = 7, \
400 .max_vs_threads = 504, \
401 .max_tcs_threads = 504, \
402 .max_tes_threads = 504, \
403 .max_gs_threads = 504, \
404 .max_wm_threads = 384, \
405 .timestamp_frequency = 12500000
406
407 static const struct gen_device_info gen_device_info_bdw_gt1 = {
408 GEN8_FEATURES, .gt = 1,
409 .is_broadwell = true,
410 .num_slices = 1,
411 .num_subslices = { 2, },
412 .num_eu_per_subslice = 6,
413 .l3_banks = 2,
414 .max_cs_threads = 42,
415 .urb = {
416 .min_entries = {
417 [MESA_SHADER_VERTEX] = 64,
418 [MESA_SHADER_TESS_EVAL] = 34,
419 },
420 .max_entries = {
421 [MESA_SHADER_VERTEX] = 2560,
422 [MESA_SHADER_TESS_CTRL] = 504,
423 [MESA_SHADER_TESS_EVAL] = 1536,
424 /* Reduced from 960, seems to be similar to the bug on Gen9 GT1. */
425 [MESA_SHADER_GEOMETRY] = 690,
426 },
427 },
428 .simulator_id = 11,
429 };
430
431 static const struct gen_device_info gen_device_info_bdw_gt2 = {
432 GEN8_FEATURES, .gt = 2,
433 .is_broadwell = true,
434 .num_slices = 1,
435 .num_subslices = { 3, },
436 .num_eu_per_subslice = 8,
437 .l3_banks = 4,
438 .max_cs_threads = 56,
439 .urb = {
440 .min_entries = {
441 [MESA_SHADER_VERTEX] = 64,
442 [MESA_SHADER_TESS_EVAL] = 34,
443 },
444 .max_entries = {
445 [MESA_SHADER_VERTEX] = 2560,
446 [MESA_SHADER_TESS_CTRL] = 504,
447 [MESA_SHADER_TESS_EVAL] = 1536,
448 [MESA_SHADER_GEOMETRY] = 960,
449 },
450 },
451 .simulator_id = 11,
452 };
453
454 static const struct gen_device_info gen_device_info_bdw_gt3 = {
455 GEN8_FEATURES, .gt = 3,
456 .is_broadwell = true,
457 .num_slices = 2,
458 .num_subslices = { 3, 3, },
459 .num_eu_per_subslice = 8,
460 .l3_banks = 8,
461 .max_cs_threads = 56,
462 .urb = {
463 .min_entries = {
464 [MESA_SHADER_VERTEX] = 64,
465 [MESA_SHADER_TESS_EVAL] = 34,
466 },
467 .max_entries = {
468 [MESA_SHADER_VERTEX] = 2560,
469 [MESA_SHADER_TESS_CTRL] = 504,
470 [MESA_SHADER_TESS_EVAL] = 1536,
471 [MESA_SHADER_GEOMETRY] = 960,
472 },
473 },
474 .simulator_id = 11,
475 };
476
477 static const struct gen_device_info gen_device_info_chv = {
478 GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
479 .has_llc = false,
480 .has_integer_dword_mul = false,
481 .num_slices = 1,
482 .num_subslices = { 2, },
483 .num_eu_per_subslice = 8,
484 .l3_banks = 2,
485 .max_vs_threads = 80,
486 .max_tcs_threads = 80,
487 .max_tes_threads = 80,
488 .max_gs_threads = 80,
489 .max_wm_threads = 128,
490 .max_cs_threads = 6 * 7,
491 .urb = {
492 .min_entries = {
493 [MESA_SHADER_VERTEX] = 34,
494 [MESA_SHADER_TESS_EVAL] = 34,
495 },
496 .max_entries = {
497 [MESA_SHADER_VERTEX] = 640,
498 [MESA_SHADER_TESS_CTRL] = 80,
499 [MESA_SHADER_TESS_EVAL] = 384,
500 [MESA_SHADER_GEOMETRY] = 256,
501 },
502 },
503 .simulator_id = 13,
504 };
505
506 #define GEN9_HW_INFO \
507 .gen = 9, \
508 .max_vs_threads = 336, \
509 .max_gs_threads = 336, \
510 .max_tcs_threads = 336, \
511 .max_tes_threads = 336, \
512 .max_cs_threads = 56, \
513 .timestamp_frequency = 12000000, \
514 .urb = { \
515 .min_entries = { \
516 [MESA_SHADER_VERTEX] = 64, \
517 [MESA_SHADER_TESS_EVAL] = 34, \
518 }, \
519 .max_entries = { \
520 [MESA_SHADER_VERTEX] = 1856, \
521 [MESA_SHADER_TESS_CTRL] = 672, \
522 [MESA_SHADER_TESS_EVAL] = 1120, \
523 [MESA_SHADER_GEOMETRY] = 640, \
524 }, \
525 }
526
527 #define GEN9_LP_FEATURES \
528 GEN8_FEATURES, \
529 GEN9_HW_INFO, \
530 .has_integer_dword_mul = false, \
531 .gt = 1, \
532 .has_llc = false, \
533 .has_sample_with_hiz = true, \
534 .num_slices = 1, \
535 .num_thread_per_eu = 6, \
536 .max_vs_threads = 112, \
537 .max_tcs_threads = 112, \
538 .max_tes_threads = 112, \
539 .max_gs_threads = 112, \
540 .max_cs_threads = 6 * 6, \
541 .timestamp_frequency = 19200000, \
542 .urb = { \
543 .min_entries = { \
544 [MESA_SHADER_VERTEX] = 34, \
545 [MESA_SHADER_TESS_EVAL] = 34, \
546 }, \
547 .max_entries = { \
548 [MESA_SHADER_VERTEX] = 704, \
549 [MESA_SHADER_TESS_CTRL] = 256, \
550 [MESA_SHADER_TESS_EVAL] = 416, \
551 [MESA_SHADER_GEOMETRY] = 256, \
552 }, \
553 }
554
555 #define GEN9_LP_FEATURES_3X6 \
556 GEN9_LP_FEATURES, \
557 .num_subslices = { 3, }, \
558 .num_eu_per_subslice = 6
559
560 #define GEN9_LP_FEATURES_2X6 \
561 GEN9_LP_FEATURES, \
562 .num_subslices = { 2, }, \
563 .num_eu_per_subslice = 6, \
564 .max_vs_threads = 56, \
565 .max_tcs_threads = 56, \
566 .max_tes_threads = 56, \
567 .max_gs_threads = 56, \
568 .max_cs_threads = 6 * 6, \
569 .urb = { \
570 .min_entries = { \
571 [MESA_SHADER_VERTEX] = 34, \
572 [MESA_SHADER_TESS_EVAL] = 34, \
573 }, \
574 .max_entries = { \
575 [MESA_SHADER_VERTEX] = 352, \
576 [MESA_SHADER_TESS_CTRL] = 128, \
577 [MESA_SHADER_TESS_EVAL] = 208, \
578 [MESA_SHADER_GEOMETRY] = 128, \
579 }, \
580 }
581
582 #define GEN9_FEATURES \
583 GEN8_FEATURES, \
584 GEN9_HW_INFO, \
585 .has_sample_with_hiz = true
586
587 static const struct gen_device_info gen_device_info_skl_gt1 = {
588 GEN9_FEATURES, .gt = 1,
589 .is_skylake = true,
590 .num_slices = 1,
591 .num_subslices = { 2, },
592 .num_eu_per_subslice = 6,
593 .l3_banks = 2,
594 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
595 * leading to some vertices to go missing if we use too much URB.
596 */
597 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
598 .simulator_id = 12,
599 };
600
601 static const struct gen_device_info gen_device_info_skl_gt2 = {
602 GEN9_FEATURES, .gt = 2,
603 .is_skylake = true,
604 .num_slices = 1,
605 .num_subslices = { 3, },
606 .num_eu_per_subslice = 8,
607 .l3_banks = 4,
608 .simulator_id = 12,
609 };
610
611 static const struct gen_device_info gen_device_info_skl_gt3 = {
612 GEN9_FEATURES, .gt = 3,
613 .is_skylake = true,
614 .num_slices = 2,
615 .num_subslices = { 3, 3, },
616 .num_eu_per_subslice = 8,
617 .l3_banks = 8,
618 .simulator_id = 12,
619 };
620
621 static const struct gen_device_info gen_device_info_skl_gt4 = {
622 GEN9_FEATURES, .gt = 4,
623 .is_skylake = true,
624 .num_slices = 3,
625 .num_subslices = { 3, 3, 3, },
626 .num_eu_per_subslice = 8,
627 .l3_banks = 12,
628 /* From the "L3 Allocation and Programming" documentation:
629 *
630 * "URB is limited to 1008KB due to programming restrictions. This is not a
631 * restriction of the L3 implementation, but of the FF and other clients.
632 * Therefore, in a GT4 implementation it is possible for the programmed
633 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
634 * only 1008KB of this will be used."
635 */
636 .simulator_id = 12,
637 };
638
639 static const struct gen_device_info gen_device_info_bxt = {
640 GEN9_LP_FEATURES_3X6,
641 .is_broxton = true,
642 .l3_banks = 2,
643 .simulator_id = 14,
644 };
645
646 static const struct gen_device_info gen_device_info_bxt_2x6 = {
647 GEN9_LP_FEATURES_2X6,
648 .is_broxton = true,
649 .l3_banks = 1,
650 .simulator_id = 14,
651 };
652 /*
653 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
654 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
655 */
656
657 static const struct gen_device_info gen_device_info_kbl_gt1 = {
658 GEN9_FEATURES,
659 .is_kabylake = true,
660 .gt = 1,
661
662 .max_cs_threads = 7 * 6,
663 .num_slices = 1,
664 .num_subslices = { 2, },
665 .num_eu_per_subslice = 6,
666 .l3_banks = 2,
667 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
668 * leading to some vertices to go missing if we use too much URB.
669 */
670 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
671 .simulator_id = 16,
672 };
673
674 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
675 GEN9_FEATURES,
676 .is_kabylake = true,
677 .gt = 1,
678
679 .max_cs_threads = 7 * 6,
680 .num_slices = 1,
681 .num_subslices = { 3, },
682 .num_eu_per_subslice = 6,
683 .l3_banks = 4,
684 .simulator_id = 16,
685 };
686
687 static const struct gen_device_info gen_device_info_kbl_gt2 = {
688 GEN9_FEATURES,
689 .is_kabylake = true,
690 .gt = 2,
691
692 .num_slices = 1,
693 .num_subslices = { 3, },
694 .num_eu_per_subslice = 8,
695 .l3_banks = 4,
696 .simulator_id = 16,
697 };
698
699 static const struct gen_device_info gen_device_info_kbl_gt3 = {
700 GEN9_FEATURES,
701 .is_kabylake = true,
702 .gt = 3,
703
704 .num_slices = 2,
705 .num_subslices = { 3, 3, },
706 .num_eu_per_subslice = 8,
707 .l3_banks = 8,
708 .simulator_id = 16,
709 };
710
711 static const struct gen_device_info gen_device_info_kbl_gt4 = {
712 GEN9_FEATURES,
713 .is_kabylake = true,
714 .gt = 4,
715
716 /*
717 * From the "L3 Allocation and Programming" documentation:
718 *
719 * "URB is limited to 1008KB due to programming restrictions. This
720 * is not a restriction of the L3 implementation, but of the FF and
721 * other clients. Therefore, in a GT4 implementation it is
722 * possible for the programmed allocation of the L3 data array to
723 * provide 3*384KB=1152KB for URB, but only 1008KB of this
724 * will be used."
725 */
726 .num_slices = 3,
727 .num_subslices = { 3, 3, 3, },
728 .num_eu_per_subslice = 8,
729 .l3_banks = 12,
730 .simulator_id = 16,
731 };
732
733 static const struct gen_device_info gen_device_info_glk = {
734 GEN9_LP_FEATURES_3X6,
735 .is_geminilake = true,
736 .l3_banks = 2,
737 .simulator_id = 17,
738 };
739
740 static const struct gen_device_info gen_device_info_glk_2x6 = {
741 GEN9_LP_FEATURES_2X6,
742 .is_geminilake = true,
743 .l3_banks = 2,
744 .simulator_id = 17,
745 };
746
747 static const struct gen_device_info gen_device_info_cfl_gt1 = {
748 GEN9_FEATURES,
749 .is_coffeelake = true,
750 .gt = 1,
751
752 .num_slices = 1,
753 .num_subslices = { 2, },
754 .num_eu_per_subslice = 6,
755 .l3_banks = 2,
756 /* GT1 seems to have a bug in the top of the pipe (VF/VS?) fixed functions
757 * leading to some vertices to go missing if we use too much URB.
758 */
759 .urb.max_entries[MESA_SHADER_VERTEX] = 928,
760 .simulator_id = 24,
761 };
762 static const struct gen_device_info gen_device_info_cfl_gt2 = {
763 GEN9_FEATURES,
764 .is_coffeelake = true,
765 .gt = 2,
766
767 .num_slices = 1,
768 .num_subslices = { 3, },
769 .num_eu_per_subslice = 8,
770 .l3_banks = 4,
771 .simulator_id = 24,
772 };
773
774 static const struct gen_device_info gen_device_info_cfl_gt3 = {
775 GEN9_FEATURES,
776 .is_coffeelake = true,
777 .gt = 3,
778
779 .num_slices = 2,
780 .num_subslices = { 3, 3, },
781 .num_eu_per_subslice = 8,
782 .l3_banks = 8,
783 .simulator_id = 24,
784 };
785
786 #define GEN10_HW_INFO \
787 .gen = 10, \
788 .num_thread_per_eu = 7, \
789 .max_vs_threads = 728, \
790 .max_gs_threads = 432, \
791 .max_tcs_threads = 432, \
792 .max_tes_threads = 624, \
793 .max_cs_threads = 56, \
794 .timestamp_frequency = 19200000, \
795 .urb = { \
796 .min_entries = { \
797 [MESA_SHADER_VERTEX] = 64, \
798 [MESA_SHADER_TESS_EVAL] = 34, \
799 }, \
800 .max_entries = { \
801 [MESA_SHADER_VERTEX] = 3936, \
802 [MESA_SHADER_TESS_CTRL] = 896, \
803 [MESA_SHADER_TESS_EVAL] = 2064, \
804 [MESA_SHADER_GEOMETRY] = 832, \
805 }, \
806 }
807
808 #define subslices(args...) { args, }
809
810 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
811 GEN8_FEATURES, \
812 GEN10_HW_INFO, \
813 .has_sample_with_hiz = true, \
814 .gt = _gt, \
815 .num_slices = _slices, \
816 .num_subslices = _subslices, \
817 .num_eu_per_subslice = 8, \
818 .l3_banks = _l3
819
820 static const struct gen_device_info gen_device_info_cnl_gt0_5 = {
821 /* GT0.5 */
822 GEN10_FEATURES(1, 1, subslices(2), 2),
823 .is_cannonlake = true,
824 .simulator_id = 15,
825 };
826
827 static const struct gen_device_info gen_device_info_cnl_gt1 = {
828 /* GT1 */
829 GEN10_FEATURES(1, 1, subslices(3), 3),
830 .is_cannonlake = true,
831 .simulator_id = 15,
832 };
833
834 static const struct gen_device_info gen_device_info_cnl_gt1_5 = {
835 /* GT 1.5 */
836 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
837 .is_cannonlake = true,
838 .simulator_id = 15,
839 };
840
841 static const struct gen_device_info gen_device_info_cnl_gt2 = {
842 /* GT2 */
843 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
844 .is_cannonlake = true,
845 .simulator_id = 15,
846 };
847
848 #define GEN11_HW_INFO \
849 .gen = 11, \
850 .has_pln = false, \
851 .max_vs_threads = 364, \
852 .max_gs_threads = 224, \
853 .max_tcs_threads = 224, \
854 .max_tes_threads = 364, \
855 .max_cs_threads = 56
856
857 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
858 GEN8_FEATURES, \
859 GEN11_HW_INFO, \
860 .has_64bit_float = false, \
861 .has_64bit_int = false, \
862 .has_integer_dword_mul = false, \
863 .has_sample_with_hiz = false, \
864 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
865 .num_subslices = _subslices, \
866 .num_eu_per_subslice = 8
867
868 #define GEN11_URB_MIN_MAX_ENTRIES \
869 .min_entries = { \
870 [MESA_SHADER_VERTEX] = 64, \
871 [MESA_SHADER_TESS_EVAL] = 34, \
872 }, \
873 .max_entries = { \
874 [MESA_SHADER_VERTEX] = 2384, \
875 [MESA_SHADER_TESS_CTRL] = 1032, \
876 [MESA_SHADER_TESS_EVAL] = 2384, \
877 [MESA_SHADER_GEOMETRY] = 1032, \
878 }
879
880 static const struct gen_device_info gen_device_info_icl_gt2 = {
881 GEN11_FEATURES(2, 1, subslices(8), 8),
882 .urb = {
883 GEN11_URB_MIN_MAX_ENTRIES,
884 },
885 .simulator_id = 19,
886 };
887
888 static const struct gen_device_info gen_device_info_icl_gt1_5 = {
889 GEN11_FEATURES(1, 1, subslices(6), 6),
890 .urb = {
891 GEN11_URB_MIN_MAX_ENTRIES,
892 },
893 .simulator_id = 19,
894 };
895
896 static const struct gen_device_info gen_device_info_icl_gt1 = {
897 GEN11_FEATURES(1, 1, subslices(4), 6),
898 .urb = {
899 GEN11_URB_MIN_MAX_ENTRIES,
900 },
901 .simulator_id = 19,
902 };
903
904 static const struct gen_device_info gen_device_info_icl_gt0_5 = {
905 GEN11_FEATURES(1, 1, subslices(1), 6),
906 .urb = {
907 GEN11_URB_MIN_MAX_ENTRIES,
908 },
909 .simulator_id = 19,
910 };
911
912 static const struct gen_device_info gen_device_info_ehl_7 = {
913 GEN11_FEATURES(1, 1, subslices(4), 4),
914 .is_elkhartlake = true,
915 .urb = {
916 .min_entries = {
917 [MESA_SHADER_VERTEX] = 64,
918 [MESA_SHADER_TESS_EVAL] = 34,
919 },
920 .max_entries = {
921 [MESA_SHADER_VERTEX] = 2384,
922 [MESA_SHADER_TESS_CTRL] = 1032,
923 [MESA_SHADER_TESS_EVAL] = 2384,
924 [MESA_SHADER_GEOMETRY] = 1032,
925 },
926 },
927 .disable_ccs_repack = true,
928 .simulator_id = 28,
929 };
930
931 static const struct gen_device_info gen_device_info_ehl_6 = {
932 GEN11_FEATURES(1, 1, subslices(4), 4),
933 .is_elkhartlake = true,
934 .urb = {
935 .min_entries = {
936 [MESA_SHADER_VERTEX] = 64,
937 [MESA_SHADER_TESS_EVAL] = 34,
938 },
939 .max_entries = {
940 [MESA_SHADER_VERTEX] = 2384,
941 [MESA_SHADER_TESS_CTRL] = 1032,
942 [MESA_SHADER_TESS_EVAL] = 2384,
943 [MESA_SHADER_GEOMETRY] = 1032,
944 },
945 },
946 .disable_ccs_repack = true,
947 .num_eu_per_subslice = 6,
948 .simulator_id = 28,
949 };
950
951 static const struct gen_device_info gen_device_info_ehl_5 = {
952 GEN11_FEATURES(1, 1, subslices(4), 4),
953 .is_elkhartlake = true,
954 .urb = {
955 .min_entries = {
956 [MESA_SHADER_VERTEX] = 64,
957 [MESA_SHADER_TESS_EVAL] = 34,
958 },
959 .max_entries = {
960 [MESA_SHADER_VERTEX] = 2384,
961 [MESA_SHADER_TESS_CTRL] = 1032,
962 [MESA_SHADER_TESS_EVAL] = 2384,
963 [MESA_SHADER_GEOMETRY] = 1032,
964 },
965 },
966 .disable_ccs_repack = true,
967 .num_eu_per_subslice = 4,
968 .simulator_id = 28,
969 };
970
971 static const struct gen_device_info gen_device_info_ehl_4 = {
972 GEN11_FEATURES(1, 1, subslices(2), 4),
973 .is_elkhartlake = true,
974 .urb = {
975 .min_entries = {
976 [MESA_SHADER_VERTEX] = 64,
977 [MESA_SHADER_TESS_EVAL] = 34,
978 },
979 .max_entries = {
980 [MESA_SHADER_VERTEX] = 2384,
981 [MESA_SHADER_TESS_CTRL] = 1032,
982 [MESA_SHADER_TESS_EVAL] = 2384,
983 [MESA_SHADER_GEOMETRY] = 1032,
984 },
985 },
986 .disable_ccs_repack = true,
987 .num_eu_per_subslice =4,
988 .simulator_id = 28,
989 };
990
991 #define GEN12_URB_MIN_MAX_ENTRIES \
992 .min_entries = { \
993 [MESA_SHADER_VERTEX] = 64, \
994 [MESA_SHADER_TESS_EVAL] = 34, \
995 }, \
996 .max_entries = { \
997 [MESA_SHADER_VERTEX] = 3576, \
998 [MESA_SHADER_TESS_CTRL] = 1548, \
999 [MESA_SHADER_TESS_EVAL] = 3576, \
1000 [MESA_SHADER_GEOMETRY] = 1548, \
1001 }
1002
1003 #define GEN12_HW_INFO \
1004 .gen = 12, \
1005 .has_pln = false, \
1006 .has_sample_with_hiz = false, \
1007 .has_aux_map = true, \
1008 .max_vs_threads = 546, \
1009 .max_gs_threads = 336, \
1010 .max_tcs_threads = 336, \
1011 .max_tes_threads = 546, \
1012 .max_cs_threads = 112, /* threads per DSS */ \
1013 .urb = { \
1014 GEN12_URB_MIN_MAX_ENTRIES, \
1015 }
1016
1017 #define GEN12_FEATURES(_gt, _slices, _l3) \
1018 GEN8_FEATURES, \
1019 GEN12_HW_INFO, \
1020 .has_64bit_float = false, \
1021 .has_64bit_int = false, \
1022 .has_integer_dword_mul = false, \
1023 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
1024 .simulator_id = 22, \
1025 .num_eu_per_subslice = 16
1026
1027 #define dual_subslices(args...) { args, }
1028
1029 #define GEN12_GT05_FEATURES \
1030 GEN12_FEATURES(1, 1, 4), \
1031 .num_subslices = dual_subslices(1)
1032
1033 #define GEN12_GT_FEATURES(_gt) \
1034 GEN12_FEATURES(_gt, 1, _gt == 1 ? 4 : 8), \
1035 .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
1036
1037 static const struct gen_device_info gen_device_info_tgl_gt1 = {
1038 GEN12_GT_FEATURES(1),
1039 };
1040
1041 static const struct gen_device_info gen_device_info_tgl_gt2 = {
1042 GEN12_GT_FEATURES(2),
1043 };
1044
1045 static const struct gen_device_info gen_device_info_rkl_gt05 = {
1046 GEN12_GT05_FEATURES,
1047 };
1048
1049 static const struct gen_device_info gen_device_info_rkl_gt1 = {
1050 GEN12_GT_FEATURES(1),
1051 };
1052
1053 static void
1054 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
1055 unsigned slice,
1056 unsigned subslice,
1057 unsigned eu_mask)
1058 {
1059 unsigned subslice_offset = slice * devinfo->eu_slice_stride +
1060 subslice * devinfo->eu_subslice_stride;
1061
1062 for (unsigned b_eu = 0; b_eu < devinfo->eu_subslice_stride; b_eu++) {
1063 devinfo->eu_masks[subslice_offset + b_eu] =
1064 (((1U << devinfo->num_eu_per_subslice) - 1) >> (b_eu * 8)) & 0xff;
1065 }
1066 }
1067
1068 /* Generate slice/subslice/eu masks from number of
1069 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
1070 * structure.
1071 *
1072 * These can be overridden with values reported by the kernel either from
1073 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
1074 * through the i915 query uapi.
1075 */
1076 static void
1077 fill_masks(struct gen_device_info *devinfo)
1078 {
1079 devinfo->slice_masks = (1U << devinfo->num_slices) - 1;
1080
1081 /* Subslice masks */
1082 unsigned max_subslices = 0;
1083 for (int s = 0; s < devinfo->num_slices; s++)
1084 max_subslices = MAX2(devinfo->num_subslices[s], max_subslices);
1085 devinfo->subslice_slice_stride = DIV_ROUND_UP(max_subslices, 8);
1086
1087 for (int s = 0; s < devinfo->num_slices; s++) {
1088 devinfo->subslice_masks[s * devinfo->subslice_slice_stride] =
1089 (1U << devinfo->num_subslices[s]) - 1;
1090 }
1091
1092 /* EU masks */
1093 devinfo->eu_subslice_stride = DIV_ROUND_UP(devinfo->num_eu_per_subslice, 8);
1094 devinfo->eu_slice_stride = max_subslices * devinfo->eu_subslice_stride;
1095
1096 for (int s = 0; s < devinfo->num_slices; s++) {
1097 for (int ss = 0; ss < devinfo->num_subslices[s]; ss++) {
1098 gen_device_info_set_eu_mask(devinfo, s, ss,
1099 (1U << devinfo->num_eu_per_subslice) - 1);
1100 }
1101 }
1102 }
1103
1104 static void
1105 reset_masks(struct gen_device_info *devinfo)
1106 {
1107 devinfo->subslice_slice_stride = 0;
1108 devinfo->eu_subslice_stride = 0;
1109 devinfo->eu_slice_stride = 0;
1110
1111 devinfo->num_slices = 0;
1112 devinfo->num_eu_per_subslice = 0;
1113 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1114
1115 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1116 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1117 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1118 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1119 }
1120
1121 static void
1122 update_from_topology(struct gen_device_info *devinfo,
1123 const struct drm_i915_query_topology_info *topology)
1124 {
1125 reset_masks(devinfo);
1126
1127 devinfo->subslice_slice_stride = topology->subslice_stride;
1128
1129 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1130 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1131
1132 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1133 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1134 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1135
1136 uint32_t subslice_mask_len =
1137 topology->max_slices * topology->subslice_stride;
1138 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1139 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1140 subslice_mask_len);
1141
1142 uint32_t n_subslices = 0;
1143 for (int s = 0; s < topology->max_slices; s++) {
1144 if ((devinfo->slice_masks & (1 << s)) == 0)
1145 continue;
1146
1147 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1148 devinfo->num_subslices[s] +=
1149 __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1150 }
1151 n_subslices += devinfo->num_subslices[s];
1152 }
1153 assert(n_subslices > 0);
1154
1155 if (devinfo->gen == 11) {
1156 /* On ICL we only have one slice */
1157 assert(devinfo->slice_masks == 1);
1158
1159 /* Count the number of subslices on each pixel pipe. Assume that
1160 * subslices 0-3 are on pixel pipe 0, and 4-7 are on pixel pipe 1.
1161 */
1162 unsigned subslices = devinfo->subslice_masks[0];
1163 unsigned ss = 0;
1164 while (subslices > 0) {
1165 if (subslices & 1)
1166 devinfo->ppipe_subslices[ss >= 4 ? 1 : 0] += 1;
1167 subslices >>= 1;
1168 ss++;
1169 }
1170 }
1171
1172 if (devinfo->gen == 12 && devinfo->num_slices == 1) {
1173 if (n_subslices >= 6) {
1174 assert(n_subslices == 6);
1175 devinfo->l3_banks = 8;
1176 } else if (n_subslices > 2) {
1177 devinfo->l3_banks = 6;
1178 } else {
1179 devinfo->l3_banks = 4;
1180 }
1181 }
1182
1183 uint32_t eu_mask_len =
1184 topology->eu_stride * topology->max_subslices * topology->max_slices;
1185 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1186 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1187
1188 uint32_t n_eus = 0;
1189 for (int b = 0; b < eu_mask_len; b++)
1190 n_eus += __builtin_popcount(devinfo->eu_masks[b]);
1191
1192 devinfo->num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1193 }
1194
1195 static bool
1196 update_from_masks(struct gen_device_info *devinfo, uint32_t slice_mask,
1197 uint32_t subslice_mask, uint32_t n_eus)
1198 {
1199 struct drm_i915_query_topology_info *topology;
1200
1201 assert((slice_mask & 0xff) == slice_mask);
1202
1203 size_t data_length = 100;
1204
1205 topology = calloc(1, sizeof(*topology) + data_length);
1206 if (!topology)
1207 return false;
1208
1209 topology->max_slices = util_last_bit(slice_mask);
1210 topology->max_subslices = util_last_bit(subslice_mask);
1211
1212 topology->subslice_offset = DIV_ROUND_UP(topology->max_slices, 8);
1213 topology->subslice_stride = DIV_ROUND_UP(topology->max_subslices, 8);
1214
1215 uint32_t n_subslices = __builtin_popcount(slice_mask) *
1216 __builtin_popcount(subslice_mask);
1217 uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
1218 uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
1219
1220 topology->eu_offset = topology->subslice_offset +
1221 DIV_ROUND_UP(topology->max_subslices, 8);
1222 topology->eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
1223
1224 /* Set slice mask in topology */
1225 for (int b = 0; b < topology->subslice_offset; b++)
1226 topology->data[b] = (slice_mask >> (b * 8)) & 0xff;
1227
1228 for (int s = 0; s < topology->max_slices; s++) {
1229
1230 /* Set subslice mask in topology */
1231 for (int b = 0; b < topology->subslice_stride; b++) {
1232 int subslice_offset = topology->subslice_offset +
1233 s * topology->subslice_stride + b;
1234
1235 topology->data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
1236 }
1237
1238 /* Set eu mask in topology */
1239 for (int ss = 0; ss < topology->max_subslices; ss++) {
1240 for (int b = 0; b < topology->eu_stride; b++) {
1241 int eu_offset = topology->eu_offset +
1242 (s * topology->max_subslices + ss) * topology->eu_stride + b;
1243
1244 topology->data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
1245 }
1246 }
1247 }
1248
1249 update_from_topology(devinfo, topology);
1250 free(topology);
1251
1252 return true;
1253 }
1254
1255 static bool
1256 getparam(int fd, uint32_t param, int *value)
1257 {
1258 int tmp;
1259
1260 struct drm_i915_getparam gp = {
1261 .param = param,
1262 .value = &tmp,
1263 };
1264
1265 int ret = gen_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
1266 if (ret != 0)
1267 return false;
1268
1269 *value = tmp;
1270 return true;
1271 }
1272
1273 bool
1274 gen_get_device_info_from_pci_id(int pci_id,
1275 struct gen_device_info *devinfo)
1276 {
1277 switch (pci_id) {
1278 #undef CHIPSET
1279 #define CHIPSET(id, family, fam_str, name) \
1280 case id: *devinfo = gen_device_info_##family; break;
1281 #include "pci_ids/i965_pci_ids.h"
1282 #include "pci_ids/iris_pci_ids.h"
1283 default:
1284 fprintf(stderr, "Driver does not support the 0x%x PCI ID.\n", pci_id);
1285 return false;
1286 }
1287
1288 fill_masks(devinfo);
1289
1290 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
1291 *
1292 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
1293 * allocate scratch space enough so that each slice has 4 slices allowed."
1294 *
1295 * The equivalent internal documentation says that this programming note
1296 * applies to all Gen9+ platforms.
1297 *
1298 * The hardware typically calculates the scratch space pointer by taking
1299 * the base address, and adding per-thread-scratch-space * thread ID.
1300 * Extra padding can be necessary depending how the thread IDs are
1301 * calculated for a particular shader stage.
1302 */
1303
1304 switch(devinfo->gen) {
1305 case 9:
1306 case 10:
1307 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1308 * devinfo->num_slices
1309 * 4; /* effective subslices per slice */
1310 break;
1311 case 11:
1312 case 12:
1313 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1314 * devinfo->num_slices
1315 * 8; /* subslices per slice */
1316 break;
1317 default:
1318 assert(devinfo->gen < 9);
1319 break;
1320 }
1321
1322 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1323
1324 devinfo->chipset_id = pci_id;
1325 return true;
1326 }
1327
1328 const char *
1329 gen_get_device_name(int devid)
1330 {
1331 switch (devid) {
1332 #undef CHIPSET
1333 #define CHIPSET(id, family, fam_str, name) case id: return name " (" fam_str ")"; break;
1334 #include "pci_ids/i965_pci_ids.h"
1335 #include "pci_ids/iris_pci_ids.h"
1336 default:
1337 return NULL;
1338 }
1339 }
1340
1341 /**
1342 * for gen8/gen9, SLICE_MASK/SUBSLICE_MASK can be used to compute the topology
1343 * (kernel 4.13+)
1344 */
1345 static bool
1346 getparam_topology(struct gen_device_info *devinfo, int fd)
1347 {
1348 int slice_mask = 0;
1349 if (!getparam(fd, I915_PARAM_SLICE_MASK, &slice_mask))
1350 return false;
1351
1352 int n_eus;
1353 if (!getparam(fd, I915_PARAM_EU_TOTAL, &n_eus))
1354 return false;
1355
1356 int subslice_mask = 0;
1357 if (!getparam(fd, I915_PARAM_SUBSLICE_MASK, &subslice_mask))
1358 return false;
1359
1360 return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1361 }
1362
1363 /**
1364 * preferred API for updating the topology in devinfo (kernel 4.17+)
1365 */
1366 static bool
1367 query_topology(struct gen_device_info *devinfo, int fd)
1368 {
1369 struct drm_i915_query_item item = {
1370 .query_id = DRM_I915_QUERY_TOPOLOGY_INFO,
1371 };
1372 struct drm_i915_query query = {
1373 .num_items = 1,
1374 .items_ptr = (uintptr_t) &item,
1375 };
1376
1377 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query))
1378 return false;
1379
1380 if (item.length < 0)
1381 return false;
1382
1383 struct drm_i915_query_topology_info *topo_info =
1384 (struct drm_i915_query_topology_info *) calloc(1, item.length);
1385 item.data_ptr = (uintptr_t) topo_info;
1386
1387 if (gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &query) ||
1388 item.length <= 0)
1389 return false;
1390
1391 update_from_topology(devinfo, topo_info);
1392
1393 free(topo_info);
1394
1395 return true;
1396
1397 }
1398
1399 int
1400 gen_get_aperture_size(int fd, uint64_t *size)
1401 {
1402 struct drm_i915_gem_get_aperture aperture = { 0 };
1403
1404 int ret = gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1405 if (ret == 0 && size)
1406 *size = aperture.aper_size;
1407
1408 return ret;
1409 }
1410
1411 bool
1412 gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
1413 {
1414 int devid = 0;
1415
1416 const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
1417 if (devid_override && strlen(devid_override) > 0) {
1418 if (geteuid() == getuid()) {
1419 devid = gen_device_name_to_pci_device_id(devid_override);
1420 /* Fallback to PCI ID. */
1421 if (devid <= 0)
1422 devid = strtol(devid_override, NULL, 0);
1423 if (devid <= 0) {
1424 fprintf(stderr, "Invalid INTEL_DEVID_OVERRIDE=\"%s\". "
1425 "Use a valid numeric PCI ID or one of the supported "
1426 "platform names: %s", devid_override, name_map[0].name);
1427 for (unsigned i = 1; i < ARRAY_SIZE(name_map); i++)
1428 fprintf(stderr, ", %s", name_map[i].name);
1429 fprintf(stderr, "\n");
1430 return false;
1431 }
1432 } else {
1433 fprintf(stderr, "Ignoring INTEL_DEVID_OVERRIDE=\"%s\" because "
1434 "real and effective user ID don't match.\n", devid_override);
1435 }
1436 }
1437
1438 if (devid > 0) {
1439 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1440 return false;
1441 devinfo->no_hw = true;
1442 } else {
1443 /* query the device id */
1444 if (!getparam(fd, I915_PARAM_CHIPSET_ID, &devid))
1445 return false;
1446 if (!gen_get_device_info_from_pci_id(devid, devinfo))
1447 return false;
1448 devinfo->no_hw = false;
1449 }
1450
1451 /* remaining initializion queries the kernel for device info */
1452 if (devinfo->no_hw)
1453 return true;
1454
1455 int timestamp_frequency;
1456 if (getparam(fd, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1457 &timestamp_frequency))
1458 devinfo->timestamp_frequency = timestamp_frequency;
1459 else if (devinfo->gen >= 10)
1460 /* gen10 and later requires the timestamp_frequency to be updated */
1461 return false;
1462
1463 if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
1464 devinfo->revision = 0;
1465
1466 if (!query_topology(devinfo, fd)) {
1467 if (devinfo->gen >= 10) {
1468 /* topology uAPI required for CNL+ (kernel 4.17+) */
1469 return false;
1470 }
1471
1472 /* else use the kernel 4.13+ api for gen8+. For older kernels, topology
1473 * will be wrong, affecting GPU metrics. In this case, fail silently.
1474 */
1475 getparam_topology(devinfo, fd);
1476 }
1477
1478 gen_get_aperture_size(fd, &devinfo->aperture_bytes);
1479
1480 return true;
1481 }