2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "gen_device_info.h"
30 #include "compiler/shader_enums.h"
31 #include "util/macros.h"
34 * Get the PCI ID for the device name.
36 * Returns -1 if the device is not known.
39 gen_device_name_to_pci_device_id(const char *name
)
63 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
64 if (!strcmp(name_map
[i
].name
, name
))
65 return name_map
[i
].pci_id
;
72 * Get the overridden PCI ID for the device. This is set with the
73 * INTEL_DEVID_OVERRIDE environment variable.
75 * Returns -1 if the override is not set.
78 gen_get_pci_device_id_override(void)
80 if (geteuid() == getuid()) {
81 const char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
83 const int id
= gen_device_name_to_pci_device_id(devid_override
);
84 return id
>= 0 ? id
: strtol(devid_override
, NULL
, 0);
91 static const struct gen_device_info gen_device_info_i965
= {
93 .has_negative_rhw_bug
= true,
95 .num_subslices
= { 1, },
96 .num_eu_per_subslice
= 8,
97 .num_thread_per_eu
= 4,
100 .max_wm_threads
= 8 * 4,
104 .timestamp_frequency
= 12500000,
107 static const struct gen_device_info gen_device_info_g4x
= {
111 .has_surface_tile_offset
= true,
114 .num_subslices
= { 1, },
115 .num_eu_per_subslice
= 10,
116 .num_thread_per_eu
= 5,
117 .max_vs_threads
= 32,
119 .max_wm_threads
= 10 * 5,
123 .timestamp_frequency
= 12500000,
126 static const struct gen_device_info gen_device_info_ilk
= {
130 .has_surface_tile_offset
= true,
132 .num_subslices
= { 1, },
133 .num_eu_per_subslice
= 12,
134 .num_thread_per_eu
= 6,
135 .max_vs_threads
= 72,
136 .max_gs_threads
= 32,
137 .max_wm_threads
= 12 * 6,
141 .timestamp_frequency
= 12500000,
144 static const struct gen_device_info gen_device_info_snb_gt1
= {
147 .has_hiz_and_separate_stencil
= true,
150 .has_surface_tile_offset
= true,
151 .needs_unlit_centroid_workaround
= true,
153 .num_subslices
= { 1, },
154 .num_eu_per_subslice
= 6,
155 .num_thread_per_eu
= 6, /* Not confirmed */
156 .max_vs_threads
= 24,
157 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
158 .max_wm_threads
= 40,
162 [MESA_SHADER_VERTEX
] = 24,
165 [MESA_SHADER_VERTEX
] = 256,
166 [MESA_SHADER_GEOMETRY
] = 256,
169 .timestamp_frequency
= 12500000,
172 static const struct gen_device_info gen_device_info_snb_gt2
= {
175 .has_hiz_and_separate_stencil
= true,
178 .has_surface_tile_offset
= true,
179 .needs_unlit_centroid_workaround
= true,
181 .num_subslices
= { 1, },
182 .num_eu_per_subslice
= 12,
183 .num_thread_per_eu
= 6, /* Not confirmed */
184 .max_vs_threads
= 60,
185 .max_gs_threads
= 60,
186 .max_wm_threads
= 80,
190 [MESA_SHADER_VERTEX
] = 24,
193 [MESA_SHADER_VERTEX
] = 256,
194 [MESA_SHADER_GEOMETRY
] = 256,
197 .timestamp_frequency
= 12500000,
200 #define GEN7_FEATURES \
202 .has_hiz_and_separate_stencil = true, \
203 .must_use_separate_stencil = true, \
206 .has_64bit_types = true, \
207 .has_surface_tile_offset = true, \
208 .timestamp_frequency = 12500000
210 static const struct gen_device_info gen_device_info_ivb_gt1
= {
211 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
213 .num_subslices
= { 1, },
214 .num_eu_per_subslice
= 6,
215 .num_thread_per_eu
= 6,
217 .max_vs_threads
= 36,
218 .max_tcs_threads
= 36,
219 .max_tes_threads
= 36,
220 .max_gs_threads
= 36,
221 .max_wm_threads
= 48,
222 .max_cs_threads
= 36,
226 [MESA_SHADER_VERTEX
] = 32,
227 [MESA_SHADER_TESS_EVAL
] = 10,
230 [MESA_SHADER_VERTEX
] = 512,
231 [MESA_SHADER_TESS_CTRL
] = 32,
232 [MESA_SHADER_TESS_EVAL
] = 288,
233 [MESA_SHADER_GEOMETRY
] = 192,
238 static const struct gen_device_info gen_device_info_ivb_gt2
= {
239 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
241 .num_subslices
= { 1, },
242 .num_eu_per_subslice
= 12,
243 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
244 * @max_wm_threads ... */
246 .max_vs_threads
= 128,
247 .max_tcs_threads
= 128,
248 .max_tes_threads
= 128,
249 .max_gs_threads
= 128,
250 .max_wm_threads
= 172,
251 .max_cs_threads
= 64,
255 [MESA_SHADER_VERTEX
] = 32,
256 [MESA_SHADER_TESS_EVAL
] = 10,
259 [MESA_SHADER_VERTEX
] = 704,
260 [MESA_SHADER_TESS_CTRL
] = 64,
261 [MESA_SHADER_TESS_EVAL
] = 448,
262 [MESA_SHADER_GEOMETRY
] = 320,
267 static const struct gen_device_info gen_device_info_byt
= {
268 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
270 .num_subslices
= { 1, },
271 .num_eu_per_subslice
= 4,
272 .num_thread_per_eu
= 8,
275 .max_vs_threads
= 36,
276 .max_tcs_threads
= 36,
277 .max_tes_threads
= 36,
278 .max_gs_threads
= 36,
279 .max_wm_threads
= 48,
280 .max_cs_threads
= 32,
284 [MESA_SHADER_VERTEX
] = 32,
285 [MESA_SHADER_TESS_EVAL
] = 10,
288 [MESA_SHADER_VERTEX
] = 512,
289 [MESA_SHADER_TESS_CTRL
] = 32,
290 [MESA_SHADER_TESS_EVAL
] = 288,
291 [MESA_SHADER_GEOMETRY
] = 192,
296 #define HSW_FEATURES \
298 .is_haswell = true, \
299 .supports_simd16_3src = true, \
300 .has_resource_streamer = true
302 static const struct gen_device_info gen_device_info_hsw_gt1
= {
303 HSW_FEATURES
, .gt
= 1,
305 .num_subslices
= { 1, },
306 .num_eu_per_subslice
= 10,
307 .num_thread_per_eu
= 7,
309 .max_vs_threads
= 70,
310 .max_tcs_threads
= 70,
311 .max_tes_threads
= 70,
312 .max_gs_threads
= 70,
313 .max_wm_threads
= 102,
314 .max_cs_threads
= 70,
318 [MESA_SHADER_VERTEX
] = 32,
319 [MESA_SHADER_TESS_EVAL
] = 10,
322 [MESA_SHADER_VERTEX
] = 640,
323 [MESA_SHADER_TESS_CTRL
] = 64,
324 [MESA_SHADER_TESS_EVAL
] = 384,
325 [MESA_SHADER_GEOMETRY
] = 256,
330 static const struct gen_device_info gen_device_info_hsw_gt2
= {
331 HSW_FEATURES
, .gt
= 2,
333 .num_subslices
= { 2, },
334 .num_eu_per_subslice
= 10,
335 .num_thread_per_eu
= 7,
337 .max_vs_threads
= 280,
338 .max_tcs_threads
= 256,
339 .max_tes_threads
= 280,
340 .max_gs_threads
= 256,
341 .max_wm_threads
= 204,
342 .max_cs_threads
= 70,
346 [MESA_SHADER_VERTEX
] = 64,
347 [MESA_SHADER_TESS_EVAL
] = 10,
350 [MESA_SHADER_VERTEX
] = 1664,
351 [MESA_SHADER_TESS_CTRL
] = 128,
352 [MESA_SHADER_TESS_EVAL
] = 960,
353 [MESA_SHADER_GEOMETRY
] = 640,
358 static const struct gen_device_info gen_device_info_hsw_gt3
= {
359 HSW_FEATURES
, .gt
= 3,
361 .num_subslices
= { 2, },
362 .num_eu_per_subslice
= 10,
363 .num_thread_per_eu
= 7,
365 .max_vs_threads
= 280,
366 .max_tcs_threads
= 256,
367 .max_tes_threads
= 280,
368 .max_gs_threads
= 256,
369 .max_wm_threads
= 408,
370 .max_cs_threads
= 70,
374 [MESA_SHADER_VERTEX
] = 64,
375 [MESA_SHADER_TESS_EVAL
] = 10,
378 [MESA_SHADER_VERTEX
] = 1664,
379 [MESA_SHADER_TESS_CTRL
] = 128,
380 [MESA_SHADER_TESS_EVAL
] = 960,
381 [MESA_SHADER_GEOMETRY
] = 640,
386 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
387 * so keep things conservative for now and set has_sample_with_hiz = false.
389 #define GEN8_FEATURES \
391 .has_hiz_and_separate_stencil = true, \
392 .has_resource_streamer = true, \
393 .must_use_separate_stencil = true, \
395 .has_sample_with_hiz = false, \
397 .has_integer_dword_mul = true, \
398 .has_64bit_types = true, \
399 .supports_simd16_3src = true, \
400 .has_surface_tile_offset = true, \
401 .max_vs_threads = 504, \
402 .max_tcs_threads = 504, \
403 .max_tes_threads = 504, \
404 .max_gs_threads = 504, \
405 .max_wm_threads = 384, \
406 .timestamp_frequency = 12500000
408 static const struct gen_device_info gen_device_info_bdw_gt1
= {
409 GEN8_FEATURES
, .gt
= 1,
410 .is_broadwell
= true,
412 .num_subslices
= { 2, },
413 .num_eu_per_subslice
= 8,
414 .num_thread_per_eu
= 7,
416 .max_cs_threads
= 42,
420 [MESA_SHADER_VERTEX
] = 64,
421 [MESA_SHADER_TESS_EVAL
] = 34,
424 [MESA_SHADER_VERTEX
] = 2560,
425 [MESA_SHADER_TESS_CTRL
] = 504,
426 [MESA_SHADER_TESS_EVAL
] = 1536,
427 [MESA_SHADER_GEOMETRY
] = 960,
432 static const struct gen_device_info gen_device_info_bdw_gt2
= {
433 GEN8_FEATURES
, .gt
= 2,
434 .is_broadwell
= true,
436 .num_subslices
= { 3, },
437 .num_eu_per_subslice
= 8,
438 .num_thread_per_eu
= 7,
440 .max_cs_threads
= 56,
444 [MESA_SHADER_VERTEX
] = 64,
445 [MESA_SHADER_TESS_EVAL
] = 34,
448 [MESA_SHADER_VERTEX
] = 2560,
449 [MESA_SHADER_TESS_CTRL
] = 504,
450 [MESA_SHADER_TESS_EVAL
] = 1536,
451 [MESA_SHADER_GEOMETRY
] = 960,
456 static const struct gen_device_info gen_device_info_bdw_gt3
= {
457 GEN8_FEATURES
, .gt
= 3,
458 .is_broadwell
= true,
460 .num_subslices
= { 3, 3, },
461 .num_eu_per_subslice
= 8,
462 .num_thread_per_eu
= 7,
464 .max_cs_threads
= 56,
468 [MESA_SHADER_VERTEX
] = 64,
469 [MESA_SHADER_TESS_EVAL
] = 34,
472 [MESA_SHADER_VERTEX
] = 2560,
473 [MESA_SHADER_TESS_CTRL
] = 504,
474 [MESA_SHADER_TESS_EVAL
] = 1536,
475 [MESA_SHADER_GEOMETRY
] = 960,
480 static const struct gen_device_info gen_device_info_chv
= {
481 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
483 .has_integer_dword_mul
= false,
485 .num_subslices
= { 2, },
486 .num_eu_per_subslice
= 8,
487 .num_thread_per_eu
= 7,
489 .max_vs_threads
= 80,
490 .max_tcs_threads
= 80,
491 .max_tes_threads
= 80,
492 .max_gs_threads
= 80,
493 .max_wm_threads
= 128,
494 .max_cs_threads
= 6 * 7,
498 [MESA_SHADER_VERTEX
] = 34,
499 [MESA_SHADER_TESS_EVAL
] = 34,
502 [MESA_SHADER_VERTEX
] = 640,
503 [MESA_SHADER_TESS_CTRL
] = 80,
504 [MESA_SHADER_TESS_EVAL
] = 384,
505 [MESA_SHADER_GEOMETRY
] = 256,
510 #define GEN9_HW_INFO \
512 .max_vs_threads = 336, \
513 .max_gs_threads = 336, \
514 .max_tcs_threads = 336, \
515 .max_tes_threads = 336, \
516 .max_cs_threads = 56, \
517 .timestamp_frequency = 12000000, \
521 [MESA_SHADER_VERTEX] = 64, \
522 [MESA_SHADER_TESS_EVAL] = 34, \
525 [MESA_SHADER_VERTEX] = 1856, \
526 [MESA_SHADER_TESS_CTRL] = 672, \
527 [MESA_SHADER_TESS_EVAL] = 1120, \
528 [MESA_SHADER_GEOMETRY] = 640, \
532 #define GEN9_LP_FEATURES \
535 .has_integer_dword_mul = false, \
538 .has_sample_with_hiz = true, \
540 .num_thread_per_eu = 6, \
541 .max_vs_threads = 112, \
542 .max_tcs_threads = 112, \
543 .max_tes_threads = 112, \
544 .max_gs_threads = 112, \
545 .max_cs_threads = 6 * 6, \
546 .timestamp_frequency = 19200000, \
550 [MESA_SHADER_VERTEX] = 34, \
551 [MESA_SHADER_TESS_EVAL] = 34, \
554 [MESA_SHADER_VERTEX] = 704, \
555 [MESA_SHADER_TESS_CTRL] = 256, \
556 [MESA_SHADER_TESS_EVAL] = 416, \
557 [MESA_SHADER_GEOMETRY] = 256, \
561 #define GEN9_LP_FEATURES_3X6 \
563 .num_subslices = { 3, }, \
564 .num_eu_per_subslice = 6
566 #define GEN9_LP_FEATURES_2X6 \
568 .num_subslices = { 2, }, \
569 .num_eu_per_subslice = 6, \
570 .max_vs_threads = 56, \
571 .max_tcs_threads = 56, \
572 .max_tes_threads = 56, \
573 .max_gs_threads = 56, \
574 .max_cs_threads = 6 * 6, \
578 [MESA_SHADER_VERTEX] = 34, \
579 [MESA_SHADER_TESS_EVAL] = 34, \
582 [MESA_SHADER_VERTEX] = 352, \
583 [MESA_SHADER_TESS_CTRL] = 128, \
584 [MESA_SHADER_TESS_EVAL] = 208, \
585 [MESA_SHADER_GEOMETRY] = 128, \
589 #define GEN9_FEATURES \
592 .has_sample_with_hiz = true, \
593 .num_thread_per_eu = 7
595 static const struct gen_device_info gen_device_info_skl_gt1
= {
596 GEN9_FEATURES
, .gt
= 1,
599 .num_subslices
= { 2, },
600 .num_eu_per_subslice
= 6,
605 static const struct gen_device_info gen_device_info_skl_gt2
= {
606 GEN9_FEATURES
, .gt
= 2,
609 .num_subslices
= { 3, },
610 .num_eu_per_subslice
= 8,
614 static const struct gen_device_info gen_device_info_skl_gt3
= {
615 GEN9_FEATURES
, .gt
= 3,
618 .num_subslices
= { 3, 3, },
619 .num_eu_per_subslice
= 8,
623 static const struct gen_device_info gen_device_info_skl_gt4
= {
624 GEN9_FEATURES
, .gt
= 4,
627 .num_subslices
= { 3, 3, 3, },
628 .num_eu_per_subslice
= 8,
630 /* From the "L3 Allocation and Programming" documentation:
632 * "URB is limited to 1008KB due to programming restrictions. This is not a
633 * restriction of the L3 implementation, but of the FF and other clients.
634 * Therefore, in a GT4 implementation it is possible for the programmed
635 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
636 * only 1008KB of this will be used."
638 .urb
.size
= 1008 / 3,
641 static const struct gen_device_info gen_device_info_bxt
= {
642 GEN9_LP_FEATURES_3X6
,
647 static const struct gen_device_info gen_device_info_bxt_2x6
= {
648 GEN9_LP_FEATURES_2X6
,
653 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
654 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
657 static const struct gen_device_info gen_device_info_kbl_gt1
= {
662 .max_cs_threads
= 7 * 6,
665 .num_subslices
= { 2, },
666 .num_eu_per_subslice
= 6,
670 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
675 .max_cs_threads
= 7 * 6,
677 .num_subslices
= { 3, },
678 .num_eu_per_subslice
= 6,
682 static const struct gen_device_info gen_device_info_kbl_gt2
= {
688 .num_subslices
= { 3, },
689 .num_eu_per_subslice
= 8,
693 static const struct gen_device_info gen_device_info_kbl_gt3
= {
699 .num_subslices
= { 3, 3, },
700 .num_eu_per_subslice
= 8,
704 static const struct gen_device_info gen_device_info_kbl_gt4
= {
710 * From the "L3 Allocation and Programming" documentation:
712 * "URB is limited to 1008KB due to programming restrictions. This
713 * is not a restriction of the L3 implementation, but of the FF and
714 * other clients. Therefore, in a GT4 implementation it is
715 * possible for the programmed allocation of the L3 data array to
716 * provide 3*384KB=1152KB for URB, but only 1008KB of this
719 .urb
.size
= 1008 / 3,
721 .num_subslices
= { 3, 3, 3, },
722 .num_eu_per_subslice
= 8,
726 static const struct gen_device_info gen_device_info_glk
= {
727 GEN9_LP_FEATURES_3X6
,
728 .is_geminilake
= true,
732 /*TODO: Initialize l3_banks when we know the number. */
733 static const struct gen_device_info gen_device_info_glk_2x6
= {
734 GEN9_LP_FEATURES_2X6
,
735 .is_geminilake
= true,
738 static const struct gen_device_info gen_device_info_cfl_gt1
= {
740 .is_coffeelake
= true,
744 .num_subslices
= { 2, },
745 .num_eu_per_subslice
= 6,
748 static const struct gen_device_info gen_device_info_cfl_gt2
= {
750 .is_coffeelake
= true,
754 .num_subslices
= { 3, },
755 .num_eu_per_subslice
= 8,
759 static const struct gen_device_info gen_device_info_cfl_gt3
= {
761 .is_coffeelake
= true,
765 .num_subslices
= { 3, 3, },
766 .num_eu_per_subslice
= 8,
770 #define GEN10_HW_INFO \
772 .num_thread_per_eu = 7, \
773 .max_vs_threads = 728, \
774 .max_gs_threads = 432, \
775 .max_tcs_threads = 432, \
776 .max_tes_threads = 624, \
777 .max_cs_threads = 56, \
778 .timestamp_frequency = 19200000, \
782 [MESA_SHADER_VERTEX] = 64, \
783 [MESA_SHADER_TESS_EVAL] = 34, \
786 [MESA_SHADER_VERTEX] = 3936, \
787 [MESA_SHADER_TESS_CTRL] = 896, \
788 [MESA_SHADER_TESS_EVAL] = 2064, \
789 [MESA_SHADER_GEOMETRY] = 832, \
793 #define subslices(args...) { args, }
795 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
798 .has_sample_with_hiz = true, \
800 .num_slices = _slices, \
801 .num_subslices = _subslices, \
802 .num_eu_per_subslice = 8, \
805 static const struct gen_device_info gen_device_info_cnl_2x8
= {
807 GEN10_FEATURES(1, 1, subslices(2), 2),
808 .is_cannonlake
= true,
811 static const struct gen_device_info gen_device_info_cnl_3x8
= {
813 GEN10_FEATURES(1, 1, subslices(3), 3),
814 .is_cannonlake
= true,
817 static const struct gen_device_info gen_device_info_cnl_4x8
= {
819 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
820 .is_cannonlake
= true,
823 static const struct gen_device_info gen_device_info_cnl_5x8
= {
825 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
826 .is_cannonlake
= true,
829 #define GEN11_HW_INFO \
832 .max_vs_threads = 364, \
833 .max_gs_threads = 224, \
834 .max_tcs_threads = 224, \
835 .max_tes_threads = 364, \
836 .max_cs_threads = 56, \
840 [MESA_SHADER_VERTEX] = 64, \
841 [MESA_SHADER_TESS_EVAL] = 34, \
844 [MESA_SHADER_VERTEX] = 2384, \
845 [MESA_SHADER_TESS_CTRL] = 1032, \
846 [MESA_SHADER_TESS_EVAL] = 2384, \
847 [MESA_SHADER_GEOMETRY] = 1032, \
851 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
854 .has_64bit_types = false, \
855 .has_integer_dword_mul = false, \
856 .has_sample_with_hiz = false, \
857 .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
858 .num_subslices = _subslices, \
859 .num_eu_per_subslice = 8
861 static const struct gen_device_info gen_device_info_icl_8x8
= {
862 GEN11_FEATURES(2, 1, subslices(8), 8),
865 static const struct gen_device_info gen_device_info_icl_6x8
= {
866 GEN11_FEATURES(1, 1, subslices(6), 6),
869 static const struct gen_device_info gen_device_info_icl_4x8
= {
870 GEN11_FEATURES(1, 1, subslices(4), 6),
873 static const struct gen_device_info gen_device_info_icl_1x8
= {
874 GEN11_FEATURES(1, 1, subslices(1), 6),
878 gen_device_info_set_eu_mask(struct gen_device_info
*devinfo
,
883 unsigned subslice_offset
= slice
* devinfo
->eu_slice_stride
+
884 subslice
* devinfo
->eu_subslice_stride
;
886 for (unsigned b_eu
= 0; b_eu
< devinfo
->eu_subslice_stride
; b_eu
++) {
887 devinfo
->eu_masks
[subslice_offset
+ b_eu
] =
888 (((1U << devinfo
->num_eu_per_subslice
) - 1) >> (b_eu
* 8)) & 0xff;
892 /* Generate slice/subslice/eu masks from number of
893 * slices/subslices/eu_per_subslices in the per generation/gt gen_device_info
896 * These can be overridden with values reported by the kernel either from
897 * getparam SLICE_MASK/SUBSLICE_MASK values or from the kernel version 4.17+
898 * through the i915 query uapi.
901 fill_masks(struct gen_device_info
*devinfo
)
903 devinfo
->slice_masks
= (1U << devinfo
->num_slices
) - 1;
906 unsigned max_subslices
= 0;
907 for (int s
= 0; s
< devinfo
->num_slices
; s
++)
908 max_subslices
= MAX2(devinfo
->num_subslices
[s
], max_subslices
);
909 devinfo
->subslice_slice_stride
= DIV_ROUND_UP(max_subslices
, 8);
911 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
912 devinfo
->subslice_masks
[s
* devinfo
->subslice_slice_stride
] =
913 (1U << devinfo
->num_subslices
[s
]) - 1;
917 devinfo
->eu_subslice_stride
= DIV_ROUND_UP(devinfo
->num_eu_per_subslice
, 8);
918 devinfo
->eu_slice_stride
= max_subslices
* devinfo
->eu_subslice_stride
;
920 for (int s
= 0; s
< devinfo
->num_slices
; s
++) {
921 for (int ss
= 0; ss
< devinfo
->num_subslices
[s
]; ss
++) {
922 gen_device_info_set_eu_mask(devinfo
, s
, ss
,
923 (1U << devinfo
->num_eu_per_subslice
) - 1);
929 gen_get_device_info(int devid
, struct gen_device_info
*devinfo
)
933 #define CHIPSET(id, family, name) \
934 case id: *devinfo = gen_device_info_##family; break;
935 #include "pci_ids/i965_pci_ids.h"
937 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
943 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
945 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
946 * allocate scratch space enough so that each slice has 4 slices allowed."
948 * The equivalent internal documentation says that this programming note
949 * applies to all Gen9+ platforms.
951 * The hardware typically calculates the scratch space pointer by taking
952 * the base address, and adding per-thread-scratch-space * thread ID.
953 * Extra padding can be necessary depending how the thread IDs are
954 * calculated for a particular shader stage.
957 switch(devinfo
->gen
) {
960 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
961 * devinfo
->num_slices
962 * 4; /* effective subslices per slice */
965 devinfo
->max_wm_threads
= 128 /* threads-per-PSD */
966 * devinfo
->num_slices
967 * 8; /* subslices per slice */
973 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
979 gen_get_device_name(int devid
)
983 #define CHIPSET(id, family, name) case id: return name;
984 #include "pci_ids/i965_pci_ids.h"