src/intel/dev/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <unistd.h>
  29 #include "gen_device_info.h"
  30 #include "compiler/shader_enums.h"
  31 #include "util/macros.h"
  32
  33 /**
  34  * Get the PCI ID for the device name.
  35  *
  36  * Returns -1 if the device is not known.
  37  */
  38 int
  39 gen_device_name_to_pci_device_id(const char *name)
  40 {
  41    static const struct {
  42       const char *name;
  43       int pci_id;
  44    } name_map[] = {
  45       { "brw", 0x2a02 },
  46       { "g4x", 0x2a42 },
  47       { "ilk", 0x0042 },
  48       { "snb", 0x0126 },
  49       { "ivb", 0x016a },
  50       { "hsw", 0x0d2e },
  51       { "byt", 0x0f33 },
  52       { "bdw", 0x162e },
  53       { "chv", 0x22B3 },
  54       { "skl", 0x1912 },
  55       { "bxt", 0x5A85 },
  56       { "kbl", 0x5912 },
  57       { "glk", 0x3185 },
  58       { "cfl", 0x3E9B },
  59       { "cnl", 0x5a52 },
  60       { "icl", 0x8a52 },
  61    };
  62
  63    for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
  64       if (!strcmp(name_map[i].name, name))
  65          return name_map[i].pci_id;
  66    }
  67
  68    return -1;
  69 }
  70
  71 /**
  72  * Get the overridden PCI ID for the device. This is set with the
  73  * INTEL_DEVID_OVERRIDE environment variable.
  74  *
  75  * Returns -1 if the override is not set.
  76  */
  77 int
  78 gen_get_pci_device_id_override(void)
  79 {
  80    if (geteuid() == getuid()) {
  81       const char *devid_override = getenv("INTEL_DEVID_OVERRIDE");
  82       if (devid_override) {
  83          const int id = gen_device_name_to_pci_device_id(devid_override);
  84          return id >= 0 ? id : strtol(devid_override, NULL, 0);
  85       }
  86    }
  87
  88    return -1;
  89 }
  90
  91 static const struct gen_device_info gen_device_info_i965 = {
  92    .gen = 4,
  93    .has_negative_rhw_bug = true,
  94    .num_slices = 1,
  95    .num_subslices = { 1, },
  96    .num_thread_per_eu = 4,
  97    .max_vs_threads = 16,
  98    .max_gs_threads = 2,
  99    .max_wm_threads = 8 * 4,
 100    .urb = {
 101       .size = 256,
 102    },
 103    .timestamp_frequency = 12500000,
 104 };
 105
 106 static const struct gen_device_info gen_device_info_g4x = {
 107    .gen = 4,
 108    .has_pln = true,
 109    .has_compr4 = true,
 110    .has_surface_tile_offset = true,
 111    .is_g4x = true,
 112    .num_slices = 1,
 113    .num_subslices = { 1, },
 114    .num_thread_per_eu = 5,
 115    .max_vs_threads = 32,
 116    .max_gs_threads = 2,
 117    .max_wm_threads = 10 * 5,
 118    .urb = {
 119       .size = 384,
 120    },
 121    .timestamp_frequency = 12500000,
 122 };
 123
 124 static const struct gen_device_info gen_device_info_ilk = {
 125    .gen = 5,
 126    .has_pln = true,
 127    .has_compr4 = true,
 128    .has_surface_tile_offset = true,
 129    .num_slices = 1,
 130    .num_subslices = { 1, },
 131    .num_thread_per_eu = 6,
 132    .max_vs_threads = 72,
 133    .max_gs_threads = 32,
 134    .max_wm_threads = 12 * 6,
 135    .urb = {
 136       .size = 1024,
 137    },
 138    .timestamp_frequency = 12500000,
 139 };
 140
 141 static const struct gen_device_info gen_device_info_snb_gt1 = {
 142    .gen = 6,
 143    .gt = 1,
 144    .has_hiz_and_separate_stencil = true,
 145    .has_llc = true,
 146    .has_pln = true,
 147    .has_surface_tile_offset = true,
 148    .needs_unlit_centroid_workaround = true,
 149    .num_slices = 1,
 150    .num_subslices = { 1, },
 151    .num_thread_per_eu = 6, /* Not confirmed */
 152    .max_vs_threads = 24,
 153    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
 154    .max_wm_threads = 40,
 155    .urb = {
 156       .size = 32,
 157       .min_entries = {
 158          [MESA_SHADER_VERTEX]   = 24,
 159       },
 160       .max_entries = {
 161          [MESA_SHADER_VERTEX]   = 256,
 162          [MESA_SHADER_GEOMETRY] = 256,
 163       },
 164    },
 165    .timestamp_frequency = 12500000,
 166 };
 167
 168 static const struct gen_device_info gen_device_info_snb_gt2 = {
 169    .gen = 6,
 170    .gt = 2,
 171    .has_hiz_and_separate_stencil = true,
 172    .has_llc = true,
 173    .has_pln = true,
 174    .has_surface_tile_offset = true,
 175    .needs_unlit_centroid_workaround = true,
 176    .num_slices = 1,
 177    .num_subslices = { 1, },
 178    .num_thread_per_eu = 6, /* Not confirmed */
 179    .max_vs_threads = 60,
 180    .max_gs_threads = 60,
 181    .max_wm_threads = 80,
 182    .urb = {
 183       .size = 64,
 184       .min_entries = {
 185          [MESA_SHADER_VERTEX]   = 24,
 186       },
 187       .max_entries = {
 188          [MESA_SHADER_VERTEX]   = 256,
 189          [MESA_SHADER_GEOMETRY] = 256,
 190       },
 191    },
 192    .timestamp_frequency = 12500000,
 193 };
 194
 195 #define GEN7_FEATURES                               \
 196    .gen = 7,                                        \
 197    .has_hiz_and_separate_stencil = true,            \
 198    .must_use_separate_stencil = true,               \
 199    .has_llc = true,                                 \
 200    .has_pln = true,                                 \
 201    .has_64bit_types = true,                         \
 202    .has_surface_tile_offset = true,                 \
 203    .timestamp_frequency = 12500000
 204
 205 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 206    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 207    .num_slices = 1,
 208    .num_subslices = { 1, },
 209    .num_thread_per_eu = 6,
 210    .l3_banks = 2,
 211    .max_vs_threads = 36,
 212    .max_tcs_threads = 36,
 213    .max_tes_threads = 36,
 214    .max_gs_threads = 36,
 215    .max_wm_threads = 48,
 216    .max_cs_threads = 36,
 217    .urb = {
 218       .size = 128,
 219       .min_entries = {
 220          [MESA_SHADER_VERTEX]    = 32,
 221          [MESA_SHADER_TESS_EVAL] = 10,
 222       },
 223       .max_entries = {
 224          [MESA_SHADER_VERTEX]    = 512,
 225          [MESA_SHADER_TESS_CTRL] = 32,
 226          [MESA_SHADER_TESS_EVAL] = 288,
 227          [MESA_SHADER_GEOMETRY]  = 192,
 228       },
 229    },
 230 };
 231
 232 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 233    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 234    .num_slices = 1,
 235    .num_subslices = { 1, },
 236    .num_thread_per_eu = 8, /* Not sure why this isn't a multiple of
 237                             * @max_wm_threads ... */
 238    .l3_banks = 4,
 239    .max_vs_threads = 128,
 240    .max_tcs_threads = 128,
 241    .max_tes_threads = 128,
 242    .max_gs_threads = 128,
 243    .max_wm_threads = 172,
 244    .max_cs_threads = 64,
 245    .urb = {
 246       .size = 256,
 247       .min_entries = {
 248          [MESA_SHADER_VERTEX]    = 32,
 249          [MESA_SHADER_TESS_EVAL] = 10,
 250       },
 251       .max_entries = {
 252          [MESA_SHADER_VERTEX]    = 704,
 253          [MESA_SHADER_TESS_CTRL] = 64,
 254          [MESA_SHADER_TESS_EVAL] = 448,
 255          [MESA_SHADER_GEOMETRY]  = 320,
 256       },
 257    },
 258 };
 259
 260 static const struct gen_device_info gen_device_info_byt = {
 261    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 262    .num_slices = 1,
 263    .num_subslices = { 1, },
 264    .num_thread_per_eu = 8,
 265    .l3_banks = 1,
 266    .has_llc = false,
 267    .max_vs_threads = 36,
 268    .max_tcs_threads = 36,
 269    .max_tes_threads = 36,
 270    .max_gs_threads = 36,
 271    .max_wm_threads = 48,
 272    .max_cs_threads = 32,
 273    .urb = {
 274       .size = 128,
 275       .min_entries = {
 276          [MESA_SHADER_VERTEX]    = 32,
 277          [MESA_SHADER_TESS_EVAL] = 10,
 278       },
 279       .max_entries = {
 280          [MESA_SHADER_VERTEX]    = 512,
 281          [MESA_SHADER_TESS_CTRL] = 32,
 282          [MESA_SHADER_TESS_EVAL] = 288,
 283          [MESA_SHADER_GEOMETRY]  = 192,
 284       },
 285    },
 286 };
 287
 288 #define HSW_FEATURES             \
 289    GEN7_FEATURES,                \
 290    .is_haswell = true,           \
 291    .supports_simd16_3src = true, \
 292    .has_resource_streamer = true
 293
 294 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 295    HSW_FEATURES, .gt = 1,
 296    .num_slices = 1,
 297    .num_subslices = { 1, },
 298    .num_thread_per_eu = 7,
 299    .l3_banks = 2,
 300    .max_vs_threads = 70,
 301    .max_tcs_threads = 70,
 302    .max_tes_threads = 70,
 303    .max_gs_threads = 70,
 304    .max_wm_threads = 102,
 305    .max_cs_threads = 70,
 306    .urb = {
 307       .size = 128,
 308       .min_entries = {
 309          [MESA_SHADER_VERTEX]    = 32,
 310          [MESA_SHADER_TESS_EVAL] = 10,
 311       },
 312       .max_entries = {
 313          [MESA_SHADER_VERTEX]    = 640,
 314          [MESA_SHADER_TESS_CTRL] = 64,
 315          [MESA_SHADER_TESS_EVAL] = 384,
 316          [MESA_SHADER_GEOMETRY]  = 256,
 317       },
 318    },
 319 };
 320
 321 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 322    HSW_FEATURES, .gt = 2,
 323    .num_slices = 1,
 324    .num_subslices = { 2, },
 325    .num_thread_per_eu = 7,
 326    .l3_banks = 4,
 327    .max_vs_threads = 280,
 328    .max_tcs_threads = 256,
 329    .max_tes_threads = 280,
 330    .max_gs_threads = 256,
 331    .max_wm_threads = 204,
 332    .max_cs_threads = 70,
 333    .urb = {
 334       .size = 256,
 335       .min_entries = {
 336          [MESA_SHADER_VERTEX]    = 64,
 337          [MESA_SHADER_TESS_EVAL] = 10,
 338       },
 339       .max_entries = {
 340          [MESA_SHADER_VERTEX]    = 1664,
 341          [MESA_SHADER_TESS_CTRL] = 128,
 342          [MESA_SHADER_TESS_EVAL] = 960,
 343          [MESA_SHADER_GEOMETRY]  = 640,
 344       },
 345    },
 346 };
 347
 348 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 349    HSW_FEATURES, .gt = 3,
 350    .num_slices = 2,
 351    .num_subslices = { 2, },
 352    .num_thread_per_eu = 7,
 353    .l3_banks = 8,
 354    .max_vs_threads = 280,
 355    .max_tcs_threads = 256,
 356    .max_tes_threads = 280,
 357    .max_gs_threads = 256,
 358    .max_wm_threads = 408,
 359    .max_cs_threads = 70,
 360    .urb = {
 361       .size = 512,
 362       .min_entries = {
 363          [MESA_SHADER_VERTEX]    = 64,
 364          [MESA_SHADER_TESS_EVAL] = 10,
 365       },
 366       .max_entries = {
 367          [MESA_SHADER_VERTEX]    = 1664,
 368          [MESA_SHADER_TESS_CTRL] = 128,
 369          [MESA_SHADER_TESS_EVAL] = 960,
 370          [MESA_SHADER_GEOMETRY]  = 640,
 371       },
 372    },
 373 };
 374
 375 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
 376  * so keep things conservative for now and set has_sample_with_hiz = false.
 377  */
 378 #define GEN8_FEATURES                               \
 379    .gen = 8,                                        \
 380    .has_hiz_and_separate_stencil = true,            \
 381    .has_resource_streamer = true,                   \
 382    .must_use_separate_stencil = true,               \
 383    .has_llc = true,                                 \
 384    .has_sample_with_hiz = false,                    \
 385    .has_pln = true,                                 \
 386    .has_integer_dword_mul = true,                   \
 387    .has_64bit_types = true,                         \
 388    .supports_simd16_3src = true,                    \
 389    .has_surface_tile_offset = true,                 \
 390    .max_vs_threads = 504,                           \
 391    .max_tcs_threads = 504,                          \
 392    .max_tes_threads = 504,                          \
 393    .max_gs_threads = 504,                           \
 394    .max_wm_threads = 384,                           \
 395    .timestamp_frequency = 12500000
 396
 397 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 398    GEN8_FEATURES, .gt = 1,
 399    .is_broadwell = true,
 400    .num_slices = 1,
 401    .num_subslices = { 2, },
 402    .num_thread_per_eu = 7,
 403    .l3_banks = 2,
 404    .max_cs_threads = 42,
 405    .urb = {
 406       .size = 192,
 407       .min_entries = {
 408          [MESA_SHADER_VERTEX]    = 64,
 409          [MESA_SHADER_TESS_EVAL] = 34,
 410       },
 411       .max_entries = {
 412          [MESA_SHADER_VERTEX]    = 2560,
 413          [MESA_SHADER_TESS_CTRL] = 504,
 414          [MESA_SHADER_TESS_EVAL] = 1536,
 415          [MESA_SHADER_GEOMETRY]  = 960,
 416       },
 417    }
 418 };
 419
 420 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 421    GEN8_FEATURES, .gt = 2,
 422    .is_broadwell = true,
 423    .num_slices = 1,
 424    .num_subslices = { 3, },
 425    .num_thread_per_eu = 7,
 426    .l3_banks = 4,
 427    .max_cs_threads = 56,
 428    .urb = {
 429       .size = 384,
 430       .min_entries = {
 431          [MESA_SHADER_VERTEX]    = 64,
 432          [MESA_SHADER_TESS_EVAL] = 34,
 433       },
 434       .max_entries = {
 435          [MESA_SHADER_VERTEX]    = 2560,
 436          [MESA_SHADER_TESS_CTRL] = 504,
 437          [MESA_SHADER_TESS_EVAL] = 1536,
 438          [MESA_SHADER_GEOMETRY]  = 960,
 439       },
 440    }
 441 };
 442
 443 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 444    GEN8_FEATURES, .gt = 3,
 445    .is_broadwell = true,
 446    .num_slices = 2,
 447    .num_subslices = { 3, 3, },
 448    .num_thread_per_eu = 7,
 449    .l3_banks = 8,
 450    .max_cs_threads = 56,
 451    .urb = {
 452       .size = 384,
 453       .min_entries = {
 454          [MESA_SHADER_VERTEX]    = 64,
 455          [MESA_SHADER_TESS_EVAL] = 34,
 456       },
 457       .max_entries = {
 458          [MESA_SHADER_VERTEX]    = 2560,
 459          [MESA_SHADER_TESS_CTRL] = 504,
 460          [MESA_SHADER_TESS_EVAL] = 1536,
 461          [MESA_SHADER_GEOMETRY]  = 960,
 462       },
 463    }
 464 };
 465
 466 static const struct gen_device_info gen_device_info_chv = {
 467    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 468    .has_llc = false,
 469    .has_integer_dword_mul = false,
 470    .num_slices = 1,
 471    .num_subslices = { 2, },
 472    .num_thread_per_eu = 7,
 473    .l3_banks = 2,
 474    .max_vs_threads = 80,
 475    .max_tcs_threads = 80,
 476    .max_tes_threads = 80,
 477    .max_gs_threads = 80,
 478    .max_wm_threads = 128,
 479    .max_cs_threads = 6 * 7,
 480    .urb = {
 481       .size = 192,
 482       .min_entries = {
 483          [MESA_SHADER_VERTEX]    = 34,
 484          [MESA_SHADER_TESS_EVAL] = 34,
 485       },
 486       .max_entries = {
 487          [MESA_SHADER_VERTEX]    = 640,
 488          [MESA_SHADER_TESS_CTRL] = 80,
 489          [MESA_SHADER_TESS_EVAL] = 384,
 490          [MESA_SHADER_GEOMETRY]  = 256,
 491       },
 492    }
 493 };
 494
 495 #define GEN9_HW_INFO                                \
 496    .gen = 9,                                        \
 497    .max_vs_threads = 336,                           \
 498    .max_gs_threads = 336,                           \
 499    .max_tcs_threads = 336,                          \
 500    .max_tes_threads = 336,                          \
 501    .max_cs_threads = 56,                            \
 502    .timestamp_frequency = 12000000,                 \
 503    .urb = {                                         \
 504       .size = 384,                                  \
 505       .min_entries = {                              \
 506          [MESA_SHADER_VERTEX]    = 64,              \
 507          [MESA_SHADER_TESS_EVAL] = 34,              \
 508       },                                            \
 509       .max_entries = {                              \
 510          [MESA_SHADER_VERTEX]    = 1856,            \
 511          [MESA_SHADER_TESS_CTRL] = 672,             \
 512          [MESA_SHADER_TESS_EVAL] = 1120,            \
 513          [MESA_SHADER_GEOMETRY]  = 640,             \
 514       },                                            \
 515    }
 516
 517 #define GEN9_LP_FEATURES                           \
 518    GEN8_FEATURES,                                  \
 519    GEN9_HW_INFO,                                   \
 520    .has_integer_dword_mul = false,                 \
 521    .gt = 1,                                        \
 522    .has_llc = false,                               \
 523    .has_sample_with_hiz = true,                    \
 524    .num_slices = 1,                                \
 525    .num_thread_per_eu = 6,                         \
 526    .max_vs_threads = 112,                          \
 527    .max_tcs_threads = 112,                         \
 528    .max_tes_threads = 112,                         \
 529    .max_gs_threads = 112,                          \
 530    .max_cs_threads = 6 * 6,                        \
 531    .timestamp_frequency = 19200000,                \
 532    .urb = {                                        \
 533       .size = 192,                                 \
 534       .min_entries = {                             \
 535          [MESA_SHADER_VERTEX]    = 34,             \
 536          [MESA_SHADER_TESS_EVAL] = 34,             \
 537       },                                           \
 538       .max_entries = {                             \
 539          [MESA_SHADER_VERTEX]    = 704,            \
 540          [MESA_SHADER_TESS_CTRL] = 256,            \
 541          [MESA_SHADER_TESS_EVAL] = 416,            \
 542          [MESA_SHADER_GEOMETRY]  = 256,            \
 543       },                                           \
 544    }
 545
 546 #define GEN9_LP_FEATURES_3X6                       \
 547    GEN9_LP_FEATURES,                               \
 548    .num_subslices = { 3, }
 549
 550 #define GEN9_LP_FEATURES_2X6                       \
 551    GEN9_LP_FEATURES,                               \
 552    .num_subslices = { 2, },                        \
 553    .max_vs_threads = 56,                           \
 554    .max_tcs_threads = 56,                          \
 555    .max_tes_threads = 56,                          \
 556    .max_gs_threads = 56,                           \
 557    .max_cs_threads = 6 * 6,                        \
 558    .urb = {                                        \
 559       .size = 128,                                 \
 560       .min_entries = {                             \
 561          [MESA_SHADER_VERTEX]    = 34,             \
 562          [MESA_SHADER_TESS_EVAL] = 34,             \
 563       },                                           \
 564       .max_entries = {                             \
 565          [MESA_SHADER_VERTEX]    = 352,            \
 566          [MESA_SHADER_TESS_CTRL] = 128,            \
 567          [MESA_SHADER_TESS_EVAL] = 208,            \
 568          [MESA_SHADER_GEOMETRY]  = 128,            \
 569       },                                           \
 570    }
 571
 572 #define GEN9_FEATURES                               \
 573    GEN8_FEATURES,                                   \
 574    GEN9_HW_INFO,                                    \
 575    .has_sample_with_hiz = true,                     \
 576    .num_thread_per_eu = 7
 577
 578 static const struct gen_device_info gen_device_info_skl_gt1 = {
 579    GEN9_FEATURES, .gt = 1,
 580    .is_skylake = true,
 581    .num_slices = 1,
 582    .num_subslices = { 2, },
 583    .l3_banks = 2,
 584    .urb.size = 192,
 585 };
 586
 587 static const struct gen_device_info gen_device_info_skl_gt2 = {
 588    GEN9_FEATURES, .gt = 2,
 589    .is_skylake = true,
 590    .num_slices = 1,
 591    .num_subslices = { 3, },
 592    .l3_banks = 4,
 593 };
 594
 595 static const struct gen_device_info gen_device_info_skl_gt3 = {
 596    GEN9_FEATURES, .gt = 3,
 597    .is_skylake = true,
 598    .num_slices = 2,
 599    .num_subslices = { 3, 3, },
 600    .l3_banks = 8,
 601 };
 602
 603 static const struct gen_device_info gen_device_info_skl_gt4 = {
 604    GEN9_FEATURES, .gt = 4,
 605    .is_skylake = true,
 606    .num_slices = 3,
 607    .num_subslices = { 3, 3, 3, },
 608    .l3_banks = 12,
 609    /* From the "L3 Allocation and Programming" documentation:
 610     *
 611     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 612     * restriction of the L3 implementation, but of the FF and other clients.
 613     * Therefore, in a GT4 implementation it is possible for the programmed
 614     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 615     * only 1008KB of this will be used."
 616     */
 617    .urb.size = 1008 / 3,
 618 };
 619
 620 static const struct gen_device_info gen_device_info_bxt = {
 621    GEN9_LP_FEATURES_3X6,
 622    .is_broxton = true,
 623    .l3_banks = 2,
 624 };
 625
 626 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 627    GEN9_LP_FEATURES_2X6,
 628    .is_broxton = true,
 629    .l3_banks = 1,
 630 };
 631 /*
 632  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 633  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 634  */
 635
 636 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 637    GEN9_FEATURES,
 638    .is_kabylake = true,
 639    .gt = 1,
 640
 641    .max_cs_threads = 7 * 6,
 642    .urb.size = 192,
 643    .num_slices = 1,
 644    .num_subslices = { 2, },
 645    .l3_banks = 2,
 646 };
 647
 648 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 649    GEN9_FEATURES,
 650    .is_kabylake = true,
 651    .gt = 1,
 652
 653    .max_cs_threads = 7 * 6,
 654    .num_slices = 1,
 655    .num_subslices = { 3, },
 656    .l3_banks = 4,
 657 };
 658
 659 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 660    GEN9_FEATURES,
 661    .is_kabylake = true,
 662    .gt = 2,
 663
 664    .num_slices = 1,
 665    .num_subslices = { 3, },
 666    .l3_banks = 4,
 667 };
 668
 669 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 670    GEN9_FEATURES,
 671    .is_kabylake = true,
 672    .gt = 3,
 673
 674    .num_slices = 2,
 675    .num_subslices = { 3, 3, },
 676    .l3_banks = 8,
 677 };
 678
 679 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 680    GEN9_FEATURES,
 681    .is_kabylake = true,
 682    .gt = 4,
 683
 684    /*
 685     * From the "L3 Allocation and Programming" documentation:
 686     *
 687     * "URB is limited to 1008KB due to programming restrictions.  This
 688     *  is not a restriction of the L3 implementation, but of the FF and
 689     *  other clients.  Therefore, in a GT4 implementation it is
 690     *  possible for the programmed allocation of the L3 data array to
 691     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 692     *  will be used."
 693     */
 694    .urb.size = 1008 / 3,
 695    .num_slices = 3,
 696    .num_subslices = { 3, 3, 3, },
 697    .l3_banks = 12,
 698 };
 699
 700 static const struct gen_device_info gen_device_info_glk = {
 701    GEN9_LP_FEATURES_3X6,
 702    .is_geminilake = true,
 703    .l3_banks = 2,
 704 };
 705
 706 /*TODO: Initialize l3_banks when we know the number. */
 707 static const struct gen_device_info gen_device_info_glk_2x6 = {
 708    GEN9_LP_FEATURES_2X6,
 709    .is_geminilake = true,
 710 };
 711
 712 static const struct gen_device_info gen_device_info_cfl_gt1 = {
 713    GEN9_FEATURES,
 714    .is_coffeelake = true,
 715    .gt = 1,
 716
 717    .num_slices = 1,
 718    .num_subslices = { 2, },
 719    .l3_banks = 2,
 720 };
 721 static const struct gen_device_info gen_device_info_cfl_gt2 = {
 722    GEN9_FEATURES,
 723    .is_coffeelake = true,
 724    .gt = 2,
 725
 726    .num_slices = 1,
 727    .num_subslices = { 3, },
 728    .l3_banks = 4,
 729 };
 730
 731 static const struct gen_device_info gen_device_info_cfl_gt3 = {
 732    GEN9_FEATURES,
 733    .is_coffeelake = true,
 734    .gt = 3,
 735
 736    .num_slices = 2,
 737    .num_subslices = { 3, 3, },
 738    .l3_banks = 8,
 739 };
 740
 741 #define GEN10_HW_INFO                               \
 742    .gen = 10,                                       \
 743    .num_thread_per_eu = 7,                          \
 744    .max_vs_threads = 728,                           \
 745    .max_gs_threads = 432,                           \
 746    .max_tcs_threads = 432,                          \
 747    .max_tes_threads = 624,                          \
 748    .max_cs_threads = 56,                            \
 749    .timestamp_frequency = 19200000,                 \
 750    .urb = {                                         \
 751       .size = 256,                                  \
 752       .min_entries = {                              \
 753          [MESA_SHADER_VERTEX]    = 64,              \
 754          [MESA_SHADER_TESS_EVAL] = 34,              \
 755       },                                            \
 756       .max_entries = {                              \
 757       [MESA_SHADER_VERTEX]       = 3936,            \
 758       [MESA_SHADER_TESS_CTRL]    = 896,             \
 759       [MESA_SHADER_TESS_EVAL]    = 2064,            \
 760       [MESA_SHADER_GEOMETRY]     = 832,             \
 761       },                                            \
 762    }
 763
 764 #define subslices(args...) { args, }
 765
 766 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
 767    GEN8_FEATURES,                                   \
 768    GEN10_HW_INFO,                                   \
 769    .has_sample_with_hiz = true,                     \
 770    .gt = _gt,                                       \
 771    .num_slices = _slices,                           \
 772    .num_subslices = _subslices,                     \
 773    .l3_banks = _l3
 774
 775 static const struct gen_device_info gen_device_info_cnl_2x8 = {
 776    /* GT0.5 */
 777    GEN10_FEATURES(1, 1, subslices(2), 2),
 778    .is_cannonlake = true,
 779 };
 780
 781 static const struct gen_device_info gen_device_info_cnl_3x8 = {
 782    /* GT1 */
 783    GEN10_FEATURES(1, 1, subslices(3), 3),
 784    .is_cannonlake = true,
 785 };
 786
 787 static const struct gen_device_info gen_device_info_cnl_4x8 = {
 788    /* GT 1.5 */
 789    GEN10_FEATURES(1, 2, subslices(2, 2), 6),
 790    .is_cannonlake = true,
 791 };
 792
 793 static const struct gen_device_info gen_device_info_cnl_5x8 = {
 794    /* GT2 */
 795    GEN10_FEATURES(2, 2, subslices(3, 2), 6),
 796    .is_cannonlake = true,
 797 };
 798
 799 #define GEN11_HW_INFO                               \
 800    .gen = 11,                                       \
 801    .has_pln = false,                                \
 802    .max_vs_threads = 364,                           \
 803    .max_gs_threads = 224,                           \
 804    .max_tcs_threads = 224,                          \
 805    .max_tes_threads = 364,                          \
 806    .max_cs_threads = 56,                            \
 807    .urb = {                                         \
 808       .size = 1024,                                 \
 809       .min_entries = {                              \
 810          [MESA_SHADER_VERTEX]    = 64,              \
 811          [MESA_SHADER_TESS_EVAL] = 34,              \
 812       },                                            \
 813       .max_entries = {                              \
 814          [MESA_SHADER_VERTEX]    = 2384,            \
 815          [MESA_SHADER_TESS_CTRL] = 1032,            \
 816          [MESA_SHADER_TESS_EVAL] = 2384,            \
 817          [MESA_SHADER_GEOMETRY]  = 1032,            \
 818       },                                            \
 819    }
 820
 821 #define GEN11_FEATURES(_gt, _slices, _subslices, _l3) \
 822    GEN8_FEATURES,                                     \
 823    GEN11_HW_INFO,                                     \
 824    .has_64bit_types = false,                          \
 825    .has_integer_dword_mul = false,                    \
 826    .has_sample_with_hiz = false,                      \
 827    .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \
 828    .num_subslices = _subslices
 829
 830 static const struct gen_device_info gen_device_info_icl_8x8 = {
 831    GEN11_FEATURES(2, 1, subslices(8), 8),
 832 };
 833
 834 static const struct gen_device_info gen_device_info_icl_6x8 = {
 835    GEN11_FEATURES(1, 1, subslices(6), 6),
 836 };
 837
 838 static const struct gen_device_info gen_device_info_icl_4x8 = {
 839    GEN11_FEATURES(1, 1, subslices(4), 6),
 840 };
 841
 842 static const struct gen_device_info gen_device_info_icl_1x8 = {
 843    GEN11_FEATURES(1, 1, subslices(1), 6),
 844 };
 845
 846 bool
 847 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 848 {
 849    switch (devid) {
 850 #undef CHIPSET
 851 #define CHIPSET(id, family, name) \
 852       case id: *devinfo = gen_device_info_##family; break;
 853 #include "pci_ids/i965_pci_ids.h"
 854    default:
 855       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 856       return false;
 857    }
 858
 859    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
 860     *
 861     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
 862     *  allocate scratch space enough so that each slice has 4 slices allowed."
 863     *
 864     * The equivalent internal documentation says that this programming note
 865     * applies to all Gen9+ platforms.
 866     *
 867     * The hardware typically calculates the scratch space pointer by taking
 868     * the base address, and adding per-thread-scratch-space * thread ID.
 869     * Extra padding can be necessary depending how the thread IDs are
 870     * calculated for a particular shader stage.
 871     */
 872
 873    switch(devinfo->gen) {
 874    case 9:
 875    case 10:
 876       devinfo->max_wm_threads = 64 /* threads-per-PSD */
 877                               * devinfo->num_slices
 878                               * 4; /* effective subslices per slice */
 879       break;
 880    case 11:
 881       devinfo->max_wm_threads = 128 /* threads-per-PSD */
 882                               * devinfo->num_slices
 883                               * 8; /* subslices per slice */
 884       break;
 885    default:
 886       break;
 887    }
 888
 889    assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
 890
 891    return true;
 892 }
 893
 894 const char *
 895 gen_get_device_name(int devid)
 896 {
 897    switch (devid) {
 898 #undef CHIPSET
 899 #define CHIPSET(id, family, name) case id: return name;
 900 #include "pci_ids/i965_pci_ids.h"
 901    default:
 902       return NULL;
 903    }
 904 }