src/intel/dev/gen_device_info.h

   1  /*
   2   * Copyright © 2013 Intel Corporation
   3   *
   4   * Permission is hereby granted, free of charge, to any person obtaining a
   5   * copy of this software and associated documentation files (the "Software"),
   6   * to deal in the Software without restriction, including without limitation
   7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8   * and/or sell copies of the Software, and to permit persons to whom the
   9   * Software is furnished to do so, subject to the following conditions:
  10   *
  11   * The above copyright notice and this permission notice (including the next
  12   * paragraph) shall be included in all copies or substantial portions of the
  13   * Software.
  14   *
  15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21   * IN THE SOFTWARE.
  22   *
  23   */
  24
  25 #ifndef GEN_DEVICE_INFO_H
  26 #define GEN_DEVICE_INFO_H
  27
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #include "util/macros.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 struct drm_i915_query_topology_info;
  38
  39 #define GEN_DEVICE_MAX_SLICES           (6)  /* Maximum on gen10 */
  40 #define GEN_DEVICE_MAX_SUBSLICES        (8)  /* Maximum on gen11 */
  41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
  42
  43 /**
  44  * Intel hardware information and quirks
  45  */
  46 struct gen_device_info
  47 {
  48    int gen; /**< Generation number: 4, 5, 6, 7, ... */
  49    int revision;
  50    int gt;
  51
  52    bool is_g4x;
  53    bool is_ivybridge;
  54    bool is_baytrail;
  55    bool is_haswell;
  56    bool is_broadwell;
  57    bool is_cherryview;
  58    bool is_skylake;
  59    bool is_broxton;
  60    bool is_kabylake;
  61    bool is_geminilake;
  62    bool is_coffeelake;
  63    bool is_cannonlake;
  64
  65    bool has_hiz_and_separate_stencil;
  66    bool must_use_separate_stencil;
  67    bool has_sample_with_hiz;
  68    bool has_llc;
  69
  70    bool has_pln;
  71    bool has_64bit_types;
  72    bool has_integer_dword_mul;
  73    bool has_compr4;
  74    bool has_surface_tile_offset;
  75    bool supports_simd16_3src;
  76    bool has_resource_streamer;
  77    bool disable_ccs_repack;
  78
  79    /**
  80     * \name Intel hardware quirks
  81     *  @{
  82     */
  83    bool has_negative_rhw_bug;
  84
  85    /**
  86     * Some versions of Gen hardware don't do centroid interpolation correctly
  87     * on unlit pixels, causing incorrect values for derivatives near triangle
  88     * edges.  Enabling this flag causes the fragment shader to use
  89     * non-centroid interpolation for unlit pixels, at the expense of two extra
  90     * fragment shader instructions.
  91     */
  92    bool needs_unlit_centroid_workaround;
  93    /** @} */
  94
  95    /**
  96     * \name GPU hardware limits
  97     *
  98     * In general, you can find shader thread maximums by looking at the "Maximum
  99     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
 100     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
 101     * limits come from the "Number of URB Entries" field in the
 102     * 3DSTATE_URB_VS command and friends.
 103     *
 104     * These fields are used to calculate the scratch space to allocate.  The
 105     * amount of scratch space can be larger without being harmful on modern
 106     * GPUs, however, prior to Haswell, programming the maximum number of threads
 107     * to greater than the hardware maximum would cause GPU performance to tank.
 108     *
 109     *  @{
 110     */
 111    /**
 112     * Total number of slices present on the device whether or not they've been
 113     * fused off.
 114     *
 115     * XXX: CS thread counts are limited by the inability to do cross subslice
 116     * communication. It is the effectively the number of logical threads which
 117     * can be executed in a subslice. Fuse configurations may cause this number
 118     * to change, so we program @max_cs_threads as the lower maximum.
 119     */
 120    unsigned num_slices;
 121
 122    /**
 123     * Number of subslices for each slice (used to be uniform until CNL).
 124     */
 125    unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
 126
 127    /**
 128     * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
 129     * fused across all subslices, like 47 EUs, in which case this number won't
 130     * be acurate for one subslice).
 131     */
 132    unsigned num_eu_per_subslice;
 133
 134    /**
 135     * Number of threads per eu, varies between 4 and 8 between generations.
 136     */
 137    unsigned num_thread_per_eu;
 138
 139    /**
 140     * A bit mask of the slices available.
 141     */
 142    uint8_t slice_masks;
 143
 144    /**
 145     * An array of bit mask of the subslices available, use subslice_slice_stride
 146     * to access this array.
 147     */
 148    uint8_t subslice_masks[GEN_DEVICE_MAX_SLICES *
 149                           DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES, 8)];
 150
 151    /**
 152     * An array of bit mask of EUs available, use eu_slice_stride &
 153     * eu_subslice_stride to access this array.
 154     */
 155    uint8_t eu_masks[GEN_DEVICE_MAX_SLICES *
 156                     GEN_DEVICE_MAX_SUBSLICES *
 157                     DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE, 8)];
 158
 159    /**
 160     * Stride to access subslice_masks[].
 161     */
 162    uint16_t subslice_slice_stride;
 163
 164    /**
 165     * Strides to access eu_masks[].
 166     */
 167    uint16_t eu_slice_stride;
 168    uint16_t eu_subslice_stride;
 169
 170    unsigned l3_banks;
 171    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
 172    unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
 173    unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
 174    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
 175    /**
 176     * Theoretical maximum number of Pixel Shader threads.
 177     *
 178     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
 179     * automatically scale pixel shader thread count, based on a single value
 180     * programmed into 3DSTATE_PS.
 181     *
 182     * To calculate the maximum number of threads for Gen8 beyond (which have
 183     * multiple Pixel Shader Dispatchers):
 184     *
 185     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
 186     * - Usually there's only one PSD per subslice, so use the number of
 187     *   subslices for number of PSDs.
 188     * - For max_wm_threads, the total should be PSD threads * #PSDs.
 189     */
 190    unsigned max_wm_threads;
 191
 192    /**
 193     * Maximum Compute Shader threads.
 194     *
 195     * Thread count * number of EUs per subslice
 196     */
 197    unsigned max_cs_threads;
 198
 199    struct {
 200       /**
 201        * Hardware default URB size.
 202        *
 203        * The units this is expressed in are somewhat inconsistent: 512b units
 204        * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
 205        *
 206        * Look up "URB Size" in the "Device Attributes" page, and take the
 207        * maximum.  Look up the slice count for each GT SKU on the same page.
 208        * urb.size = URB Size (kbytes) / slice count
 209        */
 210       unsigned size;
 211
 212       /**
 213        * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 214        */
 215       unsigned min_entries[4];
 216
 217       /**
 218        * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 219        */
 220       unsigned max_entries[4];
 221    } urb;
 222
 223    /**
 224     * For the longest time the timestamp frequency for Gen's timestamp counter
 225     * could be assumed to be 12.5MHz, where the least significant bit neatly
 226     * corresponded to 80 nanoseconds.
 227     *
 228     * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
 229     * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
 230     * BXT.
 231     *
 232     * For simplicty to fit with the current code scaling by a single constant
 233     * to map from raw timestamps to nanoseconds we now do the conversion in
 234     * floating point instead of integer arithmetic.
 235     *
 236     * In general it's probably worth noting that the documented constants we
 237     * have for the per-platform timestamp frequencies aren't perfect and
 238     * shouldn't be trusted for scaling and comparing timestamps with a large
 239     * delta.
 240     *
 241     * E.g. with crude testing on my system using the 'correct' scale factor I'm
 242     * seeing a drift of ~2 milliseconds per second.
 243     */
 244    uint64_t timestamp_frequency;
 245
 246    /**
 247     * ID to put into the .aub files.
 248     */
 249    int simulator_id;
 250
 251    /** @} */
 252 };
 253
 254 #define gen_device_info_is_9lp(devinfo) \
 255    ((devinfo)->is_broxton || (devinfo)->is_geminilake)
 256
 257 static inline bool
 258 gen_device_info_subslice_available(const struct gen_device_info *devinfo,
 259                                    int slice, int subslice)
 260 {
 261    return (devinfo->subslice_masks[slice * devinfo->subslice_slice_stride +
 262                                    subslice / 8] & (1U << (subslice % 8))) != 0;
 263 }
 264
 265 int gen_get_pci_device_id_override(void);
 266 int gen_device_name_to_pci_device_id(const char *name);
 267 bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 268 const char *gen_get_device_name(int devid);
 269
 270 /* Used with SLICE_MASK/SUBSLICE_MASK values from DRM_I915_GETPARAM. */
 271 void gen_device_info_update_from_masks(struct gen_device_info *devinfo,
 272                                        uint32_t slice_mask,
 273                                        uint32_t subslice_mask,
 274                                        uint32_t n_eus);
 275 /* Used with DRM_IOCTL_I915_QUERY & DRM_I915_QUERY_TOPOLOGY_INFO. */
 276 void gen_device_info_update_from_topology(struct gen_device_info *devinfo,
 277                                           const struct drm_i915_query_topology_info *topology);
 278
 279 static inline uint64_t
 280 gen_device_info_timebase_scale(const struct gen_device_info *devinfo,
 281                                uint64_t gpu_timestamp)
 282 {
 283    return (1000000000ull * gpu_timestamp) / devinfo->timestamp_frequency;
 284 }
 285
 286 #ifdef __cplusplus
 287 }
 288 #endif
 289
 290 #endif /* GEN_DEVICE_INFO_H */