src/intel/dev/gen_device_info.h

   1  /*
   2   * Copyright © 2013 Intel Corporation
   3   *
   4   * Permission is hereby granted, free of charge, to any person obtaining a
   5   * copy of this software and associated documentation files (the "Software"),
   6   * to deal in the Software without restriction, including without limitation
   7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8   * and/or sell copies of the Software, and to permit persons to whom the
   9   * Software is furnished to do so, subject to the following conditions:
  10   *
  11   * The above copyright notice and this permission notice (including the next
  12   * paragraph) shall be included in all copies or substantial portions of the
  13   * Software.
  14   *
  15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21   * IN THE SOFTWARE.
  22   *
  23   */
  24
  25 #ifndef GEN_DEVICE_INFO_H
  26 #define GEN_DEVICE_INFO_H
  27
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 /**
  36  * Intel hardware information and quirks
  37  */
  38 struct gen_device_info
  39 {
  40    int gen; /**< Generation number: 4, 5, 6, 7, ... */
  41    int gt;
  42
  43    bool is_g4x;
  44    bool is_ivybridge;
  45    bool is_baytrail;
  46    bool is_haswell;
  47    bool is_broadwell;
  48    bool is_cherryview;
  49    bool is_skylake;
  50    bool is_broxton;
  51    bool is_kabylake;
  52    bool is_geminilake;
  53    bool is_coffeelake;
  54    bool is_cannonlake;
  55
  56    bool has_hiz_and_separate_stencil;
  57    bool must_use_separate_stencil;
  58    bool has_sample_with_hiz;
  59    bool has_llc;
  60
  61    bool has_pln;
  62    bool has_64bit_types;
  63    bool has_integer_dword_mul;
  64    bool has_compr4;
  65    bool has_surface_tile_offset;
  66    bool supports_simd16_3src;
  67    bool has_resource_streamer;
  68
  69    /**
  70     * \name Intel hardware quirks
  71     *  @{
  72     */
  73    bool has_negative_rhw_bug;
  74
  75    /**
  76     * Some versions of Gen hardware don't do centroid interpolation correctly
  77     * on unlit pixels, causing incorrect values for derivatives near triangle
  78     * edges.  Enabling this flag causes the fragment shader to use
  79     * non-centroid interpolation for unlit pixels, at the expense of two extra
  80     * fragment shader instructions.
  81     */
  82    bool needs_unlit_centroid_workaround;
  83    /** @} */
  84
  85    /**
  86     * \name GPU hardware limits
  87     *
  88     * In general, you can find shader thread maximums by looking at the "Maximum
  89     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
  90     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
  91     * limits come from the "Number of URB Entries" field in the
  92     * 3DSTATE_URB_VS command and friends.
  93     *
  94     * These fields are used to calculate the scratch space to allocate.  The
  95     * amount of scratch space can be larger without being harmful on modern
  96     * GPUs, however, prior to Haswell, programming the maximum number of threads
  97     * to greater than the hardware maximum would cause GPU performance to tank.
  98     *
  99     *  @{
 100     */
 101    /**
 102     * Total number of slices present on the device whether or not they've been
 103     * fused off.
 104     *
 105     * XXX: CS thread counts are limited by the inability to do cross subslice
 106     * communication. It is the effectively the number of logical threads which
 107     * can be executed in a subslice. Fuse configurations may cause this number
 108     * to change, so we program @max_cs_threads as the lower maximum.
 109     */
 110    unsigned num_slices;
 111
 112    /**
 113     * Number of subslices for each slice (used to be uniform until CNL).
 114     */
 115    unsigned num_subslices[3];
 116
 117    /**
 118     * Number of threads per eu, varies between 4 and 8 between generations.
 119     */
 120    unsigned num_thread_per_eu;
 121
 122    unsigned l3_banks;
 123    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
 124    unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
 125    unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
 126    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
 127    /**
 128     * Theoretical maximum number of Pixel Shader threads.
 129     *
 130     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
 131     * automatically scale pixel shader thread count, based on a single value
 132     * programmed into 3DSTATE_PS.
 133     *
 134     * To calculate the maximum number of threads for Gen8 beyond (which have
 135     * multiple Pixel Shader Dispatchers):
 136     *
 137     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
 138     * - Usually there's only one PSD per subslice, so use the number of
 139     *   subslices for number of PSDs.
 140     * - For max_wm_threads, the total should be PSD threads * #PSDs.
 141     */
 142    unsigned max_wm_threads;
 143
 144    /**
 145     * Maximum Compute Shader threads.
 146     *
 147     * Thread count * number of EUs per subslice
 148     */
 149    unsigned max_cs_threads;
 150
 151    struct {
 152       /**
 153        * Hardware default URB size.
 154        *
 155        * The units this is expressed in are somewhat inconsistent: 512b units
 156        * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
 157        *
 158        * Look up "URB Size" in the "Device Attributes" page, and take the
 159        * maximum.  Look up the slice count for each GT SKU on the same page.
 160        * urb.size = URB Size (kbytes) / slice count
 161        */
 162       unsigned size;
 163
 164       /**
 165        * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 166        */
 167       unsigned min_entries[4];
 168
 169       /**
 170        * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 171        */
 172       unsigned max_entries[4];
 173    } urb;
 174
 175    /**
 176     * For the longest time the timestamp frequency for Gen's timestamp counter
 177     * could be assumed to be 12.5MHz, where the least significant bit neatly
 178     * corresponded to 80 nanoseconds.
 179     *
 180     * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
 181     * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
 182     * BXT.
 183     *
 184     * For simplicty to fit with the current code scaling by a single constant
 185     * to map from raw timestamps to nanoseconds we now do the conversion in
 186     * floating point instead of integer arithmetic.
 187     *
 188     * In general it's probably worth noting that the documented constants we
 189     * have for the per-platform timestamp frequencies aren't perfect and
 190     * shouldn't be trusted for scaling and comparing timestamps with a large
 191     * delta.
 192     *
 193     * E.g. with crude testing on my system using the 'correct' scale factor I'm
 194     * seeing a drift of ~2 milliseconds per second.
 195     */
 196    uint64_t timestamp_frequency;
 197
 198    /** @} */
 199 };
 200
 201 #define gen_device_info_is_9lp(devinfo) \
 202    ((devinfo)->is_broxton || (devinfo)->is_geminilake)
 203
 204 int gen_get_pci_device_id_override(void);
 205 int gen_device_name_to_pci_device_id(const char *name);
 206 bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 207 const char *gen_get_device_name(int devid);
 208
 209 #ifdef __cplusplus
 210 }
 211 #endif
 212
 213 #endif /* GEN_DEVICE_INFO_H */