189f71f6575f5f370ea9009ebbe9b68e3e5f309e
[mesa.git] / src / intel / perf / gen_perf.c
1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <dirent.h>
25
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <fcntl.h>
29 #include <unistd.h>
30 #include <errno.h>
31
32 #ifndef HAVE_DIRENT_D_TYPE
33 #include <limits.h> // PATH_MAX
34 #endif
35
36 #include <drm-uapi/i915_drm.h>
37
38 #include "common/gen_gem.h"
39
40 #include "dev/gen_debug.h"
41 #include "dev/gen_device_info.h"
42
43 #include "perf/gen_perf.h"
44 #include "perf/gen_perf_regs.h"
45 #include "perf/gen_perf_mdapi.h"
46 #include "perf/gen_perf_metrics.h"
47 #include "perf/gen_perf_private.h"
48
49 #include "util/bitscan.h"
50 #include "util/mesa-sha1.h"
51 #include "util/u_math.h"
52
53 #define FILE_DEBUG_FLAG DEBUG_PERFMON
54
55 #define OA_REPORT_INVALID_CTX_ID (0xffffffff)
56
57 static bool
58 is_dir_or_link(const struct dirent *entry, const char *parent_dir)
59 {
60 #ifdef HAVE_DIRENT_D_TYPE
61 return entry->d_type == DT_DIR || entry->d_type == DT_LNK;
62 #else
63 struct stat st;
64 char path[PATH_MAX + 1];
65 snprintf(path, sizeof(path), "%s/%s", parent_dir, entry->d_name);
66 lstat(path, &st);
67 return S_ISDIR(st.st_mode) || S_ISLNK(st.st_mode);
68 #endif
69 }
70
71 static bool
72 get_sysfs_dev_dir(struct gen_perf_config *perf, int fd)
73 {
74 struct stat sb;
75 int min, maj;
76 DIR *drmdir;
77 struct dirent *drm_entry;
78 int len;
79
80 perf->sysfs_dev_dir[0] = '\0';
81
82 if (fstat(fd, &sb)) {
83 DBG("Failed to stat DRM fd\n");
84 return false;
85 }
86
87 maj = major(sb.st_rdev);
88 min = minor(sb.st_rdev);
89
90 if (!S_ISCHR(sb.st_mode)) {
91 DBG("DRM fd is not a character device as expected\n");
92 return false;
93 }
94
95 len = snprintf(perf->sysfs_dev_dir,
96 sizeof(perf->sysfs_dev_dir),
97 "/sys/dev/char/%d:%d/device/drm", maj, min);
98 if (len < 0 || len >= sizeof(perf->sysfs_dev_dir)) {
99 DBG("Failed to concatenate sysfs path to drm device\n");
100 return false;
101 }
102
103 drmdir = opendir(perf->sysfs_dev_dir);
104 if (!drmdir) {
105 DBG("Failed to open %s: %m\n", perf->sysfs_dev_dir);
106 return false;
107 }
108
109 while ((drm_entry = readdir(drmdir))) {
110 if (is_dir_or_link(drm_entry, perf->sysfs_dev_dir) &&
111 strncmp(drm_entry->d_name, "card", 4) == 0)
112 {
113 len = snprintf(perf->sysfs_dev_dir,
114 sizeof(perf->sysfs_dev_dir),
115 "/sys/dev/char/%d:%d/device/drm/%s",
116 maj, min, drm_entry->d_name);
117 closedir(drmdir);
118 if (len < 0 || len >= sizeof(perf->sysfs_dev_dir))
119 return false;
120 else
121 return true;
122 }
123 }
124
125 closedir(drmdir);
126
127 DBG("Failed to find cardX directory under /sys/dev/char/%d:%d/device/drm\n",
128 maj, min);
129
130 return false;
131 }
132
133 static bool
134 read_file_uint64(const char *file, uint64_t *val)
135 {
136 char buf[32];
137 int fd, n;
138
139 fd = open(file, 0);
140 if (fd < 0)
141 return false;
142 while ((n = read(fd, buf, sizeof (buf) - 1)) < 0 &&
143 errno == EINTR);
144 close(fd);
145 if (n < 0)
146 return false;
147
148 buf[n] = '\0';
149 *val = strtoull(buf, NULL, 0);
150
151 return true;
152 }
153
154 static bool
155 read_sysfs_drm_device_file_uint64(struct gen_perf_config *perf,
156 const char *file,
157 uint64_t *value)
158 {
159 char buf[512];
160 int len;
161
162 len = snprintf(buf, sizeof(buf), "%s/%s", perf->sysfs_dev_dir, file);
163 if (len < 0 || len >= sizeof(buf)) {
164 DBG("Failed to concatenate sys filename to read u64 from\n");
165 return false;
166 }
167
168 return read_file_uint64(buf, value);
169 }
170
171 static void
172 register_oa_config(struct gen_perf_config *perf,
173 const struct gen_perf_query_info *query,
174 uint64_t config_id)
175 {
176 struct gen_perf_query_info *registered_query =
177 gen_perf_append_query_info(perf, 0);
178
179 *registered_query = *query;
180 registered_query->oa_metrics_set_id = config_id;
181 DBG("metric set registered: id = %" PRIu64", guid = %s\n",
182 registered_query->oa_metrics_set_id, query->guid);
183 }
184
185 static void
186 enumerate_sysfs_metrics(struct gen_perf_config *perf)
187 {
188 DIR *metricsdir = NULL;
189 struct dirent *metric_entry;
190 char buf[256];
191 int len;
192
193 len = snprintf(buf, sizeof(buf), "%s/metrics", perf->sysfs_dev_dir);
194 if (len < 0 || len >= sizeof(buf)) {
195 DBG("Failed to concatenate path to sysfs metrics/ directory\n");
196 return;
197 }
198
199 metricsdir = opendir(buf);
200 if (!metricsdir) {
201 DBG("Failed to open %s: %m\n", buf);
202 return;
203 }
204
205 while ((metric_entry = readdir(metricsdir))) {
206 struct hash_entry *entry;
207 if (!is_dir_or_link(metric_entry, buf) ||
208 metric_entry->d_name[0] == '.')
209 continue;
210
211 DBG("metric set: %s\n", metric_entry->d_name);
212 entry = _mesa_hash_table_search(perf->oa_metrics_table,
213 metric_entry->d_name);
214 if (entry) {
215 uint64_t id;
216 if (!gen_perf_load_metric_id(perf, metric_entry->d_name, &id)) {
217 DBG("Failed to read metric set id from %s: %m", buf);
218 continue;
219 }
220
221 register_oa_config(perf, (const struct gen_perf_query_info *)entry->data, id);
222 } else
223 DBG("metric set not known by mesa (skipping)\n");
224 }
225
226 closedir(metricsdir);
227 }
228
229 static bool
230 kernel_has_dynamic_config_support(struct gen_perf_config *perf, int fd)
231 {
232 uint64_t invalid_config_id = UINT64_MAX;
233
234 return gen_ioctl(fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
235 &invalid_config_id) < 0 && errno == ENOENT;
236 }
237
238 static int
239 i915_query_items(struct gen_perf_config *perf, int fd,
240 struct drm_i915_query_item *items, uint32_t n_items)
241 {
242 struct drm_i915_query q = {
243 .num_items = n_items,
244 .items_ptr = to_user_pointer(items),
245 };
246 return gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &q);
247 }
248
249 static bool
250 i915_query_perf_config_supported(struct gen_perf_config *perf, int fd)
251 {
252 struct drm_i915_query_item item = {
253 .query_id = DRM_I915_QUERY_PERF_CONFIG,
254 .flags = DRM_I915_QUERY_PERF_CONFIG_LIST,
255 };
256
257 return i915_query_items(perf, fd, &item, 1) == 0 && item.length > 0;
258 }
259
260 static bool
261 i915_query_perf_config_data(struct gen_perf_config *perf,
262 int fd, const char *guid,
263 struct drm_i915_perf_oa_config *config)
264 {
265 struct {
266 struct drm_i915_query_perf_config query;
267 struct drm_i915_perf_oa_config config;
268 } item_data;
269 struct drm_i915_query_item item = {
270 .query_id = DRM_I915_QUERY_PERF_CONFIG,
271 .flags = DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
272 .data_ptr = to_user_pointer(&item_data),
273 .length = sizeof(item_data),
274 };
275
276 memset(&item_data, 0, sizeof(item_data));
277 memcpy(item_data.query.uuid, guid, sizeof(item_data.query.uuid));
278 memcpy(&item_data.config, config, sizeof(item_data.config));
279
280 if (!(i915_query_items(perf, fd, &item, 1) == 0 && item.length > 0))
281 return false;
282
283 memcpy(config, &item_data.config, sizeof(item_data.config));
284
285 return true;
286 }
287
288 bool
289 gen_perf_load_metric_id(struct gen_perf_config *perf_cfg,
290 const char *guid,
291 uint64_t *metric_id)
292 {
293 char config_path[280];
294
295 snprintf(config_path, sizeof(config_path), "%s/metrics/%s/id",
296 perf_cfg->sysfs_dev_dir, guid);
297
298 /* Don't recreate already loaded configs. */
299 return read_file_uint64(config_path, metric_id);
300 }
301
302 static uint64_t
303 i915_add_config(struct gen_perf_config *perf, int fd,
304 const struct gen_perf_registers *config,
305 const char *guid)
306 {
307 struct drm_i915_perf_oa_config i915_config = { 0, };
308
309 memcpy(i915_config.uuid, guid, sizeof(i915_config.uuid));
310
311 i915_config.n_mux_regs = config->n_mux_regs;
312 i915_config.mux_regs_ptr = to_user_pointer(config->mux_regs);
313
314 i915_config.n_boolean_regs = config->n_b_counter_regs;
315 i915_config.boolean_regs_ptr = to_user_pointer(config->b_counter_regs);
316
317 i915_config.n_flex_regs = config->n_flex_regs;
318 i915_config.flex_regs_ptr = to_user_pointer(config->flex_regs);
319
320 int ret = gen_ioctl(fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &i915_config);
321 return ret > 0 ? ret : 0;
322 }
323
324 static void
325 init_oa_configs(struct gen_perf_config *perf, int fd)
326 {
327 hash_table_foreach(perf->oa_metrics_table, entry) {
328 const struct gen_perf_query_info *query = entry->data;
329 uint64_t config_id;
330
331 if (gen_perf_load_metric_id(perf, query->guid, &config_id)) {
332 DBG("metric set: %s (already loaded)\n", query->guid);
333 register_oa_config(perf, query, config_id);
334 continue;
335 }
336
337 int ret = i915_add_config(perf, fd, &query->config, query->guid);
338 if (ret < 0) {
339 DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
340 query->name, query->guid, strerror(errno));
341 continue;
342 }
343
344 register_oa_config(perf, query, ret);
345 DBG("metric set: %s (added)\n", query->guid);
346 }
347 }
348
349 static void
350 compute_topology_builtins(struct gen_perf_config *perf,
351 const struct gen_device_info *devinfo)
352 {
353 perf->sys_vars.slice_mask = devinfo->slice_masks;
354 perf->sys_vars.n_eu_slices = devinfo->num_slices;
355
356 for (int i = 0; i < sizeof(devinfo->subslice_masks[i]); i++) {
357 perf->sys_vars.n_eu_sub_slices +=
358 __builtin_popcount(devinfo->subslice_masks[i]);
359 }
360
361 for (int i = 0; i < sizeof(devinfo->eu_masks); i++)
362 perf->sys_vars.n_eus += __builtin_popcount(devinfo->eu_masks[i]);
363
364 perf->sys_vars.eu_threads_count = devinfo->num_thread_per_eu;
365
366 /* The subslice mask builtin contains bits for all slices. Prior to Gen11
367 * it had groups of 3bits for each slice, on Gen11 it's 8bits for each
368 * slice.
369 *
370 * Ideally equations would be updated to have a slice/subslice query
371 * function/operator.
372 */
373 perf->sys_vars.subslice_mask = 0;
374
375 int bits_per_subslice = devinfo->gen == 11 ? 8 : 3;
376
377 for (int s = 0; s < util_last_bit(devinfo->slice_masks); s++) {
378 for (int ss = 0; ss < (devinfo->subslice_slice_stride * 8); ss++) {
379 if (gen_device_info_subslice_available(devinfo, s, ss))
380 perf->sys_vars.subslice_mask |= 1ULL << (s * bits_per_subslice + ss);
381 }
382 }
383 }
384
385 static bool
386 init_oa_sys_vars(struct gen_perf_config *perf, const struct gen_device_info *devinfo)
387 {
388 uint64_t min_freq_mhz = 0, max_freq_mhz = 0;
389
390 if (!read_sysfs_drm_device_file_uint64(perf, "gt_min_freq_mhz", &min_freq_mhz))
391 return false;
392
393 if (!read_sysfs_drm_device_file_uint64(perf, "gt_max_freq_mhz", &max_freq_mhz))
394 return false;
395
396 memset(&perf->sys_vars, 0, sizeof(perf->sys_vars));
397 perf->sys_vars.gt_min_freq = min_freq_mhz * 1000000;
398 perf->sys_vars.gt_max_freq = max_freq_mhz * 1000000;
399 perf->sys_vars.timestamp_frequency = devinfo->timestamp_frequency;
400 perf->sys_vars.revision = devinfo->revision;
401 compute_topology_builtins(perf, devinfo);
402
403 return true;
404 }
405
406 typedef void (*perf_register_oa_queries_t)(struct gen_perf_config *);
407
408 static perf_register_oa_queries_t
409 get_register_queries_function(const struct gen_device_info *devinfo)
410 {
411 if (devinfo->is_haswell)
412 return gen_oa_register_queries_hsw;
413 if (devinfo->is_cherryview)
414 return gen_oa_register_queries_chv;
415 if (devinfo->is_broadwell)
416 return gen_oa_register_queries_bdw;
417 if (devinfo->is_broxton)
418 return gen_oa_register_queries_bxt;
419 if (devinfo->is_skylake) {
420 if (devinfo->gt == 2)
421 return gen_oa_register_queries_sklgt2;
422 if (devinfo->gt == 3)
423 return gen_oa_register_queries_sklgt3;
424 if (devinfo->gt == 4)
425 return gen_oa_register_queries_sklgt4;
426 }
427 if (devinfo->is_kabylake) {
428 if (devinfo->gt == 2)
429 return gen_oa_register_queries_kblgt2;
430 if (devinfo->gt == 3)
431 return gen_oa_register_queries_kblgt3;
432 }
433 if (devinfo->is_geminilake)
434 return gen_oa_register_queries_glk;
435 if (devinfo->is_coffeelake) {
436 if (devinfo->gt == 2)
437 return gen_oa_register_queries_cflgt2;
438 if (devinfo->gt == 3)
439 return gen_oa_register_queries_cflgt3;
440 }
441 if (devinfo->is_cannonlake)
442 return gen_oa_register_queries_cnl;
443 if (devinfo->gen == 11) {
444 if (devinfo->is_elkhartlake)
445 return gen_oa_register_queries_lkf;
446 return gen_oa_register_queries_icl;
447 }
448 if (devinfo->gen == 12)
449 return gen_oa_register_queries_tgl;
450
451 return NULL;
452 }
453
454 static void
455 load_pipeline_statistic_metrics(struct gen_perf_config *perf_cfg,
456 const struct gen_device_info *devinfo)
457 {
458 struct gen_perf_query_info *query =
459 gen_perf_append_query_info(perf_cfg, MAX_STAT_COUNTERS);
460
461 query->kind = GEN_PERF_QUERY_TYPE_PIPELINE;
462 query->name = "Pipeline Statistics Registers";
463
464 gen_perf_query_add_basic_stat_reg(query, IA_VERTICES_COUNT,
465 "N vertices submitted");
466 gen_perf_query_add_basic_stat_reg(query, IA_PRIMITIVES_COUNT,
467 "N primitives submitted");
468 gen_perf_query_add_basic_stat_reg(query, VS_INVOCATION_COUNT,
469 "N vertex shader invocations");
470
471 if (devinfo->gen == 6) {
472 gen_perf_query_add_stat_reg(query, GEN6_SO_PRIM_STORAGE_NEEDED, 1, 1,
473 "SO_PRIM_STORAGE_NEEDED",
474 "N geometry shader stream-out primitives (total)");
475 gen_perf_query_add_stat_reg(query, GEN6_SO_NUM_PRIMS_WRITTEN, 1, 1,
476 "SO_NUM_PRIMS_WRITTEN",
477 "N geometry shader stream-out primitives (written)");
478 } else {
479 gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(0), 1, 1,
480 "SO_PRIM_STORAGE_NEEDED (Stream 0)",
481 "N stream-out (stream 0) primitives (total)");
482 gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(1), 1, 1,
483 "SO_PRIM_STORAGE_NEEDED (Stream 1)",
484 "N stream-out (stream 1) primitives (total)");
485 gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(2), 1, 1,
486 "SO_PRIM_STORAGE_NEEDED (Stream 2)",
487 "N stream-out (stream 2) primitives (total)");
488 gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(3), 1, 1,
489 "SO_PRIM_STORAGE_NEEDED (Stream 3)",
490 "N stream-out (stream 3) primitives (total)");
491 gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(0), 1, 1,
492 "SO_NUM_PRIMS_WRITTEN (Stream 0)",
493 "N stream-out (stream 0) primitives (written)");
494 gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(1), 1, 1,
495 "SO_NUM_PRIMS_WRITTEN (Stream 1)",
496 "N stream-out (stream 1) primitives (written)");
497 gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(2), 1, 1,
498 "SO_NUM_PRIMS_WRITTEN (Stream 2)",
499 "N stream-out (stream 2) primitives (written)");
500 gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(3), 1, 1,
501 "SO_NUM_PRIMS_WRITTEN (Stream 3)",
502 "N stream-out (stream 3) primitives (written)");
503 }
504
505 gen_perf_query_add_basic_stat_reg(query, HS_INVOCATION_COUNT,
506 "N TCS shader invocations");
507 gen_perf_query_add_basic_stat_reg(query, DS_INVOCATION_COUNT,
508 "N TES shader invocations");
509
510 gen_perf_query_add_basic_stat_reg(query, GS_INVOCATION_COUNT,
511 "N geometry shader invocations");
512 gen_perf_query_add_basic_stat_reg(query, GS_PRIMITIVES_COUNT,
513 "N geometry shader primitives emitted");
514
515 gen_perf_query_add_basic_stat_reg(query, CL_INVOCATION_COUNT,
516 "N primitives entering clipping");
517 gen_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
518 "N primitives leaving clipping");
519
520 if (devinfo->is_haswell || devinfo->gen == 8) {
521 gen_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4,
522 "N fragment shader invocations",
523 "N fragment shader invocations");
524 } else {
525 gen_perf_query_add_basic_stat_reg(query, PS_INVOCATION_COUNT,
526 "N fragment shader invocations");
527 }
528
529 gen_perf_query_add_basic_stat_reg(query, PS_DEPTH_COUNT,
530 "N z-pass fragments");
531
532 if (devinfo->gen >= 7) {
533 gen_perf_query_add_basic_stat_reg(query, CS_INVOCATION_COUNT,
534 "N compute shader invocations");
535 }
536
537 query->data_size = sizeof(uint64_t) * query->n_counters;
538 }
539
540 static int
541 i915_perf_version(int drm_fd)
542 {
543 int tmp;
544 drm_i915_getparam_t gp = {
545 .param = I915_PARAM_PERF_REVISION,
546 .value = &tmp,
547 };
548
549 int ret = gen_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
550
551 /* Return 0 if this getparam is not supported, the first version supported
552 * is 1.
553 */
554 return ret < 0 ? 0 : tmp;
555 }
556
557 static void
558 i915_get_sseu(int drm_fd, struct drm_i915_gem_context_param_sseu *sseu)
559 {
560 struct drm_i915_gem_context_param arg = {
561 .param = I915_CONTEXT_PARAM_SSEU,
562 .size = sizeof(*sseu),
563 .value = to_user_pointer(sseu)
564 };
565
566 gen_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
567 }
568
569 static bool
570 load_oa_metrics(struct gen_perf_config *perf, int fd,
571 const struct gen_device_info *devinfo)
572 {
573 perf_register_oa_queries_t oa_register = get_register_queries_function(devinfo);
574 bool i915_perf_oa_available = false;
575 struct stat sb;
576
577 perf->i915_query_supported = i915_query_perf_config_supported(perf, fd);
578 perf->i915_perf_version = i915_perf_version(fd);
579
580 /* Record the default SSEU configuration. */
581 i915_get_sseu(fd, &perf->sseu);
582
583 /* The existence of this sysctl parameter implies the kernel supports
584 * the i915 perf interface.
585 */
586 if (stat("/proc/sys/dev/i915/perf_stream_paranoid", &sb) == 0) {
587
588 /* If _paranoid == 1 then on Gen8+ we won't be able to access OA
589 * metrics unless running as root.
590 */
591 if (devinfo->is_haswell)
592 i915_perf_oa_available = true;
593 else {
594 uint64_t paranoid = 1;
595
596 read_file_uint64("/proc/sys/dev/i915/perf_stream_paranoid", &paranoid);
597
598 if (paranoid == 0 || geteuid() == 0)
599 i915_perf_oa_available = true;
600 }
601 }
602
603 if (!i915_perf_oa_available ||
604 !oa_register ||
605 !get_sysfs_dev_dir(perf, fd) ||
606 !init_oa_sys_vars(perf, devinfo))
607 return false;
608
609 perf->oa_metrics_table =
610 _mesa_hash_table_create(perf, _mesa_hash_string,
611 _mesa_key_string_equal);
612
613 /* Index all the metric sets mesa knows about before looking to see what
614 * the kernel is advertising.
615 */
616 oa_register(perf);
617
618 if (likely((INTEL_DEBUG & DEBUG_NO_OACONFIG) == 0) &&
619 kernel_has_dynamic_config_support(perf, fd))
620 init_oa_configs(perf, fd);
621 else
622 enumerate_sysfs_metrics(perf);
623
624 return true;
625 }
626
627 struct gen_perf_registers *
628 gen_perf_load_configuration(struct gen_perf_config *perf_cfg, int fd, const char *guid)
629 {
630 if (!perf_cfg->i915_query_supported)
631 return NULL;
632
633 struct drm_i915_perf_oa_config i915_config = { 0, };
634 if (!i915_query_perf_config_data(perf_cfg, fd, guid, &i915_config))
635 return NULL;
636
637 struct gen_perf_registers *config = rzalloc(NULL, struct gen_perf_registers);
638 config->n_flex_regs = i915_config.n_flex_regs;
639 config->flex_regs = rzalloc_array(config, struct gen_perf_query_register_prog, config->n_flex_regs);
640 config->n_mux_regs = i915_config.n_mux_regs;
641 config->mux_regs = rzalloc_array(config, struct gen_perf_query_register_prog, config->n_mux_regs);
642 config->n_b_counter_regs = i915_config.n_boolean_regs;
643 config->b_counter_regs = rzalloc_array(config, struct gen_perf_query_register_prog, config->n_b_counter_regs);
644
645 /*
646 * struct gen_perf_query_register_prog maps exactly to the tuple of
647 * (register offset, register value) returned by the i915.
648 */
649 i915_config.flex_regs_ptr = to_user_pointer(config->flex_regs);
650 i915_config.mux_regs_ptr = to_user_pointer(config->mux_regs);
651 i915_config.boolean_regs_ptr = to_user_pointer(config->b_counter_regs);
652 if (!i915_query_perf_config_data(perf_cfg, fd, guid, &i915_config)) {
653 ralloc_free(config);
654 return NULL;
655 }
656
657 return config;
658 }
659
660 uint64_t
661 gen_perf_store_configuration(struct gen_perf_config *perf_cfg, int fd,
662 const struct gen_perf_registers *config,
663 const char *guid)
664 {
665 if (guid)
666 return i915_add_config(perf_cfg, fd, config, guid);
667
668 struct mesa_sha1 sha1_ctx;
669 _mesa_sha1_init(&sha1_ctx);
670
671 if (config->flex_regs) {
672 _mesa_sha1_update(&sha1_ctx, config->flex_regs,
673 sizeof(config->flex_regs[0]) *
674 config->n_flex_regs);
675 }
676 if (config->mux_regs) {
677 _mesa_sha1_update(&sha1_ctx, config->mux_regs,
678 sizeof(config->mux_regs[0]) *
679 config->n_mux_regs);
680 }
681 if (config->b_counter_regs) {
682 _mesa_sha1_update(&sha1_ctx, config->b_counter_regs,
683 sizeof(config->b_counter_regs[0]) *
684 config->n_b_counter_regs);
685 }
686
687 uint8_t hash[20];
688 _mesa_sha1_final(&sha1_ctx, hash);
689
690 char formatted_hash[41];
691 _mesa_sha1_format(formatted_hash, hash);
692
693 char generated_guid[37];
694 snprintf(generated_guid, sizeof(generated_guid),
695 "%.8s-%.4s-%.4s-%.4s-%.12s",
696 &formatted_hash[0], &formatted_hash[8],
697 &formatted_hash[8 + 4], &formatted_hash[8 + 4 + 4],
698 &formatted_hash[8 + 4 + 4 + 4]);
699
700 /* Check if already present. */
701 uint64_t id;
702 if (gen_perf_load_metric_id(perf_cfg, generated_guid, &id))
703 return id;
704
705 return i915_add_config(perf_cfg, fd, config, generated_guid);
706 }
707
708 /* Accumulate 32bits OA counters */
709 static inline void
710 accumulate_uint32(const uint32_t *report0,
711 const uint32_t *report1,
712 uint64_t *accumulator)
713 {
714 *accumulator += (uint32_t)(*report1 - *report0);
715 }
716
717 /* Accumulate 40bits OA counters */
718 static inline void
719 accumulate_uint40(int a_index,
720 const uint32_t *report0,
721 const uint32_t *report1,
722 uint64_t *accumulator)
723 {
724 const uint8_t *high_bytes0 = (uint8_t *)(report0 + 40);
725 const uint8_t *high_bytes1 = (uint8_t *)(report1 + 40);
726 uint64_t high0 = (uint64_t)(high_bytes0[a_index]) << 32;
727 uint64_t high1 = (uint64_t)(high_bytes1[a_index]) << 32;
728 uint64_t value0 = report0[a_index + 4] | high0;
729 uint64_t value1 = report1[a_index + 4] | high1;
730 uint64_t delta;
731
732 if (value0 > value1)
733 delta = (1ULL << 40) + value1 - value0;
734 else
735 delta = value1 - value0;
736
737 *accumulator += delta;
738 }
739
740 static void
741 gen8_read_report_clock_ratios(const uint32_t *report,
742 uint64_t *slice_freq_hz,
743 uint64_t *unslice_freq_hz)
744 {
745 /* The lower 16bits of the RPT_ID field of the OA reports contains a
746 * snapshot of the bits coming from the RP_FREQ_NORMAL register and is
747 * divided this way :
748 *
749 * RPT_ID[31:25]: RP_FREQ_NORMAL[20:14] (low squashed_slice_clock_frequency)
750 * RPT_ID[10:9]: RP_FREQ_NORMAL[22:21] (high squashed_slice_clock_frequency)
751 * RPT_ID[8:0]: RP_FREQ_NORMAL[31:23] (squashed_unslice_clock_frequency)
752 *
753 * RP_FREQ_NORMAL[31:23]: Software Unslice Ratio Request
754 * Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
755 *
756 * RP_FREQ_NORMAL[22:14]: Software Slice Ratio Request
757 * Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
758 */
759
760 uint32_t unslice_freq = report[0] & 0x1ff;
761 uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
762 uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
763 uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
764
765 *slice_freq_hz = slice_freq * 16666667ULL;
766 *unslice_freq_hz = unslice_freq * 16666667ULL;
767 }
768
769 void
770 gen_perf_query_result_read_frequencies(struct gen_perf_query_result *result,
771 const struct gen_device_info *devinfo,
772 const uint32_t *start,
773 const uint32_t *end)
774 {
775 /* Slice/Unslice frequency is only available in the OA reports when the
776 * "Disable OA reports due to clock ratio change" field in
777 * OA_DEBUG_REGISTER is set to 1. This is how the kernel programs this
778 * global register (see drivers/gpu/drm/i915/i915_perf.c)
779 *
780 * Documentation says this should be available on Gen9+ but experimentation
781 * shows that Gen8 reports similar values, so we enable it there too.
782 */
783 if (devinfo->gen < 8)
784 return;
785
786 gen8_read_report_clock_ratios(start,
787 &result->slice_frequency[0],
788 &result->unslice_frequency[0]);
789 gen8_read_report_clock_ratios(end,
790 &result->slice_frequency[1],
791 &result->unslice_frequency[1]);
792 }
793
794 void
795 gen_perf_query_result_accumulate(struct gen_perf_query_result *result,
796 const struct gen_perf_query_info *query,
797 const uint32_t *start,
798 const uint32_t *end)
799 {
800 int i, idx = 0;
801
802 if (result->hw_id == OA_REPORT_INVALID_CTX_ID &&
803 start[2] != OA_REPORT_INVALID_CTX_ID)
804 result->hw_id = start[2];
805 if (result->reports_accumulated == 0)
806 result->begin_timestamp = start[1];
807 result->reports_accumulated++;
808
809 switch (query->oa_format) {
810 case I915_OA_FORMAT_A32u40_A4u32_B8_C8:
811 accumulate_uint32(start + 1, end + 1, result->accumulator + idx++); /* timestamp */
812 accumulate_uint32(start + 3, end + 3, result->accumulator + idx++); /* clock */
813
814 /* 32x 40bit A counters... */
815 for (i = 0; i < 32; i++)
816 accumulate_uint40(i, start, end, result->accumulator + idx++);
817
818 /* 4x 32bit A counters... */
819 for (i = 0; i < 4; i++)
820 accumulate_uint32(start + 36 + i, end + 36 + i, result->accumulator + idx++);
821
822 /* 8x 32bit B counters + 8x 32bit C counters... */
823 for (i = 0; i < 16; i++)
824 accumulate_uint32(start + 48 + i, end + 48 + i, result->accumulator + idx++);
825 break;
826
827 case I915_OA_FORMAT_A45_B8_C8:
828 accumulate_uint32(start + 1, end + 1, result->accumulator); /* timestamp */
829
830 for (i = 0; i < 61; i++)
831 accumulate_uint32(start + 3 + i, end + 3 + i, result->accumulator + 1 + i);
832 break;
833
834 default:
835 unreachable("Can't accumulate OA counters in unknown format");
836 }
837
838 }
839
840 void
841 gen_perf_query_result_clear(struct gen_perf_query_result *result)
842 {
843 memset(result, 0, sizeof(*result));
844 result->hw_id = OA_REPORT_INVALID_CTX_ID; /* invalid */
845 }
846
847 void
848 gen_perf_init_metrics(struct gen_perf_config *perf_cfg,
849 const struct gen_device_info *devinfo,
850 int drm_fd)
851 {
852 load_pipeline_statistic_metrics(perf_cfg, devinfo);
853 gen_perf_register_mdapi_statistic_query(perf_cfg, devinfo);
854 if (load_oa_metrics(perf_cfg, drm_fd, devinfo))
855 gen_perf_register_mdapi_oa_query(perf_cfg, devinfo);
856 }