2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <sys/types.h>
32 #ifndef HAVE_DIRENT_D_TYPE
33 #include <limits.h> // PATH_MAX
36 #include <drm-uapi/i915_drm.h>
38 #include "common/gen_gem.h"
40 #include "dev/gen_debug.h"
41 #include "dev/gen_device_info.h"
43 #include "perf/gen_perf.h"
44 #include "perf/gen_perf_regs.h"
45 #include "perf/gen_perf_mdapi.h"
46 #include "perf/gen_perf_metrics.h"
47 #include "perf/gen_perf_private.h"
49 #include "util/bitscan.h"
50 #include "util/macros.h"
51 #include "util/mesa-sha1.h"
52 #include "util/u_math.h"
54 #define FILE_DEBUG_FLAG DEBUG_PERFMON
56 #define OA_REPORT_INVALID_CTX_ID (0xffffffff)
59 is_dir_or_link(const struct dirent
*entry
, const char *parent_dir
)
61 #ifdef HAVE_DIRENT_D_TYPE
62 return entry
->d_type
== DT_DIR
|| entry
->d_type
== DT_LNK
;
65 char path
[PATH_MAX
+ 1];
66 snprintf(path
, sizeof(path
), "%s/%s", parent_dir
, entry
->d_name
);
68 return S_ISDIR(st
.st_mode
) || S_ISLNK(st
.st_mode
);
73 get_sysfs_dev_dir(struct gen_perf_config
*perf
, int fd
)
78 struct dirent
*drm_entry
;
81 perf
->sysfs_dev_dir
[0] = '\0';
83 if (unlikely(INTEL_DEBUG
& DEBUG_NO_OACONFIG
))
87 DBG("Failed to stat DRM fd\n");
91 maj
= major(sb
.st_rdev
);
92 min
= minor(sb
.st_rdev
);
94 if (!S_ISCHR(sb
.st_mode
)) {
95 DBG("DRM fd is not a character device as expected\n");
99 len
= snprintf(perf
->sysfs_dev_dir
,
100 sizeof(perf
->sysfs_dev_dir
),
101 "/sys/dev/char/%d:%d/device/drm", maj
, min
);
102 if (len
< 0 || len
>= sizeof(perf
->sysfs_dev_dir
)) {
103 DBG("Failed to concatenate sysfs path to drm device\n");
107 drmdir
= opendir(perf
->sysfs_dev_dir
);
109 DBG("Failed to open %s: %m\n", perf
->sysfs_dev_dir
);
113 while ((drm_entry
= readdir(drmdir
))) {
114 if (is_dir_or_link(drm_entry
, perf
->sysfs_dev_dir
) &&
115 strncmp(drm_entry
->d_name
, "card", 4) == 0)
117 len
= snprintf(perf
->sysfs_dev_dir
,
118 sizeof(perf
->sysfs_dev_dir
),
119 "/sys/dev/char/%d:%d/device/drm/%s",
120 maj
, min
, drm_entry
->d_name
);
122 if (len
< 0 || len
>= sizeof(perf
->sysfs_dev_dir
))
131 DBG("Failed to find cardX directory under /sys/dev/char/%d:%d/device/drm\n",
138 read_file_uint64(const char *file
, uint64_t *val
)
146 while ((n
= read(fd
, buf
, sizeof (buf
) - 1)) < 0 &&
153 *val
= strtoull(buf
, NULL
, 0);
159 read_sysfs_drm_device_file_uint64(struct gen_perf_config
*perf
,
166 len
= snprintf(buf
, sizeof(buf
), "%s/%s", perf
->sysfs_dev_dir
, file
);
167 if (len
< 0 || len
>= sizeof(buf
)) {
168 DBG("Failed to concatenate sys filename to read u64 from\n");
172 return read_file_uint64(buf
, value
);
176 register_oa_config(struct gen_perf_config
*perf
,
177 const struct gen_device_info
*devinfo
,
178 const struct gen_perf_query_info
*query
,
181 struct gen_perf_query_info
*registered_query
=
182 gen_perf_append_query_info(perf
, 0);
184 *registered_query
= *query
;
185 registered_query
->oa_format
= devinfo
->gen
>= 8 ?
186 I915_OA_FORMAT_A32u40_A4u32_B8_C8
: I915_OA_FORMAT_A45_B8_C8
;
187 registered_query
->oa_metrics_set_id
= config_id
;
188 DBG("metric set registered: id = %" PRIu64
", guid = %s\n",
189 registered_query
->oa_metrics_set_id
, query
->guid
);
193 enumerate_sysfs_metrics(struct gen_perf_config
*perf
,
194 const struct gen_device_info
*devinfo
)
196 DIR *metricsdir
= NULL
;
197 struct dirent
*metric_entry
;
201 len
= snprintf(buf
, sizeof(buf
), "%s/metrics", perf
->sysfs_dev_dir
);
202 if (len
< 0 || len
>= sizeof(buf
)) {
203 DBG("Failed to concatenate path to sysfs metrics/ directory\n");
207 metricsdir
= opendir(buf
);
209 DBG("Failed to open %s: %m\n", buf
);
213 while ((metric_entry
= readdir(metricsdir
))) {
214 struct hash_entry
*entry
;
215 if (!is_dir_or_link(metric_entry
, buf
) ||
216 metric_entry
->d_name
[0] == '.')
219 DBG("metric set: %s\n", metric_entry
->d_name
);
220 entry
= _mesa_hash_table_search(perf
->oa_metrics_table
,
221 metric_entry
->d_name
);
224 if (!gen_perf_load_metric_id(perf
, metric_entry
->d_name
, &id
)) {
225 DBG("Failed to read metric set id from %s: %m", buf
);
229 register_oa_config(perf
, devinfo
,
230 (const struct gen_perf_query_info
*)entry
->data
, id
);
232 DBG("metric set not known by mesa (skipping)\n");
235 closedir(metricsdir
);
239 add_all_metrics(struct gen_perf_config
*perf
,
240 const struct gen_device_info
*devinfo
)
242 hash_table_foreach(perf
->oa_metrics_table
, entry
) {
243 const struct gen_perf_query_info
*query
= entry
->data
;
244 register_oa_config(perf
, devinfo
, query
, 0);
249 kernel_has_dynamic_config_support(struct gen_perf_config
*perf
, int fd
)
251 uint64_t invalid_config_id
= UINT64_MAX
;
253 return gen_ioctl(fd
, DRM_IOCTL_I915_PERF_REMOVE_CONFIG
,
254 &invalid_config_id
) < 0 && errno
== ENOENT
;
258 i915_query_items(struct gen_perf_config
*perf
, int fd
,
259 struct drm_i915_query_item
*items
, uint32_t n_items
)
261 struct drm_i915_query q
= {
262 .num_items
= n_items
,
263 .items_ptr
= to_user_pointer(items
),
265 return gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &q
);
269 i915_query_perf_config_supported(struct gen_perf_config
*perf
, int fd
)
271 struct drm_i915_query_item item
= {
272 .query_id
= DRM_I915_QUERY_PERF_CONFIG
,
273 .flags
= DRM_I915_QUERY_PERF_CONFIG_LIST
,
276 return i915_query_items(perf
, fd
, &item
, 1) == 0 && item
.length
> 0;
280 i915_query_perf_config_data(struct gen_perf_config
*perf
,
281 int fd
, const char *guid
,
282 struct drm_i915_perf_oa_config
*config
)
285 struct drm_i915_query_perf_config query
;
286 struct drm_i915_perf_oa_config config
;
288 struct drm_i915_query_item item
= {
289 .query_id
= DRM_I915_QUERY_PERF_CONFIG
,
290 .flags
= DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
,
291 .data_ptr
= to_user_pointer(&item_data
),
292 .length
= sizeof(item_data
),
295 memset(&item_data
, 0, sizeof(item_data
));
296 memcpy(item_data
.query
.uuid
, guid
, sizeof(item_data
.query
.uuid
));
297 memcpy(&item_data
.config
, config
, sizeof(item_data
.config
));
299 if (!(i915_query_items(perf
, fd
, &item
, 1) == 0 && item
.length
> 0))
302 memcpy(config
, &item_data
.config
, sizeof(item_data
.config
));
308 gen_perf_load_metric_id(struct gen_perf_config
*perf_cfg
,
312 char config_path
[280];
314 snprintf(config_path
, sizeof(config_path
), "%s/metrics/%s/id",
315 perf_cfg
->sysfs_dev_dir
, guid
);
317 /* Don't recreate already loaded configs. */
318 return read_file_uint64(config_path
, metric_id
);
322 i915_add_config(struct gen_perf_config
*perf
, int fd
,
323 const struct gen_perf_registers
*config
,
326 struct drm_i915_perf_oa_config i915_config
= { 0, };
328 memcpy(i915_config
.uuid
, guid
, sizeof(i915_config
.uuid
));
330 i915_config
.n_mux_regs
= config
->n_mux_regs
;
331 i915_config
.mux_regs_ptr
= to_const_user_pointer(config
->mux_regs
);
333 i915_config
.n_boolean_regs
= config
->n_b_counter_regs
;
334 i915_config
.boolean_regs_ptr
= to_const_user_pointer(config
->b_counter_regs
);
336 i915_config
.n_flex_regs
= config
->n_flex_regs
;
337 i915_config
.flex_regs_ptr
= to_const_user_pointer(config
->flex_regs
);
339 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_PERF_ADD_CONFIG
, &i915_config
);
340 return ret
> 0 ? ret
: 0;
344 init_oa_configs(struct gen_perf_config
*perf
, int fd
,
345 const struct gen_device_info
*devinfo
)
347 hash_table_foreach(perf
->oa_metrics_table
, entry
) {
348 const struct gen_perf_query_info
*query
= entry
->data
;
351 if (gen_perf_load_metric_id(perf
, query
->guid
, &config_id
)) {
352 DBG("metric set: %s (already loaded)\n", query
->guid
);
353 register_oa_config(perf
, devinfo
, query
, config_id
);
357 int ret
= i915_add_config(perf
, fd
, &query
->config
, query
->guid
);
359 DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
360 query
->name
, query
->guid
, strerror(errno
));
364 register_oa_config(perf
, devinfo
, query
, ret
);
365 DBG("metric set: %s (added)\n", query
->guid
);
370 compute_topology_builtins(struct gen_perf_config
*perf
,
371 const struct gen_device_info
*devinfo
)
373 perf
->sys_vars
.slice_mask
= devinfo
->slice_masks
;
374 perf
->sys_vars
.n_eu_slices
= devinfo
->num_slices
;
376 for (int i
= 0; i
< sizeof(devinfo
->subslice_masks
[i
]); i
++) {
377 perf
->sys_vars
.n_eu_sub_slices
+=
378 __builtin_popcount(devinfo
->subslice_masks
[i
]);
381 for (int i
= 0; i
< sizeof(devinfo
->eu_masks
); i
++)
382 perf
->sys_vars
.n_eus
+= __builtin_popcount(devinfo
->eu_masks
[i
]);
384 perf
->sys_vars
.eu_threads_count
= devinfo
->num_thread_per_eu
;
386 /* The subslice mask builtin contains bits for all slices. Prior to Gen11
387 * it had groups of 3bits for each slice, on Gen11 it's 8bits for each
390 * Ideally equations would be updated to have a slice/subslice query
393 perf
->sys_vars
.subslice_mask
= 0;
395 int bits_per_subslice
= devinfo
->gen
== 11 ? 8 : 3;
397 for (int s
= 0; s
< util_last_bit(devinfo
->slice_masks
); s
++) {
398 for (int ss
= 0; ss
< (devinfo
->subslice_slice_stride
* 8); ss
++) {
399 if (gen_device_info_subslice_available(devinfo
, s
, ss
))
400 perf
->sys_vars
.subslice_mask
|= 1ULL << (s
* bits_per_subslice
+ ss
);
406 init_oa_sys_vars(struct gen_perf_config
*perf
, const struct gen_device_info
*devinfo
)
408 uint64_t min_freq_mhz
= 0, max_freq_mhz
= 0;
410 if (likely(!(INTEL_DEBUG
& DEBUG_NO_OACONFIG
))) {
411 if (!read_sysfs_drm_device_file_uint64(perf
, "gt_min_freq_mhz", &min_freq_mhz
))
414 if (!read_sysfs_drm_device_file_uint64(perf
, "gt_max_freq_mhz", &max_freq_mhz
))
421 memset(&perf
->sys_vars
, 0, sizeof(perf
->sys_vars
));
422 perf
->sys_vars
.gt_min_freq
= min_freq_mhz
* 1000000;
423 perf
->sys_vars
.gt_max_freq
= max_freq_mhz
* 1000000;
424 perf
->sys_vars
.timestamp_frequency
= devinfo
->timestamp_frequency
;
425 perf
->sys_vars
.revision
= devinfo
->revision
;
426 compute_topology_builtins(perf
, devinfo
);
431 typedef void (*perf_register_oa_queries_t
)(struct gen_perf_config
*);
433 static perf_register_oa_queries_t
434 get_register_queries_function(const struct gen_device_info
*devinfo
)
436 if (devinfo
->is_haswell
)
437 return gen_oa_register_queries_hsw
;
438 if (devinfo
->is_cherryview
)
439 return gen_oa_register_queries_chv
;
440 if (devinfo
->is_broadwell
)
441 return gen_oa_register_queries_bdw
;
442 if (devinfo
->is_broxton
)
443 return gen_oa_register_queries_bxt
;
444 if (devinfo
->is_skylake
) {
445 if (devinfo
->gt
== 2)
446 return gen_oa_register_queries_sklgt2
;
447 if (devinfo
->gt
== 3)
448 return gen_oa_register_queries_sklgt3
;
449 if (devinfo
->gt
== 4)
450 return gen_oa_register_queries_sklgt4
;
452 if (devinfo
->is_kabylake
) {
453 if (devinfo
->gt
== 2)
454 return gen_oa_register_queries_kblgt2
;
455 if (devinfo
->gt
== 3)
456 return gen_oa_register_queries_kblgt3
;
458 if (devinfo
->is_geminilake
)
459 return gen_oa_register_queries_glk
;
460 if (devinfo
->is_coffeelake
) {
461 if (devinfo
->gt
== 2)
462 return gen_oa_register_queries_cflgt2
;
463 if (devinfo
->gt
== 3)
464 return gen_oa_register_queries_cflgt3
;
466 if (devinfo
->is_cannonlake
)
467 return gen_oa_register_queries_cnl
;
468 if (devinfo
->gen
== 11) {
469 if (devinfo
->is_elkhartlake
)
470 return gen_oa_register_queries_lkf
;
471 return gen_oa_register_queries_icl
;
473 if (devinfo
->gen
== 12)
474 return gen_oa_register_queries_tgl
;
480 load_pipeline_statistic_metrics(struct gen_perf_config
*perf_cfg
,
481 const struct gen_device_info
*devinfo
)
483 struct gen_perf_query_info
*query
=
484 gen_perf_append_query_info(perf_cfg
, MAX_STAT_COUNTERS
);
486 query
->kind
= GEN_PERF_QUERY_TYPE_PIPELINE
;
487 query
->name
= "Pipeline Statistics Registers";
489 gen_perf_query_add_basic_stat_reg(query
, IA_VERTICES_COUNT
,
490 "N vertices submitted");
491 gen_perf_query_add_basic_stat_reg(query
, IA_PRIMITIVES_COUNT
,
492 "N primitives submitted");
493 gen_perf_query_add_basic_stat_reg(query
, VS_INVOCATION_COUNT
,
494 "N vertex shader invocations");
496 if (devinfo
->gen
== 6) {
497 gen_perf_query_add_stat_reg(query
, GEN6_SO_PRIM_STORAGE_NEEDED
, 1, 1,
498 "SO_PRIM_STORAGE_NEEDED",
499 "N geometry shader stream-out primitives (total)");
500 gen_perf_query_add_stat_reg(query
, GEN6_SO_NUM_PRIMS_WRITTEN
, 1, 1,
501 "SO_NUM_PRIMS_WRITTEN",
502 "N geometry shader stream-out primitives (written)");
504 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(0), 1, 1,
505 "SO_PRIM_STORAGE_NEEDED (Stream 0)",
506 "N stream-out (stream 0) primitives (total)");
507 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(1), 1, 1,
508 "SO_PRIM_STORAGE_NEEDED (Stream 1)",
509 "N stream-out (stream 1) primitives (total)");
510 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(2), 1, 1,
511 "SO_PRIM_STORAGE_NEEDED (Stream 2)",
512 "N stream-out (stream 2) primitives (total)");
513 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(3), 1, 1,
514 "SO_PRIM_STORAGE_NEEDED (Stream 3)",
515 "N stream-out (stream 3) primitives (total)");
516 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(0), 1, 1,
517 "SO_NUM_PRIMS_WRITTEN (Stream 0)",
518 "N stream-out (stream 0) primitives (written)");
519 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(1), 1, 1,
520 "SO_NUM_PRIMS_WRITTEN (Stream 1)",
521 "N stream-out (stream 1) primitives (written)");
522 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(2), 1, 1,
523 "SO_NUM_PRIMS_WRITTEN (Stream 2)",
524 "N stream-out (stream 2) primitives (written)");
525 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(3), 1, 1,
526 "SO_NUM_PRIMS_WRITTEN (Stream 3)",
527 "N stream-out (stream 3) primitives (written)");
530 gen_perf_query_add_basic_stat_reg(query
, HS_INVOCATION_COUNT
,
531 "N TCS shader invocations");
532 gen_perf_query_add_basic_stat_reg(query
, DS_INVOCATION_COUNT
,
533 "N TES shader invocations");
535 gen_perf_query_add_basic_stat_reg(query
, GS_INVOCATION_COUNT
,
536 "N geometry shader invocations");
537 gen_perf_query_add_basic_stat_reg(query
, GS_PRIMITIVES_COUNT
,
538 "N geometry shader primitives emitted");
540 gen_perf_query_add_basic_stat_reg(query
, CL_INVOCATION_COUNT
,
541 "N primitives entering clipping");
542 gen_perf_query_add_basic_stat_reg(query
, CL_PRIMITIVES_COUNT
,
543 "N primitives leaving clipping");
545 if (devinfo
->is_haswell
|| devinfo
->gen
== 8) {
546 gen_perf_query_add_stat_reg(query
, PS_INVOCATION_COUNT
, 1, 4,
547 "N fragment shader invocations",
548 "N fragment shader invocations");
550 gen_perf_query_add_basic_stat_reg(query
, PS_INVOCATION_COUNT
,
551 "N fragment shader invocations");
554 gen_perf_query_add_basic_stat_reg(query
, PS_DEPTH_COUNT
,
555 "N z-pass fragments");
557 if (devinfo
->gen
>= 7) {
558 gen_perf_query_add_basic_stat_reg(query
, CS_INVOCATION_COUNT
,
559 "N compute shader invocations");
562 query
->data_size
= sizeof(uint64_t) * query
->n_counters
;
566 i915_perf_version(int drm_fd
)
569 drm_i915_getparam_t gp
= {
570 .param
= I915_PARAM_PERF_REVISION
,
574 int ret
= gen_ioctl(drm_fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
576 /* Return 0 if this getparam is not supported, the first version supported
579 return ret
< 0 ? 0 : tmp
;
583 i915_get_sseu(int drm_fd
, struct drm_i915_gem_context_param_sseu
*sseu
)
585 struct drm_i915_gem_context_param arg
= {
586 .param
= I915_CONTEXT_PARAM_SSEU
,
587 .size
= sizeof(*sseu
),
588 .value
= to_user_pointer(sseu
)
591 gen_ioctl(drm_fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &arg
);
595 compare_counters(const void *_c1
, const void *_c2
)
597 const struct gen_perf_query_counter_info
*c1
= _c1
, *c2
= _c2
;
598 return strcmp(c1
->counter
->symbol_name
, c2
->counter
->symbol_name
);
602 build_unique_counter_list(struct gen_perf_config
*perf
)
604 assert(perf
->n_queries
< 64);
606 size_t max_counters
= 0;
608 for (int q
= 0; q
< perf
->n_queries
; q
++)
609 max_counters
+= perf
->queries
[q
].n_counters
;
612 * Allocate big enough array to hold maximum possible number of counters.
613 * We can't alloc it small and realloc when needed because the hash table
614 * below contains pointers to this array.
616 struct gen_perf_query_counter_info
*counter_infos
=
617 ralloc_array_size(perf
, sizeof(counter_infos
[0]), max_counters
);
619 perf
->n_counters
= 0;
621 struct hash_table
*counters_table
=
622 _mesa_hash_table_create(perf
,
624 _mesa_key_string_equal
);
625 struct hash_entry
*entry
;
626 for (int q
= 0; q
< perf
->n_queries
; q
++) {
627 struct gen_perf_query_info
*query
= &perf
->queries
[q
];
629 for (int c
= 0; c
< query
->n_counters
; c
++) {
630 struct gen_perf_query_counter
*counter
;
631 struct gen_perf_query_counter_info
*counter_info
;
633 counter
= &query
->counters
[c
];
634 entry
= _mesa_hash_table_search(counters_table
, counter
->symbol_name
);
637 counter_info
= entry
->data
;
638 counter_info
->query_mask
|= BITFIELD64_BIT(q
);
641 assert(perf
->n_counters
< max_counters
);
643 counter_info
= &counter_infos
[perf
->n_counters
++];
644 counter_info
->counter
= counter
;
645 counter_info
->query_mask
= BITFIELD64_BIT(q
);
647 counter_info
->location
.group_idx
= q
;
648 counter_info
->location
.counter_idx
= c
;
650 _mesa_hash_table_insert(counters_table
, counter
->symbol_name
, counter_info
);
654 _mesa_hash_table_destroy(counters_table
, NULL
);
656 /* Now we can realloc counter_infos array because hash table doesn't exist. */
657 perf
->counter_infos
= reralloc_array_size(perf
, counter_infos
,
658 sizeof(counter_infos
[0]), perf
->n_counters
);
660 qsort(perf
->counter_infos
, perf
->n_counters
, sizeof(perf
->counter_infos
[0]),
665 load_oa_metrics(struct gen_perf_config
*perf
, int fd
,
666 const struct gen_device_info
*devinfo
)
668 perf_register_oa_queries_t oa_register
= get_register_queries_function(devinfo
);
669 bool i915_perf_oa_available
= false;
672 perf
->i915_query_supported
= i915_query_perf_config_supported(perf
, fd
);
673 perf
->i915_perf_version
= i915_perf_version(fd
);
675 /* Record the default SSEU configuration. */
676 i915_get_sseu(fd
, &perf
->sseu
);
678 /* The existence of this sysctl parameter implies the kernel supports
679 * the i915 perf interface.
681 if (stat("/proc/sys/dev/i915/perf_stream_paranoid", &sb
) == 0) {
683 /* If _paranoid == 1 then on Gen8+ we won't be able to access OA
684 * metrics unless running as root.
686 if (devinfo
->is_haswell
)
687 i915_perf_oa_available
= true;
689 uint64_t paranoid
= 1;
691 read_file_uint64("/proc/sys/dev/i915/perf_stream_paranoid", ¶noid
);
693 if (paranoid
== 0 || geteuid() == 0)
694 i915_perf_oa_available
= true;
697 perf
->platform_supported
= oa_register
!= NULL
;
700 if (!i915_perf_oa_available
||
702 !get_sysfs_dev_dir(perf
, fd
) ||
703 !init_oa_sys_vars(perf
, devinfo
))
706 perf
->oa_metrics_table
=
707 _mesa_hash_table_create(perf
, _mesa_hash_string
,
708 _mesa_key_string_equal
);
710 /* Index all the metric sets mesa knows about before looking to see what
711 * the kernel is advertising.
715 if (likely(!(INTEL_DEBUG
& DEBUG_NO_OACONFIG
))) {
716 if (kernel_has_dynamic_config_support(perf
, fd
))
717 init_oa_configs(perf
, fd
, devinfo
);
719 enumerate_sysfs_metrics(perf
, devinfo
);
721 add_all_metrics(perf
, devinfo
);
724 build_unique_counter_list(perf
);
729 struct gen_perf_registers
*
730 gen_perf_load_configuration(struct gen_perf_config
*perf_cfg
, int fd
, const char *guid
)
732 if (!perf_cfg
->i915_query_supported
)
735 struct drm_i915_perf_oa_config i915_config
= { 0, };
736 if (!i915_query_perf_config_data(perf_cfg
, fd
, guid
, &i915_config
))
739 struct gen_perf_registers
*config
= rzalloc(NULL
, struct gen_perf_registers
);
740 config
->n_flex_regs
= i915_config
.n_flex_regs
;
741 config
->flex_regs
= rzalloc_array(config
, struct gen_perf_query_register_prog
, config
->n_flex_regs
);
742 config
->n_mux_regs
= i915_config
.n_mux_regs
;
743 config
->mux_regs
= rzalloc_array(config
, struct gen_perf_query_register_prog
, config
->n_mux_regs
);
744 config
->n_b_counter_regs
= i915_config
.n_boolean_regs
;
745 config
->b_counter_regs
= rzalloc_array(config
, struct gen_perf_query_register_prog
, config
->n_b_counter_regs
);
748 * struct gen_perf_query_register_prog maps exactly to the tuple of
749 * (register offset, register value) returned by the i915.
751 i915_config
.flex_regs_ptr
= to_const_user_pointer(config
->flex_regs
);
752 i915_config
.mux_regs_ptr
= to_const_user_pointer(config
->mux_regs
);
753 i915_config
.boolean_regs_ptr
= to_const_user_pointer(config
->b_counter_regs
);
754 if (!i915_query_perf_config_data(perf_cfg
, fd
, guid
, &i915_config
)) {
763 gen_perf_store_configuration(struct gen_perf_config
*perf_cfg
, int fd
,
764 const struct gen_perf_registers
*config
,
768 return i915_add_config(perf_cfg
, fd
, config
, guid
);
770 struct mesa_sha1 sha1_ctx
;
771 _mesa_sha1_init(&sha1_ctx
);
773 if (config
->flex_regs
) {
774 _mesa_sha1_update(&sha1_ctx
, config
->flex_regs
,
775 sizeof(config
->flex_regs
[0]) *
776 config
->n_flex_regs
);
778 if (config
->mux_regs
) {
779 _mesa_sha1_update(&sha1_ctx
, config
->mux_regs
,
780 sizeof(config
->mux_regs
[0]) *
783 if (config
->b_counter_regs
) {
784 _mesa_sha1_update(&sha1_ctx
, config
->b_counter_regs
,
785 sizeof(config
->b_counter_regs
[0]) *
786 config
->n_b_counter_regs
);
790 _mesa_sha1_final(&sha1_ctx
, hash
);
792 char formatted_hash
[41];
793 _mesa_sha1_format(formatted_hash
, hash
);
795 char generated_guid
[37];
796 snprintf(generated_guid
, sizeof(generated_guid
),
797 "%.8s-%.4s-%.4s-%.4s-%.12s",
798 &formatted_hash
[0], &formatted_hash
[8],
799 &formatted_hash
[8 + 4], &formatted_hash
[8 + 4 + 4],
800 &formatted_hash
[8 + 4 + 4 + 4]);
802 /* Check if already present. */
804 if (gen_perf_load_metric_id(perf_cfg
, generated_guid
, &id
))
807 return i915_add_config(perf_cfg
, fd
, config
, generated_guid
);
811 get_passes_mask(struct gen_perf_config
*perf
,
812 const uint32_t *counter_indices
,
813 uint32_t counter_indices_count
)
815 uint64_t queries_mask
= 0;
817 assert(perf
->n_queries
< 64);
819 /* Compute the number of passes by going through all counters N times (with
820 * N the number of queries) to make sure we select the most constraining
821 * counters first and look at the more flexible ones (that could be
822 * obtained from multiple queries) later. That way we minimize the number
823 * of passes required.
825 for (uint32_t q
= 0; q
< perf
->n_queries
; q
++) {
826 for (uint32_t i
= 0; i
< counter_indices_count
; i
++) {
827 assert(counter_indices
[i
] < perf
->n_counters
);
829 uint32_t idx
= counter_indices
[i
];
830 if (__builtin_popcount(perf
->counter_infos
[idx
].query_mask
) != (q
+ 1))
833 if (queries_mask
& perf
->counter_infos
[idx
].query_mask
)
836 queries_mask
|= BITFIELD64_BIT(ffsll(perf
->counter_infos
[idx
].query_mask
) - 1);
844 gen_perf_get_n_passes(struct gen_perf_config
*perf
,
845 const uint32_t *counter_indices
,
846 uint32_t counter_indices_count
,
847 struct gen_perf_query_info
**pass_queries
)
849 uint64_t queries_mask
= get_passes_mask(perf
, counter_indices
, counter_indices_count
);
853 for (uint32_t q
= 0; q
< perf
->n_queries
; q
++) {
854 if ((1ULL << q
) & queries_mask
)
855 pass_queries
[pass
++] = &perf
->queries
[q
];
859 return __builtin_popcount(queries_mask
);
863 gen_perf_get_counters_passes(struct gen_perf_config
*perf
,
864 const uint32_t *counter_indices
,
865 uint32_t counter_indices_count
,
866 struct gen_perf_counter_pass
*counter_pass
)
868 uint64_t queries_mask
= get_passes_mask(perf
, counter_indices
, counter_indices_count
);
869 ASSERTED
uint32_t n_passes
= __builtin_popcount(queries_mask
);
871 for (uint32_t i
= 0; i
< counter_indices_count
; i
++) {
872 assert(counter_indices
[i
] < perf
->n_counters
);
874 uint32_t idx
= counter_indices
[i
];
875 counter_pass
[i
].counter
= perf
->counter_infos
[idx
].counter
;
877 uint32_t query_idx
= ffsll(perf
->counter_infos
[idx
].query_mask
& queries_mask
) - 1;
878 counter_pass
[i
].query
= &perf
->queries
[query_idx
];
880 uint32_t clear_bits
= 63 - query_idx
;
881 counter_pass
[i
].pass
= __builtin_popcount((queries_mask
<< clear_bits
) >> clear_bits
) - 1;
882 assert(counter_pass
[i
].pass
< n_passes
);
886 /* Accumulate 32bits OA counters */
888 accumulate_uint32(const uint32_t *report0
,
889 const uint32_t *report1
,
890 uint64_t *accumulator
)
892 *accumulator
+= (uint32_t)(*report1
- *report0
);
895 /* Accumulate 40bits OA counters */
897 accumulate_uint40(int a_index
,
898 const uint32_t *report0
,
899 const uint32_t *report1
,
900 uint64_t *accumulator
)
902 const uint8_t *high_bytes0
= (uint8_t *)(report0
+ 40);
903 const uint8_t *high_bytes1
= (uint8_t *)(report1
+ 40);
904 uint64_t high0
= (uint64_t)(high_bytes0
[a_index
]) << 32;
905 uint64_t high1
= (uint64_t)(high_bytes1
[a_index
]) << 32;
906 uint64_t value0
= report0
[a_index
+ 4] | high0
;
907 uint64_t value1
= report1
[a_index
+ 4] | high1
;
911 delta
= (1ULL << 40) + value1
- value0
;
913 delta
= value1
- value0
;
915 *accumulator
+= delta
;
919 gen8_read_report_clock_ratios(const uint32_t *report
,
920 uint64_t *slice_freq_hz
,
921 uint64_t *unslice_freq_hz
)
923 /* The lower 16bits of the RPT_ID field of the OA reports contains a
924 * snapshot of the bits coming from the RP_FREQ_NORMAL register and is
927 * RPT_ID[31:25]: RP_FREQ_NORMAL[20:14] (low squashed_slice_clock_frequency)
928 * RPT_ID[10:9]: RP_FREQ_NORMAL[22:21] (high squashed_slice_clock_frequency)
929 * RPT_ID[8:0]: RP_FREQ_NORMAL[31:23] (squashed_unslice_clock_frequency)
931 * RP_FREQ_NORMAL[31:23]: Software Unslice Ratio Request
932 * Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
934 * RP_FREQ_NORMAL[22:14]: Software Slice Ratio Request
935 * Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
938 uint32_t unslice_freq
= report
[0] & 0x1ff;
939 uint32_t slice_freq_low
= (report
[0] >> 25) & 0x7f;
940 uint32_t slice_freq_high
= (report
[0] >> 9) & 0x3;
941 uint32_t slice_freq
= slice_freq_low
| (slice_freq_high
<< 7);
943 *slice_freq_hz
= slice_freq
* 16666667ULL;
944 *unslice_freq_hz
= unslice_freq
* 16666667ULL;
948 gen_perf_query_result_read_frequencies(struct gen_perf_query_result
*result
,
949 const struct gen_device_info
*devinfo
,
950 const uint32_t *start
,
953 /* Slice/Unslice frequency is only available in the OA reports when the
954 * "Disable OA reports due to clock ratio change" field in
955 * OA_DEBUG_REGISTER is set to 1. This is how the kernel programs this
956 * global register (see drivers/gpu/drm/i915/i915_perf.c)
958 * Documentation says this should be available on Gen9+ but experimentation
959 * shows that Gen8 reports similar values, so we enable it there too.
961 if (devinfo
->gen
< 8)
964 gen8_read_report_clock_ratios(start
,
965 &result
->slice_frequency
[0],
966 &result
->unslice_frequency
[0]);
967 gen8_read_report_clock_ratios(end
,
968 &result
->slice_frequency
[1],
969 &result
->unslice_frequency
[1]);
973 gen_perf_query_result_accumulate(struct gen_perf_query_result
*result
,
974 const struct gen_perf_query_info
*query
,
975 const uint32_t *start
,
980 if (result
->hw_id
== OA_REPORT_INVALID_CTX_ID
&&
981 start
[2] != OA_REPORT_INVALID_CTX_ID
)
982 result
->hw_id
= start
[2];
983 if (result
->reports_accumulated
== 0)
984 result
->begin_timestamp
= start
[1];
985 result
->reports_accumulated
++;
987 switch (query
->oa_format
) {
988 case I915_OA_FORMAT_A32u40_A4u32_B8_C8
:
989 accumulate_uint32(start
+ 1, end
+ 1,
990 result
->accumulator
+ query
->gpu_time_offset
); /* timestamp */
991 accumulate_uint32(start
+ 3, end
+ 3,
992 result
->accumulator
+ query
->gpu_clock_offset
); /* clock */
994 /* 32x 40bit A counters... */
995 for (i
= 0; i
< 32; i
++) {
996 accumulate_uint40(i
, start
, end
,
997 result
->accumulator
+ query
->a_offset
+ i
);
1000 /* 4x 32bit A counters... */
1001 for (i
= 0; i
< 4; i
++) {
1002 accumulate_uint32(start
+ 36 + i
, end
+ 36 + i
,
1003 result
->accumulator
+ query
->a_offset
+ 32 + i
);
1006 /* 8x 32bit B counters */
1007 for (i
= 0; i
< 8; i
++) {
1008 accumulate_uint32(start
+ 48 + i
, end
+ 48 + i
,
1009 result
->accumulator
+ query
->b_offset
+ i
);
1012 /* 8x 32bit C counters... */
1013 for (i
= 0; i
< 8; i
++) {
1014 accumulate_uint32(start
+ 56 + i
, end
+ 56 + i
,
1015 result
->accumulator
+ query
->c_offset
+ i
);
1019 case I915_OA_FORMAT_A45_B8_C8
:
1020 accumulate_uint32(start
+ 1, end
+ 1, result
->accumulator
); /* timestamp */
1022 for (i
= 0; i
< 61; i
++) {
1023 accumulate_uint32(start
+ 3 + i
, end
+ 3 + i
,
1024 result
->accumulator
+ query
->a_offset
+ i
);
1029 unreachable("Can't accumulate OA counters in unknown format");
1035 gen_perf_query_result_clear(struct gen_perf_query_result
*result
)
1037 memset(result
, 0, sizeof(*result
));
1038 result
->hw_id
= OA_REPORT_INVALID_CTX_ID
; /* invalid */
1042 gen_perf_init_metrics(struct gen_perf_config
*perf_cfg
,
1043 const struct gen_device_info
*devinfo
,
1045 bool include_pipeline_statistics
)
1047 if (include_pipeline_statistics
) {
1048 load_pipeline_statistic_metrics(perf_cfg
, devinfo
);
1049 gen_perf_register_mdapi_statistic_query(perf_cfg
, devinfo
);
1051 if (load_oa_metrics(perf_cfg
, drm_fd
, devinfo
))
1052 gen_perf_register_mdapi_oa_query(perf_cfg
, devinfo
);