src/intel/perf/gen_perf.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <dirent.h>
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <unistd.h>
  30 #include <errno.h>
  31
  32 #ifndef HAVE_DIRENT_D_TYPE
  33 #include <limits.h> // PATH_MAX
  34 #endif
  35
  36 #include <drm-uapi/i915_drm.h>
  37
  38 #include "common/gen_gem.h"
  39
  40 #include "dev/gen_debug.h"
  41 #include "dev/gen_device_info.h"
  42
  43 #include "perf/gen_perf.h"
  44 #include "perf/gen_perf_regs.h"
  45 #include "perf/gen_perf_mdapi.h"
  46 #include "perf/gen_perf_metrics.h"
  47 #include "perf/gen_perf_private.h"
  48
  49 #include "util/bitscan.h"
  50 #include "util/macros.h"
  51 #include "util/mesa-sha1.h"
  52 #include "util/u_math.h"
  53
  54 #define FILE_DEBUG_FLAG DEBUG_PERFMON
  55
  56 #define OA_REPORT_INVALID_CTX_ID (0xffffffff)
  57
  58 static bool
  59 is_dir_or_link(const struct dirent *entry, const char *parent_dir)
  60 {
  61 #ifdef HAVE_DIRENT_D_TYPE
  62    return entry->d_type == DT_DIR || entry->d_type == DT_LNK;
  63 #else
  64    struct stat st;
  65    char path[PATH_MAX + 1];
  66    snprintf(path, sizeof(path), "%s/%s", parent_dir, entry->d_name);
  67    lstat(path, &st);
  68    return S_ISDIR(st.st_mode) || S_ISLNK(st.st_mode);
  69 #endif
  70 }
  71
  72 static bool
  73 get_sysfs_dev_dir(struct gen_perf_config *perf, int fd)
  74 {
  75    struct stat sb;
  76    int min, maj;
  77    DIR *drmdir;
  78    struct dirent *drm_entry;
  79    int len;
  80
  81    perf->sysfs_dev_dir[0] = '\0';
  82
  83    if (unlikely(INTEL_DEBUG & DEBUG_NO_OACONFIG))
  84       return true;
  85
  86    if (fstat(fd, &sb)) {
  87       DBG("Failed to stat DRM fd\n");
  88       return false;
  89    }
  90
  91    maj = major(sb.st_rdev);
  92    min = minor(sb.st_rdev);
  93
  94    if (!S_ISCHR(sb.st_mode)) {
  95       DBG("DRM fd is not a character device as expected\n");
  96       return false;
  97    }
  98
  99    len = snprintf(perf->sysfs_dev_dir,
 100                   sizeof(perf->sysfs_dev_dir),
 101                   "/sys/dev/char/%d:%d/device/drm", maj, min);
 102    if (len < 0 || len >= sizeof(perf->sysfs_dev_dir)) {
 103       DBG("Failed to concatenate sysfs path to drm device\n");
 104       return false;
 105    }
 106
 107    drmdir = opendir(perf->sysfs_dev_dir);
 108    if (!drmdir) {
 109       DBG("Failed to open %s: %m\n", perf->sysfs_dev_dir);
 110       return false;
 111    }
 112
 113    while ((drm_entry = readdir(drmdir))) {
 114       if (is_dir_or_link(drm_entry, perf->sysfs_dev_dir) &&
 115           strncmp(drm_entry->d_name, "card", 4) == 0)
 116       {
 117          len = snprintf(perf->sysfs_dev_dir,
 118                         sizeof(perf->sysfs_dev_dir),
 119                         "/sys/dev/char/%d:%d/device/drm/%s",
 120                         maj, min, drm_entry->d_name);
 121          closedir(drmdir);
 122          if (len < 0 || len >= sizeof(perf->sysfs_dev_dir))
 123             return false;
 124          else
 125             return true;
 126       }
 127    }
 128
 129    closedir(drmdir);
 130
 131    DBG("Failed to find cardX directory under /sys/dev/char/%d:%d/device/drm\n",
 132        maj, min);
 133
 134    return false;
 135 }
 136
 137 static bool
 138 read_file_uint64(const char *file, uint64_t *val)
 139 {
 140     char buf[32];
 141     int fd, n;
 142
 143     fd = open(file, 0);
 144     if (fd < 0)
 145        return false;
 146     while ((n = read(fd, buf, sizeof (buf) - 1)) < 0 &&
 147            errno == EINTR);
 148     close(fd);
 149     if (n < 0)
 150        return false;
 151
 152     buf[n] = '\0';
 153     *val = strtoull(buf, NULL, 0);
 154
 155     return true;
 156 }
 157
 158 static bool
 159 read_sysfs_drm_device_file_uint64(struct gen_perf_config *perf,
 160                                   const char *file,
 161                                   uint64_t *value)
 162 {
 163    char buf[512];
 164    int len;
 165
 166    len = snprintf(buf, sizeof(buf), "%s/%s", perf->sysfs_dev_dir, file);
 167    if (len < 0 || len >= sizeof(buf)) {
 168       DBG("Failed to concatenate sys filename to read u64 from\n");
 169       return false;
 170    }
 171
 172    return read_file_uint64(buf, value);
 173 }
 174
 175 static void
 176 register_oa_config(struct gen_perf_config *perf,
 177                    const struct gen_device_info *devinfo,
 178                    const struct gen_perf_query_info *query,
 179                    uint64_t config_id)
 180 {
 181    struct gen_perf_query_info *registered_query =
 182       gen_perf_append_query_info(perf, 0);
 183
 184    *registered_query = *query;
 185    registered_query->oa_format = devinfo->gen >= 8 ?
 186       I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_A45_B8_C8;
 187    registered_query->oa_metrics_set_id = config_id;
 188    DBG("metric set registered: id = %" PRIu64", guid = %s\n",
 189        registered_query->oa_metrics_set_id, query->guid);
 190 }
 191
 192 static void
 193 enumerate_sysfs_metrics(struct gen_perf_config *perf,
 194                         const struct gen_device_info *devinfo)
 195 {
 196    DIR *metricsdir = NULL;
 197    struct dirent *metric_entry;
 198    char buf[256];
 199    int len;
 200
 201    len = snprintf(buf, sizeof(buf), "%s/metrics", perf->sysfs_dev_dir);
 202    if (len < 0 || len >= sizeof(buf)) {
 203       DBG("Failed to concatenate path to sysfs metrics/ directory\n");
 204       return;
 205    }
 206
 207    metricsdir = opendir(buf);
 208    if (!metricsdir) {
 209       DBG("Failed to open %s: %m\n", buf);
 210       return;
 211    }
 212
 213    while ((metric_entry = readdir(metricsdir))) {
 214       struct hash_entry *entry;
 215       if (!is_dir_or_link(metric_entry, buf) ||
 216           metric_entry->d_name[0] == '.')
 217          continue;
 218
 219       DBG("metric set: %s\n", metric_entry->d_name);
 220       entry = _mesa_hash_table_search(perf->oa_metrics_table,
 221                                       metric_entry->d_name);
 222       if (entry) {
 223          uint64_t id;
 224          if (!gen_perf_load_metric_id(perf, metric_entry->d_name, &id)) {
 225             DBG("Failed to read metric set id from %s: %m", buf);
 226             continue;
 227          }
 228
 229          register_oa_config(perf, devinfo,
 230                             (const struct gen_perf_query_info *)entry->data, id);
 231       } else
 232          DBG("metric set not known by mesa (skipping)\n");
 233    }
 234
 235    closedir(metricsdir);
 236 }
 237
 238 static void
 239 add_all_metrics(struct gen_perf_config *perf,
 240                 const struct gen_device_info *devinfo)
 241 {
 242    hash_table_foreach(perf->oa_metrics_table, entry) {
 243       const struct gen_perf_query_info *query = entry->data;
 244       register_oa_config(perf, devinfo, query, 0);
 245    }
 246 }
 247
 248 static bool
 249 kernel_has_dynamic_config_support(struct gen_perf_config *perf, int fd)
 250 {
 251    uint64_t invalid_config_id = UINT64_MAX;
 252
 253    return gen_ioctl(fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
 254                     &invalid_config_id) < 0 && errno == ENOENT;
 255 }
 256
 257 static int
 258 i915_query_items(struct gen_perf_config *perf, int fd,
 259                  struct drm_i915_query_item *items, uint32_t n_items)
 260 {
 261    struct drm_i915_query q = {
 262       .num_items = n_items,
 263       .items_ptr = to_user_pointer(items),
 264    };
 265    return gen_ioctl(fd, DRM_IOCTL_I915_QUERY, &q);
 266 }
 267
 268 static bool
 269 i915_query_perf_config_supported(struct gen_perf_config *perf, int fd)
 270 {
 271    struct drm_i915_query_item item = {
 272       .query_id = DRM_I915_QUERY_PERF_CONFIG,
 273       .flags = DRM_I915_QUERY_PERF_CONFIG_LIST,
 274    };
 275
 276    return i915_query_items(perf, fd, &item, 1) == 0 && item.length > 0;
 277 }
 278
 279 static bool
 280 i915_query_perf_config_data(struct gen_perf_config *perf,
 281                             int fd, const char *guid,
 282                             struct drm_i915_perf_oa_config *config)
 283 {
 284    struct {
 285       struct drm_i915_query_perf_config query;
 286       struct drm_i915_perf_oa_config config;
 287    } item_data;
 288    struct drm_i915_query_item item = {
 289       .query_id = DRM_I915_QUERY_PERF_CONFIG,
 290       .flags = DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
 291       .data_ptr = to_user_pointer(&item_data),
 292       .length = sizeof(item_data),
 293    };
 294
 295    memset(&item_data, 0, sizeof(item_data));
 296    memcpy(item_data.query.uuid, guid, sizeof(item_data.query.uuid));
 297    memcpy(&item_data.config, config, sizeof(item_data.config));
 298
 299    if (!(i915_query_items(perf, fd, &item, 1) == 0 && item.length > 0))
 300       return false;
 301
 302    memcpy(config, &item_data.config, sizeof(item_data.config));
 303
 304    return true;
 305 }
 306
 307 bool
 308 gen_perf_load_metric_id(struct gen_perf_config *perf_cfg,
 309                         const char *guid,
 310                         uint64_t *metric_id)
 311 {
 312    char config_path[280];
 313
 314    snprintf(config_path, sizeof(config_path), "%s/metrics/%s/id",
 315             perf_cfg->sysfs_dev_dir, guid);
 316
 317    /* Don't recreate already loaded configs. */
 318    return read_file_uint64(config_path, metric_id);
 319 }
 320
 321 static uint64_t
 322 i915_add_config(struct gen_perf_config *perf, int fd,
 323                 const struct gen_perf_registers *config,
 324                 const char *guid)
 325 {
 326    struct drm_i915_perf_oa_config i915_config = { 0, };
 327
 328    memcpy(i915_config.uuid, guid, sizeof(i915_config.uuid));
 329
 330    i915_config.n_mux_regs = config->n_mux_regs;
 331    i915_config.mux_regs_ptr = to_user_pointer(config->mux_regs);
 332
 333    i915_config.n_boolean_regs = config->n_b_counter_regs;
 334    i915_config.boolean_regs_ptr = to_user_pointer(config->b_counter_regs);
 335
 336    i915_config.n_flex_regs = config->n_flex_regs;
 337    i915_config.flex_regs_ptr = to_user_pointer(config->flex_regs);
 338
 339    int ret = gen_ioctl(fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, &i915_config);
 340    return ret > 0 ? ret : 0;
 341 }
 342
 343 static void
 344 init_oa_configs(struct gen_perf_config *perf, int fd,
 345                 const struct gen_device_info *devinfo)
 346 {
 347    hash_table_foreach(perf->oa_metrics_table, entry) {
 348       const struct gen_perf_query_info *query = entry->data;
 349       uint64_t config_id;
 350
 351       if (gen_perf_load_metric_id(perf, query->guid, &config_id)) {
 352          DBG("metric set: %s (already loaded)\n", query->guid);
 353          register_oa_config(perf, devinfo, query, config_id);
 354          continue;
 355       }
 356
 357       int ret = i915_add_config(perf, fd, &query->config, query->guid);
 358       if (ret < 0) {
 359          DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
 360              query->name, query->guid, strerror(errno));
 361          continue;
 362       }
 363
 364       register_oa_config(perf, devinfo, query, ret);
 365       DBG("metric set: %s (added)\n", query->guid);
 366    }
 367 }
 368
 369 static void
 370 compute_topology_builtins(struct gen_perf_config *perf,
 371                           const struct gen_device_info *devinfo)
 372 {
 373    perf->sys_vars.slice_mask = devinfo->slice_masks;
 374    perf->sys_vars.n_eu_slices = devinfo->num_slices;
 375
 376    for (int i = 0; i < sizeof(devinfo->subslice_masks[i]); i++) {
 377       perf->sys_vars.n_eu_sub_slices +=
 378          __builtin_popcount(devinfo->subslice_masks[i]);
 379    }
 380
 381    for (int i = 0; i < sizeof(devinfo->eu_masks); i++)
 382       perf->sys_vars.n_eus += __builtin_popcount(devinfo->eu_masks[i]);
 383
 384    perf->sys_vars.eu_threads_count = devinfo->num_thread_per_eu;
 385
 386    /* The subslice mask builtin contains bits for all slices. Prior to Gen11
 387     * it had groups of 3bits for each slice, on Gen11 it's 8bits for each
 388     * slice.
 389     *
 390     * Ideally equations would be updated to have a slice/subslice query
 391     * function/operator.
 392     */
 393    perf->sys_vars.subslice_mask = 0;
 394
 395    int bits_per_subslice = devinfo->gen == 11 ? 8 : 3;
 396
 397    for (int s = 0; s < util_last_bit(devinfo->slice_masks); s++) {
 398       for (int ss = 0; ss < (devinfo->subslice_slice_stride * 8); ss++) {
 399          if (gen_device_info_subslice_available(devinfo, s, ss))
 400             perf->sys_vars.subslice_mask |= 1ULL << (s * bits_per_subslice + ss);
 401       }
 402    }
 403 }
 404
 405 static bool
 406 init_oa_sys_vars(struct gen_perf_config *perf, const struct gen_device_info *devinfo)
 407 {
 408    uint64_t min_freq_mhz = 0, max_freq_mhz = 0;
 409
 410    if (likely(!(INTEL_DEBUG & DEBUG_NO_OACONFIG))) {
 411       if (!read_sysfs_drm_device_file_uint64(perf, "gt_min_freq_mhz", &min_freq_mhz))
 412          return false;
 413
 414       if (!read_sysfs_drm_device_file_uint64(perf,  "gt_max_freq_mhz", &max_freq_mhz))
 415          return false;
 416    } else {
 417       min_freq_mhz = 300;
 418       max_freq_mhz = 1000;
 419    }
 420
 421    memset(&perf->sys_vars, 0, sizeof(perf->sys_vars));
 422    perf->sys_vars.gt_min_freq = min_freq_mhz * 1000000;
 423    perf->sys_vars.gt_max_freq = max_freq_mhz * 1000000;
 424    perf->sys_vars.timestamp_frequency = devinfo->timestamp_frequency;
 425    perf->sys_vars.revision = devinfo->revision;
 426    compute_topology_builtins(perf, devinfo);
 427
 428    return true;
 429 }
 430
 431 typedef void (*perf_register_oa_queries_t)(struct gen_perf_config *);
 432
 433 static perf_register_oa_queries_t
 434 get_register_queries_function(const struct gen_device_info *devinfo)
 435 {
 436    if (devinfo->is_haswell)
 437       return gen_oa_register_queries_hsw;
 438    if (devinfo->is_cherryview)
 439       return gen_oa_register_queries_chv;
 440    if (devinfo->is_broadwell)
 441       return gen_oa_register_queries_bdw;
 442    if (devinfo->is_broxton)
 443       return gen_oa_register_queries_bxt;
 444    if (devinfo->is_skylake) {
 445       if (devinfo->gt == 2)
 446          return gen_oa_register_queries_sklgt2;
 447       if (devinfo->gt == 3)
 448          return gen_oa_register_queries_sklgt3;
 449       if (devinfo->gt == 4)
 450          return gen_oa_register_queries_sklgt4;
 451    }
 452    if (devinfo->is_kabylake) {
 453       if (devinfo->gt == 2)
 454          return gen_oa_register_queries_kblgt2;
 455       if (devinfo->gt == 3)
 456          return gen_oa_register_queries_kblgt3;
 457    }
 458    if (devinfo->is_geminilake)
 459       return gen_oa_register_queries_glk;
 460    if (devinfo->is_coffeelake) {
 461       if (devinfo->gt == 2)
 462          return gen_oa_register_queries_cflgt2;
 463       if (devinfo->gt == 3)
 464          return gen_oa_register_queries_cflgt3;
 465    }
 466    if (devinfo->is_cannonlake)
 467       return gen_oa_register_queries_cnl;
 468    if (devinfo->gen == 11) {
 469       if (devinfo->is_elkhartlake)
 470          return gen_oa_register_queries_lkf;
 471       return gen_oa_register_queries_icl;
 472    }
 473    if (devinfo->gen == 12)
 474       return gen_oa_register_queries_tgl;
 475
 476    return NULL;
 477 }
 478
 479 static void
 480 load_pipeline_statistic_metrics(struct gen_perf_config *perf_cfg,
 481                                 const struct gen_device_info *devinfo)
 482 {
 483    struct gen_perf_query_info *query =
 484       gen_perf_append_query_info(perf_cfg, MAX_STAT_COUNTERS);
 485
 486    query->kind = GEN_PERF_QUERY_TYPE_PIPELINE;
 487    query->name = "Pipeline Statistics Registers";
 488
 489    gen_perf_query_add_basic_stat_reg(query, IA_VERTICES_COUNT,
 490                                      "N vertices submitted");
 491    gen_perf_query_add_basic_stat_reg(query, IA_PRIMITIVES_COUNT,
 492                                      "N primitives submitted");
 493    gen_perf_query_add_basic_stat_reg(query, VS_INVOCATION_COUNT,
 494                                      "N vertex shader invocations");
 495
 496    if (devinfo->gen == 6) {
 497       gen_perf_query_add_stat_reg(query, GEN6_SO_PRIM_STORAGE_NEEDED, 1, 1,
 498                                   "SO_PRIM_STORAGE_NEEDED",
 499                                   "N geometry shader stream-out primitives (total)");
 500       gen_perf_query_add_stat_reg(query, GEN6_SO_NUM_PRIMS_WRITTEN, 1, 1,
 501                                   "SO_NUM_PRIMS_WRITTEN",
 502                                   "N geometry shader stream-out primitives (written)");
 503    } else {
 504       gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(0), 1, 1,
 505                                   "SO_PRIM_STORAGE_NEEDED (Stream 0)",
 506                                   "N stream-out (stream 0) primitives (total)");
 507       gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(1), 1, 1,
 508                                   "SO_PRIM_STORAGE_NEEDED (Stream 1)",
 509                                   "N stream-out (stream 1) primitives (total)");
 510       gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(2), 1, 1,
 511                                   "SO_PRIM_STORAGE_NEEDED (Stream 2)",
 512                                   "N stream-out (stream 2) primitives (total)");
 513       gen_perf_query_add_stat_reg(query, GEN7_SO_PRIM_STORAGE_NEEDED(3), 1, 1,
 514                                   "SO_PRIM_STORAGE_NEEDED (Stream 3)",
 515                                   "N stream-out (stream 3) primitives (total)");
 516       gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(0), 1, 1,
 517                                   "SO_NUM_PRIMS_WRITTEN (Stream 0)",
 518                                   "N stream-out (stream 0) primitives (written)");
 519       gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(1), 1, 1,
 520                                   "SO_NUM_PRIMS_WRITTEN (Stream 1)",
 521                                   "N stream-out (stream 1) primitives (written)");
 522       gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(2), 1, 1,
 523                                   "SO_NUM_PRIMS_WRITTEN (Stream 2)",
 524                                   "N stream-out (stream 2) primitives (written)");
 525       gen_perf_query_add_stat_reg(query, GEN7_SO_NUM_PRIMS_WRITTEN(3), 1, 1,
 526                                   "SO_NUM_PRIMS_WRITTEN (Stream 3)",
 527                                   "N stream-out (stream 3) primitives (written)");
 528    }
 529
 530    gen_perf_query_add_basic_stat_reg(query, HS_INVOCATION_COUNT,
 531                                      "N TCS shader invocations");
 532    gen_perf_query_add_basic_stat_reg(query, DS_INVOCATION_COUNT,
 533                                      "N TES shader invocations");
 534
 535    gen_perf_query_add_basic_stat_reg(query, GS_INVOCATION_COUNT,
 536                                      "N geometry shader invocations");
 537    gen_perf_query_add_basic_stat_reg(query, GS_PRIMITIVES_COUNT,
 538                                      "N geometry shader primitives emitted");
 539
 540    gen_perf_query_add_basic_stat_reg(query, CL_INVOCATION_COUNT,
 541                                      "N primitives entering clipping");
 542    gen_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
 543                                      "N primitives leaving clipping");
 544
 545    if (devinfo->is_haswell || devinfo->gen == 8) {
 546       gen_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4,
 547                                   "N fragment shader invocations",
 548                                   "N fragment shader invocations");
 549    } else {
 550       gen_perf_query_add_basic_stat_reg(query, PS_INVOCATION_COUNT,
 551                                         "N fragment shader invocations");
 552    }
 553
 554    gen_perf_query_add_basic_stat_reg(query, PS_DEPTH_COUNT,
 555                                      "N z-pass fragments");
 556
 557    if (devinfo->gen >= 7) {
 558       gen_perf_query_add_basic_stat_reg(query, CS_INVOCATION_COUNT,
 559                                         "N compute shader invocations");
 560    }
 561
 562    query->data_size = sizeof(uint64_t) * query->n_counters;
 563 }
 564
 565 static int
 566 i915_perf_version(int drm_fd)
 567 {
 568    int tmp;
 569    drm_i915_getparam_t gp = {
 570       .param = I915_PARAM_PERF_REVISION,
 571       .value = &tmp,
 572    };
 573
 574    int ret = gen_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
 575
 576    /* Return 0 if this getparam is not supported, the first version supported
 577     * is 1.
 578     */
 579    return ret < 0 ? 0 : tmp;
 580 }
 581
 582 static void
 583 i915_get_sseu(int drm_fd, struct drm_i915_gem_context_param_sseu *sseu)
 584 {
 585    struct drm_i915_gem_context_param arg = {
 586       .param = I915_CONTEXT_PARAM_SSEU,
 587       .size = sizeof(*sseu),
 588       .value = to_user_pointer(sseu)
 589    };
 590
 591    gen_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
 592 }
 593
 594 static int
 595 compare_counters(const void *_c1, const void *_c2)
 596 {
 597    const struct gen_perf_query_counter * const *c1 = _c1, * const *c2 = _c2;
 598    return strcmp((*c1)->symbol_name, (*c2)->symbol_name);
 599 }
 600
 601 static void
 602 build_unique_counter_list(struct gen_perf_config *perf)
 603 {
 604    assert(perf->n_queries < 64);
 605
 606    struct hash_table *counters_table =
 607       _mesa_hash_table_create(perf,
 608                               _mesa_hash_string,
 609                               _mesa_key_string_equal);
 610    struct hash_entry *entry;
 611    for (int q = 0; q < perf->n_queries ; q++) {
 612       struct gen_perf_query_info *query = &perf->queries[q];
 613
 614       for (int c = 0; c < query->n_counters; c++) {
 615          struct gen_perf_query_counter *counter, *unique_counter;
 616
 617          counter = &query->counters[c];
 618          entry = _mesa_hash_table_search(counters_table, counter->symbol_name);
 619
 620          if (entry) {
 621             unique_counter = entry->data;
 622             unique_counter->query_mask |= BITFIELD64_BIT(q);
 623             continue;
 624          }
 625
 626          unique_counter = counter;
 627          unique_counter->query_mask = BITFIELD64_BIT(q);
 628
 629          _mesa_hash_table_insert(counters_table, unique_counter->symbol_name, unique_counter);
 630       }
 631    }
 632
 633    perf->n_counters = _mesa_hash_table_num_entries(counters_table);
 634    perf->counters = ralloc_array(perf, struct gen_perf_query_counter *,
 635                                  perf->n_counters);
 636
 637    int c = 0;
 638    hash_table_foreach(counters_table, entry) {
 639       struct gen_perf_query_counter *counter = entry->data;
 640       perf->counters[c++] = counter;
 641    }
 642
 643    _mesa_hash_table_destroy(counters_table, NULL);
 644
 645    qsort(perf->counters, perf->n_counters, sizeof(perf->counters[0]),
 646          compare_counters);
 647 }
 648
 649 static bool
 650 load_oa_metrics(struct gen_perf_config *perf, int fd,
 651                 const struct gen_device_info *devinfo)
 652 {
 653    perf_register_oa_queries_t oa_register = get_register_queries_function(devinfo);
 654    bool i915_perf_oa_available = false;
 655    struct stat sb;
 656
 657    perf->i915_query_supported = i915_query_perf_config_supported(perf, fd);
 658    perf->i915_perf_version = i915_perf_version(fd);
 659
 660    /* Record the default SSEU configuration. */
 661    i915_get_sseu(fd, &perf->sseu);
 662
 663    /* The existence of this sysctl parameter implies the kernel supports
 664     * the i915 perf interface.
 665     */
 666    if (stat("/proc/sys/dev/i915/perf_stream_paranoid", &sb) == 0) {
 667
 668       /* If _paranoid == 1 then on Gen8+ we won't be able to access OA
 669        * metrics unless running as root.
 670        */
 671       if (devinfo->is_haswell)
 672          i915_perf_oa_available = true;
 673       else {
 674          uint64_t paranoid = 1;
 675
 676          read_file_uint64("/proc/sys/dev/i915/perf_stream_paranoid", &paranoid);
 677
 678          if (paranoid == 0 || geteuid() == 0)
 679             i915_perf_oa_available = true;
 680       }
 681    }
 682
 683    perf->platform_supported = oa_register != NULL;
 684
 685    if (!i915_perf_oa_available ||
 686        !oa_register ||
 687        !get_sysfs_dev_dir(perf, fd) ||
 688        !init_oa_sys_vars(perf, devinfo))
 689       return false;
 690
 691    perf->oa_metrics_table =
 692       _mesa_hash_table_create(perf, _mesa_hash_string,
 693                               _mesa_key_string_equal);
 694
 695    /* Index all the metric sets mesa knows about before looking to see what
 696     * the kernel is advertising.
 697     */
 698    oa_register(perf);
 699
 700    if (likely(!(INTEL_DEBUG & DEBUG_NO_OACONFIG))) {
 701       if (kernel_has_dynamic_config_support(perf, fd))
 702          init_oa_configs(perf, fd, devinfo);
 703       else
 704          enumerate_sysfs_metrics(perf, devinfo);
 705    } else {
 706       add_all_metrics(perf, devinfo);
 707    }
 708
 709    build_unique_counter_list(perf);
 710
 711    return true;
 712 }
 713
 714 struct gen_perf_registers *
 715 gen_perf_load_configuration(struct gen_perf_config *perf_cfg, int fd, const char *guid)
 716 {
 717    if (!perf_cfg->i915_query_supported)
 718       return NULL;
 719
 720    struct drm_i915_perf_oa_config i915_config = { 0, };
 721    if (!i915_query_perf_config_data(perf_cfg, fd, guid, &i915_config))
 722       return NULL;
 723
 724    struct gen_perf_registers *config = rzalloc(NULL, struct gen_perf_registers);
 725    config->n_flex_regs = i915_config.n_flex_regs;
 726    config->flex_regs = rzalloc_array(config, struct gen_perf_query_register_prog, config->n_flex_regs);
 727    config->n_mux_regs = i915_config.n_mux_regs;
 728    config->mux_regs = rzalloc_array(config, struct gen_perf_query_register_prog, config->n_mux_regs);
 729    config->n_b_counter_regs = i915_config.n_boolean_regs;
 730    config->b_counter_regs = rzalloc_array(config, struct gen_perf_query_register_prog, config->n_b_counter_regs);
 731
 732    /*
 733     * struct gen_perf_query_register_prog maps exactly to the tuple of
 734     * (register offset, register value) returned by the i915.
 735     */
 736    i915_config.flex_regs_ptr = to_user_pointer(config->flex_regs);
 737    i915_config.mux_regs_ptr = to_user_pointer(config->mux_regs);
 738    i915_config.boolean_regs_ptr = to_user_pointer(config->b_counter_regs);
 739    if (!i915_query_perf_config_data(perf_cfg, fd, guid, &i915_config)) {
 740       ralloc_free(config);
 741       return NULL;
 742    }
 743
 744    return config;
 745 }
 746
 747 uint64_t
 748 gen_perf_store_configuration(struct gen_perf_config *perf_cfg, int fd,
 749                              const struct gen_perf_registers *config,
 750                              const char *guid)
 751 {
 752    if (guid)
 753       return i915_add_config(perf_cfg, fd, config, guid);
 754
 755    struct mesa_sha1 sha1_ctx;
 756    _mesa_sha1_init(&sha1_ctx);
 757
 758    if (config->flex_regs) {
 759       _mesa_sha1_update(&sha1_ctx, config->flex_regs,
 760                         sizeof(config->flex_regs[0]) *
 761                         config->n_flex_regs);
 762    }
 763    if (config->mux_regs) {
 764       _mesa_sha1_update(&sha1_ctx, config->mux_regs,
 765                         sizeof(config->mux_regs[0]) *
 766                         config->n_mux_regs);
 767    }
 768    if (config->b_counter_regs) {
 769       _mesa_sha1_update(&sha1_ctx, config->b_counter_regs,
 770                         sizeof(config->b_counter_regs[0]) *
 771                         config->n_b_counter_regs);
 772    }
 773
 774    uint8_t hash[20];
 775    _mesa_sha1_final(&sha1_ctx, hash);
 776
 777    char formatted_hash[41];
 778    _mesa_sha1_format(formatted_hash, hash);
 779
 780    char generated_guid[37];
 781    snprintf(generated_guid, sizeof(generated_guid),
 782             "%.8s-%.4s-%.4s-%.4s-%.12s",
 783             &formatted_hash[0], &formatted_hash[8],
 784             &formatted_hash[8 + 4], &formatted_hash[8 + 4 + 4],
 785             &formatted_hash[8 + 4 + 4 + 4]);
 786
 787    /* Check if already present. */
 788    uint64_t id;
 789    if (gen_perf_load_metric_id(perf_cfg, generated_guid, &id))
 790       return id;
 791
 792    return i915_add_config(perf_cfg, fd, config, generated_guid);
 793 }
 794
 795 static uint64_t
 796 get_passes_mask(struct gen_perf_config *perf,
 797                 const uint32_t *counter_indices,
 798                 uint32_t counter_indices_count)
 799 {
 800    uint64_t queries_mask = 0;
 801
 802    assert(perf->n_queries < 64);
 803
 804    /* Compute the number of passes by going through all counters N times (with
 805     * N the number of queries) to make sure we select the most constraining
 806     * counters first and look at the more flexible ones (that could be
 807     * obtained from multiple queries) later. That way we minimize the number
 808     * of passes required.
 809     */
 810    for (uint32_t q = 0; q < perf->n_queries; q++) {
 811       for (uint32_t i = 0; i < counter_indices_count; i++) {
 812          assert(counter_indices[i] < perf->n_counters);
 813
 814          uint32_t idx = counter_indices[i];
 815          if (__builtin_popcount(perf->counters[idx]->query_mask) != (q + 1))
 816             continue;
 817
 818          if (queries_mask & perf->counters[idx]->query_mask)
 819             continue;
 820
 821          queries_mask |= BITFIELD64_BIT(ffsll(perf->counters[idx]->query_mask) - 1);
 822       }
 823    }
 824
 825    return queries_mask;
 826 }
 827
 828 uint32_t
 829 gen_perf_get_n_passes(struct gen_perf_config *perf,
 830                       const uint32_t *counter_indices,
 831                       uint32_t counter_indices_count,
 832                       struct gen_perf_query_info **pass_queries)
 833 {
 834    uint64_t queries_mask = get_passes_mask(perf, counter_indices, counter_indices_count);
 835
 836    if (pass_queries) {
 837       uint32_t pass = 0;
 838       for (uint32_t q = 0; q < perf->n_queries; q++) {
 839          if ((1ULL << q) & queries_mask)
 840             pass_queries[pass++] = &perf->queries[q];
 841       }
 842    }
 843
 844    return __builtin_popcount(queries_mask);
 845 }
 846
 847 void
 848 gen_perf_get_counters_passes(struct gen_perf_config *perf,
 849                              const uint32_t *counter_indices,
 850                              uint32_t counter_indices_count,
 851                              struct gen_perf_counter_pass *counter_pass)
 852 {
 853    uint64_t queries_mask = get_passes_mask(perf, counter_indices, counter_indices_count);
 854    uint32_t n_passes = __builtin_popcount(queries_mask);
 855
 856    for (uint32_t i = 0; i < counter_indices_count; i++) {
 857       assert(counter_indices[i] < perf->n_counters);
 858
 859       uint32_t idx = counter_indices[i];
 860       counter_pass[i].counter = perf->counters[idx];
 861
 862       uint32_t query_idx = ffsll(perf->counters[idx]->query_mask & queries_mask) - 1;
 863       counter_pass[i].query = &perf->queries[query_idx];
 864
 865       uint32_t clear_bits = 63 - query_idx;
 866       counter_pass[i].pass = __builtin_popcount((queries_mask << clear_bits) >> clear_bits) - 1;
 867       assert(counter_pass[i].pass < n_passes);
 868    }
 869 }
 870
 871 /* Accumulate 32bits OA counters */
 872 static inline void
 873 accumulate_uint32(const uint32_t *report0,
 874                   const uint32_t *report1,
 875                   uint64_t *accumulator)
 876 {
 877    *accumulator += (uint32_t)(*report1 - *report0);
 878 }
 879
 880 /* Accumulate 40bits OA counters */
 881 static inline void
 882 accumulate_uint40(int a_index,
 883                   const uint32_t *report0,
 884                   const uint32_t *report1,
 885                   uint64_t *accumulator)
 886 {
 887    const uint8_t *high_bytes0 = (uint8_t *)(report0 + 40);
 888    const uint8_t *high_bytes1 = (uint8_t *)(report1 + 40);
 889    uint64_t high0 = (uint64_t)(high_bytes0[a_index]) << 32;
 890    uint64_t high1 = (uint64_t)(high_bytes1[a_index]) << 32;
 891    uint64_t value0 = report0[a_index + 4] | high0;
 892    uint64_t value1 = report1[a_index + 4] | high1;
 893    uint64_t delta;
 894
 895    if (value0 > value1)
 896       delta = (1ULL << 40) + value1 - value0;
 897    else
 898       delta = value1 - value0;
 899
 900    *accumulator += delta;
 901 }
 902
 903 static void
 904 gen8_read_report_clock_ratios(const uint32_t *report,
 905                               uint64_t *slice_freq_hz,
 906                               uint64_t *unslice_freq_hz)
 907 {
 908    /* The lower 16bits of the RPT_ID field of the OA reports contains a
 909     * snapshot of the bits coming from the RP_FREQ_NORMAL register and is
 910     * divided this way :
 911     *
 912     * RPT_ID[31:25]: RP_FREQ_NORMAL[20:14] (low squashed_slice_clock_frequency)
 913     * RPT_ID[10:9]:  RP_FREQ_NORMAL[22:21] (high squashed_slice_clock_frequency)
 914     * RPT_ID[8:0]:   RP_FREQ_NORMAL[31:23] (squashed_unslice_clock_frequency)
 915     *
 916     * RP_FREQ_NORMAL[31:23]: Software Unslice Ratio Request
 917     *                        Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
 918     *
 919     * RP_FREQ_NORMAL[22:14]: Software Slice Ratio Request
 920     *                        Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
 921     */
 922
 923    uint32_t unslice_freq = report[0] & 0x1ff;
 924    uint32_t slice_freq_low = (report[0] >> 25) & 0x7f;
 925    uint32_t slice_freq_high = (report[0] >> 9) & 0x3;
 926    uint32_t slice_freq = slice_freq_low | (slice_freq_high << 7);
 927
 928    *slice_freq_hz = slice_freq * 16666667ULL;
 929    *unslice_freq_hz = unslice_freq * 16666667ULL;
 930 }
 931
 932 void
 933 gen_perf_query_result_read_frequencies(struct gen_perf_query_result *result,
 934                                        const struct gen_device_info *devinfo,
 935                                        const uint32_t *start,
 936                                        const uint32_t *end)
 937 {
 938    /* Slice/Unslice frequency is only available in the OA reports when the
 939     * "Disable OA reports due to clock ratio change" field in
 940     * OA_DEBUG_REGISTER is set to 1. This is how the kernel programs this
 941     * global register (see drivers/gpu/drm/i915/i915_perf.c)
 942     *
 943     * Documentation says this should be available on Gen9+ but experimentation
 944     * shows that Gen8 reports similar values, so we enable it there too.
 945     */
 946    if (devinfo->gen < 8)
 947       return;
 948
 949    gen8_read_report_clock_ratios(start,
 950                                  &result->slice_frequency[0],
 951                                  &result->unslice_frequency[0]);
 952    gen8_read_report_clock_ratios(end,
 953                                  &result->slice_frequency[1],
 954                                  &result->unslice_frequency[1]);
 955 }
 956
 957 void
 958 gen_perf_query_result_accumulate(struct gen_perf_query_result *result,
 959                                  const struct gen_perf_query_info *query,
 960                                  const uint32_t *start,
 961                                  const uint32_t *end)
 962 {
 963    int i;
 964
 965    if (result->hw_id == OA_REPORT_INVALID_CTX_ID &&
 966        start[2] != OA_REPORT_INVALID_CTX_ID)
 967       result->hw_id = start[2];
 968    if (result->reports_accumulated == 0)
 969       result->begin_timestamp = start[1];
 970    result->reports_accumulated++;
 971
 972    switch (query->oa_format) {
 973    case I915_OA_FORMAT_A32u40_A4u32_B8_C8:
 974       accumulate_uint32(start + 1, end + 1,
 975                         result->accumulator + query->gpu_time_offset); /* timestamp */
 976       accumulate_uint32(start + 3, end + 3,
 977                         result->accumulator + query->gpu_clock_offset); /* clock */
 978
 979       /* 32x 40bit A counters... */
 980       for (i = 0; i < 32; i++) {
 981          accumulate_uint40(i, start, end,
 982                            result->accumulator + query->a_offset + i);
 983       }
 984
 985       /* 4x 32bit A counters... */
 986       for (i = 0; i < 4; i++) {
 987          accumulate_uint32(start + 36 + i, end + 36 + i,
 988                            result->accumulator + query->a_offset + 32 + i);
 989       }
 990
 991       /* 8x 32bit B counters */
 992       for (i = 0; i < 8; i++) {
 993          accumulate_uint32(start + 48 + i, end + 48 + i,
 994                            result->accumulator + query->b_offset + i);
 995       }
 996
 997       /* 8x 32bit C counters... */
 998       for (i = 0; i < 8; i++) {
 999          accumulate_uint32(start + 56 + i, end + 56 + i,
1000                            result->accumulator + query->c_offset + i);
1001       }
1002       break;
1003
1004    case I915_OA_FORMAT_A45_B8_C8:
1005       accumulate_uint32(start + 1, end + 1, result->accumulator); /* timestamp */
1006
1007       for (i = 0; i < 61; i++) {
1008          accumulate_uint32(start + 3 + i, end + 3 + i,
1009                            result->accumulator + query->a_offset + i);
1010       }
1011       break;
1012
1013    default:
1014       unreachable("Can't accumulate OA counters in unknown format");
1015    }
1016
1017 }
1018
1019 void
1020 gen_perf_query_result_clear(struct gen_perf_query_result *result)
1021 {
1022    memset(result, 0, sizeof(*result));
1023    result->hw_id = OA_REPORT_INVALID_CTX_ID; /* invalid */
1024 }
1025
1026 void
1027 gen_perf_init_metrics(struct gen_perf_config *perf_cfg,
1028                       const struct gen_device_info *devinfo,
1029                       int drm_fd,
1030                       bool include_pipeline_statistics)
1031 {
1032    if (include_pipeline_statistics) {
1033       load_pipeline_statistic_metrics(perf_cfg, devinfo);
1034       gen_perf_register_mdapi_statistic_query(perf_cfg, devinfo);
1035    }
1036    if (load_oa_metrics(perf_cfg, drm_fd, devinfo))
1037       gen_perf_register_mdapi_oa_query(perf_cfg, devinfo);
1038 }