intel/dump_gpu: add an option to capture a single frame
[mesa.git] / src / intel / perf / gen_perf_regs.h
1 /*
2 * Copyright © 2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef GEN_PERF_REGS_H
25 #define GEN_PERF_REGS_H
26
27 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
28
29 /* GT core frequency counters */
30 #define GEN7_RPSTAT1 0xA01C
31 #define GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
32 #define GEN7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
33 #define GEN7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
34 #define GEN7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
35
36 #define GEN9_RPSTAT0 0xA01C
37 #define GEN9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
38 #define GEN9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
39 #define GEN9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
40 #define GEN9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
41
42 /* Pipeline statistic counters */
43 #define IA_VERTICES_COUNT 0x2310
44 #define IA_PRIMITIVES_COUNT 0x2318
45 #define VS_INVOCATION_COUNT 0x2320
46 #define HS_INVOCATION_COUNT 0x2300
47 #define DS_INVOCATION_COUNT 0x2308
48 #define GS_INVOCATION_COUNT 0x2328
49 #define GS_PRIMITIVES_COUNT 0x2330
50 #define CL_INVOCATION_COUNT 0x2338
51 #define CL_PRIMITIVES_COUNT 0x2340
52 #define PS_INVOCATION_COUNT 0x2348
53 #define CS_INVOCATION_COUNT 0x2290
54 #define PS_DEPTH_COUNT 0x2350
55
56 /* Stream-out counters */
57 #define GEN6_SO_PRIM_STORAGE_NEEDED 0x2280
58 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
59 #define GEN6_SO_NUM_PRIMS_WRITTEN 0x2288
60 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
61
62 #endif /* GEN_PERF_REGS_H */