3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
322 unsigned long long int llint;
324 enum brw_reg_type reg_type;
325 struct brw_codegen *program;
326 struct predicate predicate;
327 struct condition condition;
328 struct options options;
329 brw_inst *instruction;
339 %token LSQUARE RSQUARE
344 %token <integer> TYPE_B TYPE_UB
345 %token <integer> TYPE_W TYPE_UW
346 %token <integer> TYPE_D TYPE_UD
347 %token <integer> TYPE_Q TYPE_UQ
348 %token <integer> TYPE_V TYPE_UV
349 %token <integer> TYPE_F TYPE_HF
350 %token <integer> TYPE_DF TYPE_NF
351 %token <integer> TYPE_VF
354 %token <integer> ADD ADD3 ADDC AND ASR AVG
355 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
356 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
357 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
358 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
359 %token <integer> GOTO
360 %token <integer> HALT
361 %token <integer> IF IFF ILLEGAL
362 %token <integer> JMPI JOIN
363 %token <integer> LINE LRP LZD
364 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
365 %token <integer> NENOP NOP NOT
367 %token <integer> PLN POP PUSH
368 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
369 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
370 %token <integer> WAIT WHILE
373 /* extended math functions */
374 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
375 %token <integer> RSQRTM SIN SINCOS SQRT
377 /* shared functions for send */
378 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
379 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
381 /* Conditional modifiers */
382 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
383 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
385 /* register Access Modes */
386 %token ALIGN1 ALIGN16
388 /* accumulator write control */
391 /* compaction control */
394 /* compression control */
395 %token COMPR COMPR4 SECHALF
397 /* mask control (WeCtrl) */
403 /* dependency control */
404 %token NODDCLR NODDCHK
412 /* predicate control */
413 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
414 %token <integer> ANY32H ALL32H
416 /* round instructions */
417 %token <integer> ROUND_INCREMENT
426 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
427 %token QTR_6N QTR_7N QTR_8N
430 %token <integer> X Y Z W
433 %token GENREGFILE MSGREGFILE
435 /* vertical stride in register region */
439 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
440 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
441 %token <integer> MASKREG
443 %token <integer> INTEGER
447 %precedence SUBREGNUM
450 %precedence EMPTYEXECSIZE
453 %type <integer> execsize simple_int exp
456 /* predicate control */
457 %type <integer> predctrl predstate
458 %type <predicate> predicate
460 /* conditional modifier */
461 %type <condition> cond_mod
462 %type <integer> condModifiers
464 /* instruction options */
465 %type <options> instoptions instoption_list
466 %type <integer> instoption
469 %type <integer> writemask_x writemask_y writemask_z writemask_w
470 %type <integer> writemask
473 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
474 %type <integer> dstregion
476 %type <integer> saturate relativelocation rellocation
477 %type <reg> relativelocation2
480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
482 %type <reg> indirectgenreg indirectregion
483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
484 %type <reg> region_wh directgenreg directmsgreg indirectmsgreg
485 %type <integer> swizzle
488 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
489 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
490 %type <integer> subregnum
493 %type <reg_type> reg_type imm_type
495 /* immediate values */
498 /* instruction opcodes */
499 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
500 %type <integer> sendop
501 %type <instruction> sendopcode
503 %type <integer> negate abs chansel math_function sharedfunction
508 add_instruction_option(struct options *options, int option)
512 options->access_mode = BRW_ALIGN_1;
515 options->access_mode = BRW_ALIGN_16;
518 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
521 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
522 options->is_compr = true;
525 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
528 options->thread_control |= BRW_THREAD_SWITCH;
531 options->thread_control |= BRW_THREAD_ATOMIC;
534 options->no_dd_check = true;
537 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
540 options->mask_control |= BRW_MASK_DISABLE;
543 options->debug_control = BRW_DEBUG_BREAKPOINT;
546 options->mask_control |= BRW_WE_ALL;
549 options->compaction = true;
552 options->acc_wr_control = true;
555 options->end_of_thread = true;
557 /* TODO : Figure out how to set instruction group and get rid of
561 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
564 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
567 options->qtr_ctrl = 3;
570 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
573 options->qtr_ctrl = BRW_COMPRESSION_NONE;
574 options->nib_ctrl = true;
577 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
580 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
581 options->nib_ctrl = true;
584 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
587 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
588 options->nib_ctrl = true;
591 options->qtr_ctrl = 3;
594 options->qtr_ctrl = 3;
595 options->nib_ctrl = true;
607 instrseq instruction SEMICOLON
608 | instrseq relocatableinstruction SEMICOLON
609 | instruction SEMICOLON
610 | relocatableinstruction SEMICOLON
613 /* Instruction Group */
617 | binaryaccinstruction
626 relocatableinstruction:
634 ILLEGAL execsize instoptions
636 brw_next_insn(p, $1);
637 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
638 i965_asm_set_instruction_options(p, $3);
642 /* Unary instruction */
644 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
646 i965_asm_set_dst_nr(p, &$6, $8);
647 brw_set_default_access_mode(p, $8.access_mode);
648 i965_asm_unary_instruction($2, p, $6, $7);
649 brw_pop_insn_state(p);
650 i965_asm_set_instruction_options(p, $8);
651 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
654 if (p->devinfo->gen >= 7) {
655 if ($2 != BRW_OPCODE_DIM) {
656 brw_inst_set_flag_reg_nr(p->devinfo,
659 brw_inst_set_flag_subreg_nr(p->devinfo,
665 if ($7.file != BRW_IMMEDIATE_VALUE) {
666 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
669 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
670 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
671 // TODO: set instruction group instead of qtr and nib ctrl
672 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
675 if (p->devinfo->gen >= 7)
676 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
699 /* Binary instruction */
701 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
703 i965_asm_set_dst_nr(p, &$6, $9);
704 brw_set_default_access_mode(p, $9.access_mode);
705 i965_asm_binary_instruction($2, p, $6, $7, $8);
706 i965_asm_set_instruction_options(p, $9);
707 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
710 if (p->devinfo->gen >= 7) {
711 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
713 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
717 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
718 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
719 // TODO: set instruction group instead of qtr and nib ctrl
720 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
723 if (p->devinfo->gen >= 7)
724 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
727 brw_pop_insn_state(p);
750 /* Binary acc instruction */
751 binaryaccinstruction:
752 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
754 i965_asm_set_dst_nr(p, &$6, $9);
755 brw_set_default_access_mode(p, $9.access_mode);
756 i965_asm_binary_instruction($2, p, $6, $7, $8);
757 brw_pop_insn_state(p);
758 i965_asm_set_instruction_options(p, $9);
759 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
762 if (p->devinfo->gen >= 7) {
763 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
764 brw_inst_set_flag_reg_nr(p->devinfo,
767 brw_inst_set_flag_subreg_nr(p->devinfo,
773 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
774 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
775 // TODO: set instruction group instead of qtr and nib ctrl
776 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
779 if (p->devinfo->gen >= 7)
780 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
799 /* Math instruction */
801 predicate MATH saturate math_function execsize dst src srcimm instoptions
803 brw_set_default_access_mode(p, $9.access_mode);
804 gen6_math(p, $6, $4, $7, $8);
805 i965_asm_set_instruction_options(p, $9);
806 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
807 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
808 // TODO: set instruction group instead
809 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
812 if (p->devinfo->gen >= 7)
813 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
816 brw_pop_insn_state(p);
838 /* NOP instruction */
846 /* Ternary operand instruction */
848 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
850 brw_set_default_access_mode(p, $10.access_mode);
851 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
852 brw_pop_insn_state(p);
853 i965_asm_set_instruction_options(p, $10);
854 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
857 if (p->devinfo->gen >= 7) {
858 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
860 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
864 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
865 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
866 // TODO: set instruction group instead of qtr and nib ctrl
867 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
870 if (p->devinfo->gen >= 7)
871 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
884 /* Sync instruction */
886 WAIT execsize src instoptions
888 brw_next_insn(p, $1);
889 i965_asm_set_instruction_options(p, $4);
890 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
891 brw_set_default_access_mode(p, $4.access_mode);
892 struct brw_reg src = brw_notification_reg();
893 brw_set_dest(p, brw_last_inst, src);
894 brw_set_src0(p, brw_last_inst, src);
895 brw_set_src1(p, brw_last_inst, brw_null_reg());
896 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
900 /* Send instruction */
902 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
904 i965_asm_set_instruction_options(p, $8);
905 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
906 brw_set_dest(p, brw_last_inst, $4);
907 brw_set_src0(p, brw_last_inst, $5);
908 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
909 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
911 BRW_REGISTER_TYPE_UD);
912 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
913 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
914 // TODO: set instruction group instead of qtr and nib ctrl
915 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
918 if (p->devinfo->gen >= 7)
919 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
922 brw_pop_insn_state(p);
924 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
926 i965_asm_set_instruction_options(p, $9);
927 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
928 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
929 brw_set_dest(p, brw_last_inst, $5);
930 brw_set_src0(p, brw_last_inst, $6);
931 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
932 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
934 BRW_REGISTER_TYPE_UD);
935 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
936 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
937 // TODO: set instruction group instead of qtr and nib ctrl
938 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
941 if (p->devinfo->gen >= 7)
942 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
945 brw_pop_insn_state(p);
947 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
949 i965_asm_set_instruction_options(p, $9);
950 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
951 brw_set_dest(p, brw_last_inst, $4);
952 brw_set_src0(p, brw_last_inst, $5);
953 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
954 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
955 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
956 // TODO: set instruction group instead of qtr and nib ctrl
957 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
960 if (p->devinfo->gen >= 7)
961 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
964 brw_pop_insn_state(p);
966 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
968 brw_next_insn(p, $2);
969 i965_asm_set_instruction_options(p, $10);
970 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
971 brw_set_dest(p, brw_last_inst, $4);
972 brw_set_src0(p, brw_last_inst, $5);
973 brw_set_src1(p, brw_last_inst, $6);
975 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
976 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
978 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
981 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
982 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
983 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
984 // TODO: set instruction group instead of qtr and nib ctrl
985 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
988 if (p->devinfo->gen >= 7)
989 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
992 brw_pop_insn_state(p);
994 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
996 brw_next_insn(p, $2);
997 i965_asm_set_instruction_options(p, $10);
998 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
999 brw_set_dest(p, brw_last_inst, $4);
1000 brw_set_src0(p, brw_last_inst, $5);
1001 brw_set_src1(p, brw_last_inst, $6);
1003 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1004 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1006 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1007 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1008 // TODO: set instruction group instead of qtr and nib ctrl
1009 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1012 if (p->devinfo->gen >= 7)
1013 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1016 brw_pop_insn_state(p);
1026 sendop { $$ = brw_next_insn(p, $1); }
1030 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1031 | MATH { $$ = BRW_SFID_MATH; }
1032 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1033 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1034 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1035 | URB { $$ = BRW_SFID_URB; }
1036 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1037 | VME { $$ = BRW_SFID_VME; }
1038 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1039 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1040 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1041 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1042 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1043 | CRE { $$ = HSW_SFID_CRE; }
1044 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1045 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1050 | MINUS LONG { $$ = -$2; }
1053 /* Jump instruction */
1055 predicate JMPI execsize relativelocation2 instoptions
1057 brw_next_insn(p, $2);
1058 i965_asm_set_instruction_options(p, $5);
1059 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1060 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1061 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1062 brw_set_src1(p, brw_last_inst, $4);
1063 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1064 brw_inst_pred_control(p->devinfo,
1066 brw_pop_insn_state(p);
1070 /* branch instruction */
1072 predicate ENDIF execsize relativelocation instoptions
1074 brw_next_insn(p, $2);
1075 i965_asm_set_instruction_options(p, $5);
1076 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1078 if (p->devinfo->gen < 6) {
1079 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1080 BRW_REGISTER_TYPE_D));
1081 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1082 BRW_REGISTER_TYPE_D));
1083 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1084 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1086 } else if (p->devinfo->gen == 6) {
1087 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1088 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1090 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1091 BRW_REGISTER_TYPE_D));
1092 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1093 BRW_REGISTER_TYPE_D));
1094 } else if (p->devinfo->gen == 7) {
1095 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1096 BRW_REGISTER_TYPE_D));
1097 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1098 BRW_REGISTER_TYPE_D));
1099 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1100 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1102 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1105 if (p->devinfo->gen < 6)
1106 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1108 brw_pop_insn_state(p);
1110 | ELSE execsize relativelocation rellocation instoptions
1112 brw_next_insn(p, $1);
1113 i965_asm_set_instruction_options(p, $5);
1114 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1116 if (p->devinfo->gen < 6) {
1117 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1118 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1119 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1120 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1122 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1124 } else if (p->devinfo->gen == 6) {
1125 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1126 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1128 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1129 BRW_REGISTER_TYPE_D));
1130 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1131 BRW_REGISTER_TYPE_D));
1132 } else if (p->devinfo->gen == 7) {
1133 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1134 BRW_REGISTER_TYPE_D));
1135 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1136 BRW_REGISTER_TYPE_D));
1137 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1138 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1139 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1141 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1142 BRW_REGISTER_TYPE_D));
1143 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1144 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1145 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1148 if (!p->single_program_flow && p->devinfo->gen < 6)
1149 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1152 | predicate IF execsize relativelocation rellocation instoptions
1154 brw_next_insn(p, $2);
1155 i965_asm_set_instruction_options(p, $6);
1156 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1158 if (p->devinfo->gen < 6) {
1159 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1160 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1161 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1162 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1164 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1166 } else if (p->devinfo->gen == 6) {
1167 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1168 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1170 brw_set_src0(p, brw_last_inst,
1171 vec1(retype(brw_null_reg(),
1172 BRW_REGISTER_TYPE_D)));
1173 brw_set_src1(p, brw_last_inst,
1174 vec1(retype(brw_null_reg(),
1175 BRW_REGISTER_TYPE_D)));
1176 } else if (p->devinfo->gen == 7) {
1177 brw_set_dest(p, brw_last_inst,
1178 vec1(retype(brw_null_reg(),
1179 BRW_REGISTER_TYPE_D)));
1180 brw_set_src0(p, brw_last_inst,
1181 vec1(retype(brw_null_reg(),
1182 BRW_REGISTER_TYPE_D)));
1183 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1184 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1185 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1187 brw_set_dest(p, brw_last_inst,
1188 vec1(retype(brw_null_reg(),
1189 BRW_REGISTER_TYPE_D)));
1190 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1191 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1192 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1195 if (!p->single_program_flow && p->devinfo->gen < 6)
1196 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1199 brw_pop_insn_state(p);
1201 | predicate IFF execsize relativelocation instoptions
1203 brw_next_insn(p, $2);
1204 i965_asm_set_instruction_options(p, $5);
1205 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1207 if (p->devinfo->gen < 6) {
1208 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1209 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1210 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1212 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1213 } else if (p->devinfo->gen == 6) {
1214 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1215 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1217 brw_set_src0(p, brw_last_inst,
1218 vec1(retype(brw_null_reg(),
1219 BRW_REGISTER_TYPE_D)));
1220 brw_set_src1(p, brw_last_inst,
1221 vec1(retype(brw_null_reg(),
1222 BRW_REGISTER_TYPE_D)));
1223 } else if (p->devinfo->gen == 7) {
1224 brw_set_dest(p, brw_last_inst,
1225 vec1(retype(brw_null_reg(),
1226 BRW_REGISTER_TYPE_D)));
1227 brw_set_src0(p, brw_last_inst,
1228 vec1(retype(brw_null_reg(),
1229 BRW_REGISTER_TYPE_D)));
1230 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1231 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1233 brw_set_dest(p, brw_last_inst,
1234 vec1(retype(brw_null_reg(),
1235 BRW_REGISTER_TYPE_D)));
1236 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1237 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1240 if (!p->single_program_flow && p->devinfo->gen < 6)
1241 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1244 brw_pop_insn_state(p);
1248 /* break instruction */
1250 predicate BREAK execsize relativelocation relativelocation instoptions
1252 brw_next_insn(p, $2);
1253 i965_asm_set_instruction_options(p, $6);
1254 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1256 if (p->devinfo->gen >= 8) {
1257 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1258 BRW_REGISTER_TYPE_D));
1259 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1260 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1261 } else if (p->devinfo->gen >= 6) {
1262 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1263 BRW_REGISTER_TYPE_D));
1264 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1265 BRW_REGISTER_TYPE_D));
1266 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1267 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1268 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1270 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1271 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1272 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1273 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1275 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1279 brw_pop_insn_state(p);
1281 | predicate HALT execsize relativelocation relativelocation instoptions
1283 brw_next_insn(p, $2);
1284 i965_asm_set_instruction_options(p, $6);
1285 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1286 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1287 BRW_REGISTER_TYPE_D));
1289 if (p->devinfo->gen >= 8) {
1290 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1291 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1293 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1294 BRW_REGISTER_TYPE_D));
1295 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1298 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1299 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1300 brw_pop_insn_state(p);
1302 | predicate CONT execsize relativelocation relativelocation instoptions
1304 brw_next_insn(p, $2);
1305 i965_asm_set_instruction_options(p, $6);
1306 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1307 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1309 if (p->devinfo->gen >= 8) {
1310 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1311 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1312 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1314 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1315 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1316 if (p->devinfo->gen >= 6) {
1317 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1318 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1320 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1322 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1327 brw_pop_insn_state(p);
1331 /* loop instruction */
1333 predicate WHILE execsize relativelocation instoptions
1335 brw_next_insn(p, $2);
1336 i965_asm_set_instruction_options(p, $5);
1337 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1339 if (p->devinfo->gen >= 6) {
1340 if (p->devinfo->gen >= 8) {
1341 brw_set_dest(p, brw_last_inst,
1342 retype(brw_null_reg(),
1343 BRW_REGISTER_TYPE_D));
1344 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1345 } else if (p->devinfo->gen == 7) {
1346 brw_set_dest(p, brw_last_inst,
1347 retype(brw_null_reg(),
1348 BRW_REGISTER_TYPE_D));
1349 brw_set_src0(p, brw_last_inst,
1350 retype(brw_null_reg(),
1351 BRW_REGISTER_TYPE_D));
1352 brw_set_src1(p, brw_last_inst,
1354 brw_inst_set_jip(p->devinfo, brw_last_inst,
1357 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1358 brw_inst_set_gen6_jump_count(p->devinfo,
1361 brw_set_src0(p, brw_last_inst,
1362 retype(brw_null_reg(),
1363 BRW_REGISTER_TYPE_D));
1364 brw_set_src1(p, brw_last_inst,
1365 retype(brw_null_reg(),
1366 BRW_REGISTER_TYPE_D));
1369 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1370 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1371 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1372 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1374 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1377 brw_pop_insn_state(p);
1379 | DO execsize instoptions
1381 brw_next_insn(p, $1);
1382 if (p->devinfo->gen < 6) {
1383 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1384 i965_asm_set_instruction_options(p, $3);
1385 brw_set_dest(p, brw_last_inst, brw_null_reg());
1386 brw_set_src0(p, brw_last_inst, brw_null_reg());
1387 brw_set_src1(p, brw_last_inst, brw_null_reg());
1389 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1394 /* Relative location */
1401 INTEGER { $$ = $1; }
1402 | MINUS INTEGER { $$ = -$2; }
1404 | MINUS LONG { $$ = -$2; }
1409 | %empty { $$ = 0; }
1419 /* Destination register */
1426 dstreg dstregion writemask reg_type
1429 $$.vstride = BRW_VERTICAL_STRIDE_1;
1430 $$.width = BRW_WIDTH_1;
1434 $$.swizzle = BRW_SWIZZLE_NOOP;
1435 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1440 dstoperandex_typed dstregion writemask reg_type
1446 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1448 /* BSpec says "When the conditional modifier is present, updates
1449 * to the selected flag register also occur. In this case, the
1450 * register region fields of the ‘null’ operand are valid."
1452 | nullreg dstregion writemask reg_type
1455 $$.vstride = BRW_VERTICAL_STRIDE_1;
1456 $$.width = BRW_WIDTH_1;
1465 $$.type = BRW_REGISTER_TYPE_UW;
1485 $$.address_mode = BRW_ADDRESS_DIRECT;
1490 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1495 $$.address_mode = BRW_ADDRESS_DIRECT;
1500 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1504 /* Source register */
1514 case BRW_REGISTER_TYPE_UD:
1515 $$ = brw_imm_ud($1);
1517 case BRW_REGISTER_TYPE_D:
1520 case BRW_REGISTER_TYPE_UW:
1521 $$ = brw_imm_uw($1 | ($1 << 16));
1523 case BRW_REGISTER_TYPE_W:
1526 case BRW_REGISTER_TYPE_F:
1527 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1528 /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1531 case BRW_REGISTER_TYPE_V:
1534 case BRW_REGISTER_TYPE_UV:
1535 $$ = brw_imm_uv($1);
1537 case BRW_REGISTER_TYPE_VF:
1538 $$ = brw_imm_vf($1);
1540 case BRW_REGISTER_TYPE_Q:
1543 case BRW_REGISTER_TYPE_UQ:
1544 $$ = brw_imm_uq($1);
1546 case BRW_REGISTER_TYPE_DF:
1547 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1551 error(&@2, "Unknown immediate type %s\n",
1552 brw_reg_type_to_letters($2));
1558 directgenreg region reg_type
1560 $$ = set_direct_src_operand(&$1, $3);
1561 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1571 | indirectsrcoperand
1576 | indirectsrcoperand
1581 | indirectsrcoperand
1585 directsrcaccoperand:
1587 | accreg region reg_type
1589 $$ = set_direct_src_operand(&$1, $3);
1590 $$.vstride = $2.vstride;
1591 $$.width = $2.width;
1592 $$.hstride = $2.hstride;
1597 srcarcoperandex_typed region reg_type
1599 $$ = brw_reg($1.file,
1611 | nullreg region reg_type
1613 $$ = set_direct_src_operand(&$1, $3);
1614 $$.vstride = $2.vstride;
1615 $$.width = $2.width;
1616 $$.hstride = $2.hstride;
1620 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1624 srcarcoperandex_typed:
1634 negate abs indirectgenreg indirectregion swizzle reg_type
1636 $$ = brw_reg($3.file,
1648 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1649 // brw_reg set indirect_offset to 0 so set it to valid value
1650 $$.indirect_offset = $3.indirect_offset;
1663 negate abs directgenreg_list region swizzle reg_type
1665 $$ = brw_reg($3.file,
1680 /* Address register */
1684 memset(&$$, '\0', sizeof($$));
1685 $$.subnr = $1.subnr;
1686 $$.indirect_offset = $2;
1691 /* Register files and register numbers */
1693 INTEGER { $$ = $1; }
1698 DOT exp { $$ = $2; }
1699 | %empty %prec SUBREGNUM { $$ = 0; }
1705 memset(&$$, '\0', sizeof($$));
1706 $$.file = BRW_GENERAL_REGISTER_FILE;
1713 GENREGFILE LSQUARE addrparam RSQUARE
1715 memset(&$$, '\0', sizeof($$));
1716 $$.file = BRW_GENERAL_REGISTER_FILE;
1717 $$.subnr = $3.subnr;
1718 $$.indirect_offset = $3.indirect_offset;
1725 $$ = brw_message_reg($1);
1731 MSGREGFILE LSQUARE addrparam RSQUARE
1733 memset(&$$, '\0', sizeof($$));
1734 $$.file = BRW_MESSAGE_REGISTER_FILE;
1735 $$.subnr = $3.subnr;
1736 $$.indirect_offset = $3.indirect_offset;
1743 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1746 error(&@2, "Address sub register number %d"
1747 "out of range\n", $2);
1749 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1750 $$.nr = BRW_ARF_ADDRESS;
1759 if (p->devinfo->gen < 8)
1765 error(&@1, "Accumulator register number %d"
1766 " out of range\n", $1);
1768 memset(&$$, '\0', sizeof($$));
1769 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1770 $$.nr = BRW_ARF_ACCUMULATOR;
1778 // SNB = 1 flag reg and IVB+ = 2 flag reg
1779 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1783 error(&@1, "Flag register number %d"
1784 " out of range \n", $1);
1786 error(&@2, "Flag subregister number %d"
1787 " out of range\n", $2);
1789 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1790 $$.nr = BRW_ARF_FLAG | $1;
1799 error(&@1, "Mask register number %d"
1800 " out of range\n", $1);
1802 $$ = brw_mask_reg($2);
1810 error(&@1, "Notification register number %d"
1811 " out of range\n", $1);
1813 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1815 error(&@2, "Notification sub register number %d"
1816 " out of range\n", $2);
1818 $$ = brw_notification_reg();
1827 error(&@1, "State register number %d"
1828 " out of range\n", $1);
1831 error(&@2, "State sub register number %d"
1832 " out of range\n", $2);
1834 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1835 $$.nr = BRW_ARF_STATE;
1841 CONTROLREG subregnum
1844 error(&@2, "control sub register number %d"
1845 " out of range\n", $2);
1847 $$ = brw_cr0_reg($2);
1852 IPREG { $$ = brw_ip_reg(); }
1856 NULL_TOKEN { $$ = brw_null_reg(); }
1863 error(&@1, "Thread control register number %d"
1864 " out of range\n", $1);
1867 error(&@2, "Thread control sub register number %d"
1868 " out of range\n", $2);
1876 PERFORMANCEREG subregnum
1879 if (p->devinfo->gen >= 10)
1881 else if (p->devinfo->gen <= 8)
1887 error(&@2, "Performance sub register number %d"
1888 " out of range\n", $2);
1890 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1891 $$.nr = BRW_ARF_TIMESTAMP;
1896 CHANNELENABLEREG subregnum
1899 error(&@1, "Channel enable register number %d"
1900 " out of range\n", $1);
1902 $$ = brw_mask_reg($2);
1906 /* Immediate values */
1912 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1914 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1922 $$ = BRW_HORIZONTAL_STRIDE_1;
1926 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1927 error(&@2, "Invalid Horizontal stride %d\n", $2);
1941 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1945 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1946 error(&@2, "Invalid VertStride %d\n", $2);
1948 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1950 | LANGLE exp COMMA exp COMMA exp RANGLE
1953 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1954 error(&@2, "Invalid VertStride %d\n", $2);
1956 if ($4 > 16 || !isPowerofTwo($4))
1957 error(&@4, "Invalid width %d\n", $4);
1959 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1960 error(&@6, "Invalid Horizontal stride in"
1961 " region_wh %d\n", $6);
1963 $$ = stride($$, $2, $4, $6);
1965 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1967 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1968 error(&@2, "Invalid VertStride %d\n", $2);
1970 if ($4 > 16 || !isPowerofTwo($4))
1971 error(&@4, "Invalid width %d\n", $4);
1973 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1974 error(&@6, "Invalid Horizontal stride in"
1975 " region_wh %d\n", $6);
1977 $$ = stride($$, $2, $4, $6);
1979 | LANGLE VxH COMMA exp COMMA exp RANGLE
1981 if ($4 > 16 || !isPowerofTwo($4))
1982 error(&@4, "Invalid width %d\n", $4);
1984 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1985 error(&@6, "Invalid Horizontal stride in"
1986 " region_wh %d\n", $6);
1988 $$ = brw_VxH_indirect(0, 0);
1993 LANGLE exp COMMA exp RANGLE
1995 if ($2 > 16 || !isPowerofTwo($2))
1996 error(&@2, "Invalid width %d\n", $2);
1998 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
1999 error(&@4, "Invalid Horizontal stride in"
2000 " region_wh %d\n", $4);
2002 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2007 TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
2008 | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
2009 | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
2010 | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
2011 | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
2012 | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
2013 | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
2014 | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
2015 | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
2016 | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
2017 | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
2018 | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
2022 reg_type { $$ = $1; }
2023 | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
2024 | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
2025 | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
2031 $$ = WRITEMASK_XYZW;
2033 | DOT writemask_x writemask_y writemask_z writemask_w
2035 $$ = $2 | $3 | $4 | $5;
2041 | X { $$ = 1 << BRW_CHANNEL_X; }
2046 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2051 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2056 | W { $$ = 1 << BRW_CHANNEL_W; }
2062 $$ = BRW_SWIZZLE_NOOP;
2066 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
2068 | DOT chansel chansel chansel chansel
2070 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
2081 /* Instruction prediction and modifiers */
2085 brw_push_insn_state(p);
2086 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2087 brw_set_default_flag_reg(p, 0, 0);
2088 brw_set_default_predicate_inverse(p, false);
2090 | LPAREN predstate flagreg predctrl RPAREN
2092 brw_push_insn_state(p);
2093 brw_set_default_predicate_inverse(p, $2);
2094 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2095 brw_set_default_predicate_control(p, $4);
2106 %empty { $$ = BRW_PREDICATE_NORMAL; }
2107 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2108 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2109 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2110 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2125 /* Source Modification */
2136 /* Flag (Conditional) Modifier */
2140 $$.cond_modifier = $1;
2142 $$.flag_subreg_nr = 0;
2144 | condModifiers DOT flagreg
2146 $$.cond_modifier = $1;
2147 $$.flag_reg_nr = $3.nr;
2148 $$.flag_subreg_nr = $3.subnr;
2153 %empty { $$ = BRW_CONDITIONAL_NONE; }
2168 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2169 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2172 /* Execution size */
2174 %empty %prec EMPTYEXECSIZE
2178 | LPAREN exp2 RPAREN
2180 if ($2 > 32 || !isPowerofTwo($2))
2181 error(&@2, "Invalid execution size %d\n", $2);
2187 /* Instruction options */
2191 memset(&$$, 0, sizeof($$));
2193 | LCURLY instoption_list RCURLY
2195 memset(&$$, 0, sizeof($$));
2201 instoption_list COMMA instoption
2203 memset(&$$, 0, sizeof($$));
2205 add_instruction_option(&$$, $3);
2207 | instoption_list instoption
2209 memset(&$$, 0, sizeof($$));
2211 add_instruction_option(&$$, $2);
2215 memset(&$$, 0, sizeof($$));
2220 ALIGN1 { $$ = ALIGN1;}
2221 | ALIGN16 { $$ = ALIGN16; }
2222 | ACCWREN { $$ = ACCWREN; }
2223 | SECHALF { $$ = SECHALF; }
2224 | COMPR { $$ = COMPR; }
2225 | COMPR4 { $$ = COMPR4; }
2226 | BREAKPOINT { $$ = BREAKPOINT; }
2227 | NODDCLR { $$ = NODDCLR; }
2228 | NODDCHK { $$ = NODDCHK; }
2229 | MASK_DISABLE { $$ = MASK_DISABLE; }
2231 | SWITCH { $$ = SWITCH; }
2232 | ATOMIC { $$ = ATOMIC; }
2233 | CMPTCTRL { $$ = CMPTCTRL; }
2234 | WECTRL { $$ = WECTRL; }
2235 | QTR_2Q { $$ = QTR_2Q; }
2236 | QTR_3Q { $$ = QTR_3Q; }
2237 | QTR_4Q { $$ = QTR_4Q; }
2238 | QTR_2H { $$ = QTR_2H; }
2239 | QTR_2N { $$ = QTR_2N; }
2240 | QTR_3N { $$ = QTR_3N; }
2241 | QTR_4N { $$ = QTR_4N; }
2242 | QTR_5N { $$ = QTR_5N; }
2243 | QTR_6N { $$ = QTR_6N; }
2244 | QTR_7N { $$ = QTR_7N; }
2245 | QTR_8N { $$ = QTR_8N; }
2250 extern int yylineno;
2255 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2256 input_filename, yylineno, msg, lex_text());