pan/bit: Remove BI_SHIFT stub
[mesa.git] / src / intel / tools / i965_gram.y
1 %{
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <strings.h>
29 #include "i965_asm.h"
30
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
33 {
34 int first_line;
35 int first_column;
36 int last_line;
37 int last_column;
38 } YYLTYPE;
39
40 enum message_level {
41 WARN,
42 ERROR,
43 };
44
45 int yydebug = 1;
46
47 static void
48 message(enum message_level level, YYLTYPE *location,
49 const char *fmt, ...)
50 {
51 static const char *level_str[] = { "warning", "error" };
52 va_list args;
53
54 if (location)
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
56 location->first_line,
57 location->first_column, level_str[level]);
58 else
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
60
61 va_start(args, fmt);
62 vfprintf(stderr, fmt, args);
63 va_end(args);
64 }
65
66 #define warn(flag, l, fmt, ...) \
67 do { \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
70 } while (0)
71
72 #define error(l, fmt, ...) \
73 do { \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
75 } while (0)
76
77 static bool
78 isPowerofTwo(unsigned int x)
79 {
80 return x && (!(x & (x - 1)));
81 }
82
83 static struct brw_reg
84 set_direct_src_operand(struct brw_reg *reg, int type)
85 {
86 return brw_reg(reg->file,
87 reg->nr,
88 reg->subnr,
89 0, // negate
90 0, // abs
91 type,
92 0, // vstride
93 0, // width
94 0, // hstride
95 BRW_SWIZZLE_NOOP,
96 WRITEMASK_XYZW);
97 }
98
99 static void
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
102 {
103 switch (opcode) {
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
106 break;
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
109 break;
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
112 break;
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
115 break;
116 case BRW_OPCODE_MOV:
117 brw_MOV(p, dest, src0);
118 break;
119 case BRW_OPCODE_FBL:
120 brw_FBL(p, dest, src0);
121 break;
122 case BRW_OPCODE_FRC:
123 brw_FRC(p, dest, src0);
124 break;
125 case BRW_OPCODE_FBH:
126 brw_FBH(p, dest, src0);
127 break;
128 case BRW_OPCODE_NOT:
129 brw_NOT(p, dest, src0);
130 break;
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
133 break;
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
136 break;
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
139 break;
140 case BRW_OPCODE_LZD:
141 brw_LZD(p, dest, src0);
142 break;
143 case BRW_OPCODE_DIM:
144 brw_DIM(p, dest, src0);
145 break;
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
148 break;
149 default:
150 fprintf(stderr, "Unsupported unary opcode\n");
151 }
152 }
153
154 static void
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
157 struct brw_reg dest,
158 struct brw_reg src0,
159 struct brw_reg src1)
160 {
161 switch (opcode) {
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
164 break;
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
167 break;
168 case BRW_OPCODE_DP2:
169 brw_DP2(p, dest, src0, src1);
170 break;
171 case BRW_OPCODE_DP3:
172 brw_DP3(p, dest, src0, src1);
173 break;
174 case BRW_OPCODE_DP4:
175 brw_DP4(p, dest, src0, src1);
176 break;
177 case BRW_OPCODE_DPH:
178 brw_DPH(p, dest, src0, src1);
179 break;
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
182 break;
183 case BRW_OPCODE_MAC:
184 brw_MAC(p, dest, src0, src1);
185 break;
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
188 break;
189 case BRW_OPCODE_PLN:
190 brw_PLN(p, dest, src0, src1);
191 break;
192 case BRW_OPCODE_ROL:
193 brw_ROL(p, dest, src0, src1);
194 break;
195 case BRW_OPCODE_ROR:
196 brw_ROR(p, dest, src0, src1);
197 break;
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
200 break;
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
203 break;
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
206 break;
207 case BRW_OPCODE_ADD:
208 brw_ADD(p, dest, src0, src1);
209 break;
210 case BRW_OPCODE_CMP:
211 /* Third parameter is conditional modifier
212 * which gets updated later
213 */
214 brw_CMP(p, dest, 0, src0, src1);
215 break;
216 case BRW_OPCODE_AND:
217 brw_AND(p, dest, src0, src1);
218 break;
219 case BRW_OPCODE_ASR:
220 brw_ASR(p, dest, src0, src1);
221 break;
222 case BRW_OPCODE_AVG:
223 brw_AVG(p, dest, src0, src1);
224 break;
225 case BRW_OPCODE_OR:
226 brw_OR(p, dest, src0, src1);
227 break;
228 case BRW_OPCODE_SEL:
229 brw_SEL(p, dest, src0, src1);
230 break;
231 case BRW_OPCODE_SHL:
232 brw_SHL(p, dest, src0, src1);
233 break;
234 case BRW_OPCODE_SHR:
235 brw_SHR(p, dest, src0, src1);
236 break;
237 case BRW_OPCODE_XOR:
238 brw_XOR(p, dest, src0, src1);
239 break;
240 case BRW_OPCODE_MUL:
241 brw_MUL(p, dest, src0, src1);
242 break;
243 default:
244 fprintf(stderr, "Unsupported binary opcode\n");
245 }
246 }
247
248 static void
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
251 struct brw_reg dest,
252 struct brw_reg src0,
253 struct brw_reg src1,
254 struct brw_reg src2)
255 {
256 switch (opcode) {
257 case BRW_OPCODE_MAD:
258 brw_MAD(p, dest, src0, src1, src2);
259 break;
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
262 break;
263 case BRW_OPCODE_LRP:
264 brw_LRP(p, dest, src0, src1, src2);
265 break;
266 case BRW_OPCODE_BFE:
267 brw_BFE(p, dest, src0, src1, src2);
268 break;
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
271 break;
272 default:
273 fprintf(stderr, "Unsupported ternary opcode\n");
274 }
275 }
276
277 static void
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
280 {
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
297 options.compaction);
298 }
299
300 static void
301 i965_asm_set_dst_nr(struct brw_codegen *p,
302 struct brw_reg *reg,
303 struct options options)
304 {
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
308 !options.is_compr)
309 reg->nr |= BRW_MRF_COMPR4;
310 }
311 }
312
313 %}
314
315 %locations
316
317 %start ROOT
318
319 %union {
320 double number;
321 int integer;
322 unsigned long long int llint;
323 struct brw_reg reg;
324 struct brw_codegen *program;
325 struct predicate predicate;
326 struct condition condition;
327 struct options options;
328 brw_inst *instruction;
329 }
330
331 %token ABS
332 %token COLON
333 %token COMMA
334 %token DOT
335 %token LANGLE RANGLE
336 %token LCURLY RCURLY
337 %token LPAREN RPAREN
338 %token LSQUARE RSQUARE
339 %token PLUS MINUS
340 %token SEMICOLON
341
342 /* datatypes */
343 %token <integer> TYPE_B TYPE_UB
344 %token <integer> TYPE_W TYPE_UW
345 %token <integer> TYPE_D TYPE_UD
346 %token <integer> TYPE_Q TYPE_UQ
347 %token <integer> TYPE_V TYPE_UV
348 %token <integer> TYPE_F TYPE_HF
349 %token <integer> TYPE_DF TYPE_NF
350 %token <integer> TYPE_VF
351
352 /* opcodes */
353 %token <integer> ADD ADD3 ADDC AND ASR AVG
354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
358 %token <integer> GOTO
359 %token <integer> HALT
360 %token <integer> IF IFF ILLEGAL
361 %token <integer> JMPI JOIN
362 %token <integer> LINE LRP LZD
363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
364 %token <integer> NENOP NOP NOT
365 %token <integer> OR
366 %token <integer> PLN POP PUSH
367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
369 %token <integer> WAIT WHILE
370 %token <integer> XOR
371
372 /* extended math functions */
373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
374 %token <integer> RSQRTM SIN SINCOS SQRT
375
376 /* shared functions for send */
377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
379
380 /* Conditional modifiers */
381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
383
384 /* register Access Modes */
385 %token ALIGN1 ALIGN16
386
387 /* accumulator write control */
388 %token ACCWREN
389
390 /* compaction control */
391 %token CMPTCTRL
392
393 /* compression control */
394 %token COMPR COMPR4 SECHALF
395
396 /* mask control (WeCtrl) */
397 %token WECTRL
398
399 /* debug control */
400 %token BREAKPOINT
401
402 /* dependency control */
403 %token NODDCLR NODDCHK
404
405 /* end of thread */
406 %token EOT
407
408 /* mask control */
409 %token MASK_DISABLE;
410
411 /* predicate control */
412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
413 %token <integer> ANY32H ALL32H
414
415 /* round instructions */
416 %token <integer> ROUND_INCREMENT
417
418 /* staturation */
419 %token SATURATE
420
421 /* thread control */
422 %token ATOMIC SWITCH
423
424 /* quater control */
425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
426 %token QTR_6N QTR_7N QTR_8N
427
428 /* channels */
429 %token <integer> X Y Z W
430
431 /* reg files */
432 %token GENREGFILE MSGREGFILE
433
434 /* vertical stride in register region */
435 %token VxH
436
437 /* register type */
438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
440 %token <integer> MASKREG
441
442 %token <integer> INTEGER
443 %token <llint> LONG
444 %token NULL_TOKEN
445
446 %precedence SUBREGNUM
447 %left PLUS MINUS
448 %precedence DOT
449 %precedence EMPTYEXECSIZE
450 %precedence LPAREN
451
452 %type <integer> execsize simple_int exp
453 %type <llint> exp2
454
455 /* predicate control */
456 %type <integer> predctrl predstate
457 %type <predicate> predicate
458
459 /* conditional modifier */
460 %type <condition> cond_mod
461 %type <integer> condModifiers
462
463 /* instruction options */
464 %type <options> instoptions instoption_list
465 %type <integer> instoption
466
467 /* writemask */
468 %type <integer> writemask_x writemask_y writemask_z writemask_w
469 %type <reg> writemask
470
471 /* dst operand */
472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
473 %type <integer> dstregion
474
475 %type <integer> saturate relativelocation rellocation
476 %type <reg> relativelocation2
477
478 /* src operand */
479 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
480 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
481 %type <reg> srcimmtype indirectgenreg indirectregion
482 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
483 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
484
485 /* registers */
486 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
487 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
488 %type <integer> subregnum
489
490 /* immediate values */
491 %type <llint> immval
492
493 /* instruction opcodes */
494 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
495 %type <integer> sendop
496 %type <instruction> sendopcode
497
498 %type <integer> negate abs chansel math_function sharedfunction
499
500 %code {
501
502 static void
503 add_instruction_option(struct options *options, int option)
504 {
505 switch (option) {
506 case ALIGN1:
507 options->access_mode = BRW_ALIGN_1;
508 break;
509 case ALIGN16:
510 options->access_mode = BRW_ALIGN_16;
511 break;
512 case SECHALF:
513 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
514 break;
515 case COMPR:
516 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
517 options->is_compr = true;
518 break;
519 case COMPR4:
520 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
521 break;
522 case SWITCH:
523 options->thread_control |= BRW_THREAD_SWITCH;
524 break;
525 case ATOMIC:
526 options->thread_control |= BRW_THREAD_ATOMIC;
527 break;
528 case NODDCHK:
529 options->no_dd_check = true;
530 break;
531 case NODDCLR:
532 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
533 break;
534 case MASK_DISABLE:
535 options->mask_control |= BRW_MASK_DISABLE;
536 break;
537 case BREAKPOINT:
538 options->debug_control = BRW_DEBUG_BREAKPOINT;
539 break;
540 case WECTRL:
541 options->mask_control |= BRW_WE_ALL;
542 break;
543 case CMPTCTRL:
544 options->compaction = true;
545 break;
546 case ACCWREN:
547 options->acc_wr_control = true;
548 break;
549 case EOT:
550 options->end_of_thread = true;
551 break;
552 /* TODO : Figure out how to set instruction group and get rid of
553 * code below
554 */
555 case QTR_2Q:
556 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
557 break;
558 case QTR_3Q:
559 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
560 break;
561 case QTR_4Q:
562 options->qtr_ctrl = 3;
563 break;
564 case QTR_2H:
565 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
566 break;
567 case QTR_2N:
568 options->qtr_ctrl = BRW_COMPRESSION_NONE;
569 options->nib_ctrl = true;
570 break;
571 case QTR_3N:
572 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
573 break;
574 case QTR_4N:
575 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
576 options->nib_ctrl = true;
577 break;
578 case QTR_5N:
579 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
580 break;
581 case QTR_6N:
582 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
583 options->nib_ctrl = true;
584 break;
585 case QTR_7N:
586 options->qtr_ctrl = 3;
587 break;
588 case QTR_8N:
589 options->qtr_ctrl = 3;
590 options->nib_ctrl = true;
591 break;
592 }
593 }
594 }
595 %%
596
597 ROOT:
598 instrseq
599 ;
600
601 instrseq:
602 instrseq instruction SEMICOLON
603 | instrseq relocatableinstruction SEMICOLON
604 | instruction SEMICOLON
605 | relocatableinstruction SEMICOLON
606 ;
607
608 /* Instruction Group */
609 instruction:
610 unaryinstruction
611 | binaryinstruction
612 | binaryaccinstruction
613 | mathinstruction
614 | nopinstruction
615 | syncinstruction
616 | ternaryinstruction
617 | sendinstruction
618 | illegalinstruction
619 ;
620
621 relocatableinstruction:
622 jumpinstruction
623 | branchinstruction
624 | breakinstruction
625 | loopinstruction
626 ;
627
628 illegalinstruction:
629 ILLEGAL execsize instoptions
630 {
631 brw_next_insn(p, $1);
632 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
633 i965_asm_set_instruction_options(p, $3);
634 }
635 ;
636
637 /* Unary instruction */
638 unaryinstruction:
639 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
640 {
641 i965_asm_set_dst_nr(p, &$6, $8);
642 brw_set_default_access_mode(p, $8.access_mode);
643 i965_asm_unary_instruction($2, p, $6, $7);
644 brw_pop_insn_state(p);
645 i965_asm_set_instruction_options(p, $8);
646 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
647 $4.cond_modifier);
648
649 if (p->devinfo->gen >= 7) {
650 if ($2 != BRW_OPCODE_DIM) {
651 brw_inst_set_flag_reg_nr(p->devinfo,
652 brw_last_inst,
653 $4.flag_reg_nr);
654 brw_inst_set_flag_subreg_nr(p->devinfo,
655 brw_last_inst,
656 $4.flag_subreg_nr);
657 }
658 }
659
660 if ($7.file != BRW_IMMEDIATE_VALUE) {
661 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
662 $7.vstride);
663 }
664 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
665 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
666 // TODO: set instruction group instead of qtr and nib ctrl
667 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
668 $8.qtr_ctrl);
669
670 if (p->devinfo->gen >= 7)
671 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
672 $8.nib_ctrl);
673 }
674 ;
675
676 unaryopcodes:
677 BFREV
678 | CBIT
679 | DIM
680 | F16TO32
681 | F32TO16
682 | FBH
683 | FBL
684 | FRC
685 | LZD
686 | MOV
687 | NOT
688 | RNDD
689 | RNDE
690 | RNDU
691 | RNDZ
692 ;
693
694 /* Binary instruction */
695 binaryinstruction:
696 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
697 {
698 i965_asm_set_dst_nr(p, &$6, $9);
699 brw_set_default_access_mode(p, $9.access_mode);
700 i965_asm_binary_instruction($2, p, $6, $7, $8);
701 i965_asm_set_instruction_options(p, $9);
702 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
703 $4.cond_modifier);
704
705 if (p->devinfo->gen >= 7) {
706 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
707 $4.flag_reg_nr);
708 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
709 $4.flag_subreg_nr);
710 }
711
712 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
713 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
714 // TODO: set instruction group instead of qtr and nib ctrl
715 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
716 $9.qtr_ctrl);
717
718 if (p->devinfo->gen >= 7)
719 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
720 $9.nib_ctrl);
721
722 brw_pop_insn_state(p);
723 }
724 ;
725
726 binaryopcodes:
727 ADDC
728 | BFI1
729 | DP2
730 | DP3
731 | DP4
732 | DPH
733 | LINE
734 | MAC
735 | MACH
736 | MUL
737 | PLN
738 | ROL
739 | ROR
740 | SAD2
741 | SADA2
742 | SUBB
743 ;
744
745 /* Binary acc instruction */
746 binaryaccinstruction:
747 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
748 {
749 i965_asm_set_dst_nr(p, &$6, $9);
750 brw_set_default_access_mode(p, $9.access_mode);
751 i965_asm_binary_instruction($2, p, $6, $7, $8);
752 brw_pop_insn_state(p);
753 i965_asm_set_instruction_options(p, $9);
754 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
755 $4.cond_modifier);
756
757 if (p->devinfo->gen >= 7) {
758 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
759 brw_inst_set_flag_reg_nr(p->devinfo,
760 brw_last_inst,
761 $4.flag_reg_nr);
762 brw_inst_set_flag_subreg_nr(p->devinfo,
763 brw_last_inst,
764 $4.flag_subreg_nr);
765 }
766 }
767
768 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
769 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
770 // TODO: set instruction group instead of qtr and nib ctrl
771 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
772 $9.qtr_ctrl);
773
774 if (p->devinfo->gen >= 7)
775 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
776 $9.nib_ctrl);
777
778 }
779 ;
780
781 binaryaccopcodes:
782 ADD
783 | AND
784 | ASR
785 | AVG
786 | CMP
787 | CMPN
788 | OR
789 | SEL
790 | SHL
791 | SHR
792 | XOR
793 ;
794
795 /* Math instruction */
796 mathinstruction:
797 predicate MATH saturate math_function execsize dst src srcimm instoptions
798 {
799 brw_set_default_access_mode(p, $9.access_mode);
800 gen6_math(p, $6, $4, $7, $8);
801 i965_asm_set_instruction_options(p, $9);
802 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
803 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
804 // TODO: set instruction group instead
805 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
806 $9.qtr_ctrl);
807
808 if (p->devinfo->gen >= 7)
809 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
810 $9.nib_ctrl);
811
812 brw_pop_insn_state(p);
813 }
814 ;
815
816 math_function:
817 COS
818 | EXP
819 | FDIV
820 | INV
821 | INVM
822 | INTDIV
823 | INTDIVMOD
824 | INTMOD
825 | LOG
826 | POW
827 | RSQ
828 | RSQRTM
829 | SIN
830 | SQRT
831 | SINCOS
832 ;
833
834 /* NOP instruction */
835 nopinstruction:
836 NOP
837 {
838 brw_NOP(p);
839 }
840 ;
841
842 /* Ternary operand instruction */
843 ternaryinstruction:
844 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
845 {
846 brw_set_default_access_mode(p, $10.access_mode);
847 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
848 brw_pop_insn_state(p);
849 i965_asm_set_instruction_options(p, $10);
850 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
851 $4.cond_modifier);
852
853 if (p->devinfo->gen >= 7) {
854 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
855 $4.flag_reg_nr);
856 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
857 $4.flag_subreg_nr);
858 }
859
860 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
861 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
862 // TODO: set instruction group instead of qtr and nib ctrl
863 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
864 $10.qtr_ctrl);
865
866 if (p->devinfo->gen >= 7)
867 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
868 $10.nib_ctrl);
869 }
870 ;
871
872 ternaryopcodes:
873 CSEL
874 | BFE
875 | BFI2
876 | LRP
877 | MAD
878 ;
879
880 /* Sync instruction */
881 syncinstruction:
882 WAIT execsize src instoptions
883 {
884 brw_next_insn(p, $1);
885 i965_asm_set_instruction_options(p, $4);
886 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
887 brw_set_default_access_mode(p, $4.access_mode);
888 struct brw_reg src = brw_notification_reg();
889 brw_set_dest(p, brw_last_inst, src);
890 brw_set_src0(p, brw_last_inst, src);
891 brw_set_src1(p, brw_last_inst, brw_null_reg());
892 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
893 }
894 ;
895
896 /* Send instruction */
897 sendinstruction:
898 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
899 {
900 i965_asm_set_instruction_options(p, $8);
901 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
902 brw_set_dest(p, brw_last_inst, $4);
903 brw_set_src0(p, brw_last_inst, $5);
904 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
905 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
906 BRW_IMMEDIATE_VALUE,
907 BRW_REGISTER_TYPE_UD);
908 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
909 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
910 // TODO: set instruction group instead of qtr and nib ctrl
911 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
912 $8.qtr_ctrl);
913
914 if (p->devinfo->gen >= 7)
915 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
916 $8.nib_ctrl);
917
918 brw_pop_insn_state(p);
919 }
920 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
921 {
922 i965_asm_set_instruction_options(p, $9);
923 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
924 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
925 brw_set_dest(p, brw_last_inst, $5);
926 brw_set_src0(p, brw_last_inst, $6);
927 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
928 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
929 BRW_IMMEDIATE_VALUE,
930 BRW_REGISTER_TYPE_UD);
931 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
932 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
933 // TODO: set instruction group instead of qtr and nib ctrl
934 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
935 $9.qtr_ctrl);
936
937 if (p->devinfo->gen >= 7)
938 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
939 $9.nib_ctrl);
940
941 brw_pop_insn_state(p);
942 }
943 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
944 {
945 i965_asm_set_instruction_options(p, $9);
946 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
947 brw_set_dest(p, brw_last_inst, $4);
948 brw_set_src0(p, brw_last_inst, $5);
949 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
950 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
951 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
952 // TODO: set instruction group instead of qtr and nib ctrl
953 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
954 $9.qtr_ctrl);
955
956 if (p->devinfo->gen >= 7)
957 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
958 $9.nib_ctrl);
959
960 brw_pop_insn_state(p);
961 }
962 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
963 {
964 brw_next_insn(p, $2);
965 i965_asm_set_instruction_options(p, $10);
966 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
967 brw_set_dest(p, brw_last_inst, $4);
968 brw_set_src0(p, brw_last_inst, $5);
969 brw_set_src1(p, brw_last_inst, $6);
970
971 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
972 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
973 } else {
974 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
975 }
976
977 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
978 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
979 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
980 // TODO: set instruction group instead of qtr and nib ctrl
981 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
982 $10.qtr_ctrl);
983
984 if (p->devinfo->gen >= 7)
985 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
986 $10.nib_ctrl);
987
988 brw_pop_insn_state(p);
989 }
990 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
991 {
992 brw_next_insn(p, $2);
993 i965_asm_set_instruction_options(p, $10);
994 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
995 brw_set_dest(p, brw_last_inst, $4);
996 brw_set_src0(p, brw_last_inst, $5);
997 brw_set_src1(p, brw_last_inst, $6);
998
999 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1000 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1001
1002 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1003 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1004 // TODO: set instruction group instead of qtr and nib ctrl
1005 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1006 $10.qtr_ctrl);
1007
1008 if (p->devinfo->gen >= 7)
1009 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1010 $10.nib_ctrl);
1011
1012 brw_pop_insn_state(p);
1013 }
1014 ;
1015
1016 sendop:
1017 SEND
1018 | SENDC
1019 ;
1020
1021 sendopcode:
1022 sendop { $$ = brw_next_insn(p, $1); }
1023 ;
1024
1025 sharedfunction:
1026 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1027 | MATH { $$ = BRW_SFID_MATH; }
1028 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1029 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1030 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1031 | URB { $$ = BRW_SFID_URB; }
1032 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1033 | VME { $$ = BRW_SFID_VME; }
1034 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1035 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1036 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1037 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1038 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1039 | CRE { $$ = HSW_SFID_CRE; }
1040 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1041 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1042 ;
1043
1044 exp2:
1045 LONG { $$ = $1; }
1046 | MINUS LONG { $$ = -$2; }
1047 ;
1048
1049 /* Jump instruction */
1050 jumpinstruction:
1051 predicate JMPI execsize relativelocation2 instoptions
1052 {
1053 brw_next_insn(p, $2);
1054 i965_asm_set_instruction_options(p, $5);
1055 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1056 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1057 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1058 brw_set_src1(p, brw_last_inst, $4);
1059 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1060 brw_inst_pred_control(p->devinfo,
1061 brw_last_inst));
1062 brw_pop_insn_state(p);
1063 }
1064 ;
1065
1066 /* branch instruction */
1067 branchinstruction:
1068 predicate ENDIF execsize relativelocation instoptions
1069 {
1070 brw_next_insn(p, $2);
1071 i965_asm_set_instruction_options(p, $5);
1072 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1073
1074 if (p->devinfo->gen < 6) {
1075 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1076 BRW_REGISTER_TYPE_D));
1077 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1078 BRW_REGISTER_TYPE_D));
1079 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1080 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1081 $4);
1082 } else if (p->devinfo->gen == 6) {
1083 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1084 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1085 $4);
1086 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1087 BRW_REGISTER_TYPE_D));
1088 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1089 BRW_REGISTER_TYPE_D));
1090 } else if (p->devinfo->gen == 7) {
1091 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1092 BRW_REGISTER_TYPE_D));
1093 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1094 BRW_REGISTER_TYPE_D));
1095 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1096 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1097 } else {
1098 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1099 }
1100
1101 if (p->devinfo->gen < 6)
1102 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1103 BRW_THREAD_SWITCH);
1104 brw_pop_insn_state(p);
1105 }
1106 | ELSE execsize relativelocation rellocation instoptions
1107 {
1108 brw_next_insn(p, $1);
1109 i965_asm_set_instruction_options(p, $5);
1110 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1111
1112 if (p->devinfo->gen < 6) {
1113 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1114 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1115 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1116 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1117 $3);
1118 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1119 $4);
1120 } else if (p->devinfo->gen == 6) {
1121 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1122 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1123 $3);
1124 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1125 BRW_REGISTER_TYPE_D));
1126 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1127 BRW_REGISTER_TYPE_D));
1128 } else if (p->devinfo->gen == 7) {
1129 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1130 BRW_REGISTER_TYPE_D));
1131 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1132 BRW_REGISTER_TYPE_D));
1133 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1134 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1135 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1136 } else {
1137 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1138 BRW_REGISTER_TYPE_D));
1139 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1140 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1141 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1142 }
1143
1144 if (!p->single_program_flow && p->devinfo->gen < 6)
1145 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1146 BRW_THREAD_SWITCH);
1147 }
1148 | predicate IF execsize relativelocation rellocation instoptions
1149 {
1150 brw_next_insn(p, $2);
1151 i965_asm_set_instruction_options(p, $6);
1152 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1153
1154 if (p->devinfo->gen < 6) {
1155 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1156 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1157 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1158 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1159 $4);
1160 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1161 $5);
1162 } else if (p->devinfo->gen == 6) {
1163 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1164 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1165 $4);
1166 brw_set_src0(p, brw_last_inst,
1167 vec1(retype(brw_null_reg(),
1168 BRW_REGISTER_TYPE_D)));
1169 brw_set_src1(p, brw_last_inst,
1170 vec1(retype(brw_null_reg(),
1171 BRW_REGISTER_TYPE_D)));
1172 } else if (p->devinfo->gen == 7) {
1173 brw_set_dest(p, brw_last_inst,
1174 vec1(retype(brw_null_reg(),
1175 BRW_REGISTER_TYPE_D)));
1176 brw_set_src0(p, brw_last_inst,
1177 vec1(retype(brw_null_reg(),
1178 BRW_REGISTER_TYPE_D)));
1179 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1180 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1181 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1182 } else {
1183 brw_set_dest(p, brw_last_inst,
1184 vec1(retype(brw_null_reg(),
1185 BRW_REGISTER_TYPE_D)));
1186 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1187 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1188 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1189 }
1190
1191 if (!p->single_program_flow && p->devinfo->gen < 6)
1192 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1193 BRW_THREAD_SWITCH);
1194
1195 brw_pop_insn_state(p);
1196 }
1197 | predicate IFF execsize relativelocation instoptions
1198 {
1199 brw_next_insn(p, $2);
1200 i965_asm_set_instruction_options(p, $5);
1201 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1202
1203 if (p->devinfo->gen < 6) {
1204 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1205 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1206 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1207 $4);
1208 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1209 } else if (p->devinfo->gen == 6) {
1210 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1211 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1212 $4);
1213 brw_set_src0(p, brw_last_inst,
1214 vec1(retype(brw_null_reg(),
1215 BRW_REGISTER_TYPE_D)));
1216 brw_set_src1(p, brw_last_inst,
1217 vec1(retype(brw_null_reg(),
1218 BRW_REGISTER_TYPE_D)));
1219 } else if (p->devinfo->gen == 7) {
1220 brw_set_dest(p, brw_last_inst,
1221 vec1(retype(brw_null_reg(),
1222 BRW_REGISTER_TYPE_D)));
1223 brw_set_src0(p, brw_last_inst,
1224 vec1(retype(brw_null_reg(),
1225 BRW_REGISTER_TYPE_D)));
1226 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1227 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1228 } else {
1229 brw_set_dest(p, brw_last_inst,
1230 vec1(retype(brw_null_reg(),
1231 BRW_REGISTER_TYPE_D)));
1232 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1233 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1234 }
1235
1236 if (!p->single_program_flow && p->devinfo->gen < 6)
1237 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1238 BRW_THREAD_SWITCH);
1239
1240 brw_pop_insn_state(p);
1241 }
1242 ;
1243
1244 /* break instruction */
1245 breakinstruction:
1246 predicate BREAK execsize relativelocation relativelocation instoptions
1247 {
1248 brw_next_insn(p, $2);
1249 i965_asm_set_instruction_options(p, $6);
1250 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1251
1252 if (p->devinfo->gen >= 8) {
1253 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1254 BRW_REGISTER_TYPE_D));
1255 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1256 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1257 } else if (p->devinfo->gen >= 6) {
1258 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1259 BRW_REGISTER_TYPE_D));
1260 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1261 BRW_REGISTER_TYPE_D));
1262 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1263 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1264 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1265 } else {
1266 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1267 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1268 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1269 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1270 $4);
1271 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1272 $5);
1273 }
1274
1275 brw_pop_insn_state(p);
1276 }
1277 | predicate HALT execsize relativelocation relativelocation instoptions
1278 {
1279 brw_next_insn(p, $2);
1280 i965_asm_set_instruction_options(p, $6);
1281 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1282 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1283 BRW_REGISTER_TYPE_D));
1284
1285 if (p->devinfo->gen >= 8) {
1286 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1287 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1288 } else {
1289 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1290 BRW_REGISTER_TYPE_D));
1291 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1292 }
1293
1294 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1295 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1296 brw_pop_insn_state(p);
1297 }
1298 | predicate CONT execsize relativelocation relativelocation instoptions
1299 {
1300 brw_next_insn(p, $2);
1301 i965_asm_set_instruction_options(p, $6);
1302 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1303 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1304
1305 if (p->devinfo->gen >= 8) {
1306 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1307 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1308 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1309 } else {
1310 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1311 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1312 if (p->devinfo->gen >= 6) {
1313 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1314 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1315 } else {
1316 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1317 $4);
1318 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1319 $5);
1320 }
1321 }
1322
1323 brw_pop_insn_state(p);
1324 }
1325 ;
1326
1327 /* loop instruction */
1328 loopinstruction:
1329 predicate WHILE execsize relativelocation instoptions
1330 {
1331 brw_next_insn(p, $2);
1332 i965_asm_set_instruction_options(p, $5);
1333 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1334
1335 if (p->devinfo->gen >= 6) {
1336 if (p->devinfo->gen >= 8) {
1337 brw_set_dest(p, brw_last_inst,
1338 retype(brw_null_reg(),
1339 BRW_REGISTER_TYPE_D));
1340 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1341 } else if (p->devinfo->gen == 7) {
1342 brw_set_dest(p, brw_last_inst,
1343 retype(brw_null_reg(),
1344 BRW_REGISTER_TYPE_D));
1345 brw_set_src0(p, brw_last_inst,
1346 retype(brw_null_reg(),
1347 BRW_REGISTER_TYPE_D));
1348 brw_set_src1(p, brw_last_inst,
1349 brw_imm_w(0x0));
1350 brw_inst_set_jip(p->devinfo, brw_last_inst,
1351 $4);
1352 } else {
1353 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1354 brw_inst_set_gen6_jump_count(p->devinfo,
1355 brw_last_inst,
1356 $4);
1357 brw_set_src0(p, brw_last_inst,
1358 retype(brw_null_reg(),
1359 BRW_REGISTER_TYPE_D));
1360 brw_set_src1(p, brw_last_inst,
1361 retype(brw_null_reg(),
1362 BRW_REGISTER_TYPE_D));
1363 }
1364 } else {
1365 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1366 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1367 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1368 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1369 $4);
1370 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1371 0);
1372 }
1373 brw_pop_insn_state(p);
1374 }
1375 | DO execsize instoptions
1376 {
1377 brw_next_insn(p, $1);
1378 if (p->devinfo->gen < 6) {
1379 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1380 i965_asm_set_instruction_options(p, $3);
1381 brw_set_dest(p, brw_last_inst, brw_null_reg());
1382 brw_set_src0(p, brw_last_inst, brw_null_reg());
1383 brw_set_src1(p, brw_last_inst, brw_null_reg());
1384
1385 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1386 }
1387 }
1388 ;
1389
1390 /* Relative location */
1391 relativelocation2:
1392 immreg
1393 | reg32
1394 ;
1395
1396 simple_int:
1397 INTEGER { $$ = $1; }
1398 | MINUS INTEGER { $$ = -$2; }
1399 | LONG { $$ = $1; }
1400 | MINUS LONG { $$ = -$2; }
1401 ;
1402
1403 rellocation:
1404 relativelocation
1405 | %empty { $$ = 0; }
1406 ;
1407
1408 relativelocation:
1409 simple_int
1410 {
1411 $$ = $1;
1412 }
1413 ;
1414
1415 /* Destination register */
1416 dst:
1417 dstoperand
1418 | dstoperandex
1419 ;
1420
1421 dstoperand:
1422 dstreg dstregion writemask dsttype
1423 {
1424 $$ = $1;
1425
1426 if ($2 == -1) {
1427 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1428 $$.vstride = BRW_VERTICAL_STRIDE_1;
1429 $$.width = BRW_WIDTH_1;
1430 } else {
1431 $$.hstride = $2;
1432 }
1433 $$.type = $4.type;
1434 $$.writemask = $3.writemask;
1435 $$.swizzle = BRW_SWIZZLE_NOOP;
1436 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1437 }
1438 ;
1439
1440 dstoperandex:
1441 dstoperandex_typed dstregion writemask dsttype
1442 {
1443 $$ = $1;
1444 $$.hstride = $2;
1445 $$.type = $4.type;
1446 $$.writemask = $3.writemask;
1447 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1448 }
1449 /* BSpec says "When the conditional modifier is present, updates
1450 * to the selected flag register also occur. In this case, the
1451 * register region fields of the ‘null’ operand are valid."
1452 */
1453 | nullreg dstregion writemask dsttype
1454 {
1455 $$ = $1;
1456 if ($2 == -1) {
1457 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1458 $$.vstride = BRW_VERTICAL_STRIDE_1;
1459 $$.width = BRW_WIDTH_1;
1460 } else {
1461 $$.hstride = $2;
1462 }
1463 $$.writemask = $3.writemask;
1464 $$.type = $4.type;
1465 }
1466 | threadcontrolreg
1467 {
1468 $$ = $1;
1469 $$.hstride = 1;
1470 $$.type = BRW_REGISTER_TYPE_UW;
1471 }
1472 ;
1473
1474 dstoperandex_typed:
1475 accreg
1476 | addrreg
1477 | channelenablereg
1478 | controlreg
1479 | flagreg
1480 | ipreg
1481 | maskreg
1482 | performancereg
1483 | statereg
1484 ;
1485
1486 dstreg:
1487 directgenreg
1488 {
1489 $$ = $1;
1490 $$.address_mode = BRW_ADDRESS_DIRECT;
1491 }
1492 | indirectgenreg
1493 {
1494 $$ = $1;
1495 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1496 }
1497 | directmsgreg
1498 {
1499 $$ = $1;
1500 $$.address_mode = BRW_ADDRESS_DIRECT;
1501 }
1502 | indirectmsgreg
1503 {
1504 $$ = $1;
1505 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1506 }
1507 ;
1508
1509 /* Source register */
1510 srcaccimm:
1511 srcacc
1512 | immreg
1513 ;
1514
1515 immreg:
1516 immval srcimmtype
1517 {
1518 uint32_t u32;
1519 uint64_t u64;
1520 switch ($2.type) {
1521 case BRW_REGISTER_TYPE_UD:
1522 u32 = $1;
1523 $$ = brw_imm_ud(u32);
1524 break;
1525 case BRW_REGISTER_TYPE_D:
1526 $$ = brw_imm_d($1);
1527 break;
1528 case BRW_REGISTER_TYPE_UW:
1529 u32 = $1 | ($1 << 16);
1530 $$ = brw_imm_uw(u32);
1531 break;
1532 case BRW_REGISTER_TYPE_W:
1533 u32 = $1;
1534 $$ = brw_imm_w(u32);
1535 break;
1536 case BRW_REGISTER_TYPE_F:
1537 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1538 $$.u64 = $1;
1539 $$.ud = $1;
1540 break;
1541 case BRW_REGISTER_TYPE_V:
1542 $$ = brw_imm_v($1);
1543 break;
1544 case BRW_REGISTER_TYPE_UV:
1545 $$ = brw_imm_uv($1);
1546 break;
1547 case BRW_REGISTER_TYPE_VF:
1548 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1549 $$.d = $1;
1550 break;
1551 case BRW_REGISTER_TYPE_Q:
1552 u64 = $1;
1553 $$ = brw_imm_q(u64);
1554 break;
1555 case BRW_REGISTER_TYPE_UQ:
1556 u64 = $1;
1557 $$ = brw_imm_uq(u64);
1558 break;
1559 case BRW_REGISTER_TYPE_DF:
1560 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1561 $$.d64 = $1;
1562 break;
1563 default:
1564 error(&@2, "Unkown immdediate type %s\n",
1565 brw_reg_type_to_letters($2.type));
1566 }
1567 }
1568 ;
1569
1570 reg32:
1571 directgenreg region srctype
1572 {
1573 $$ = set_direct_src_operand(&$1, $3.type);
1574 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1575 }
1576 ;
1577
1578 payload:
1579 directsrcoperand
1580 ;
1581
1582 src:
1583 directsrcoperand
1584 | indirectsrcoperand
1585 ;
1586
1587 srcacc:
1588 directsrcaccoperand
1589 | indirectsrcoperand
1590 ;
1591
1592 srcimm:
1593 directsrcoperand
1594 | indirectsrcoperand
1595 | immreg
1596 ;
1597
1598 directsrcaccoperand:
1599 directsrcoperand
1600 | accreg region srctype
1601 {
1602 $$ = set_direct_src_operand(&$1, $3.type);
1603 $$.vstride = $2.vstride;
1604 $$.width = $2.width;
1605 $$.hstride = $2.hstride;
1606 }
1607 ;
1608
1609 srcarcoperandex:
1610 srcarcoperandex_typed region srctype
1611 {
1612 $$ = brw_reg($1.file,
1613 $1.nr,
1614 $1.subnr,
1615 0,
1616 0,
1617 $3.type,
1618 $2.vstride,
1619 $2.width,
1620 $2.hstride,
1621 BRW_SWIZZLE_NOOP,
1622 WRITEMASK_XYZW);
1623 }
1624 | nullreg region srctype
1625 {
1626 $$ = set_direct_src_operand(&$1, $3.type);
1627 $$.vstride = $2.vstride;
1628 $$.width = $2.width;
1629 $$.hstride = $2.hstride;
1630 }
1631 | threadcontrolreg
1632 {
1633 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1634 }
1635 ;
1636
1637 srcarcoperandex_typed:
1638 channelenablereg
1639 | controlreg
1640 | flagreg
1641 | ipreg
1642 | maskreg
1643 | statereg
1644 ;
1645
1646 indirectsrcoperand:
1647 negate abs indirectgenreg indirectregion swizzle srctype
1648 {
1649 $$ = brw_reg($3.file,
1650 0,
1651 $3.subnr,
1652 $1, // negate
1653 $2, // abs
1654 $6.type,
1655 $4.vstride,
1656 $4.width,
1657 $4.hstride,
1658 $5.swizzle,
1659 WRITEMASK_X);
1660
1661 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1662 // brw_reg set indirect_offset to 0 so set it to valid value
1663 $$.indirect_offset = $3.indirect_offset;
1664 }
1665 ;
1666
1667 directgenreg_list:
1668 directgenreg
1669 | directmsgreg
1670 | notifyreg
1671 | addrreg
1672 | performancereg
1673 ;
1674
1675 directsrcoperand:
1676 negate abs directgenreg_list region swizzle srctype
1677 {
1678 $$ = brw_reg($3.file,
1679 $3.nr,
1680 $3.subnr,
1681 $1,
1682 $2,
1683 $6.type,
1684 $4.vstride,
1685 $4.width,
1686 $4.hstride,
1687 $5.swizzle,
1688 WRITEMASK_X);
1689 }
1690 | srcarcoperandex
1691 ;
1692
1693 /* Address register */
1694 addrparam:
1695 addrreg exp
1696 {
1697 memset(&$$, '\0', sizeof($$));
1698 $$.subnr = $1.subnr;
1699 $$.indirect_offset = $2;
1700 }
1701 | addrreg
1702 ;
1703
1704 /* Register files and register numbers */
1705 exp:
1706 INTEGER { $$ = $1; }
1707 | LONG { $$ = $1; }
1708 ;
1709
1710 subregnum:
1711 DOT exp { $$ = $2; }
1712 | %empty %prec SUBREGNUM { $$ = 0; }
1713 ;
1714
1715 directgenreg:
1716 GENREG subregnum
1717 {
1718 memset(&$$, '\0', sizeof($$));
1719 $$.file = BRW_GENERAL_REGISTER_FILE;
1720 $$.nr = $1;
1721 $$.subnr = $2;
1722 }
1723 ;
1724
1725 indirectgenreg:
1726 GENREGFILE LSQUARE addrparam RSQUARE
1727 {
1728 memset(&$$, '\0', sizeof($$));
1729 $$.file = BRW_GENERAL_REGISTER_FILE;
1730 $$.subnr = $3.subnr;
1731 $$.indirect_offset = $3.indirect_offset;
1732 }
1733 ;
1734
1735 directmsgreg:
1736 MSGREG subregnum
1737 {
1738 $$ = brw_message_reg($1);
1739 $$.subnr = $2;
1740 }
1741 ;
1742
1743 indirectmsgreg:
1744 MSGREGFILE LSQUARE addrparam RSQUARE
1745 {
1746 memset(&$$, '\0', sizeof($$));
1747 $$.file = BRW_MESSAGE_REGISTER_FILE;
1748 $$.subnr = $3.subnr;
1749 $$.indirect_offset = $3.indirect_offset;
1750 }
1751 ;
1752
1753 addrreg:
1754 ADDRREG subregnum
1755 {
1756 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1757
1758 if ($2 > subnr)
1759 error(&@2, "Address sub resgister number %d"
1760 "out of range\n", $2);
1761
1762 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1763 $$.nr = BRW_ARF_ADDRESS;
1764 $$.subnr = $2;
1765 }
1766 ;
1767
1768 accreg:
1769 ACCREG subregnum
1770 {
1771 int nr_reg;
1772 if (p->devinfo->gen < 8)
1773 nr_reg = 2;
1774 else
1775 nr_reg = 10;
1776
1777 if ($1 > nr_reg)
1778 error(&@1, "Accumulator register number %d"
1779 " out of range\n", $1);
1780
1781 memset(&$$, '\0', sizeof($$));
1782 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1783 $$.nr = BRW_ARF_ACCUMULATOR;
1784 $$.subnr = $2;
1785 }
1786 ;
1787
1788 flagreg:
1789 FLAGREG subregnum
1790 {
1791 // SNB = 1 flag reg and IVB+ = 2 flag reg
1792 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1793 int subnr = nr_reg;
1794
1795 if ($1 > nr_reg)
1796 error(&@1, "Flag register number %d"
1797 " out of range \n", $1);
1798 if ($2 > subnr)
1799 error(&@2, "Flag subregister number %d"
1800 " out of range\n", $2);
1801
1802 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1803 $$.nr = BRW_ARF_FLAG | $1;
1804 $$.subnr = $2;
1805 }
1806 ;
1807
1808 maskreg:
1809 MASKREG subregnum
1810 {
1811 if ($1 > 0)
1812 error(&@1, "Mask register number %d"
1813 " out of range\n", $1);
1814
1815 $$ = brw_mask_reg($2);
1816 }
1817 ;
1818
1819 notifyreg:
1820 NOTIFYREG subregnum
1821 {
1822 if ($1 > 0)
1823 error(&@1, "Notification register number %d"
1824 " out of range\n", $1);
1825
1826 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1827 if ($2 > subnr)
1828 error(&@2, "Notification sub register number %d"
1829 " out of range\n", $2);
1830
1831 $$ = brw_notification_reg();
1832 $$.subnr = $2;
1833 }
1834 ;
1835
1836 statereg:
1837 STATEREG subregnum
1838 {
1839 if ($1 > 2)
1840 error(&@1, "State register number %d"
1841 " out of range\n", $1);
1842
1843 if ($2 > 4)
1844 error(&@2, "State sub register number %d"
1845 " out of range\n", $2);
1846
1847 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1848 $$.nr = BRW_ARF_STATE;
1849 $$.subnr = $2;
1850 }
1851 ;
1852
1853 controlreg:
1854 CONTROLREG subregnum
1855 {
1856 if ($2 > 3)
1857 error(&@2, "control sub register number %d"
1858 " out of range\n", $2);
1859
1860 $$ = brw_cr0_reg($2);
1861 }
1862 ;
1863
1864 ipreg:
1865 IPREG { $$ = brw_ip_reg(); }
1866 ;
1867
1868 nullreg:
1869 NULL_TOKEN { $$ = brw_null_reg(); }
1870 ;
1871
1872 threadcontrolreg:
1873 THREADREG subregnum
1874 {
1875 if ($1 > 0)
1876 error(&@1, "Thread control register number %d"
1877 " out of range\n", $1);
1878
1879 if ($2 > 7)
1880 error(&@2, "Thread control sub register number %d"
1881 " out of range\n", $2);
1882
1883 $$ = brw_tdr_reg();
1884 $$.subnr = $2;
1885 }
1886 ;
1887
1888 performancereg:
1889 PERFORMANCEREG subregnum
1890 {
1891 int subnr;
1892 if (p->devinfo->gen >= 10)
1893 subnr = 5;
1894 else if (p->devinfo->gen <= 8)
1895 subnr = 3;
1896 else
1897 subnr = 4;
1898
1899 if ($2 > subnr)
1900 error(&@2, "Performance sub register number %d"
1901 " out of range\n", $2);
1902
1903 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1904 $$.nr = BRW_ARF_TIMESTAMP;
1905 }
1906 ;
1907
1908 channelenablereg:
1909 CHANNELENABLEREG subregnum
1910 {
1911 if ($1 > 0)
1912 error(&@1, "Channel enable register number %d"
1913 " out of range\n", $1);
1914
1915 $$ = brw_mask_reg($2);
1916 }
1917 ;
1918
1919 /* Immediate values */
1920 immval:
1921 exp2
1922 {
1923 $$ = $1;
1924 }
1925 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1926 {
1927 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1928 }
1929 ;
1930
1931 /* Regions */
1932 dstregion:
1933 %empty { $$ = -1; }
1934 | LANGLE exp RANGLE
1935 {
1936 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1937 error(&@2, "Invalid Horizontal stride %d\n", $2);
1938
1939 $$ = ffs($2);
1940 }
1941 ;
1942
1943 indirectregion:
1944 region
1945 | region_wh
1946 ;
1947
1948 region:
1949 %empty
1950 {
1951 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1952 }
1953 | LANGLE exp RANGLE
1954 {
1955 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1956 error(&@2, "Invalid VertStride %d\n", $2);
1957
1958 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1959 }
1960 | LANGLE exp COMMA exp COMMA exp RANGLE
1961 {
1962
1963 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1964 error(&@2, "Invalid VertStride %d\n", $2);
1965
1966 if ($4 > 16 || !isPowerofTwo($4))
1967 error(&@4, "Invalid width %d\n", $4);
1968
1969 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1970 error(&@6, "Invalid Horizontal stride in"
1971 " region_wh %d\n", $6);
1972
1973 $$ = stride($$, $2, $4, $6);
1974 }
1975 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1976 {
1977 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1978 error(&@2, "Invalid VertStride %d\n", $2);
1979
1980 if ($4 > 16 || !isPowerofTwo($4))
1981 error(&@4, "Invalid width %d\n", $4);
1982
1983 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1984 error(&@6, "Invalid Horizontal stride in"
1985 " region_wh %d\n", $6);
1986
1987 $$ = stride($$, $2, $4, $6);
1988 }
1989 | LANGLE VxH COMMA exp COMMA exp RANGLE
1990 {
1991 if ($4 > 16 || !isPowerofTwo($4))
1992 error(&@4, "Invalid width %d\n", $4);
1993
1994 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1995 error(&@6, "Invalid Horizontal stride in"
1996 " region_wh %d\n", $6);
1997
1998 $$ = brw_VxH_indirect(0, 0);
1999 }
2000 ;
2001
2002 region_wh:
2003 LANGLE exp COMMA exp RANGLE
2004 {
2005 if ($2 > 16 || !isPowerofTwo($2))
2006 error(&@2, "Invalid width %d\n", $2);
2007
2008 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2009 error(&@4, "Invalid Horizontal stride in"
2010 " region_wh %d\n", $4);
2011
2012 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2013 }
2014 ;
2015
2016 srctype:
2017 %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2018 | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2019 | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2020 | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2021 | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2022 | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2023 | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2024 | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2025 | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2026 | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2027 | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2028 | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2029 | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2030 ;
2031
2032 srcimmtype:
2033 srctype { $$ = $1; }
2034 | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2035 | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2036 | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2037 ;
2038
2039 dsttype:
2040 srctype { $$ = $1; }
2041 ;
2042
2043 writemask:
2044 %empty
2045 {
2046 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2047 }
2048 | DOT writemask_x writemask_y writemask_z writemask_w
2049 {
2050 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2051 }
2052 ;
2053
2054 writemask_x:
2055 %empty { $$ = 0; }
2056 | X { $$ = 1 << BRW_CHANNEL_X; }
2057 ;
2058
2059 writemask_y:
2060 %empty { $$ = 0; }
2061 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2062 ;
2063
2064 writemask_z:
2065 %empty { $$ = 0; }
2066 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2067 ;
2068
2069 writemask_w:
2070 %empty { $$ = 0; }
2071 | W { $$ = 1 << BRW_CHANNEL_W; }
2072 ;
2073
2074 swizzle:
2075 %empty
2076 {
2077 $$.swizzle = BRW_SWIZZLE_NOOP;
2078 }
2079 | DOT chansel
2080 {
2081 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2082 }
2083 | DOT chansel chansel chansel chansel
2084 {
2085 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2086 }
2087 ;
2088
2089 chansel:
2090 X
2091 | Y
2092 | Z
2093 | W
2094 ;
2095
2096 /* Instruction prediction and modifiers */
2097 predicate:
2098 %empty
2099 {
2100 brw_push_insn_state(p);
2101 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2102 brw_set_default_flag_reg(p, 0, 0);
2103 brw_set_default_predicate_inverse(p, false);
2104 }
2105 | LPAREN predstate flagreg predctrl RPAREN
2106 {
2107 brw_push_insn_state(p);
2108 brw_set_default_predicate_inverse(p, $2);
2109 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2110 brw_set_default_predicate_control(p, $4);
2111 }
2112 ;
2113
2114 predstate:
2115 %empty { $$ = 0; }
2116 | PLUS { $$ = 0; }
2117 | MINUS { $$ = 1; }
2118 ;
2119
2120 predctrl:
2121 %empty { $$ = BRW_PREDICATE_NORMAL; }
2122 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2123 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2124 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2125 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2126 | ANYV
2127 | ALLV
2128 | ANY2H
2129 | ALL2H
2130 | ANY4H
2131 | ALL4H
2132 | ANY8H
2133 | ALL8H
2134 | ANY16H
2135 | ALL16H
2136 | ANY32H
2137 | ALL32H
2138 ;
2139
2140 /* Source Modification */
2141 negate:
2142 %empty { $$ = 0; }
2143 | MINUS { $$ = 1; }
2144 ;
2145
2146 abs:
2147 %empty { $$ = 0; }
2148 | ABS { $$ = 1; }
2149 ;
2150
2151 /* Flag (Conditional) Modifier */
2152 cond_mod:
2153 condModifiers
2154 {
2155 $$.cond_modifier = $1;
2156 $$.flag_reg_nr = 0;
2157 $$.flag_subreg_nr = 0;
2158 }
2159 | condModifiers DOT flagreg
2160 {
2161 $$.cond_modifier = $1;
2162 $$.flag_reg_nr = $3.nr;
2163 $$.flag_subreg_nr = $3.subnr;
2164 }
2165 ;
2166
2167 condModifiers:
2168 %empty { $$ = BRW_CONDITIONAL_NONE; }
2169 | ZERO
2170 | EQUAL
2171 | NOT_ZERO
2172 | NOT_EQUAL
2173 | GREATER
2174 | GREATER_EQUAL
2175 | LESS
2176 | LESS_EQUAL
2177 | OVERFLOW
2178 | ROUND_INCREMENT
2179 | UNORDERED
2180 ;
2181
2182 saturate:
2183 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2184 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2185 ;
2186
2187 /* Execution size */
2188 execsize:
2189 %empty %prec EMPTYEXECSIZE
2190 {
2191 $$ = 0;
2192 }
2193 | LPAREN exp2 RPAREN
2194 {
2195 if ($2 > 32 || !isPowerofTwo($2))
2196 error(&@2, "Invalid execution size %d\n", $2);
2197
2198 $$ = cvt($2) - 1;
2199 }
2200 ;
2201
2202 /* Instruction options */
2203 instoptions:
2204 %empty
2205 {
2206 memset(&$$, 0, sizeof($$));
2207 }
2208 | LCURLY instoption_list RCURLY
2209 {
2210 memset(&$$, 0, sizeof($$));
2211 $$ = $2;
2212 }
2213 ;
2214
2215 instoption_list:
2216 instoption_list COMMA instoption
2217 {
2218 memset(&$$, 0, sizeof($$));
2219 $$ = $1;
2220 add_instruction_option(&$$, $3);
2221 }
2222 | instoption_list instoption
2223 {
2224 memset(&$$, 0, sizeof($$));
2225 $$ = $1;
2226 add_instruction_option(&$$, $2);
2227 }
2228 | %empty
2229 {
2230 memset(&$$, 0, sizeof($$));
2231 }
2232 ;
2233
2234 instoption:
2235 ALIGN1 { $$ = ALIGN1;}
2236 | ALIGN16 { $$ = ALIGN16; }
2237 | ACCWREN { $$ = ACCWREN; }
2238 | SECHALF { $$ = SECHALF; }
2239 | COMPR { $$ = COMPR; }
2240 | COMPR4 { $$ = COMPR4; }
2241 | BREAKPOINT { $$ = BREAKPOINT; }
2242 | NODDCLR { $$ = NODDCLR; }
2243 | NODDCHK { $$ = NODDCHK; }
2244 | MASK_DISABLE { $$ = MASK_DISABLE; }
2245 | EOT { $$ = EOT; }
2246 | SWITCH { $$ = SWITCH; }
2247 | ATOMIC { $$ = ATOMIC; }
2248 | CMPTCTRL { $$ = CMPTCTRL; }
2249 | WECTRL { $$ = WECTRL; }
2250 | QTR_2Q { $$ = QTR_2Q; }
2251 | QTR_3Q { $$ = QTR_3Q; }
2252 | QTR_4Q { $$ = QTR_4Q; }
2253 | QTR_2H { $$ = QTR_2H; }
2254 | QTR_2N { $$ = QTR_2N; }
2255 | QTR_3N { $$ = QTR_3N; }
2256 | QTR_4N { $$ = QTR_4N; }
2257 | QTR_5N { $$ = QTR_5N; }
2258 | QTR_6N { $$ = QTR_6N; }
2259 | QTR_7N { $$ = QTR_7N; }
2260 | QTR_8N { $$ = QTR_8N; }
2261 ;
2262
2263 %%
2264
2265 extern int yylineno;
2266
2267 void
2268 yyerror(char *msg)
2269 {
2270 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2271 input_filename, yylineno, msg, lex_text());
2272 ++errors;
2273 }