src/intel/tools/i965_gram.y

   1 %{
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <strings.h>
  29 #include "i965_asm.h"
  30
  31 #define YYLTYPE YYLTYPE
  32 typedef struct YYLTYPE
  33 {
  34         int first_line;
  35         int first_column;
  36         int last_line;
  37         int last_column;
  38 } YYLTYPE;
  39
  40 enum message_level {
  41         WARN,
  42         ERROR,
  43 };
  44
  45 int yydebug = 1;
  46
  47 static void
  48 message(enum message_level level, YYLTYPE *location,
  49         const char *fmt, ...)
  50 {
  51         static const char *level_str[] = { "warning", "error" };
  52         va_list args;
  53
  54         if (location)
  55                 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
  56                         location->first_line,
  57                         location->first_column, level_str[level]);
  58         else
  59                 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
  60
  61         va_start(args, fmt);
  62         vfprintf(stderr, fmt, args);
  63         va_end(args);
  64 }
  65
  66 #define warn(flag, l, fmt, ...)                                  \
  67         do {                                                     \
  68                 if (warning_flags & WARN_ ## flag)               \
  69                         message(WARN, l, fmt, ## __VA_ARGS__);   \
  70         } while (0)
  71
  72 #define error(l, fmt, ...)                                       \
  73         do {                                                     \
  74                 message(ERROR, l, fmt, ## __VA_ARGS__);          \
  75         } while (0)
  76
  77 static bool
  78 isPowerofTwo(unsigned int x)
  79 {
  80         return x && (!(x & (x - 1)));
  81 }
  82
  83 static struct brw_reg
  84 set_direct_src_operand(struct brw_reg *reg, int type)
  85 {
  86         return brw_reg(reg->file,
  87                        reg->nr,
  88                        reg->subnr,
  89                        0,               // negate
  90                        0,               // abs
  91                        type,
  92                        0,               // vstride
  93                        0,               // width
  94                        0,               // hstride
  95                        BRW_SWIZZLE_NOOP,
  96                        WRITEMASK_XYZW);
  97 }
  98
  99 static void
 100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
 101                            struct brw_reg dest, struct brw_reg src0)
 102 {
 103         switch (opcode) {
 104         case BRW_OPCODE_BFREV:
 105                 brw_BFREV(p, dest, src0);
 106                 break;
 107         case BRW_OPCODE_CBIT:
 108                 brw_CBIT(p, dest, src0);
 109                 break;
 110         case BRW_OPCODE_F32TO16:
 111                 brw_F32TO16(p, dest, src0);
 112                 break;
 113         case BRW_OPCODE_F16TO32:
 114                 brw_F16TO32(p, dest, src0);
 115                 break;
 116         case BRW_OPCODE_MOV:
 117                 brw_MOV(p, dest, src0);
 118                 break;
 119         case BRW_OPCODE_FBL:
 120                 brw_FBL(p, dest, src0);
 121                 break;
 122         case BRW_OPCODE_FRC:
 123                 brw_FRC(p, dest, src0);
 124                 break;
 125         case BRW_OPCODE_FBH:
 126                 brw_FBH(p, dest, src0);
 127                 break;
 128         case BRW_OPCODE_NOT:
 129                 brw_NOT(p, dest, src0);
 130                 break;
 131         case BRW_OPCODE_RNDE:
 132                 brw_RNDE(p, dest, src0);
 133                 break;
 134         case BRW_OPCODE_RNDZ:
 135                 brw_RNDZ(p, dest, src0);
 136                 break;
 137         case BRW_OPCODE_RNDD:
 138                 brw_RNDD(p, dest, src0);
 139                 break;
 140         case BRW_OPCODE_LZD:
 141                 brw_LZD(p, dest, src0);
 142                 break;
 143         case BRW_OPCODE_DIM:
 144                 brw_DIM(p, dest, src0);
 145                 break;
 146         case BRW_OPCODE_RNDU:
 147                 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
 148                 break;
 149         default:
 150                 fprintf(stderr, "Unsupported unary opcode\n");
 151         }
 152 }
 153
 154 static void
 155 i965_asm_binary_instruction(int opcode,
 156                             struct brw_codegen *p,
 157                             struct brw_reg dest,
 158                             struct brw_reg src0,
 159                             struct brw_reg src1)
 160 {
 161         switch (opcode) {
 162         case BRW_OPCODE_ADDC:
 163                 brw_ADDC(p, dest, src0, src1);
 164                 break;
 165         case BRW_OPCODE_BFI1:
 166                 brw_BFI1(p, dest, src0, src1);
 167                 break;
 168         case BRW_OPCODE_DP2:
 169                 brw_DP2(p, dest, src0, src1);
 170                 break;
 171         case BRW_OPCODE_DP3:
 172                 brw_DP3(p, dest, src0, src1);
 173                 break;
 174         case BRW_OPCODE_DP4:
 175                 brw_DP4(p, dest, src0, src1);
 176                 break;
 177         case BRW_OPCODE_DPH:
 178                 brw_DPH(p, dest, src0, src1);
 179                 break;
 180         case BRW_OPCODE_LINE:
 181                 brw_LINE(p, dest, src0, src1);
 182                 break;
 183         case BRW_OPCODE_MAC:
 184                 brw_MAC(p, dest, src0, src1);
 185                 break;
 186         case BRW_OPCODE_MACH:
 187                 brw_MACH(p, dest, src0, src1);
 188                 break;
 189         case BRW_OPCODE_PLN:
 190                 brw_PLN(p, dest, src0, src1);
 191                 break;
 192         case BRW_OPCODE_ROL:
 193                 brw_ROL(p, dest, src0, src1);
 194                 break;
 195         case BRW_OPCODE_ROR:
 196                 brw_ROR(p, dest, src0, src1);
 197                 break;
 198         case BRW_OPCODE_SAD2:
 199                 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
 200                 break;
 201         case BRW_OPCODE_SADA2:
 202                 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
 203                 break;
 204         case BRW_OPCODE_SUBB:
 205                 brw_SUBB(p, dest, src0, src1);
 206                 break;
 207         case BRW_OPCODE_ADD:
 208                 brw_ADD(p, dest, src0, src1);
 209                 break;
 210         case BRW_OPCODE_CMP:
 211                 /* Third parameter is conditional modifier
 212                  * which gets updated later
 213                  */
 214                 brw_CMP(p, dest, 0, src0, src1);
 215                 break;
 216         case BRW_OPCODE_AND:
 217                 brw_AND(p, dest, src0, src1);
 218                 break;
 219         case BRW_OPCODE_ASR:
 220                 brw_ASR(p, dest, src0, src1);
 221                 break;
 222         case BRW_OPCODE_AVG:
 223                 brw_AVG(p, dest, src0, src1);
 224                 break;
 225         case BRW_OPCODE_OR:
 226                 brw_OR(p, dest, src0, src1);
 227                 break;
 228         case BRW_OPCODE_SEL:
 229                 brw_SEL(p, dest, src0, src1);
 230                 break;
 231         case BRW_OPCODE_SHL:
 232                 brw_SHL(p, dest, src0, src1);
 233                 break;
 234         case BRW_OPCODE_SHR:
 235                 brw_SHR(p, dest, src0, src1);
 236                 break;
 237         case BRW_OPCODE_XOR:
 238                 brw_XOR(p, dest, src0, src1);
 239                 break;
 240         case BRW_OPCODE_MUL:
 241                 brw_MUL(p, dest, src0, src1);
 242                 break;
 243         default:
 244                 fprintf(stderr, "Unsupported binary opcode\n");
 245         }
 246 }
 247
 248 static void
 249 i965_asm_ternary_instruction(int opcode,
 250                              struct brw_codegen *p,
 251                              struct brw_reg dest,
 252                              struct brw_reg src0,
 253                              struct brw_reg src1,
 254                              struct brw_reg src2)
 255 {
 256         switch (opcode) {
 257         case BRW_OPCODE_MAD:
 258                 brw_MAD(p, dest, src0, src1, src2);
 259                 break;
 260         case BRW_OPCODE_CSEL:
 261                 brw_CSEL(p, dest, src0, src1, src2);
 262                 break;
 263         case BRW_OPCODE_LRP:
 264                 brw_LRP(p, dest, src0, src1, src2);
 265                 break;
 266         case BRW_OPCODE_BFE:
 267                 brw_BFE(p, dest, src0, src1, src2);
 268                 break;
 269         case BRW_OPCODE_BFI2:
 270                 brw_BFI2(p, dest, src0, src1, src2);
 271                 break;
 272         default:
 273                 fprintf(stderr, "Unsupported ternary opcode\n");
 274         }
 275 }
 276
 277 static void
 278 i965_asm_set_instruction_options(struct brw_codegen *p,
 279                                  struct options options)
 280 {
 281         brw_inst_set_access_mode(p->devinfo, brw_last_inst,
 282                                  options.access_mode);
 283         brw_inst_set_mask_control(p->devinfo, brw_last_inst,
 284                                   options.mask_control);
 285         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
 286                                     options.thread_control);
 287         brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
 288                                  options.no_dd_check);
 289         brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 290                                  options.no_dd_clear);
 291         brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 292                                    options.debug_control);
 293         if (p->devinfo->gen >= 6)
 294                 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
 295                                             options.acc_wr_control);
 296         brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
 297                                   options.compaction);
 298 }
 299
 300 static void
 301 i965_asm_set_dst_nr(struct brw_codegen *p,
 302                     struct brw_reg *reg,
 303                     struct options options)
 304 {
 305         if (p->devinfo->gen <= 6) {
 306                 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
 307                     options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
 308                     !options.is_compr)
 309                         reg->nr |= BRW_MRF_COMPR4;
 310         }
 311 }
 312
 313 %}
 314
 315 %locations
 316
 317 %start ROOT
 318
 319 %union {
 320         double number;
 321         int integer;
 322         unsigned long long int llint;
 323         struct brw_reg reg;
 324         enum brw_reg_type reg_type;
 325         struct brw_codegen *program;
 326         struct predicate predicate;
 327         struct condition condition;
 328         struct options options;
 329         brw_inst *instruction;
 330 }
 331
 332 %token ABS
 333 %token COLON
 334 %token COMMA
 335 %token DOT
 336 %token LANGLE RANGLE
 337 %token LCURLY RCURLY
 338 %token LPAREN RPAREN
 339 %token LSQUARE RSQUARE
 340 %token PLUS MINUS
 341 %token SEMICOLON
 342
 343 /* datatypes */
 344 %token <integer> TYPE_B TYPE_UB
 345 %token <integer> TYPE_W TYPE_UW
 346 %token <integer> TYPE_D TYPE_UD
 347 %token <integer> TYPE_Q TYPE_UQ
 348 %token <integer> TYPE_V TYPE_UV
 349 %token <integer> TYPE_F TYPE_HF
 350 %token <integer> TYPE_DF TYPE_NF
 351 %token <integer> TYPE_VF
 352
 353 /* opcodes */
 354 %token <integer> ADD ADD3 ADDC AND ASR AVG
 355 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 356 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
 357 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
 358 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
 359 %token <integer> GOTO
 360 %token <integer> HALT
 361 %token <integer> IF IFF ILLEGAL
 362 %token <integer> JMPI JOIN
 363 %token <integer> LINE LRP LZD
 364 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
 365 %token <integer> NENOP NOP NOT
 366 %token <integer> OR
 367 %token <integer> PLN POP PUSH
 368 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
 369 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
 370 %token <integer> WAIT WHILE
 371 %token <integer> XOR
 372
 373 /* extended math functions */
 374 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
 375 %token <integer> RSQRTM SIN SINCOS SQRT
 376
 377 /* shared functions for send */
 378 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
 379 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
 380
 381 /* Conditional modifiers */
 382 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
 383 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
 384
 385 /* register Access Modes */
 386 %token ALIGN1 ALIGN16
 387
 388 /* accumulator write control */
 389 %token ACCWREN
 390
 391 /* compaction control */
 392 %token CMPTCTRL
 393
 394 /* compression control */
 395 %token COMPR COMPR4 SECHALF
 396
 397 /* mask control (WeCtrl) */
 398 %token WECTRL
 399
 400 /* debug control */
 401 %token BREAKPOINT
 402
 403 /* dependency control */
 404 %token NODDCLR NODDCHK
 405
 406 /* end of thread */
 407 %token EOT
 408
 409 /* mask control */
 410 %token MASK_DISABLE;
 411
 412 /* predicate control */
 413 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
 414 %token <integer> ANY32H ALL32H
 415
 416 /* round instructions */
 417 %token <integer> ROUND_INCREMENT
 418
 419 /* staturation */
 420 %token SATURATE
 421
 422 /* thread control */
 423 %token ATOMIC SWITCH
 424
 425 /* quater control */
 426 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
 427 %token QTR_6N QTR_7N QTR_8N
 428
 429 /* channels */
 430 %token <integer> X Y Z W
 431
 432 /* reg files */
 433 %token GENREGFILE MSGREGFILE
 434
 435 /* vertical stride in register region */
 436 %token VxH
 437
 438 /* register type */
 439 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
 440 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
 441 %token <integer> MASKREG
 442
 443 %token <integer> INTEGER
 444 %token <llint> LONG
 445 %token NULL_TOKEN
 446
 447 %precedence SUBREGNUM
 448 %left PLUS MINUS
 449 %precedence DOT
 450 %precedence EMPTYEXECSIZE
 451 %precedence LPAREN
 452
 453 %type <integer> execsize simple_int exp
 454 %type <llint> exp2
 455
 456 /* predicate control */
 457 %type <integer> predctrl predstate
 458 %type <predicate> predicate
 459
 460 /* conditional modifier */
 461 %type <condition> cond_mod
 462 %type <integer> condModifiers
 463
 464 /* instruction options  */
 465 %type <options> instoptions instoption_list
 466 %type <integer> instoption
 467
 468 /* writemask */
 469 %type <integer> writemask_x writemask_y writemask_z writemask_w
 470 %type <integer> writemask
 471
 472 /* dst operand */
 473 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
 474 %type <integer> dstregion
 475
 476 %type <integer> saturate relativelocation rellocation
 477 %type <reg> relativelocation2
 478
 479 /* src operand */
 480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
 482 %type <reg> indirectgenreg indirectregion
 483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 484 %type <reg> region_wh directgenreg directmsgreg indirectmsgreg
 485 %type <integer> swizzle
 486
 487 /* registers */
 488 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
 489 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
 490 %type <integer> subregnum
 491
 492 /* register types */
 493 %type <reg_type> reg_type imm_type
 494
 495 /* immediate values */
 496 %type <llint> immval
 497
 498 /* instruction opcodes */
 499 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
 500 %type <integer> sendop
 501 %type <instruction> sendopcode
 502
 503 %type <integer> negate abs chansel math_function sharedfunction
 504
 505 %code {
 506
 507 static void
 508 add_instruction_option(struct options *options, int option)
 509 {
 510         switch (option) {
 511         case ALIGN1:
 512                 options->access_mode = BRW_ALIGN_1;
 513                 break;
 514         case ALIGN16:
 515                 options->access_mode = BRW_ALIGN_16;
 516                 break;
 517         case SECHALF:
 518                 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
 519                 break;
 520         case COMPR:
 521                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 522                 options->is_compr = true;
 523                 break;
 524         case COMPR4:
 525                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 526                 break;
 527         case SWITCH:
 528                 options->thread_control |= BRW_THREAD_SWITCH;
 529                 break;
 530         case ATOMIC:
 531                 options->thread_control |= BRW_THREAD_ATOMIC;
 532                 break;
 533         case NODDCHK:
 534                 options->no_dd_check = true;
 535                 break;
 536         case NODDCLR:
 537                 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
 538                 break;
 539         case MASK_DISABLE:
 540                 options->mask_control |= BRW_MASK_DISABLE;
 541                 break;
 542         case BREAKPOINT:
 543                 options->debug_control = BRW_DEBUG_BREAKPOINT;
 544                 break;
 545         case WECTRL:
 546                 options->mask_control |= BRW_WE_ALL;
 547                 break;
 548         case CMPTCTRL:
 549                 options->compaction = true;
 550                 break;
 551         case ACCWREN:
 552                 options->acc_wr_control = true;
 553                 break;
 554         case EOT:
 555                 options->end_of_thread = true;
 556                 break;
 557         /* TODO : Figure out how to set instruction group and get rid of
 558          * code below
 559          */
 560         case QTR_2Q:
 561                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 562                 break;
 563         case QTR_3Q:
 564                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 565                 break;
 566         case QTR_4Q:
 567                 options->qtr_ctrl = 3;
 568                 break;
 569         case QTR_2H:
 570                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 571                 break;
 572         case QTR_2N:
 573                 options->qtr_ctrl = BRW_COMPRESSION_NONE;
 574                 options->nib_ctrl = true;
 575                 break;
 576         case QTR_3N:
 577                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 578                 break;
 579         case QTR_4N:
 580                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 581                 options->nib_ctrl = true;
 582                 break;
 583         case QTR_5N:
 584                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 585                 break;
 586         case QTR_6N:
 587                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 588                 options->nib_ctrl = true;
 589                 break;
 590         case QTR_7N:
 591                 options->qtr_ctrl = 3;
 592                 break;
 593         case QTR_8N:
 594                 options->qtr_ctrl = 3;
 595                 options->nib_ctrl = true;
 596                 break;
 597         }
 598 }
 599 }
 600 %%
 601
 602 ROOT:
 603         instrseq
 604         ;
 605
 606 instrseq:
 607         instrseq instruction SEMICOLON
 608         | instrseq relocatableinstruction SEMICOLON
 609         | instruction SEMICOLON
 610         | relocatableinstruction SEMICOLON
 611         ;
 612
 613 /* Instruction Group */
 614 instruction:
 615         unaryinstruction
 616         | binaryinstruction
 617         | binaryaccinstruction
 618         | mathinstruction
 619         | nopinstruction
 620         | syncinstruction
 621         | ternaryinstruction
 622         | sendinstruction
 623         | illegalinstruction
 624         ;
 625
 626 relocatableinstruction:
 627         jumpinstruction
 628         | branchinstruction
 629         | breakinstruction
 630         | loopinstruction
 631         ;
 632
 633 illegalinstruction:
 634         ILLEGAL execsize instoptions
 635         {
 636                 brw_next_insn(p, $1);
 637                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 638                 i965_asm_set_instruction_options(p, $3);
 639         }
 640         ;
 641
 642 /* Unary instruction */
 643 unaryinstruction:
 644         predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
 645         {
 646                 i965_asm_set_dst_nr(p, &$6, $8);
 647                 brw_set_default_access_mode(p, $8.access_mode);
 648                 i965_asm_unary_instruction($2, p, $6, $7);
 649                 brw_pop_insn_state(p);
 650                 i965_asm_set_instruction_options(p, $8);
 651                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 652                                            $4.cond_modifier);
 653
 654                 if (p->devinfo->gen >= 7) {
 655                         if ($2 != BRW_OPCODE_DIM) {
 656                                 brw_inst_set_flag_reg_nr(p->devinfo,
 657                                                          brw_last_inst,
 658                                                          $4.flag_reg_nr);
 659                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 660                                                             brw_last_inst,
 661                                                             $4.flag_subreg_nr);
 662                         }
 663                 }
 664
 665                 if ($7.file != BRW_IMMEDIATE_VALUE) {
 666                         brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
 667                                                   $7.vstride);
 668                 }
 669                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 670                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 671                 // TODO: set instruction group instead of qtr and nib ctrl
 672                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 673                                          $8.qtr_ctrl);
 674
 675                 if (p->devinfo->gen >= 7)
 676                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 677                                                  $8.nib_ctrl);
 678         }
 679         ;
 680
 681 unaryopcodes:
 682         BFREV
 683         | CBIT
 684         | DIM
 685         | F16TO32
 686         | F32TO16
 687         | FBH
 688         | FBL
 689         | FRC
 690         | LZD
 691         | MOV
 692         | NOT
 693         | RNDD
 694         | RNDE
 695         | RNDU
 696         | RNDZ
 697         ;
 698
 699 /* Binary instruction */
 700 binaryinstruction:
 701         predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
 702         {
 703                 i965_asm_set_dst_nr(p, &$6, $9);
 704                 brw_set_default_access_mode(p, $9.access_mode);
 705                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 706                 i965_asm_set_instruction_options(p, $9);
 707                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 708                                            $4.cond_modifier);
 709
 710                 if (p->devinfo->gen >= 7) {
 711                         brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
 712                                                  $4.flag_reg_nr);
 713                         brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
 714                                                     $4.flag_subreg_nr);
 715                 }
 716
 717                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 718                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 719                 // TODO: set instruction group instead of qtr and nib ctrl
 720                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 721                                          $9.qtr_ctrl);
 722
 723                 if (p->devinfo->gen >= 7)
 724                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 725                                                  $9.nib_ctrl);
 726
 727                 brw_pop_insn_state(p);
 728         }
 729         ;
 730
 731 binaryopcodes:
 732         ADDC
 733         | BFI1
 734         | DP2
 735         | DP3
 736         | DP4
 737         | DPH
 738         | LINE
 739         | MAC
 740         | MACH
 741         | MUL
 742         | PLN
 743         | ROL
 744         | ROR
 745         | SAD2
 746         | SADA2
 747         | SUBB
 748         ;
 749
 750 /* Binary acc instruction */
 751 binaryaccinstruction:
 752         predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
 753         {
 754                 i965_asm_set_dst_nr(p, &$6, $9);
 755                 brw_set_default_access_mode(p, $9.access_mode);
 756                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 757                 brw_pop_insn_state(p);
 758                 i965_asm_set_instruction_options(p, $9);
 759                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 760                                            $4.cond_modifier);
 761
 762                 if (p->devinfo->gen >= 7) {
 763                         if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
 764                                 brw_inst_set_flag_reg_nr(p->devinfo,
 765                                                          brw_last_inst,
 766                                                          $4.flag_reg_nr);
 767                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 768                                                             brw_last_inst,
 769                                                             $4.flag_subreg_nr);
 770                         }
 771                 }
 772
 773                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 774                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 775                 // TODO: set instruction group instead of qtr and nib ctrl
 776                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 777                                          $9.qtr_ctrl);
 778
 779                 if (p->devinfo->gen >= 7)
 780                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 781                                                  $9.nib_ctrl);
 782         }
 783         ;
 784
 785 binaryaccopcodes:
 786         ADD
 787         | AND
 788         | ASR
 789         | AVG
 790         | CMP
 791         | CMPN
 792         | OR
 793         | SEL
 794         | SHL
 795         | SHR
 796         | XOR
 797         ;
 798
 799 /* Math instruction */
 800 mathinstruction:
 801         predicate MATH saturate math_function execsize dst src srcimm instoptions
 802         {
 803                 brw_set_default_access_mode(p, $9.access_mode);
 804                 gen6_math(p, $6, $4, $7, $8);
 805                 i965_asm_set_instruction_options(p, $9);
 806                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 807                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 808                 // TODO: set instruction group instead
 809                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 810                                          $9.qtr_ctrl);
 811
 812                 if (p->devinfo->gen >= 7)
 813                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 814                                                  $9.nib_ctrl);
 815
 816                 brw_pop_insn_state(p);
 817         }
 818         ;
 819
 820 math_function:
 821         COS
 822         | EXP
 823         | FDIV
 824         | INV
 825         | INVM
 826         | INTDIV
 827         | INTDIVMOD
 828         | INTMOD
 829         | LOG
 830         | POW
 831         | RSQ
 832         | RSQRTM
 833         | SIN
 834         | SQRT
 835         | SINCOS
 836         ;
 837
 838 /* NOP instruction */
 839 nopinstruction:
 840         NOP
 841         {
 842                 brw_NOP(p);
 843         }
 844         ;
 845
 846 /* Ternary operand instruction */
 847 ternaryinstruction:
 848         predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
 849         {
 850                 brw_set_default_access_mode(p, $10.access_mode);
 851                 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
 852                 brw_pop_insn_state(p);
 853                 i965_asm_set_instruction_options(p, $10);
 854                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 855                                            $4.cond_modifier);
 856
 857                 if (p->devinfo->gen >= 7) {
 858                         brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
 859                                                  $4.flag_reg_nr);
 860                         brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
 861                                                     $4.flag_subreg_nr);
 862                 }
 863
 864                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 865                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 866                 // TODO: set instruction group instead of qtr and nib ctrl
 867                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 868                                          $10.qtr_ctrl);
 869
 870                 if (p->devinfo->gen >= 7)
 871                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 872                                                  $10.nib_ctrl);
 873         }
 874         ;
 875
 876 ternaryopcodes:
 877         CSEL
 878         | BFE
 879         | BFI2
 880         | LRP
 881         | MAD
 882         ;
 883
 884 /* Sync instruction */
 885 syncinstruction:
 886         WAIT execsize dst instoptions
 887         {
 888                 brw_next_insn(p, $1);
 889                 i965_asm_set_instruction_options(p, $4);
 890                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 891                 brw_set_default_access_mode(p, $4.access_mode);
 892                 struct brw_reg dest = $3;
 893                 dest.swizzle = brw_swizzle_for_mask(dest.writemask);
 894                 if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
 895                         error(&@1, "WAIT must use the notification register\n");
 896                 brw_set_dest(p, brw_last_inst, dest);
 897                 brw_set_src0(p, brw_last_inst, dest);
 898                 brw_set_src1(p, brw_last_inst, brw_null_reg());
 899                 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
 900         }
 901         ;
 902
 903 /* Send instruction */
 904 sendinstruction:
 905         predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
 906         {
 907                 i965_asm_set_instruction_options(p, $8);
 908                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 909                 brw_set_dest(p, brw_last_inst, $4);
 910                 brw_set_src0(p, brw_last_inst, $5);
 911                 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
 912                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 913                                             BRW_IMMEDIATE_VALUE,
 914                                             BRW_REGISTER_TYPE_UD);
 915                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
 916                 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
 917                 // TODO: set instruction group instead of qtr and nib ctrl
 918                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 919                                          $8.qtr_ctrl);
 920
 921                 if (p->devinfo->gen >= 7)
 922                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 923                                                  $8.nib_ctrl);
 924
 925                 brw_pop_insn_state(p);
 926         }
 927         | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
 928         {
 929                 i965_asm_set_instruction_options(p, $9);
 930                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 931                 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
 932                 brw_set_dest(p, brw_last_inst, $5);
 933                 brw_set_src0(p, brw_last_inst, $6);
 934                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 935                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 936                                             BRW_IMMEDIATE_VALUE,
 937                                             BRW_REGISTER_TYPE_UD);
 938                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 939                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 940                 // TODO: set instruction group instead of qtr and nib ctrl
 941                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 942                                          $9.qtr_ctrl);
 943
 944                 if (p->devinfo->gen >= 7)
 945                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 946                                                  $9.nib_ctrl);
 947
 948                 brw_pop_insn_state(p);
 949         }
 950         | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
 951         {
 952                 i965_asm_set_instruction_options(p, $9);
 953                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 954                 brw_set_dest(p, brw_last_inst, $4);
 955                 brw_set_src0(p, brw_last_inst, $5);
 956                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 957                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 958                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 959                 // TODO: set instruction group instead of qtr and nib ctrl
 960                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 961                                          $9.qtr_ctrl);
 962
 963                 if (p->devinfo->gen >= 7)
 964                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 965                                                  $9.nib_ctrl);
 966
 967                 brw_pop_insn_state(p);
 968         }
 969         | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
 970         {
 971                 brw_next_insn(p, $2);
 972                 i965_asm_set_instruction_options(p, $10);
 973                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 974                 brw_set_dest(p, brw_last_inst, $4);
 975                 brw_set_src0(p, brw_last_inst, $5);
 976                 brw_set_src1(p, brw_last_inst, $6);
 977
 978                 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
 979                         brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
 980                 } else {
 981                         brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
 982                 }
 983
 984                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 985                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
 986                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
 987                 // TODO: set instruction group instead of qtr and nib ctrl
 988                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 989                                          $10.qtr_ctrl);
 990
 991                 if (p->devinfo->gen >= 7)
 992                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 993                                                  $10.nib_ctrl);
 994
 995                 brw_pop_insn_state(p);
 996         }
 997         | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
 998         {
 999                 brw_next_insn(p, $2);
1000                 i965_asm_set_instruction_options(p, $10);
1001                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1002                 brw_set_dest(p, brw_last_inst, $4);
1003                 brw_set_src0(p, brw_last_inst, $5);
1004                 brw_set_src1(p, brw_last_inst, $6);
1005
1006                 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1007                 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1008
1009                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1010                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1011                 // TODO: set instruction group instead of qtr and nib ctrl
1012                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1013                                          $10.qtr_ctrl);
1014
1015                 if (p->devinfo->gen >= 7)
1016                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1017                                                  $10.nib_ctrl);
1018
1019                 brw_pop_insn_state(p);
1020         }
1021         ;
1022
1023 sendop:
1024         SEND
1025         | SENDC
1026         ;
1027
1028 sendopcode:
1029         sendop   { $$ = brw_next_insn(p, $1); }
1030         ;
1031
1032 sharedfunction:
1033         NULL_TOKEN              { $$ = BRW_SFID_NULL; }
1034         | MATH                  { $$ = BRW_SFID_MATH; }
1035         | GATEWAY               { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1036         | READ                  { $$ = BRW_SFID_DATAPORT_READ; }
1037         | WRITE                 { $$ = BRW_SFID_DATAPORT_WRITE; }
1038         | URB                   { $$ = BRW_SFID_URB; }
1039         | THREAD_SPAWNER        { $$ = BRW_SFID_THREAD_SPAWNER; }
1040         | VME                   { $$ = BRW_SFID_VME; }
1041         | RENDER                { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1042         | CONST                 { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1043         | DATA                  { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1044         | PIXEL_INTERP          { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1045         | DP_DATA_1             { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1046         | CRE                   { $$ = HSW_SFID_CRE; }
1047         | SAMPLER               { $$ = BRW_SFID_SAMPLER; }
1048         | DP_SAMPLER            { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1049         ;
1050
1051 exp2:
1052         LONG            { $$ = $1; }
1053         | MINUS LONG    { $$ = -$2; }
1054         ;
1055
1056 /* Jump instruction */
1057 jumpinstruction:
1058         predicate JMPI execsize relativelocation2 instoptions
1059         {
1060                 brw_next_insn(p, $2);
1061                 i965_asm_set_instruction_options(p, $5);
1062                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1063                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1064                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1065                 brw_set_src1(p, brw_last_inst, $4);
1066                 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1067                                           brw_inst_pred_control(p->devinfo,
1068                                                                 brw_last_inst));
1069                 brw_pop_insn_state(p);
1070         }
1071         ;
1072
1073 /* branch instruction */
1074 branchinstruction:
1075         predicate ENDIF execsize relativelocation instoptions
1076         {
1077                 brw_next_insn(p, $2);
1078                 i965_asm_set_instruction_options(p, $5);
1079                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1080
1081                 if (p->devinfo->gen < 6) {
1082                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1083                                      BRW_REGISTER_TYPE_D));
1084                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1085                                      BRW_REGISTER_TYPE_D));
1086                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1087                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1088                                                     $4);
1089                 } else if (p->devinfo->gen == 6) {
1090                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1091                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1092                                                      $4);
1093                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1094                                      BRW_REGISTER_TYPE_D));
1095                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1096                                      BRW_REGISTER_TYPE_D));
1097                 } else if (p->devinfo->gen == 7) {
1098                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1099                                      BRW_REGISTER_TYPE_D));
1100                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1101                                      BRW_REGISTER_TYPE_D));
1102                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1103                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1104                 } else {
1105                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1106                 }
1107
1108                 if (p->devinfo->gen < 6)
1109                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1110                                                     BRW_THREAD_SWITCH);
1111                 brw_pop_insn_state(p);
1112         }
1113         | ELSE execsize relativelocation rellocation instoptions
1114         {
1115                 brw_next_insn(p, $1);
1116                 i965_asm_set_instruction_options(p, $5);
1117                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1118
1119                 if (p->devinfo->gen < 6) {
1120                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1121                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1122                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1123                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1124                                                      $3);
1125                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1126                                                     $4);
1127                 } else if (p->devinfo->gen == 6) {
1128                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1129                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1130                                                      $3);
1131                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1132                                      BRW_REGISTER_TYPE_D));
1133                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1134                                      BRW_REGISTER_TYPE_D));
1135                 } else if (p->devinfo->gen == 7) {
1136                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1137                                      BRW_REGISTER_TYPE_D));
1138                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1139                                      BRW_REGISTER_TYPE_D));
1140                         brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1141                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1142                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1143                 } else {
1144                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1145                                      BRW_REGISTER_TYPE_D));
1146                         brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1147                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1148                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1149                 }
1150
1151                 if (!p->single_program_flow && p->devinfo->gen < 6)
1152                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1153                                                     BRW_THREAD_SWITCH);
1154         }
1155         | predicate IF execsize relativelocation rellocation instoptions
1156         {
1157                 brw_next_insn(p, $2);
1158                 i965_asm_set_instruction_options(p, $6);
1159                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1160
1161                 if (p->devinfo->gen < 6) {
1162                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1163                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1164                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1165                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1166                                                      $4);
1167                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1168                                                     $5);
1169                 } else if (p->devinfo->gen == 6) {
1170                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1171                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1172                                                      $4);
1173                         brw_set_src0(p, brw_last_inst,
1174                                      vec1(retype(brw_null_reg(),
1175                                      BRW_REGISTER_TYPE_D)));
1176                         brw_set_src1(p, brw_last_inst,
1177                                      vec1(retype(brw_null_reg(),
1178                                      BRW_REGISTER_TYPE_D)));
1179                 } else if (p->devinfo->gen == 7) {
1180                         brw_set_dest(p, brw_last_inst,
1181                                      vec1(retype(brw_null_reg(),
1182                                      BRW_REGISTER_TYPE_D)));
1183                         brw_set_src0(p, brw_last_inst,
1184                                      vec1(retype(brw_null_reg(),
1185                                      BRW_REGISTER_TYPE_D)));
1186                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1187                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1188                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1189                 } else {
1190                         brw_set_dest(p, brw_last_inst,
1191                                      vec1(retype(brw_null_reg(),
1192                                      BRW_REGISTER_TYPE_D)));
1193                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1194                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1195                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1196                 }
1197
1198                 if (!p->single_program_flow && p->devinfo->gen < 6)
1199                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1200                                                     BRW_THREAD_SWITCH);
1201
1202                 brw_pop_insn_state(p);
1203         }
1204         | predicate IFF execsize relativelocation instoptions
1205         {
1206                 brw_next_insn(p, $2);
1207                 i965_asm_set_instruction_options(p, $5);
1208                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1209
1210                 if (p->devinfo->gen < 6) {
1211                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1212                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1213                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1214                                                      $4);
1215                         brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1216                 } else if (p->devinfo->gen == 6) {
1217                         brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1218                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1219                                                      $4);
1220                         brw_set_src0(p, brw_last_inst,
1221                                      vec1(retype(brw_null_reg(),
1222                                      BRW_REGISTER_TYPE_D)));
1223                         brw_set_src1(p, brw_last_inst,
1224                                      vec1(retype(brw_null_reg(),
1225                                      BRW_REGISTER_TYPE_D)));
1226                 } else if (p->devinfo->gen == 7) {
1227                         brw_set_dest(p, brw_last_inst,
1228                                      vec1(retype(brw_null_reg(),
1229                                      BRW_REGISTER_TYPE_D)));
1230                         brw_set_src0(p, brw_last_inst,
1231                                      vec1(retype(brw_null_reg(),
1232                                      BRW_REGISTER_TYPE_D)));
1233                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1234                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1235                 } else {
1236                         brw_set_dest(p, brw_last_inst,
1237                                      vec1(retype(brw_null_reg(),
1238                                      BRW_REGISTER_TYPE_D)));
1239                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1240                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1241                 }
1242
1243                 if (!p->single_program_flow && p->devinfo->gen < 6)
1244                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1245                                                     BRW_THREAD_SWITCH);
1246
1247                 brw_pop_insn_state(p);
1248         }
1249         ;
1250
1251 /* break instruction */
1252 breakinstruction:
1253         predicate BREAK execsize relativelocation relativelocation instoptions
1254         {
1255                 brw_next_insn(p, $2);
1256                 i965_asm_set_instruction_options(p, $6);
1257                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1258
1259                 if (p->devinfo->gen >= 8) {
1260                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1261                                      BRW_REGISTER_TYPE_D));
1262                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1263                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1264                 } else if (p->devinfo->gen >= 6) {
1265                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1266                                      BRW_REGISTER_TYPE_D));
1267                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1268                                      BRW_REGISTER_TYPE_D));
1269                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1270                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1271                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1272                 } else {
1273                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1274                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1275                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1276                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1277                                                      $4);
1278                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1279                                                     $5);
1280                 }
1281
1282                 brw_pop_insn_state(p);
1283         }
1284         | predicate HALT execsize relativelocation relativelocation instoptions
1285         {
1286                 brw_next_insn(p, $2);
1287                 i965_asm_set_instruction_options(p, $6);
1288                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1289                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1290                              BRW_REGISTER_TYPE_D));
1291
1292                 if (p->devinfo->gen >= 8) {
1293                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1294                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1295                 } else {
1296                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1297                                      BRW_REGISTER_TYPE_D));
1298                         brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1299                 }
1300
1301                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1302                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1303                 brw_pop_insn_state(p);
1304         }
1305         | predicate CONT execsize relativelocation relativelocation instoptions
1306         {
1307                 brw_next_insn(p, $2);
1308                 i965_asm_set_instruction_options(p, $6);
1309                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1310                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1311
1312                 if (p->devinfo->gen >= 8) {
1313                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1314                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1315                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1316                 } else {
1317                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1318                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1319                         if (p->devinfo->gen >= 6) {
1320                                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1321                                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1322                         } else {
1323                                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1324                                                              $4);
1325                                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1326                                                             $5);
1327                         }
1328                 }
1329
1330                 brw_pop_insn_state(p);
1331         }
1332         ;
1333
1334 /* loop instruction */
1335 loopinstruction:
1336         predicate WHILE execsize relativelocation instoptions
1337         {
1338                 brw_next_insn(p, $2);
1339                 i965_asm_set_instruction_options(p, $5);
1340                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1341
1342                 if (p->devinfo->gen >= 6) {
1343                         if (p->devinfo->gen >= 8) {
1344                                 brw_set_dest(p, brw_last_inst,
1345                                              retype(brw_null_reg(),
1346                                              BRW_REGISTER_TYPE_D));
1347                                 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1348                         } else if (p->devinfo->gen == 7) {
1349                                 brw_set_dest(p, brw_last_inst,
1350                                              retype(brw_null_reg(),
1351                                              BRW_REGISTER_TYPE_D));
1352                                 brw_set_src0(p, brw_last_inst,
1353                                              retype(brw_null_reg(),
1354                                              BRW_REGISTER_TYPE_D));
1355                                 brw_set_src1(p, brw_last_inst,
1356                                              brw_imm_w(0x0));
1357                                 brw_inst_set_jip(p->devinfo, brw_last_inst,
1358                                                  $4);
1359                         } else {
1360                                 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1361                                 brw_inst_set_gen6_jump_count(p->devinfo,
1362                                                              brw_last_inst,
1363                                                              $4);
1364                                 brw_set_src0(p, brw_last_inst,
1365                                              retype(brw_null_reg(),
1366                                              BRW_REGISTER_TYPE_D));
1367                                 brw_set_src1(p, brw_last_inst,
1368                                              retype(brw_null_reg(),
1369                                              BRW_REGISTER_TYPE_D));
1370                         }
1371                 } else {
1372                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1373                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1374                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1375                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1376                                                      $4);
1377                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1378                                                     0);
1379                 }
1380                 brw_pop_insn_state(p);
1381         }
1382         | DO execsize instoptions
1383         {
1384                 brw_next_insn(p, $1);
1385                 if (p->devinfo->gen < 6) {
1386                         brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1387                         i965_asm_set_instruction_options(p, $3);
1388                         brw_set_dest(p, brw_last_inst, brw_null_reg());
1389                         brw_set_src0(p, brw_last_inst, brw_null_reg());
1390                         brw_set_src1(p, brw_last_inst, brw_null_reg());
1391
1392                         brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1393                 }
1394         }
1395         ;
1396
1397 /* Relative location */
1398 relativelocation2:
1399         immreg
1400         | reg32
1401         ;
1402
1403 simple_int:
1404         INTEGER                 { $$ = $1; }
1405         | MINUS INTEGER         { $$ = -$2; }
1406         | LONG                  { $$ = $1; }
1407         | MINUS LONG            { $$ = -$2; }
1408         ;
1409
1410 rellocation:
1411         relativelocation
1412         | %empty { $$ = 0; }
1413         ;
1414
1415 relativelocation:
1416         simple_int
1417         {
1418                 $$ = $1;
1419         }
1420         ;
1421
1422 /* Destination register */
1423 dst:
1424         dstoperand
1425         | dstoperandex
1426         ;
1427
1428 dstoperand:
1429         dstreg dstregion writemask reg_type
1430         {
1431                 $$ = $1;
1432                 $$.vstride = BRW_VERTICAL_STRIDE_1;
1433                 $$.width = BRW_WIDTH_1;
1434                 $$.hstride = $2;
1435                 $$.type = $4;
1436                 $$.writemask = $3;
1437                 $$.swizzle = BRW_SWIZZLE_NOOP;
1438                 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1439         }
1440         ;
1441
1442 dstoperandex:
1443         dstoperandex_typed dstregion writemask reg_type
1444         {
1445                 $$ = $1;
1446                 $$.hstride = $2;
1447                 $$.type = $4;
1448                 $$.writemask = $3;
1449                 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1450         }
1451         /* BSpec says "When the conditional modifier is present, updates
1452          * to the selected flag register also occur. In this case, the
1453          * register region fields of the ‘null’ operand are valid."
1454          */
1455         | nullreg dstregion writemask reg_type
1456         {
1457                 $$ = $1;
1458                 $$.vstride = BRW_VERTICAL_STRIDE_1;
1459                 $$.width = BRW_WIDTH_1;
1460                 $$.hstride = $2;
1461                 $$.writemask = $3;
1462                 $$.type = $4;
1463         }
1464         | threadcontrolreg
1465         {
1466                 $$ = $1;
1467                 $$.hstride = 1;
1468                 $$.type = BRW_REGISTER_TYPE_UW;
1469         }
1470         ;
1471
1472 dstoperandex_typed:
1473         accreg
1474         | addrreg
1475         | channelenablereg
1476         | controlreg
1477         | flagreg
1478         | ipreg
1479         | maskreg
1480         | notifyreg
1481         | performancereg
1482         | statereg
1483         ;
1484
1485 dstreg:
1486         directgenreg
1487         {
1488                 $$ = $1;
1489                 $$.address_mode = BRW_ADDRESS_DIRECT;
1490         }
1491         | indirectgenreg
1492         {
1493                 $$ = $1;
1494                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1495         }
1496         | directmsgreg
1497         {
1498                 $$ = $1;
1499                 $$.address_mode = BRW_ADDRESS_DIRECT;
1500         }
1501         | indirectmsgreg
1502         {
1503                 $$ = $1;
1504                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1505         }
1506         ;
1507
1508 /* Source register */
1509 srcaccimm:
1510         srcacc
1511         | immreg
1512         ;
1513
1514 immreg:
1515         immval imm_type
1516         {
1517                 switch ($2) {
1518                 case BRW_REGISTER_TYPE_UD:
1519                         $$ = brw_imm_ud($1);
1520                         break;
1521                 case BRW_REGISTER_TYPE_D:
1522                         $$ = brw_imm_d($1);
1523                         break;
1524                 case BRW_REGISTER_TYPE_UW:
1525                         $$ = brw_imm_uw($1 | ($1 << 16));
1526                         break;
1527                 case BRW_REGISTER_TYPE_W:
1528                         $$ = brw_imm_w($1);
1529                         break;
1530                 case BRW_REGISTER_TYPE_F:
1531                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1532                         /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1533                         $$.u64 = $1;
1534                         break;
1535                 case BRW_REGISTER_TYPE_V:
1536                         $$ = brw_imm_v($1);
1537                         break;
1538                 case BRW_REGISTER_TYPE_UV:
1539                         $$ = brw_imm_uv($1);
1540                         break;
1541                 case BRW_REGISTER_TYPE_VF:
1542                         $$ = brw_imm_vf($1);
1543                         break;
1544                 case BRW_REGISTER_TYPE_Q:
1545                         $$ = brw_imm_q($1);
1546                         break;
1547                 case BRW_REGISTER_TYPE_UQ:
1548                         $$ = brw_imm_uq($1);
1549                         break;
1550                 case BRW_REGISTER_TYPE_DF:
1551                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1552                         $$.d64 = $1;
1553                         break;
1554                 default:
1555                         error(&@2, "Unknown immediate type %s\n",
1556                               brw_reg_type_to_letters($2));
1557                 }
1558         }
1559         ;
1560
1561 reg32:
1562         directgenreg region reg_type
1563         {
1564                 $$ = set_direct_src_operand(&$1, $3);
1565                 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1566         }
1567         ;
1568
1569 payload:
1570         directsrcoperand
1571         ;
1572
1573 src:
1574         directsrcoperand
1575         | indirectsrcoperand
1576         ;
1577
1578 srcacc:
1579         directsrcaccoperand
1580         | indirectsrcoperand
1581         ;
1582
1583 srcimm:
1584         directsrcoperand
1585         | indirectsrcoperand
1586         | immreg
1587         ;
1588
1589 directsrcaccoperand:
1590         directsrcoperand
1591         | accreg region reg_type
1592         {
1593                 $$ = set_direct_src_operand(&$1, $3);
1594                 $$.vstride = $2.vstride;
1595                 $$.width = $2.width;
1596                 $$.hstride = $2.hstride;
1597         }
1598         ;
1599
1600 srcarcoperandex:
1601         srcarcoperandex_typed region reg_type
1602         {
1603                 $$ = brw_reg($1.file,
1604                              $1.nr,
1605                              $1.subnr,
1606                              0,
1607                              0,
1608                              $3,
1609                              $2.vstride,
1610                              $2.width,
1611                              $2.hstride,
1612                              BRW_SWIZZLE_NOOP,
1613                              WRITEMASK_XYZW);
1614         }
1615         | nullreg region reg_type
1616         {
1617                 $$ = set_direct_src_operand(&$1, $3);
1618                 $$.vstride = $2.vstride;
1619                 $$.width = $2.width;
1620                 $$.hstride = $2.hstride;
1621         }
1622         | threadcontrolreg
1623         {
1624                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1625         }
1626         ;
1627
1628 srcarcoperandex_typed:
1629         channelenablereg
1630         | controlreg
1631         | flagreg
1632         | ipreg
1633         | maskreg
1634         | statereg
1635         ;
1636
1637 indirectsrcoperand:
1638         negate abs indirectgenreg indirectregion swizzle reg_type
1639         {
1640                 $$ = brw_reg($3.file,
1641                              0,
1642                              $3.subnr,
1643                              $1,  // negate
1644                              $2,  // abs
1645                              $6,
1646                              $4.vstride,
1647                              $4.width,
1648                              $4.hstride,
1649                              $5,
1650                              WRITEMASK_X);
1651
1652                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1653                 // brw_reg set indirect_offset to 0 so set it to valid value
1654                 $$.indirect_offset = $3.indirect_offset;
1655         }
1656         ;
1657
1658 directgenreg_list:
1659         directgenreg
1660         | directmsgreg
1661         | notifyreg
1662         | addrreg
1663         | performancereg
1664         ;
1665
1666 directsrcoperand:
1667         negate abs directgenreg_list region swizzle reg_type
1668         {
1669                 $$ = brw_reg($3.file,
1670                              $3.nr,
1671                              $3.subnr,
1672                              $1,
1673                              $2,
1674                              $6,
1675                              $4.vstride,
1676                              $4.width,
1677                              $4.hstride,
1678                              $5,
1679                              WRITEMASK_X);
1680         }
1681         | srcarcoperandex
1682         ;
1683
1684 /* Address register */
1685 addrparam:
1686         addrreg exp
1687         {
1688                 memset(&$$, '\0', sizeof($$));
1689                 $$.subnr = $1.subnr;
1690                 $$.indirect_offset = $2;
1691         }
1692         | addrreg
1693         ;
1694
1695 /* Register files and register numbers */
1696 exp:
1697         INTEGER         { $$ = $1; }
1698         | LONG          { $$ = $1; }
1699         ;
1700
1701 subregnum:
1702         DOT exp                         { $$ = $2; }
1703         | %empty %prec SUBREGNUM        { $$ = 0; }
1704         ;
1705
1706 directgenreg:
1707         GENREG subregnum
1708         {
1709                 memset(&$$, '\0', sizeof($$));
1710                 $$.file = BRW_GENERAL_REGISTER_FILE;
1711                 $$.nr = $1;
1712                 $$.subnr = $2;
1713         }
1714         ;
1715
1716 indirectgenreg:
1717         GENREGFILE LSQUARE addrparam RSQUARE
1718         {
1719                 memset(&$$, '\0', sizeof($$));
1720                 $$.file = BRW_GENERAL_REGISTER_FILE;
1721                 $$.subnr = $3.subnr;
1722                 $$.indirect_offset = $3.indirect_offset;
1723         }
1724         ;
1725
1726 directmsgreg:
1727         MSGREG subregnum
1728         {
1729                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1730                 $$.nr = $1;
1731                 $$.subnr = $2;
1732         }
1733         ;
1734
1735 indirectmsgreg:
1736         MSGREGFILE LSQUARE addrparam RSQUARE
1737         {
1738                 memset(&$$, '\0', sizeof($$));
1739                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1740                 $$.subnr = $3.subnr;
1741                 $$.indirect_offset = $3.indirect_offset;
1742         }
1743         ;
1744
1745 addrreg:
1746         ADDRREG subregnum
1747         {
1748                 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1749
1750                 if ($2 > subnr)
1751                         error(&@2, "Address sub register number %d"
1752                                    "out of range\n", $2);
1753
1754                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1755                 $$.nr = BRW_ARF_ADDRESS;
1756                 $$.subnr = $2;
1757         }
1758         ;
1759
1760 accreg:
1761         ACCREG subregnum
1762         {
1763                 int nr_reg;
1764                 if (p->devinfo->gen < 8)
1765                         nr_reg = 2;
1766                 else
1767                         nr_reg = 10;
1768
1769                 if ($1 > nr_reg)
1770                         error(&@1, "Accumulator register number %d"
1771                                    " out of range\n", $1);
1772
1773                 memset(&$$, '\0', sizeof($$));
1774                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1775                 $$.nr = BRW_ARF_ACCUMULATOR;
1776                 $$.subnr = $2;
1777         }
1778         ;
1779
1780 flagreg:
1781         FLAGREG subregnum
1782         {
1783                 // SNB = 1 flag reg and IVB+ = 2 flag reg
1784                 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1785                 int subnr = nr_reg;
1786
1787                 if ($1 > nr_reg)
1788                         error(&@1, "Flag register number %d"
1789                                    " out of range \n", $1);
1790                 if ($2 > subnr)
1791                         error(&@2, "Flag subregister number %d"
1792                                    " out of range\n", $2);
1793
1794                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1795                 $$.nr = BRW_ARF_FLAG | $1;
1796                 $$.subnr = $2;
1797         }
1798         ;
1799
1800 maskreg:
1801         MASKREG subregnum
1802         {
1803                 if ($1 > 0)
1804                         error(&@1, "Mask register number %d"
1805                                    " out of range\n", $1);
1806
1807                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1808                 $$.nr = BRW_ARF_MASK;
1809                 $$.subnr = $2;
1810         }
1811         ;
1812
1813 notifyreg:
1814         NOTIFYREG subregnum
1815         {
1816                 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1817                 if ($2 > subnr)
1818                         error(&@2, "Notification sub register number %d"
1819                                    " out of range\n", $2);
1820
1821                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1822                 $$.nr = BRW_ARF_NOTIFICATION_COUNT;
1823                 $$.subnr = $2;
1824         }
1825         ;
1826
1827 statereg:
1828         STATEREG subregnum
1829         {
1830                 if ($1 > 2)
1831                         error(&@1, "State register number %d"
1832                                    " out of range\n", $1);
1833
1834                 if ($2 > 4)
1835                         error(&@2, "State sub register number %d"
1836                                    " out of range\n", $2);
1837
1838                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1839                 $$.nr = BRW_ARF_STATE;
1840                 $$.subnr = $2;
1841         }
1842         ;
1843
1844 controlreg:
1845         CONTROLREG subregnum
1846         {
1847                 if ($2 > 3)
1848                         error(&@2, "control sub register number %d"
1849                                    " out of range\n", $2);
1850
1851                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1852                 $$.nr = BRW_ARF_CONTROL;
1853                 $$.subnr = $2;
1854         }
1855         ;
1856
1857 ipreg:
1858         IPREG           { $$ = brw_ip_reg(); }
1859         ;
1860
1861 nullreg:
1862         NULL_TOKEN      { $$ = brw_null_reg(); }
1863         ;
1864
1865 threadcontrolreg:
1866         THREADREG subregnum
1867         {
1868                 if ($2 > 7)
1869                         error(&@2, "Thread control sub register number %d"
1870                                    " out of range\n", $2);
1871
1872                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1873                 $$.nr = BRW_ARF_TDR;
1874                 $$.subnr = $2;
1875         }
1876         ;
1877
1878 performancereg:
1879         PERFORMANCEREG subregnum
1880         {
1881                 int subnr;
1882                 if (p->devinfo->gen >= 10)
1883                         subnr = 5;
1884                 else if (p->devinfo->gen <= 8)
1885                         subnr = 3;
1886                 else
1887                         subnr = 4;
1888
1889                 if ($2 > subnr)
1890                         error(&@2, "Performance sub register number %d"
1891                                    " out of range\n", $2);
1892
1893                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1894                 $$.nr = BRW_ARF_TIMESTAMP;
1895                 $$.subnr = $2;
1896         }
1897         ;
1898
1899 channelenablereg:
1900         CHANNELENABLEREG subregnum
1901         {
1902                 if ($1 > 0)
1903                         error(&@1, "Channel enable register number %d"
1904                                    " out of range\n", $1);
1905
1906                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1907                 $$.nr = BRW_ARF_MASK;
1908                 $$.subnr = $2;
1909         }
1910         ;
1911
1912 /* Immediate values */
1913 immval:
1914         exp2
1915         {
1916                 $$ = $1;
1917         }
1918         | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1919         {
1920                 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1921         }
1922         ;
1923
1924 /* Regions */
1925 dstregion:
1926         %empty
1927         {
1928                 $$ = BRW_HORIZONTAL_STRIDE_1;
1929         }
1930         | LANGLE exp RANGLE
1931         {
1932                 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1933                         error(&@2, "Invalid Horizontal stride %d\n", $2);
1934
1935                 $$ = ffs($2);
1936         }
1937         ;
1938
1939 indirectregion:
1940         region
1941         | region_wh
1942         ;
1943
1944 region:
1945         %empty
1946         {
1947                 $$ = stride($$, 0, 1, 0);
1948         }
1949         | LANGLE exp RANGLE
1950         {
1951                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1952                         error(&@2, "Invalid VertStride %d\n", $2);
1953
1954                 $$ = stride($$, $2, 1, 0);
1955         }
1956         | LANGLE exp COMMA exp COMMA exp RANGLE
1957         {
1958
1959                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1960                         error(&@2, "Invalid VertStride %d\n", $2);
1961
1962                 if ($4 > 16 || !isPowerofTwo($4))
1963                         error(&@4, "Invalid width %d\n", $4);
1964
1965                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1966                         error(&@6, "Invalid Horizontal stride in"
1967                                    "  region_wh %d\n", $6);
1968
1969                 $$ = stride($$, $2, $4, $6);
1970         }
1971         | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1972         {
1973                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1974                         error(&@2, "Invalid VertStride %d\n", $2);
1975
1976                 if ($4 > 16 || !isPowerofTwo($4))
1977                         error(&@4, "Invalid width %d\n", $4);
1978
1979                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1980                         error(&@6, "Invalid Horizontal stride in"
1981                                    " region_wh %d\n", $6);
1982
1983                 $$ = stride($$, $2, $4, $6);
1984         }
1985         | LANGLE VxH COMMA exp COMMA exp RANGLE
1986         {
1987                 if ($4 > 16 || !isPowerofTwo($4))
1988                         error(&@4, "Invalid width %d\n", $4);
1989
1990                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1991                         error(&@6, "Invalid Horizontal stride in"
1992                                    " region_wh %d\n", $6);
1993
1994                 $$ = brw_VxH_indirect(0, 0);
1995         }
1996         ;
1997
1998 region_wh:
1999         LANGLE exp COMMA exp RANGLE
2000         {
2001                 if ($2 > 16 || !isPowerofTwo($2))
2002                         error(&@2, "Invalid width %d\n", $2);
2003
2004                 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2005                         error(&@4, "Invalid Horizontal stride in"
2006                                    " region_wh %d\n", $4);
2007
2008                 $$ = stride($$, 0, $2, $4);
2009                 $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
2010         }
2011         ;
2012
2013 reg_type:
2014           TYPE_F        { $$ = BRW_REGISTER_TYPE_F;  }
2015         | TYPE_UD       { $$ = BRW_REGISTER_TYPE_UD; }
2016         | TYPE_D        { $$ = BRW_REGISTER_TYPE_D;  }
2017         | TYPE_UW       { $$ = BRW_REGISTER_TYPE_UW; }
2018         | TYPE_W        { $$ = BRW_REGISTER_TYPE_W;  }
2019         | TYPE_UB       { $$ = BRW_REGISTER_TYPE_UB; }
2020         | TYPE_B        { $$ = BRW_REGISTER_TYPE_B;  }
2021         | TYPE_DF       { $$ = BRW_REGISTER_TYPE_DF; }
2022         | TYPE_UQ       { $$ = BRW_REGISTER_TYPE_UQ; }
2023         | TYPE_Q        { $$ = BRW_REGISTER_TYPE_Q;  }
2024         | TYPE_HF       { $$ = BRW_REGISTER_TYPE_HF; }
2025         | TYPE_NF       { $$ = BRW_REGISTER_TYPE_NF; }
2026         ;
2027
2028 imm_type:
2029         reg_type        { $$ = $1; }
2030         | TYPE_V        { $$ = BRW_REGISTER_TYPE_V;  }
2031         | TYPE_VF       { $$ = BRW_REGISTER_TYPE_VF; }
2032         | TYPE_UV       { $$ = BRW_REGISTER_TYPE_UV; }
2033         ;
2034
2035 writemask:
2036         %empty
2037         {
2038                 $$ = WRITEMASK_XYZW;
2039         }
2040         | DOT writemask_x writemask_y writemask_z writemask_w
2041         {
2042                 $$ = $2 | $3 | $4 | $5;
2043         }
2044         ;
2045
2046 writemask_x:
2047         %empty  { $$ = 0; }
2048         | X     { $$ = 1 << BRW_CHANNEL_X; }
2049         ;
2050
2051 writemask_y:
2052         %empty  { $$ = 0; }
2053         | Y     { $$ = 1 << BRW_CHANNEL_Y; }
2054         ;
2055
2056 writemask_z:
2057         %empty  { $$ = 0; }
2058         | Z     { $$ = 1 << BRW_CHANNEL_Z; }
2059         ;
2060
2061 writemask_w:
2062         %empty  { $$ = 0; }
2063         | W     { $$ = 1 << BRW_CHANNEL_W; }
2064         ;
2065
2066 swizzle:
2067         %empty
2068         {
2069                 $$ = BRW_SWIZZLE_NOOP;
2070         }
2071         | DOT chansel
2072         {
2073                 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
2074         }
2075         | DOT chansel chansel chansel chansel
2076         {
2077                 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
2078         }
2079         ;
2080
2081 chansel:
2082         X
2083         | Y
2084         | Z
2085         | W
2086         ;
2087
2088 /* Instruction prediction and modifiers */
2089 predicate:
2090         %empty
2091         {
2092                 brw_push_insn_state(p);
2093                 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2094                 brw_set_default_flag_reg(p, 0, 0);
2095                 brw_set_default_predicate_inverse(p, false);
2096         }
2097         | LPAREN predstate flagreg predctrl RPAREN
2098         {
2099                 brw_push_insn_state(p);
2100                 brw_set_default_predicate_inverse(p, $2);
2101                 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2102                 brw_set_default_predicate_control(p, $4);
2103         }
2104         ;
2105
2106 predstate:
2107         %empty          { $$ = 0; }
2108         | PLUS          { $$ = 0; }
2109         | MINUS         { $$ = 1; }
2110         ;
2111
2112 predctrl:
2113         %empty          { $$ = BRW_PREDICATE_NORMAL; }
2114         | DOT X         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2115         | DOT Y         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2116         | DOT Z         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2117         | DOT W         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2118         | ANYV
2119         | ALLV
2120         | ANY2H
2121         | ALL2H
2122         | ANY4H
2123         | ALL4H
2124         | ANY8H
2125         | ALL8H
2126         | ANY16H
2127         | ALL16H
2128         | ANY32H
2129         | ALL32H
2130         ;
2131
2132 /* Source Modification */
2133 negate:
2134         %empty          { $$ = 0; }
2135         | MINUS         { $$ = 1; }
2136         ;
2137
2138 abs:
2139         %empty  { $$ = 0; }
2140         | ABS   { $$ = 1; }
2141         ;
2142
2143 /* Flag (Conditional) Modifier */
2144 cond_mod:
2145         condModifiers
2146         {
2147                 $$.cond_modifier = $1;
2148                 $$.flag_reg_nr = 0;
2149                 $$.flag_subreg_nr = 0;
2150         }
2151         | condModifiers DOT flagreg
2152         {
2153                 $$.cond_modifier = $1;
2154                 $$.flag_reg_nr = $3.nr;
2155                 $$.flag_subreg_nr = $3.subnr;
2156         }
2157         ;
2158
2159 condModifiers:
2160         %empty  { $$ = BRW_CONDITIONAL_NONE; }
2161         | ZERO
2162         | EQUAL
2163         | NOT_ZERO
2164         | NOT_EQUAL
2165         | GREATER
2166         | GREATER_EQUAL
2167         | LESS
2168         | LESS_EQUAL
2169         | OVERFLOW
2170         | ROUND_INCREMENT
2171         | UNORDERED
2172         ;
2173
2174 saturate:
2175         %empty          { $$ = BRW_INSTRUCTION_NORMAL; }
2176         | SATURATE      { $$ = BRW_INSTRUCTION_SATURATE; }
2177         ;
2178
2179 /* Execution size */
2180 execsize:
2181         %empty %prec EMPTYEXECSIZE
2182         {
2183                 $$ = 0;
2184         }
2185         | LPAREN exp2 RPAREN
2186         {
2187                 if ($2 > 32 || !isPowerofTwo($2))
2188                         error(&@2, "Invalid execution size %d\n", $2);
2189
2190                 $$ = cvt($2) - 1;
2191         }
2192         ;
2193
2194 /* Instruction options */
2195 instoptions:
2196         %empty
2197         {
2198                 memset(&$$, 0, sizeof($$));
2199         }
2200         | LCURLY instoption_list RCURLY
2201         {
2202                 memset(&$$, 0, sizeof($$));
2203                 $$ = $2;
2204         }
2205         ;
2206
2207 instoption_list:
2208         instoption_list COMMA instoption
2209         {
2210                 memset(&$$, 0, sizeof($$));
2211                 $$ = $1;
2212                 add_instruction_option(&$$, $3);
2213         }
2214         | instoption_list instoption
2215         {
2216                 memset(&$$, 0, sizeof($$));
2217                 $$ = $1;
2218                 add_instruction_option(&$$, $2);
2219         }
2220         | %empty
2221         {
2222                 memset(&$$, 0, sizeof($$));
2223         }
2224         ;
2225
2226 instoption:
2227         ALIGN1          { $$ = ALIGN1;}
2228         | ALIGN16       { $$ = ALIGN16; }
2229         | ACCWREN       { $$ = ACCWREN; }
2230         | SECHALF       { $$ = SECHALF; }
2231         | COMPR         { $$ = COMPR; }
2232         | COMPR4        { $$ = COMPR4; }
2233         | BREAKPOINT    { $$ = BREAKPOINT; }
2234         | NODDCLR       { $$ = NODDCLR; }
2235         | NODDCHK       { $$ = NODDCHK; }
2236         | MASK_DISABLE  { $$ = MASK_DISABLE; }
2237         | EOT           { $$ = EOT; }
2238         | SWITCH        { $$ = SWITCH; }
2239         | ATOMIC        { $$ = ATOMIC; }
2240         | CMPTCTRL      { $$ = CMPTCTRL; }
2241         | WECTRL        { $$ = WECTRL; }
2242         | QTR_2Q        { $$ = QTR_2Q; }
2243         | QTR_3Q        { $$ = QTR_3Q; }
2244         | QTR_4Q        { $$ = QTR_4Q; }
2245         | QTR_2H        { $$ = QTR_2H; }
2246         | QTR_2N        { $$ = QTR_2N; }
2247         | QTR_3N        { $$ = QTR_3N; }
2248         | QTR_4N        { $$ = QTR_4N; }
2249         | QTR_5N        { $$ = QTR_5N; }
2250         | QTR_6N        { $$ = QTR_6N; }
2251         | QTR_7N        { $$ = QTR_7N; }
2252         | QTR_8N        { $$ = QTR_8N; }
2253         ;
2254
2255 %%
2256
2257 extern int yylineno;
2258
2259 void
2260 yyerror(char *msg)
2261 {
2262         fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2263                 input_filename, yylineno, msg, lex_text());
2264         ++errors;
2265 }