3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
322 unsigned long long int llint;
324 enum brw_reg_type reg_type;
325 struct brw_codegen *program;
326 struct predicate predicate;
327 struct condition condition;
328 struct options options;
329 brw_inst *instruction;
339 %token LSQUARE RSQUARE
344 %token <integer> TYPE_B TYPE_UB
345 %token <integer> TYPE_W TYPE_UW
346 %token <integer> TYPE_D TYPE_UD
347 %token <integer> TYPE_Q TYPE_UQ
348 %token <integer> TYPE_V TYPE_UV
349 %token <integer> TYPE_F TYPE_HF
350 %token <integer> TYPE_DF TYPE_NF
351 %token <integer> TYPE_VF
354 %token <integer> ADD ADD3 ADDC AND ASR AVG
355 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
356 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
357 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
358 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
359 %token <integer> GOTO
360 %token <integer> HALT
361 %token <integer> IF IFF ILLEGAL
362 %token <integer> JMPI JOIN
363 %token <integer> LINE LRP LZD
364 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
365 %token <integer> NENOP NOP NOT
367 %token <integer> PLN POP PUSH
368 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
369 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
370 %token <integer> WAIT WHILE
373 /* extended math functions */
374 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
375 %token <integer> RSQRTM SIN SINCOS SQRT
377 /* shared functions for send */
378 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
379 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
381 /* Conditional modifiers */
382 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
383 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
385 /* register Access Modes */
386 %token ALIGN1 ALIGN16
388 /* accumulator write control */
391 /* compaction control */
394 /* compression control */
395 %token COMPR COMPR4 SECHALF
397 /* mask control (WeCtrl) */
403 /* dependency control */
404 %token NODDCLR NODDCHK
412 /* predicate control */
413 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
414 %token <integer> ANY32H ALL32H
416 /* round instructions */
417 %token <integer> ROUND_INCREMENT
426 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
427 %token QTR_6N QTR_7N QTR_8N
430 %token <integer> X Y Z W
433 %token GENREGFILE MSGREGFILE
435 /* vertical stride in register region */
439 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
440 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
441 %token <integer> MASKREG
443 %token <integer> INTEGER
447 %precedence SUBREGNUM
450 %precedence EMPTYEXECSIZE
453 %type <integer> execsize simple_int exp
456 /* predicate control */
457 %type <integer> predctrl predstate
458 %type <predicate> predicate
460 /* conditional modifier */
461 %type <condition> cond_mod
462 %type <integer> condModifiers
464 /* instruction options */
465 %type <options> instoptions instoption_list
466 %type <integer> instoption
469 %type <integer> writemask_x writemask_y writemask_z writemask_w
470 %type <reg> writemask
473 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
474 %type <integer> dstregion
476 %type <integer> saturate relativelocation rellocation
477 %type <reg> relativelocation2
480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
482 %type <reg> indirectgenreg indirectregion
483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
484 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
487 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
488 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
489 %type <integer> subregnum
492 %type <reg_type> reg_type imm_type
494 /* immediate values */
497 /* instruction opcodes */
498 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
499 %type <integer> sendop
500 %type <instruction> sendopcode
502 %type <integer> negate abs chansel math_function sharedfunction
507 add_instruction_option(struct options *options, int option)
511 options->access_mode = BRW_ALIGN_1;
514 options->access_mode = BRW_ALIGN_16;
517 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
520 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
521 options->is_compr = true;
524 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
527 options->thread_control |= BRW_THREAD_SWITCH;
530 options->thread_control |= BRW_THREAD_ATOMIC;
533 options->no_dd_check = true;
536 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
539 options->mask_control |= BRW_MASK_DISABLE;
542 options->debug_control = BRW_DEBUG_BREAKPOINT;
545 options->mask_control |= BRW_WE_ALL;
548 options->compaction = true;
551 options->acc_wr_control = true;
554 options->end_of_thread = true;
556 /* TODO : Figure out how to set instruction group and get rid of
560 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
563 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
566 options->qtr_ctrl = 3;
569 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
572 options->qtr_ctrl = BRW_COMPRESSION_NONE;
573 options->nib_ctrl = true;
576 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
579 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
580 options->nib_ctrl = true;
583 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
586 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
587 options->nib_ctrl = true;
590 options->qtr_ctrl = 3;
593 options->qtr_ctrl = 3;
594 options->nib_ctrl = true;
606 instrseq instruction SEMICOLON
607 | instrseq relocatableinstruction SEMICOLON
608 | instruction SEMICOLON
609 | relocatableinstruction SEMICOLON
612 /* Instruction Group */
616 | binaryaccinstruction
625 relocatableinstruction:
633 ILLEGAL execsize instoptions
635 brw_next_insn(p, $1);
636 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
637 i965_asm_set_instruction_options(p, $3);
641 /* Unary instruction */
643 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
645 i965_asm_set_dst_nr(p, &$6, $8);
646 brw_set_default_access_mode(p, $8.access_mode);
647 i965_asm_unary_instruction($2, p, $6, $7);
648 brw_pop_insn_state(p);
649 i965_asm_set_instruction_options(p, $8);
650 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
653 if (p->devinfo->gen >= 7) {
654 if ($2 != BRW_OPCODE_DIM) {
655 brw_inst_set_flag_reg_nr(p->devinfo,
658 brw_inst_set_flag_subreg_nr(p->devinfo,
664 if ($7.file != BRW_IMMEDIATE_VALUE) {
665 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
668 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
669 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
670 // TODO: set instruction group instead of qtr and nib ctrl
671 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
674 if (p->devinfo->gen >= 7)
675 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
698 /* Binary instruction */
700 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
702 i965_asm_set_dst_nr(p, &$6, $9);
703 brw_set_default_access_mode(p, $9.access_mode);
704 i965_asm_binary_instruction($2, p, $6, $7, $8);
705 i965_asm_set_instruction_options(p, $9);
706 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
709 if (p->devinfo->gen >= 7) {
710 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
712 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
716 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
717 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
718 // TODO: set instruction group instead of qtr and nib ctrl
719 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
722 if (p->devinfo->gen >= 7)
723 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
726 brw_pop_insn_state(p);
749 /* Binary acc instruction */
750 binaryaccinstruction:
751 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
753 i965_asm_set_dst_nr(p, &$6, $9);
754 brw_set_default_access_mode(p, $9.access_mode);
755 i965_asm_binary_instruction($2, p, $6, $7, $8);
756 brw_pop_insn_state(p);
757 i965_asm_set_instruction_options(p, $9);
758 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
761 if (p->devinfo->gen >= 7) {
762 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
763 brw_inst_set_flag_reg_nr(p->devinfo,
766 brw_inst_set_flag_subreg_nr(p->devinfo,
772 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
773 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
774 // TODO: set instruction group instead of qtr and nib ctrl
775 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
778 if (p->devinfo->gen >= 7)
779 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
798 /* Math instruction */
800 predicate MATH saturate math_function execsize dst src srcimm instoptions
802 brw_set_default_access_mode(p, $9.access_mode);
803 gen6_math(p, $6, $4, $7, $8);
804 i965_asm_set_instruction_options(p, $9);
805 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
806 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
807 // TODO: set instruction group instead
808 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
811 if (p->devinfo->gen >= 7)
812 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
815 brw_pop_insn_state(p);
837 /* NOP instruction */
845 /* Ternary operand instruction */
847 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
849 brw_set_default_access_mode(p, $10.access_mode);
850 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
851 brw_pop_insn_state(p);
852 i965_asm_set_instruction_options(p, $10);
853 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
856 if (p->devinfo->gen >= 7) {
857 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
859 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
863 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
864 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
865 // TODO: set instruction group instead of qtr and nib ctrl
866 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
869 if (p->devinfo->gen >= 7)
870 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
883 /* Sync instruction */
885 WAIT execsize src instoptions
887 brw_next_insn(p, $1);
888 i965_asm_set_instruction_options(p, $4);
889 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
890 brw_set_default_access_mode(p, $4.access_mode);
891 struct brw_reg src = brw_notification_reg();
892 brw_set_dest(p, brw_last_inst, src);
893 brw_set_src0(p, brw_last_inst, src);
894 brw_set_src1(p, brw_last_inst, brw_null_reg());
895 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
899 /* Send instruction */
901 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
903 i965_asm_set_instruction_options(p, $8);
904 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
905 brw_set_dest(p, brw_last_inst, $4);
906 brw_set_src0(p, brw_last_inst, $5);
907 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
908 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
910 BRW_REGISTER_TYPE_UD);
911 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
912 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
913 // TODO: set instruction group instead of qtr and nib ctrl
914 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
917 if (p->devinfo->gen >= 7)
918 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
921 brw_pop_insn_state(p);
923 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
925 i965_asm_set_instruction_options(p, $9);
926 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
927 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
928 brw_set_dest(p, brw_last_inst, $5);
929 brw_set_src0(p, brw_last_inst, $6);
930 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
931 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
933 BRW_REGISTER_TYPE_UD);
934 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
935 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
936 // TODO: set instruction group instead of qtr and nib ctrl
937 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
940 if (p->devinfo->gen >= 7)
941 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
944 brw_pop_insn_state(p);
946 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
948 i965_asm_set_instruction_options(p, $9);
949 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
950 brw_set_dest(p, brw_last_inst, $4);
951 brw_set_src0(p, brw_last_inst, $5);
952 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
953 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
954 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
955 // TODO: set instruction group instead of qtr and nib ctrl
956 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
959 if (p->devinfo->gen >= 7)
960 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
963 brw_pop_insn_state(p);
965 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
967 brw_next_insn(p, $2);
968 i965_asm_set_instruction_options(p, $10);
969 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
970 brw_set_dest(p, brw_last_inst, $4);
971 brw_set_src0(p, brw_last_inst, $5);
972 brw_set_src1(p, brw_last_inst, $6);
974 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
975 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
977 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
980 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
981 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
982 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
983 // TODO: set instruction group instead of qtr and nib ctrl
984 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
987 if (p->devinfo->gen >= 7)
988 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
991 brw_pop_insn_state(p);
993 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
995 brw_next_insn(p, $2);
996 i965_asm_set_instruction_options(p, $10);
997 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
998 brw_set_dest(p, brw_last_inst, $4);
999 brw_set_src0(p, brw_last_inst, $5);
1000 brw_set_src1(p, brw_last_inst, $6);
1002 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1003 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1005 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1006 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1007 // TODO: set instruction group instead of qtr and nib ctrl
1008 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1011 if (p->devinfo->gen >= 7)
1012 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1015 brw_pop_insn_state(p);
1025 sendop { $$ = brw_next_insn(p, $1); }
1029 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1030 | MATH { $$ = BRW_SFID_MATH; }
1031 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1032 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1033 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1034 | URB { $$ = BRW_SFID_URB; }
1035 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1036 | VME { $$ = BRW_SFID_VME; }
1037 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1038 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1039 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1040 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1041 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1042 | CRE { $$ = HSW_SFID_CRE; }
1043 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1044 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1049 | MINUS LONG { $$ = -$2; }
1052 /* Jump instruction */
1054 predicate JMPI execsize relativelocation2 instoptions
1056 brw_next_insn(p, $2);
1057 i965_asm_set_instruction_options(p, $5);
1058 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1059 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1060 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1061 brw_set_src1(p, brw_last_inst, $4);
1062 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1063 brw_inst_pred_control(p->devinfo,
1065 brw_pop_insn_state(p);
1069 /* branch instruction */
1071 predicate ENDIF execsize relativelocation instoptions
1073 brw_next_insn(p, $2);
1074 i965_asm_set_instruction_options(p, $5);
1075 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1077 if (p->devinfo->gen < 6) {
1078 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1079 BRW_REGISTER_TYPE_D));
1080 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1081 BRW_REGISTER_TYPE_D));
1082 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1083 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1085 } else if (p->devinfo->gen == 6) {
1086 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1087 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1089 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1090 BRW_REGISTER_TYPE_D));
1091 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1092 BRW_REGISTER_TYPE_D));
1093 } else if (p->devinfo->gen == 7) {
1094 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1095 BRW_REGISTER_TYPE_D));
1096 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1097 BRW_REGISTER_TYPE_D));
1098 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1099 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1101 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1104 if (p->devinfo->gen < 6)
1105 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1107 brw_pop_insn_state(p);
1109 | ELSE execsize relativelocation rellocation instoptions
1111 brw_next_insn(p, $1);
1112 i965_asm_set_instruction_options(p, $5);
1113 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1115 if (p->devinfo->gen < 6) {
1116 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1117 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1118 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1119 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1121 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1123 } else if (p->devinfo->gen == 6) {
1124 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1125 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1127 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1128 BRW_REGISTER_TYPE_D));
1129 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1130 BRW_REGISTER_TYPE_D));
1131 } else if (p->devinfo->gen == 7) {
1132 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1133 BRW_REGISTER_TYPE_D));
1134 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1135 BRW_REGISTER_TYPE_D));
1136 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1137 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1138 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1140 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1141 BRW_REGISTER_TYPE_D));
1142 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1143 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1144 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1147 if (!p->single_program_flow && p->devinfo->gen < 6)
1148 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1151 | predicate IF execsize relativelocation rellocation instoptions
1153 brw_next_insn(p, $2);
1154 i965_asm_set_instruction_options(p, $6);
1155 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1157 if (p->devinfo->gen < 6) {
1158 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1159 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1160 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1161 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1163 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1165 } else if (p->devinfo->gen == 6) {
1166 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1167 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1169 brw_set_src0(p, brw_last_inst,
1170 vec1(retype(brw_null_reg(),
1171 BRW_REGISTER_TYPE_D)));
1172 brw_set_src1(p, brw_last_inst,
1173 vec1(retype(brw_null_reg(),
1174 BRW_REGISTER_TYPE_D)));
1175 } else if (p->devinfo->gen == 7) {
1176 brw_set_dest(p, brw_last_inst,
1177 vec1(retype(brw_null_reg(),
1178 BRW_REGISTER_TYPE_D)));
1179 brw_set_src0(p, brw_last_inst,
1180 vec1(retype(brw_null_reg(),
1181 BRW_REGISTER_TYPE_D)));
1182 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1183 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1184 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1186 brw_set_dest(p, brw_last_inst,
1187 vec1(retype(brw_null_reg(),
1188 BRW_REGISTER_TYPE_D)));
1189 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1190 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1191 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1194 if (!p->single_program_flow && p->devinfo->gen < 6)
1195 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1198 brw_pop_insn_state(p);
1200 | predicate IFF execsize relativelocation instoptions
1202 brw_next_insn(p, $2);
1203 i965_asm_set_instruction_options(p, $5);
1204 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1206 if (p->devinfo->gen < 6) {
1207 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1208 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1209 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1211 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1212 } else if (p->devinfo->gen == 6) {
1213 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1214 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1216 brw_set_src0(p, brw_last_inst,
1217 vec1(retype(brw_null_reg(),
1218 BRW_REGISTER_TYPE_D)));
1219 brw_set_src1(p, brw_last_inst,
1220 vec1(retype(brw_null_reg(),
1221 BRW_REGISTER_TYPE_D)));
1222 } else if (p->devinfo->gen == 7) {
1223 brw_set_dest(p, brw_last_inst,
1224 vec1(retype(brw_null_reg(),
1225 BRW_REGISTER_TYPE_D)));
1226 brw_set_src0(p, brw_last_inst,
1227 vec1(retype(brw_null_reg(),
1228 BRW_REGISTER_TYPE_D)));
1229 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1230 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1232 brw_set_dest(p, brw_last_inst,
1233 vec1(retype(brw_null_reg(),
1234 BRW_REGISTER_TYPE_D)));
1235 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1236 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1239 if (!p->single_program_flow && p->devinfo->gen < 6)
1240 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1243 brw_pop_insn_state(p);
1247 /* break instruction */
1249 predicate BREAK execsize relativelocation relativelocation instoptions
1251 brw_next_insn(p, $2);
1252 i965_asm_set_instruction_options(p, $6);
1253 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1255 if (p->devinfo->gen >= 8) {
1256 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1257 BRW_REGISTER_TYPE_D));
1258 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1259 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1260 } else if (p->devinfo->gen >= 6) {
1261 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1262 BRW_REGISTER_TYPE_D));
1263 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1264 BRW_REGISTER_TYPE_D));
1265 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1266 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1267 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1269 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1270 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1271 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1272 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1274 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1278 brw_pop_insn_state(p);
1280 | predicate HALT execsize relativelocation relativelocation instoptions
1282 brw_next_insn(p, $2);
1283 i965_asm_set_instruction_options(p, $6);
1284 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1285 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1286 BRW_REGISTER_TYPE_D));
1288 if (p->devinfo->gen >= 8) {
1289 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1290 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1292 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1293 BRW_REGISTER_TYPE_D));
1294 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1297 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1298 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1299 brw_pop_insn_state(p);
1301 | predicate CONT execsize relativelocation relativelocation instoptions
1303 brw_next_insn(p, $2);
1304 i965_asm_set_instruction_options(p, $6);
1305 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1306 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1308 if (p->devinfo->gen >= 8) {
1309 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1310 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1311 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1313 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1314 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1315 if (p->devinfo->gen >= 6) {
1316 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1317 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1319 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1321 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1326 brw_pop_insn_state(p);
1330 /* loop instruction */
1332 predicate WHILE execsize relativelocation instoptions
1334 brw_next_insn(p, $2);
1335 i965_asm_set_instruction_options(p, $5);
1336 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1338 if (p->devinfo->gen >= 6) {
1339 if (p->devinfo->gen >= 8) {
1340 brw_set_dest(p, brw_last_inst,
1341 retype(brw_null_reg(),
1342 BRW_REGISTER_TYPE_D));
1343 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1344 } else if (p->devinfo->gen == 7) {
1345 brw_set_dest(p, brw_last_inst,
1346 retype(brw_null_reg(),
1347 BRW_REGISTER_TYPE_D));
1348 brw_set_src0(p, brw_last_inst,
1349 retype(brw_null_reg(),
1350 BRW_REGISTER_TYPE_D));
1351 brw_set_src1(p, brw_last_inst,
1353 brw_inst_set_jip(p->devinfo, brw_last_inst,
1356 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1357 brw_inst_set_gen6_jump_count(p->devinfo,
1360 brw_set_src0(p, brw_last_inst,
1361 retype(brw_null_reg(),
1362 BRW_REGISTER_TYPE_D));
1363 brw_set_src1(p, brw_last_inst,
1364 retype(brw_null_reg(),
1365 BRW_REGISTER_TYPE_D));
1368 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1369 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1370 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1371 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1373 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1376 brw_pop_insn_state(p);
1378 | DO execsize instoptions
1380 brw_next_insn(p, $1);
1381 if (p->devinfo->gen < 6) {
1382 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1383 i965_asm_set_instruction_options(p, $3);
1384 brw_set_dest(p, brw_last_inst, brw_null_reg());
1385 brw_set_src0(p, brw_last_inst, brw_null_reg());
1386 brw_set_src1(p, brw_last_inst, brw_null_reg());
1388 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1393 /* Relative location */
1400 INTEGER { $$ = $1; }
1401 | MINUS INTEGER { $$ = -$2; }
1403 | MINUS LONG { $$ = -$2; }
1408 | %empty { $$ = 0; }
1418 /* Destination register */
1425 dstreg dstregion writemask reg_type
1430 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1431 $$.vstride = BRW_VERTICAL_STRIDE_1;
1432 $$.width = BRW_WIDTH_1;
1437 $$.writemask = $3.writemask;
1438 $$.swizzle = BRW_SWIZZLE_NOOP;
1439 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1444 dstoperandex_typed dstregion writemask reg_type
1449 $$.writemask = $3.writemask;
1450 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1452 /* BSpec says "When the conditional modifier is present, updates
1453 * to the selected flag register also occur. In this case, the
1454 * register region fields of the ‘null’ operand are valid."
1456 | nullreg dstregion writemask reg_type
1460 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1461 $$.vstride = BRW_VERTICAL_STRIDE_1;
1462 $$.width = BRW_WIDTH_1;
1466 $$.writemask = $3.writemask;
1473 $$.type = BRW_REGISTER_TYPE_UW;
1493 $$.address_mode = BRW_ADDRESS_DIRECT;
1498 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1503 $$.address_mode = BRW_ADDRESS_DIRECT;
1508 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1512 /* Source register */
1524 case BRW_REGISTER_TYPE_UD:
1526 $$ = brw_imm_ud(u32);
1528 case BRW_REGISTER_TYPE_D:
1531 case BRW_REGISTER_TYPE_UW:
1532 u32 = $1 | ($1 << 16);
1533 $$ = brw_imm_uw(u32);
1535 case BRW_REGISTER_TYPE_W:
1537 $$ = brw_imm_w(u32);
1539 case BRW_REGISTER_TYPE_F:
1540 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1544 case BRW_REGISTER_TYPE_V:
1547 case BRW_REGISTER_TYPE_UV:
1548 $$ = brw_imm_uv($1);
1550 case BRW_REGISTER_TYPE_VF:
1551 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1554 case BRW_REGISTER_TYPE_Q:
1556 $$ = brw_imm_q(u64);
1558 case BRW_REGISTER_TYPE_UQ:
1560 $$ = brw_imm_uq(u64);
1562 case BRW_REGISTER_TYPE_DF:
1563 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1567 error(&@2, "Unknown immediate type %s\n",
1568 brw_reg_type_to_letters($2));
1574 directgenreg region reg_type
1576 $$ = set_direct_src_operand(&$1, $3);
1577 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1587 | indirectsrcoperand
1592 | indirectsrcoperand
1597 | indirectsrcoperand
1601 directsrcaccoperand:
1603 | accreg region reg_type
1605 $$ = set_direct_src_operand(&$1, $3);
1606 $$.vstride = $2.vstride;
1607 $$.width = $2.width;
1608 $$.hstride = $2.hstride;
1613 srcarcoperandex_typed region reg_type
1615 $$ = brw_reg($1.file,
1627 | nullreg region reg_type
1629 $$ = set_direct_src_operand(&$1, $3);
1630 $$.vstride = $2.vstride;
1631 $$.width = $2.width;
1632 $$.hstride = $2.hstride;
1636 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1640 srcarcoperandex_typed:
1650 negate abs indirectgenreg indirectregion swizzle reg_type
1652 $$ = brw_reg($3.file,
1664 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1665 // brw_reg set indirect_offset to 0 so set it to valid value
1666 $$.indirect_offset = $3.indirect_offset;
1679 negate abs directgenreg_list region swizzle reg_type
1681 $$ = brw_reg($3.file,
1696 /* Address register */
1700 memset(&$$, '\0', sizeof($$));
1701 $$.subnr = $1.subnr;
1702 $$.indirect_offset = $2;
1707 /* Register files and register numbers */
1709 INTEGER { $$ = $1; }
1714 DOT exp { $$ = $2; }
1715 | %empty %prec SUBREGNUM { $$ = 0; }
1721 memset(&$$, '\0', sizeof($$));
1722 $$.file = BRW_GENERAL_REGISTER_FILE;
1729 GENREGFILE LSQUARE addrparam RSQUARE
1731 memset(&$$, '\0', sizeof($$));
1732 $$.file = BRW_GENERAL_REGISTER_FILE;
1733 $$.subnr = $3.subnr;
1734 $$.indirect_offset = $3.indirect_offset;
1741 $$ = brw_message_reg($1);
1747 MSGREGFILE LSQUARE addrparam RSQUARE
1749 memset(&$$, '\0', sizeof($$));
1750 $$.file = BRW_MESSAGE_REGISTER_FILE;
1751 $$.subnr = $3.subnr;
1752 $$.indirect_offset = $3.indirect_offset;
1759 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1762 error(&@2, "Address sub register number %d"
1763 "out of range\n", $2);
1765 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1766 $$.nr = BRW_ARF_ADDRESS;
1775 if (p->devinfo->gen < 8)
1781 error(&@1, "Accumulator register number %d"
1782 " out of range\n", $1);
1784 memset(&$$, '\0', sizeof($$));
1785 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1786 $$.nr = BRW_ARF_ACCUMULATOR;
1794 // SNB = 1 flag reg and IVB+ = 2 flag reg
1795 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1799 error(&@1, "Flag register number %d"
1800 " out of range \n", $1);
1802 error(&@2, "Flag subregister number %d"
1803 " out of range\n", $2);
1805 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1806 $$.nr = BRW_ARF_FLAG | $1;
1815 error(&@1, "Mask register number %d"
1816 " out of range\n", $1);
1818 $$ = brw_mask_reg($2);
1826 error(&@1, "Notification register number %d"
1827 " out of range\n", $1);
1829 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1831 error(&@2, "Notification sub register number %d"
1832 " out of range\n", $2);
1834 $$ = brw_notification_reg();
1843 error(&@1, "State register number %d"
1844 " out of range\n", $1);
1847 error(&@2, "State sub register number %d"
1848 " out of range\n", $2);
1850 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1851 $$.nr = BRW_ARF_STATE;
1857 CONTROLREG subregnum
1860 error(&@2, "control sub register number %d"
1861 " out of range\n", $2);
1863 $$ = brw_cr0_reg($2);
1868 IPREG { $$ = brw_ip_reg(); }
1872 NULL_TOKEN { $$ = brw_null_reg(); }
1879 error(&@1, "Thread control register number %d"
1880 " out of range\n", $1);
1883 error(&@2, "Thread control sub register number %d"
1884 " out of range\n", $2);
1892 PERFORMANCEREG subregnum
1895 if (p->devinfo->gen >= 10)
1897 else if (p->devinfo->gen <= 8)
1903 error(&@2, "Performance sub register number %d"
1904 " out of range\n", $2);
1906 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1907 $$.nr = BRW_ARF_TIMESTAMP;
1912 CHANNELENABLEREG subregnum
1915 error(&@1, "Channel enable register number %d"
1916 " out of range\n", $1);
1918 $$ = brw_mask_reg($2);
1922 /* Immediate values */
1928 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1930 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1939 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1940 error(&@2, "Invalid Horizontal stride %d\n", $2);
1954 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1958 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1959 error(&@2, "Invalid VertStride %d\n", $2);
1961 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1963 | LANGLE exp COMMA exp COMMA exp RANGLE
1966 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1967 error(&@2, "Invalid VertStride %d\n", $2);
1969 if ($4 > 16 || !isPowerofTwo($4))
1970 error(&@4, "Invalid width %d\n", $4);
1972 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1973 error(&@6, "Invalid Horizontal stride in"
1974 " region_wh %d\n", $6);
1976 $$ = stride($$, $2, $4, $6);
1978 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1980 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1981 error(&@2, "Invalid VertStride %d\n", $2);
1983 if ($4 > 16 || !isPowerofTwo($4))
1984 error(&@4, "Invalid width %d\n", $4);
1986 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1987 error(&@6, "Invalid Horizontal stride in"
1988 " region_wh %d\n", $6);
1990 $$ = stride($$, $2, $4, $6);
1992 | LANGLE VxH COMMA exp COMMA exp RANGLE
1994 if ($4 > 16 || !isPowerofTwo($4))
1995 error(&@4, "Invalid width %d\n", $4);
1997 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1998 error(&@6, "Invalid Horizontal stride in"
1999 " region_wh %d\n", $6);
2001 $$ = brw_VxH_indirect(0, 0);
2006 LANGLE exp COMMA exp RANGLE
2008 if ($2 > 16 || !isPowerofTwo($2))
2009 error(&@2, "Invalid width %d\n", $2);
2011 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2012 error(&@4, "Invalid Horizontal stride in"
2013 " region_wh %d\n", $4);
2015 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2020 TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
2021 | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
2022 | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
2023 | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
2024 | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
2025 | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
2026 | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
2027 | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
2028 | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
2029 | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
2030 | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
2031 | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
2035 reg_type { $$ = $1; }
2036 | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
2037 | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
2038 | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
2044 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2046 | DOT writemask_x writemask_y writemask_z writemask_w
2048 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2054 | X { $$ = 1 << BRW_CHANNEL_X; }
2059 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2064 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2069 | W { $$ = 1 << BRW_CHANNEL_W; }
2075 $$.swizzle = BRW_SWIZZLE_NOOP;
2079 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2081 | DOT chansel chansel chansel chansel
2083 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2094 /* Instruction prediction and modifiers */
2098 brw_push_insn_state(p);
2099 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2100 brw_set_default_flag_reg(p, 0, 0);
2101 brw_set_default_predicate_inverse(p, false);
2103 | LPAREN predstate flagreg predctrl RPAREN
2105 brw_push_insn_state(p);
2106 brw_set_default_predicate_inverse(p, $2);
2107 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2108 brw_set_default_predicate_control(p, $4);
2119 %empty { $$ = BRW_PREDICATE_NORMAL; }
2120 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2121 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2122 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2123 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2138 /* Source Modification */
2149 /* Flag (Conditional) Modifier */
2153 $$.cond_modifier = $1;
2155 $$.flag_subreg_nr = 0;
2157 | condModifiers DOT flagreg
2159 $$.cond_modifier = $1;
2160 $$.flag_reg_nr = $3.nr;
2161 $$.flag_subreg_nr = $3.subnr;
2166 %empty { $$ = BRW_CONDITIONAL_NONE; }
2181 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2182 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2185 /* Execution size */
2187 %empty %prec EMPTYEXECSIZE
2191 | LPAREN exp2 RPAREN
2193 if ($2 > 32 || !isPowerofTwo($2))
2194 error(&@2, "Invalid execution size %d\n", $2);
2200 /* Instruction options */
2204 memset(&$$, 0, sizeof($$));
2206 | LCURLY instoption_list RCURLY
2208 memset(&$$, 0, sizeof($$));
2214 instoption_list COMMA instoption
2216 memset(&$$, 0, sizeof($$));
2218 add_instruction_option(&$$, $3);
2220 | instoption_list instoption
2222 memset(&$$, 0, sizeof($$));
2224 add_instruction_option(&$$, $2);
2228 memset(&$$, 0, sizeof($$));
2233 ALIGN1 { $$ = ALIGN1;}
2234 | ALIGN16 { $$ = ALIGN16; }
2235 | ACCWREN { $$ = ACCWREN; }
2236 | SECHALF { $$ = SECHALF; }
2237 | COMPR { $$ = COMPR; }
2238 | COMPR4 { $$ = COMPR4; }
2239 | BREAKPOINT { $$ = BREAKPOINT; }
2240 | NODDCLR { $$ = NODDCLR; }
2241 | NODDCHK { $$ = NODDCHK; }
2242 | MASK_DISABLE { $$ = MASK_DISABLE; }
2244 | SWITCH { $$ = SWITCH; }
2245 | ATOMIC { $$ = ATOMIC; }
2246 | CMPTCTRL { $$ = CMPTCTRL; }
2247 | WECTRL { $$ = WECTRL; }
2248 | QTR_2Q { $$ = QTR_2Q; }
2249 | QTR_3Q { $$ = QTR_3Q; }
2250 | QTR_4Q { $$ = QTR_4Q; }
2251 | QTR_2H { $$ = QTR_2H; }
2252 | QTR_2N { $$ = QTR_2N; }
2253 | QTR_3N { $$ = QTR_3N; }
2254 | QTR_4N { $$ = QTR_4N; }
2255 | QTR_5N { $$ = QTR_5N; }
2256 | QTR_6N { $$ = QTR_6N; }
2257 | QTR_7N { $$ = QTR_7N; }
2258 | QTR_8N { $$ = QTR_8N; }
2263 extern int yylineno;
2268 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2269 input_filename, yylineno, msg, lex_text());