a98451f15491340356cfc64dc43d2860c39a2e61
[mesa.git] / src / intel / tools / i965_gram.y
1 %{
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include <string.h>
28 #include <strings.h>
29 #include "i965_asm.h"
30
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
33 {
34 int first_line;
35 int first_column;
36 int last_line;
37 int last_column;
38 } YYLTYPE;
39
40 enum message_level {
41 WARN,
42 ERROR,
43 };
44
45 int yydebug = 1;
46
47 static void
48 message(enum message_level level, YYLTYPE *location,
49 const char *fmt, ...)
50 {
51 static const char *level_str[] = { "warning", "error" };
52 va_list args;
53
54 if (location)
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
56 location->first_line,
57 location->first_column, level_str[level]);
58 else
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
60
61 va_start(args, fmt);
62 vfprintf(stderr, fmt, args);
63 va_end(args);
64 }
65
66 #define warn(flag, l, fmt, ...) \
67 do { \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
70 } while (0)
71
72 #define error(l, fmt, ...) \
73 do { \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
75 } while (0)
76
77 static bool
78 isPowerofTwo(unsigned int x)
79 {
80 return x && (!(x & (x - 1)));
81 }
82
83 static struct brw_reg
84 set_direct_src_operand(struct brw_reg *reg, int type)
85 {
86 return brw_reg(reg->file,
87 reg->nr,
88 reg->subnr,
89 0, // negate
90 0, // abs
91 type,
92 0, // vstride
93 0, // width
94 0, // hstride
95 BRW_SWIZZLE_NOOP,
96 WRITEMASK_XYZW);
97 }
98
99 static void
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
102 {
103 switch (opcode) {
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
106 break;
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
109 break;
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
112 break;
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
115 break;
116 case BRW_OPCODE_MOV:
117 brw_MOV(p, dest, src0);
118 break;
119 case BRW_OPCODE_FBL:
120 brw_FBL(p, dest, src0);
121 break;
122 case BRW_OPCODE_FRC:
123 brw_FRC(p, dest, src0);
124 break;
125 case BRW_OPCODE_FBH:
126 brw_FBH(p, dest, src0);
127 break;
128 case BRW_OPCODE_NOT:
129 brw_NOT(p, dest, src0);
130 break;
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
133 break;
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
136 break;
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
139 break;
140 case BRW_OPCODE_LZD:
141 brw_LZD(p, dest, src0);
142 break;
143 case BRW_OPCODE_DIM:
144 brw_DIM(p, dest, src0);
145 break;
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
148 break;
149 default:
150 fprintf(stderr, "Unsupported unary opcode\n");
151 }
152 }
153
154 static void
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
157 struct brw_reg dest,
158 struct brw_reg src0,
159 struct brw_reg src1)
160 {
161 switch (opcode) {
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
164 break;
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
167 break;
168 case BRW_OPCODE_DP2:
169 brw_DP2(p, dest, src0, src1);
170 break;
171 case BRW_OPCODE_DP3:
172 brw_DP3(p, dest, src0, src1);
173 break;
174 case BRW_OPCODE_DP4:
175 brw_DP4(p, dest, src0, src1);
176 break;
177 case BRW_OPCODE_DPH:
178 brw_DPH(p, dest, src0, src1);
179 break;
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
182 break;
183 case BRW_OPCODE_MAC:
184 brw_MAC(p, dest, src0, src1);
185 break;
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
188 break;
189 case BRW_OPCODE_PLN:
190 brw_PLN(p, dest, src0, src1);
191 break;
192 case BRW_OPCODE_ROL:
193 brw_ROL(p, dest, src0, src1);
194 break;
195 case BRW_OPCODE_ROR:
196 brw_ROR(p, dest, src0, src1);
197 break;
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
200 break;
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
203 break;
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
206 break;
207 case BRW_OPCODE_ADD:
208 brw_ADD(p, dest, src0, src1);
209 break;
210 case BRW_OPCODE_CMP:
211 /* Third parameter is conditional modifier
212 * which gets updated later
213 */
214 brw_CMP(p, dest, 0, src0, src1);
215 break;
216 case BRW_OPCODE_AND:
217 brw_AND(p, dest, src0, src1);
218 break;
219 case BRW_OPCODE_ASR:
220 brw_ASR(p, dest, src0, src1);
221 break;
222 case BRW_OPCODE_AVG:
223 brw_AVG(p, dest, src0, src1);
224 break;
225 case BRW_OPCODE_OR:
226 brw_OR(p, dest, src0, src1);
227 break;
228 case BRW_OPCODE_SEL:
229 brw_SEL(p, dest, src0, src1);
230 break;
231 case BRW_OPCODE_SHL:
232 brw_SHL(p, dest, src0, src1);
233 break;
234 case BRW_OPCODE_SHR:
235 brw_SHR(p, dest, src0, src1);
236 break;
237 case BRW_OPCODE_XOR:
238 brw_XOR(p, dest, src0, src1);
239 break;
240 case BRW_OPCODE_MUL:
241 brw_MUL(p, dest, src0, src1);
242 break;
243 default:
244 fprintf(stderr, "Unsupported binary opcode\n");
245 }
246 }
247
248 static void
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
251 struct brw_reg dest,
252 struct brw_reg src0,
253 struct brw_reg src1,
254 struct brw_reg src2)
255 {
256 switch (opcode) {
257 case BRW_OPCODE_MAD:
258 brw_MAD(p, dest, src0, src1, src2);
259 break;
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
262 break;
263 case BRW_OPCODE_LRP:
264 brw_LRP(p, dest, src0, src1, src2);
265 break;
266 case BRW_OPCODE_BFE:
267 brw_BFE(p, dest, src0, src1, src2);
268 break;
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
271 break;
272 default:
273 fprintf(stderr, "Unsupported ternary opcode\n");
274 }
275 }
276
277 static void
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
280 {
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
297 options.compaction);
298 }
299
300 static void
301 i965_asm_set_dst_nr(struct brw_codegen *p,
302 struct brw_reg *reg,
303 struct options options)
304 {
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
308 !options.is_compr)
309 reg->nr |= BRW_MRF_COMPR4;
310 }
311 }
312
313 %}
314
315 %locations
316
317 %start ROOT
318
319 %union {
320 double number;
321 int integer;
322 unsigned long long int llint;
323 struct brw_reg reg;
324 enum brw_reg_type reg_type;
325 struct brw_codegen *program;
326 struct predicate predicate;
327 struct condition condition;
328 struct options options;
329 brw_inst *instruction;
330 }
331
332 %token ABS
333 %token COLON
334 %token COMMA
335 %token DOT
336 %token LANGLE RANGLE
337 %token LCURLY RCURLY
338 %token LPAREN RPAREN
339 %token LSQUARE RSQUARE
340 %token PLUS MINUS
341 %token SEMICOLON
342
343 /* datatypes */
344 %token <integer> TYPE_B TYPE_UB
345 %token <integer> TYPE_W TYPE_UW
346 %token <integer> TYPE_D TYPE_UD
347 %token <integer> TYPE_Q TYPE_UQ
348 %token <integer> TYPE_V TYPE_UV
349 %token <integer> TYPE_F TYPE_HF
350 %token <integer> TYPE_DF TYPE_NF
351 %token <integer> TYPE_VF
352
353 /* opcodes */
354 %token <integer> ADD ADD3 ADDC AND ASR AVG
355 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
356 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
357 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
358 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
359 %token <integer> GOTO
360 %token <integer> HALT
361 %token <integer> IF IFF ILLEGAL
362 %token <integer> JMPI JOIN
363 %token <integer> LINE LRP LZD
364 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
365 %token <integer> NENOP NOP NOT
366 %token <integer> OR
367 %token <integer> PLN POP PUSH
368 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
369 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
370 %token <integer> WAIT WHILE
371 %token <integer> XOR
372
373 /* extended math functions */
374 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
375 %token <integer> RSQRTM SIN SINCOS SQRT
376
377 /* shared functions for send */
378 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
379 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
380
381 /* Conditional modifiers */
382 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
383 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
384
385 /* register Access Modes */
386 %token ALIGN1 ALIGN16
387
388 /* accumulator write control */
389 %token ACCWREN
390
391 /* compaction control */
392 %token CMPTCTRL
393
394 /* compression control */
395 %token COMPR COMPR4 SECHALF
396
397 /* mask control (WeCtrl) */
398 %token WECTRL
399
400 /* debug control */
401 %token BREAKPOINT
402
403 /* dependency control */
404 %token NODDCLR NODDCHK
405
406 /* end of thread */
407 %token EOT
408
409 /* mask control */
410 %token MASK_DISABLE;
411
412 /* predicate control */
413 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
414 %token <integer> ANY32H ALL32H
415
416 /* round instructions */
417 %token <integer> ROUND_INCREMENT
418
419 /* staturation */
420 %token SATURATE
421
422 /* thread control */
423 %token ATOMIC SWITCH
424
425 /* quater control */
426 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
427 %token QTR_6N QTR_7N QTR_8N
428
429 /* channels */
430 %token <integer> X Y Z W
431
432 /* reg files */
433 %token GENREGFILE MSGREGFILE
434
435 /* vertical stride in register region */
436 %token VxH
437
438 /* register type */
439 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
440 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
441 %token <integer> MASKREG
442
443 %token <integer> INTEGER
444 %token <llint> LONG
445 %token NULL_TOKEN
446
447 %precedence SUBREGNUM
448 %left PLUS MINUS
449 %precedence DOT
450 %precedence EMPTYEXECSIZE
451 %precedence LPAREN
452
453 %type <integer> execsize simple_int exp
454 %type <llint> exp2
455
456 /* predicate control */
457 %type <integer> predctrl predstate
458 %type <predicate> predicate
459
460 /* conditional modifier */
461 %type <condition> cond_mod
462 %type <integer> condModifiers
463
464 /* instruction options */
465 %type <options> instoptions instoption_list
466 %type <integer> instoption
467
468 /* writemask */
469 %type <integer> writemask_x writemask_y writemask_z writemask_w
470 %type <reg> writemask
471
472 /* dst operand */
473 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
474 %type <integer> dstregion
475
476 %type <integer> saturate relativelocation rellocation
477 %type <reg> relativelocation2
478
479 /* src operand */
480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
482 %type <reg> indirectgenreg indirectregion
483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
484 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
485
486 /* registers */
487 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
488 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
489 %type <integer> subregnum
490
491 /* register types */
492 %type <reg_type> reg_type imm_type
493
494 /* immediate values */
495 %type <llint> immval
496
497 /* instruction opcodes */
498 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
499 %type <integer> sendop
500 %type <instruction> sendopcode
501
502 %type <integer> negate abs chansel math_function sharedfunction
503
504 %code {
505
506 static void
507 add_instruction_option(struct options *options, int option)
508 {
509 switch (option) {
510 case ALIGN1:
511 options->access_mode = BRW_ALIGN_1;
512 break;
513 case ALIGN16:
514 options->access_mode = BRW_ALIGN_16;
515 break;
516 case SECHALF:
517 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
518 break;
519 case COMPR:
520 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
521 options->is_compr = true;
522 break;
523 case COMPR4:
524 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
525 break;
526 case SWITCH:
527 options->thread_control |= BRW_THREAD_SWITCH;
528 break;
529 case ATOMIC:
530 options->thread_control |= BRW_THREAD_ATOMIC;
531 break;
532 case NODDCHK:
533 options->no_dd_check = true;
534 break;
535 case NODDCLR:
536 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
537 break;
538 case MASK_DISABLE:
539 options->mask_control |= BRW_MASK_DISABLE;
540 break;
541 case BREAKPOINT:
542 options->debug_control = BRW_DEBUG_BREAKPOINT;
543 break;
544 case WECTRL:
545 options->mask_control |= BRW_WE_ALL;
546 break;
547 case CMPTCTRL:
548 options->compaction = true;
549 break;
550 case ACCWREN:
551 options->acc_wr_control = true;
552 break;
553 case EOT:
554 options->end_of_thread = true;
555 break;
556 /* TODO : Figure out how to set instruction group and get rid of
557 * code below
558 */
559 case QTR_2Q:
560 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
561 break;
562 case QTR_3Q:
563 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
564 break;
565 case QTR_4Q:
566 options->qtr_ctrl = 3;
567 break;
568 case QTR_2H:
569 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
570 break;
571 case QTR_2N:
572 options->qtr_ctrl = BRW_COMPRESSION_NONE;
573 options->nib_ctrl = true;
574 break;
575 case QTR_3N:
576 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
577 break;
578 case QTR_4N:
579 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
580 options->nib_ctrl = true;
581 break;
582 case QTR_5N:
583 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
584 break;
585 case QTR_6N:
586 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
587 options->nib_ctrl = true;
588 break;
589 case QTR_7N:
590 options->qtr_ctrl = 3;
591 break;
592 case QTR_8N:
593 options->qtr_ctrl = 3;
594 options->nib_ctrl = true;
595 break;
596 }
597 }
598 }
599 %%
600
601 ROOT:
602 instrseq
603 ;
604
605 instrseq:
606 instrseq instruction SEMICOLON
607 | instrseq relocatableinstruction SEMICOLON
608 | instruction SEMICOLON
609 | relocatableinstruction SEMICOLON
610 ;
611
612 /* Instruction Group */
613 instruction:
614 unaryinstruction
615 | binaryinstruction
616 | binaryaccinstruction
617 | mathinstruction
618 | nopinstruction
619 | syncinstruction
620 | ternaryinstruction
621 | sendinstruction
622 | illegalinstruction
623 ;
624
625 relocatableinstruction:
626 jumpinstruction
627 | branchinstruction
628 | breakinstruction
629 | loopinstruction
630 ;
631
632 illegalinstruction:
633 ILLEGAL execsize instoptions
634 {
635 brw_next_insn(p, $1);
636 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
637 i965_asm_set_instruction_options(p, $3);
638 }
639 ;
640
641 /* Unary instruction */
642 unaryinstruction:
643 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
644 {
645 i965_asm_set_dst_nr(p, &$6, $8);
646 brw_set_default_access_mode(p, $8.access_mode);
647 i965_asm_unary_instruction($2, p, $6, $7);
648 brw_pop_insn_state(p);
649 i965_asm_set_instruction_options(p, $8);
650 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
651 $4.cond_modifier);
652
653 if (p->devinfo->gen >= 7) {
654 if ($2 != BRW_OPCODE_DIM) {
655 brw_inst_set_flag_reg_nr(p->devinfo,
656 brw_last_inst,
657 $4.flag_reg_nr);
658 brw_inst_set_flag_subreg_nr(p->devinfo,
659 brw_last_inst,
660 $4.flag_subreg_nr);
661 }
662 }
663
664 if ($7.file != BRW_IMMEDIATE_VALUE) {
665 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
666 $7.vstride);
667 }
668 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
669 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
670 // TODO: set instruction group instead of qtr and nib ctrl
671 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
672 $8.qtr_ctrl);
673
674 if (p->devinfo->gen >= 7)
675 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
676 $8.nib_ctrl);
677 }
678 ;
679
680 unaryopcodes:
681 BFREV
682 | CBIT
683 | DIM
684 | F16TO32
685 | F32TO16
686 | FBH
687 | FBL
688 | FRC
689 | LZD
690 | MOV
691 | NOT
692 | RNDD
693 | RNDE
694 | RNDU
695 | RNDZ
696 ;
697
698 /* Binary instruction */
699 binaryinstruction:
700 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
701 {
702 i965_asm_set_dst_nr(p, &$6, $9);
703 brw_set_default_access_mode(p, $9.access_mode);
704 i965_asm_binary_instruction($2, p, $6, $7, $8);
705 i965_asm_set_instruction_options(p, $9);
706 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
707 $4.cond_modifier);
708
709 if (p->devinfo->gen >= 7) {
710 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
711 $4.flag_reg_nr);
712 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
713 $4.flag_subreg_nr);
714 }
715
716 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
717 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
718 // TODO: set instruction group instead of qtr and nib ctrl
719 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
720 $9.qtr_ctrl);
721
722 if (p->devinfo->gen >= 7)
723 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
724 $9.nib_ctrl);
725
726 brw_pop_insn_state(p);
727 }
728 ;
729
730 binaryopcodes:
731 ADDC
732 | BFI1
733 | DP2
734 | DP3
735 | DP4
736 | DPH
737 | LINE
738 | MAC
739 | MACH
740 | MUL
741 | PLN
742 | ROL
743 | ROR
744 | SAD2
745 | SADA2
746 | SUBB
747 ;
748
749 /* Binary acc instruction */
750 binaryaccinstruction:
751 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
752 {
753 i965_asm_set_dst_nr(p, &$6, $9);
754 brw_set_default_access_mode(p, $9.access_mode);
755 i965_asm_binary_instruction($2, p, $6, $7, $8);
756 brw_pop_insn_state(p);
757 i965_asm_set_instruction_options(p, $9);
758 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
759 $4.cond_modifier);
760
761 if (p->devinfo->gen >= 7) {
762 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
763 brw_inst_set_flag_reg_nr(p->devinfo,
764 brw_last_inst,
765 $4.flag_reg_nr);
766 brw_inst_set_flag_subreg_nr(p->devinfo,
767 brw_last_inst,
768 $4.flag_subreg_nr);
769 }
770 }
771
772 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
773 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
774 // TODO: set instruction group instead of qtr and nib ctrl
775 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
776 $9.qtr_ctrl);
777
778 if (p->devinfo->gen >= 7)
779 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
780 $9.nib_ctrl);
781 }
782 ;
783
784 binaryaccopcodes:
785 ADD
786 | AND
787 | ASR
788 | AVG
789 | CMP
790 | CMPN
791 | OR
792 | SEL
793 | SHL
794 | SHR
795 | XOR
796 ;
797
798 /* Math instruction */
799 mathinstruction:
800 predicate MATH saturate math_function execsize dst src srcimm instoptions
801 {
802 brw_set_default_access_mode(p, $9.access_mode);
803 gen6_math(p, $6, $4, $7, $8);
804 i965_asm_set_instruction_options(p, $9);
805 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
806 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
807 // TODO: set instruction group instead
808 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
809 $9.qtr_ctrl);
810
811 if (p->devinfo->gen >= 7)
812 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
813 $9.nib_ctrl);
814
815 brw_pop_insn_state(p);
816 }
817 ;
818
819 math_function:
820 COS
821 | EXP
822 | FDIV
823 | INV
824 | INVM
825 | INTDIV
826 | INTDIVMOD
827 | INTMOD
828 | LOG
829 | POW
830 | RSQ
831 | RSQRTM
832 | SIN
833 | SQRT
834 | SINCOS
835 ;
836
837 /* NOP instruction */
838 nopinstruction:
839 NOP
840 {
841 brw_NOP(p);
842 }
843 ;
844
845 /* Ternary operand instruction */
846 ternaryinstruction:
847 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
848 {
849 brw_set_default_access_mode(p, $10.access_mode);
850 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
851 brw_pop_insn_state(p);
852 i965_asm_set_instruction_options(p, $10);
853 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
854 $4.cond_modifier);
855
856 if (p->devinfo->gen >= 7) {
857 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
858 $4.flag_reg_nr);
859 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
860 $4.flag_subreg_nr);
861 }
862
863 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
864 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
865 // TODO: set instruction group instead of qtr and nib ctrl
866 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
867 $10.qtr_ctrl);
868
869 if (p->devinfo->gen >= 7)
870 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
871 $10.nib_ctrl);
872 }
873 ;
874
875 ternaryopcodes:
876 CSEL
877 | BFE
878 | BFI2
879 | LRP
880 | MAD
881 ;
882
883 /* Sync instruction */
884 syncinstruction:
885 WAIT execsize src instoptions
886 {
887 brw_next_insn(p, $1);
888 i965_asm_set_instruction_options(p, $4);
889 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
890 brw_set_default_access_mode(p, $4.access_mode);
891 struct brw_reg src = brw_notification_reg();
892 brw_set_dest(p, brw_last_inst, src);
893 brw_set_src0(p, brw_last_inst, src);
894 brw_set_src1(p, brw_last_inst, brw_null_reg());
895 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
896 }
897 ;
898
899 /* Send instruction */
900 sendinstruction:
901 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
902 {
903 i965_asm_set_instruction_options(p, $8);
904 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
905 brw_set_dest(p, brw_last_inst, $4);
906 brw_set_src0(p, brw_last_inst, $5);
907 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
908 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
909 BRW_IMMEDIATE_VALUE,
910 BRW_REGISTER_TYPE_UD);
911 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
912 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
913 // TODO: set instruction group instead of qtr and nib ctrl
914 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
915 $8.qtr_ctrl);
916
917 if (p->devinfo->gen >= 7)
918 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
919 $8.nib_ctrl);
920
921 brw_pop_insn_state(p);
922 }
923 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
924 {
925 i965_asm_set_instruction_options(p, $9);
926 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
927 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
928 brw_set_dest(p, brw_last_inst, $5);
929 brw_set_src0(p, brw_last_inst, $6);
930 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
931 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
932 BRW_IMMEDIATE_VALUE,
933 BRW_REGISTER_TYPE_UD);
934 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
935 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
936 // TODO: set instruction group instead of qtr and nib ctrl
937 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
938 $9.qtr_ctrl);
939
940 if (p->devinfo->gen >= 7)
941 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
942 $9.nib_ctrl);
943
944 brw_pop_insn_state(p);
945 }
946 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
947 {
948 i965_asm_set_instruction_options(p, $9);
949 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
950 brw_set_dest(p, brw_last_inst, $4);
951 brw_set_src0(p, brw_last_inst, $5);
952 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
953 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
954 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
955 // TODO: set instruction group instead of qtr and nib ctrl
956 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
957 $9.qtr_ctrl);
958
959 if (p->devinfo->gen >= 7)
960 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
961 $9.nib_ctrl);
962
963 brw_pop_insn_state(p);
964 }
965 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
966 {
967 brw_next_insn(p, $2);
968 i965_asm_set_instruction_options(p, $10);
969 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
970 brw_set_dest(p, brw_last_inst, $4);
971 brw_set_src0(p, brw_last_inst, $5);
972 brw_set_src1(p, brw_last_inst, $6);
973
974 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
975 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
976 } else {
977 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
978 }
979
980 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
981 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
982 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
983 // TODO: set instruction group instead of qtr and nib ctrl
984 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
985 $10.qtr_ctrl);
986
987 if (p->devinfo->gen >= 7)
988 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
989 $10.nib_ctrl);
990
991 brw_pop_insn_state(p);
992 }
993 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
994 {
995 brw_next_insn(p, $2);
996 i965_asm_set_instruction_options(p, $10);
997 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
998 brw_set_dest(p, brw_last_inst, $4);
999 brw_set_src0(p, brw_last_inst, $5);
1000 brw_set_src1(p, brw_last_inst, $6);
1001
1002 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1003 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1004
1005 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1006 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1007 // TODO: set instruction group instead of qtr and nib ctrl
1008 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1009 $10.qtr_ctrl);
1010
1011 if (p->devinfo->gen >= 7)
1012 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1013 $10.nib_ctrl);
1014
1015 brw_pop_insn_state(p);
1016 }
1017 ;
1018
1019 sendop:
1020 SEND
1021 | SENDC
1022 ;
1023
1024 sendopcode:
1025 sendop { $$ = brw_next_insn(p, $1); }
1026 ;
1027
1028 sharedfunction:
1029 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1030 | MATH { $$ = BRW_SFID_MATH; }
1031 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1032 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1033 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1034 | URB { $$ = BRW_SFID_URB; }
1035 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1036 | VME { $$ = BRW_SFID_VME; }
1037 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1038 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1039 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1040 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1041 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1042 | CRE { $$ = HSW_SFID_CRE; }
1043 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1044 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1045 ;
1046
1047 exp2:
1048 LONG { $$ = $1; }
1049 | MINUS LONG { $$ = -$2; }
1050 ;
1051
1052 /* Jump instruction */
1053 jumpinstruction:
1054 predicate JMPI execsize relativelocation2 instoptions
1055 {
1056 brw_next_insn(p, $2);
1057 i965_asm_set_instruction_options(p, $5);
1058 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1059 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1060 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1061 brw_set_src1(p, brw_last_inst, $4);
1062 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1063 brw_inst_pred_control(p->devinfo,
1064 brw_last_inst));
1065 brw_pop_insn_state(p);
1066 }
1067 ;
1068
1069 /* branch instruction */
1070 branchinstruction:
1071 predicate ENDIF execsize relativelocation instoptions
1072 {
1073 brw_next_insn(p, $2);
1074 i965_asm_set_instruction_options(p, $5);
1075 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1076
1077 if (p->devinfo->gen < 6) {
1078 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1079 BRW_REGISTER_TYPE_D));
1080 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1081 BRW_REGISTER_TYPE_D));
1082 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1083 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1084 $4);
1085 } else if (p->devinfo->gen == 6) {
1086 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1087 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1088 $4);
1089 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1090 BRW_REGISTER_TYPE_D));
1091 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1092 BRW_REGISTER_TYPE_D));
1093 } else if (p->devinfo->gen == 7) {
1094 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1095 BRW_REGISTER_TYPE_D));
1096 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1097 BRW_REGISTER_TYPE_D));
1098 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1099 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1100 } else {
1101 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1102 }
1103
1104 if (p->devinfo->gen < 6)
1105 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1106 BRW_THREAD_SWITCH);
1107 brw_pop_insn_state(p);
1108 }
1109 | ELSE execsize relativelocation rellocation instoptions
1110 {
1111 brw_next_insn(p, $1);
1112 i965_asm_set_instruction_options(p, $5);
1113 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1114
1115 if (p->devinfo->gen < 6) {
1116 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1117 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1118 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1119 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1120 $3);
1121 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1122 $4);
1123 } else if (p->devinfo->gen == 6) {
1124 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1125 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1126 $3);
1127 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1128 BRW_REGISTER_TYPE_D));
1129 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1130 BRW_REGISTER_TYPE_D));
1131 } else if (p->devinfo->gen == 7) {
1132 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1133 BRW_REGISTER_TYPE_D));
1134 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1135 BRW_REGISTER_TYPE_D));
1136 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1137 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1138 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1139 } else {
1140 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1141 BRW_REGISTER_TYPE_D));
1142 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1143 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1144 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1145 }
1146
1147 if (!p->single_program_flow && p->devinfo->gen < 6)
1148 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1149 BRW_THREAD_SWITCH);
1150 }
1151 | predicate IF execsize relativelocation rellocation instoptions
1152 {
1153 brw_next_insn(p, $2);
1154 i965_asm_set_instruction_options(p, $6);
1155 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1156
1157 if (p->devinfo->gen < 6) {
1158 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1159 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1160 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1161 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1162 $4);
1163 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1164 $5);
1165 } else if (p->devinfo->gen == 6) {
1166 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1167 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1168 $4);
1169 brw_set_src0(p, brw_last_inst,
1170 vec1(retype(brw_null_reg(),
1171 BRW_REGISTER_TYPE_D)));
1172 brw_set_src1(p, brw_last_inst,
1173 vec1(retype(brw_null_reg(),
1174 BRW_REGISTER_TYPE_D)));
1175 } else if (p->devinfo->gen == 7) {
1176 brw_set_dest(p, brw_last_inst,
1177 vec1(retype(brw_null_reg(),
1178 BRW_REGISTER_TYPE_D)));
1179 brw_set_src0(p, brw_last_inst,
1180 vec1(retype(brw_null_reg(),
1181 BRW_REGISTER_TYPE_D)));
1182 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1183 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1184 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1185 } else {
1186 brw_set_dest(p, brw_last_inst,
1187 vec1(retype(brw_null_reg(),
1188 BRW_REGISTER_TYPE_D)));
1189 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1190 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1191 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1192 }
1193
1194 if (!p->single_program_flow && p->devinfo->gen < 6)
1195 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1196 BRW_THREAD_SWITCH);
1197
1198 brw_pop_insn_state(p);
1199 }
1200 | predicate IFF execsize relativelocation instoptions
1201 {
1202 brw_next_insn(p, $2);
1203 i965_asm_set_instruction_options(p, $5);
1204 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1205
1206 if (p->devinfo->gen < 6) {
1207 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1208 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1209 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1210 $4);
1211 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1212 } else if (p->devinfo->gen == 6) {
1213 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1214 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1215 $4);
1216 brw_set_src0(p, brw_last_inst,
1217 vec1(retype(brw_null_reg(),
1218 BRW_REGISTER_TYPE_D)));
1219 brw_set_src1(p, brw_last_inst,
1220 vec1(retype(brw_null_reg(),
1221 BRW_REGISTER_TYPE_D)));
1222 } else if (p->devinfo->gen == 7) {
1223 brw_set_dest(p, brw_last_inst,
1224 vec1(retype(brw_null_reg(),
1225 BRW_REGISTER_TYPE_D)));
1226 brw_set_src0(p, brw_last_inst,
1227 vec1(retype(brw_null_reg(),
1228 BRW_REGISTER_TYPE_D)));
1229 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1230 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1231 } else {
1232 brw_set_dest(p, brw_last_inst,
1233 vec1(retype(brw_null_reg(),
1234 BRW_REGISTER_TYPE_D)));
1235 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1236 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1237 }
1238
1239 if (!p->single_program_flow && p->devinfo->gen < 6)
1240 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1241 BRW_THREAD_SWITCH);
1242
1243 brw_pop_insn_state(p);
1244 }
1245 ;
1246
1247 /* break instruction */
1248 breakinstruction:
1249 predicate BREAK execsize relativelocation relativelocation instoptions
1250 {
1251 brw_next_insn(p, $2);
1252 i965_asm_set_instruction_options(p, $6);
1253 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1254
1255 if (p->devinfo->gen >= 8) {
1256 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1257 BRW_REGISTER_TYPE_D));
1258 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1259 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1260 } else if (p->devinfo->gen >= 6) {
1261 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1262 BRW_REGISTER_TYPE_D));
1263 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1264 BRW_REGISTER_TYPE_D));
1265 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1266 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1267 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1268 } else {
1269 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1270 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1271 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1272 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1273 $4);
1274 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1275 $5);
1276 }
1277
1278 brw_pop_insn_state(p);
1279 }
1280 | predicate HALT execsize relativelocation relativelocation instoptions
1281 {
1282 brw_next_insn(p, $2);
1283 i965_asm_set_instruction_options(p, $6);
1284 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1285 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1286 BRW_REGISTER_TYPE_D));
1287
1288 if (p->devinfo->gen >= 8) {
1289 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1290 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1291 } else {
1292 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1293 BRW_REGISTER_TYPE_D));
1294 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1295 }
1296
1297 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1298 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1299 brw_pop_insn_state(p);
1300 }
1301 | predicate CONT execsize relativelocation relativelocation instoptions
1302 {
1303 brw_next_insn(p, $2);
1304 i965_asm_set_instruction_options(p, $6);
1305 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1306 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1307
1308 if (p->devinfo->gen >= 8) {
1309 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1310 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1311 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1312 } else {
1313 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1314 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1315 if (p->devinfo->gen >= 6) {
1316 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1317 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1318 } else {
1319 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1320 $4);
1321 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1322 $5);
1323 }
1324 }
1325
1326 brw_pop_insn_state(p);
1327 }
1328 ;
1329
1330 /* loop instruction */
1331 loopinstruction:
1332 predicate WHILE execsize relativelocation instoptions
1333 {
1334 brw_next_insn(p, $2);
1335 i965_asm_set_instruction_options(p, $5);
1336 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1337
1338 if (p->devinfo->gen >= 6) {
1339 if (p->devinfo->gen >= 8) {
1340 brw_set_dest(p, brw_last_inst,
1341 retype(brw_null_reg(),
1342 BRW_REGISTER_TYPE_D));
1343 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1344 } else if (p->devinfo->gen == 7) {
1345 brw_set_dest(p, brw_last_inst,
1346 retype(brw_null_reg(),
1347 BRW_REGISTER_TYPE_D));
1348 brw_set_src0(p, brw_last_inst,
1349 retype(brw_null_reg(),
1350 BRW_REGISTER_TYPE_D));
1351 brw_set_src1(p, brw_last_inst,
1352 brw_imm_w(0x0));
1353 brw_inst_set_jip(p->devinfo, brw_last_inst,
1354 $4);
1355 } else {
1356 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1357 brw_inst_set_gen6_jump_count(p->devinfo,
1358 brw_last_inst,
1359 $4);
1360 brw_set_src0(p, brw_last_inst,
1361 retype(brw_null_reg(),
1362 BRW_REGISTER_TYPE_D));
1363 brw_set_src1(p, brw_last_inst,
1364 retype(brw_null_reg(),
1365 BRW_REGISTER_TYPE_D));
1366 }
1367 } else {
1368 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1369 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1370 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1371 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1372 $4);
1373 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1374 0);
1375 }
1376 brw_pop_insn_state(p);
1377 }
1378 | DO execsize instoptions
1379 {
1380 brw_next_insn(p, $1);
1381 if (p->devinfo->gen < 6) {
1382 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1383 i965_asm_set_instruction_options(p, $3);
1384 brw_set_dest(p, brw_last_inst, brw_null_reg());
1385 brw_set_src0(p, brw_last_inst, brw_null_reg());
1386 brw_set_src1(p, brw_last_inst, brw_null_reg());
1387
1388 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1389 }
1390 }
1391 ;
1392
1393 /* Relative location */
1394 relativelocation2:
1395 immreg
1396 | reg32
1397 ;
1398
1399 simple_int:
1400 INTEGER { $$ = $1; }
1401 | MINUS INTEGER { $$ = -$2; }
1402 | LONG { $$ = $1; }
1403 | MINUS LONG { $$ = -$2; }
1404 ;
1405
1406 rellocation:
1407 relativelocation
1408 | %empty { $$ = 0; }
1409 ;
1410
1411 relativelocation:
1412 simple_int
1413 {
1414 $$ = $1;
1415 }
1416 ;
1417
1418 /* Destination register */
1419 dst:
1420 dstoperand
1421 | dstoperandex
1422 ;
1423
1424 dstoperand:
1425 dstreg dstregion writemask reg_type
1426 {
1427 $$ = $1;
1428
1429 if ($2 == -1) {
1430 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1431 $$.vstride = BRW_VERTICAL_STRIDE_1;
1432 $$.width = BRW_WIDTH_1;
1433 } else {
1434 $$.hstride = $2;
1435 }
1436 $$.type = $4;
1437 $$.writemask = $3.writemask;
1438 $$.swizzle = BRW_SWIZZLE_NOOP;
1439 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1440 }
1441 ;
1442
1443 dstoperandex:
1444 dstoperandex_typed dstregion writemask reg_type
1445 {
1446 $$ = $1;
1447 $$.hstride = $2;
1448 $$.type = $4;
1449 $$.writemask = $3.writemask;
1450 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1451 }
1452 /* BSpec says "When the conditional modifier is present, updates
1453 * to the selected flag register also occur. In this case, the
1454 * register region fields of the ‘null’ operand are valid."
1455 */
1456 | nullreg dstregion writemask reg_type
1457 {
1458 $$ = $1;
1459 if ($2 == -1) {
1460 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1461 $$.vstride = BRW_VERTICAL_STRIDE_1;
1462 $$.width = BRW_WIDTH_1;
1463 } else {
1464 $$.hstride = $2;
1465 }
1466 $$.writemask = $3.writemask;
1467 $$.type = $4;
1468 }
1469 | threadcontrolreg
1470 {
1471 $$ = $1;
1472 $$.hstride = 1;
1473 $$.type = BRW_REGISTER_TYPE_UW;
1474 }
1475 ;
1476
1477 dstoperandex_typed:
1478 accreg
1479 | addrreg
1480 | channelenablereg
1481 | controlreg
1482 | flagreg
1483 | ipreg
1484 | maskreg
1485 | performancereg
1486 | statereg
1487 ;
1488
1489 dstreg:
1490 directgenreg
1491 {
1492 $$ = $1;
1493 $$.address_mode = BRW_ADDRESS_DIRECT;
1494 }
1495 | indirectgenreg
1496 {
1497 $$ = $1;
1498 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1499 }
1500 | directmsgreg
1501 {
1502 $$ = $1;
1503 $$.address_mode = BRW_ADDRESS_DIRECT;
1504 }
1505 | indirectmsgreg
1506 {
1507 $$ = $1;
1508 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1509 }
1510 ;
1511
1512 /* Source register */
1513 srcaccimm:
1514 srcacc
1515 | immreg
1516 ;
1517
1518 immreg:
1519 immval imm_type
1520 {
1521 uint32_t u32;
1522 uint64_t u64;
1523 switch ($2) {
1524 case BRW_REGISTER_TYPE_UD:
1525 u32 = $1;
1526 $$ = brw_imm_ud(u32);
1527 break;
1528 case BRW_REGISTER_TYPE_D:
1529 $$ = brw_imm_d($1);
1530 break;
1531 case BRW_REGISTER_TYPE_UW:
1532 u32 = $1 | ($1 << 16);
1533 $$ = brw_imm_uw(u32);
1534 break;
1535 case BRW_REGISTER_TYPE_W:
1536 u32 = $1;
1537 $$ = brw_imm_w(u32);
1538 break;
1539 case BRW_REGISTER_TYPE_F:
1540 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1541 $$.u64 = $1;
1542 $$.ud = $1;
1543 break;
1544 case BRW_REGISTER_TYPE_V:
1545 $$ = brw_imm_v($1);
1546 break;
1547 case BRW_REGISTER_TYPE_UV:
1548 $$ = brw_imm_uv($1);
1549 break;
1550 case BRW_REGISTER_TYPE_VF:
1551 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1552 $$.d = $1;
1553 break;
1554 case BRW_REGISTER_TYPE_Q:
1555 u64 = $1;
1556 $$ = brw_imm_q(u64);
1557 break;
1558 case BRW_REGISTER_TYPE_UQ:
1559 u64 = $1;
1560 $$ = brw_imm_uq(u64);
1561 break;
1562 case BRW_REGISTER_TYPE_DF:
1563 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1564 $$.d64 = $1;
1565 break;
1566 default:
1567 error(&@2, "Unknown immediate type %s\n",
1568 brw_reg_type_to_letters($2));
1569 }
1570 }
1571 ;
1572
1573 reg32:
1574 directgenreg region reg_type
1575 {
1576 $$ = set_direct_src_operand(&$1, $3);
1577 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1578 }
1579 ;
1580
1581 payload:
1582 directsrcoperand
1583 ;
1584
1585 src:
1586 directsrcoperand
1587 | indirectsrcoperand
1588 ;
1589
1590 srcacc:
1591 directsrcaccoperand
1592 | indirectsrcoperand
1593 ;
1594
1595 srcimm:
1596 directsrcoperand
1597 | indirectsrcoperand
1598 | immreg
1599 ;
1600
1601 directsrcaccoperand:
1602 directsrcoperand
1603 | accreg region reg_type
1604 {
1605 $$ = set_direct_src_operand(&$1, $3);
1606 $$.vstride = $2.vstride;
1607 $$.width = $2.width;
1608 $$.hstride = $2.hstride;
1609 }
1610 ;
1611
1612 srcarcoperandex:
1613 srcarcoperandex_typed region reg_type
1614 {
1615 $$ = brw_reg($1.file,
1616 $1.nr,
1617 $1.subnr,
1618 0,
1619 0,
1620 $3,
1621 $2.vstride,
1622 $2.width,
1623 $2.hstride,
1624 BRW_SWIZZLE_NOOP,
1625 WRITEMASK_XYZW);
1626 }
1627 | nullreg region reg_type
1628 {
1629 $$ = set_direct_src_operand(&$1, $3);
1630 $$.vstride = $2.vstride;
1631 $$.width = $2.width;
1632 $$.hstride = $2.hstride;
1633 }
1634 | threadcontrolreg
1635 {
1636 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1637 }
1638 ;
1639
1640 srcarcoperandex_typed:
1641 channelenablereg
1642 | controlreg
1643 | flagreg
1644 | ipreg
1645 | maskreg
1646 | statereg
1647 ;
1648
1649 indirectsrcoperand:
1650 negate abs indirectgenreg indirectregion swizzle reg_type
1651 {
1652 $$ = brw_reg($3.file,
1653 0,
1654 $3.subnr,
1655 $1, // negate
1656 $2, // abs
1657 $6,
1658 $4.vstride,
1659 $4.width,
1660 $4.hstride,
1661 $5.swizzle,
1662 WRITEMASK_X);
1663
1664 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1665 // brw_reg set indirect_offset to 0 so set it to valid value
1666 $$.indirect_offset = $3.indirect_offset;
1667 }
1668 ;
1669
1670 directgenreg_list:
1671 directgenreg
1672 | directmsgreg
1673 | notifyreg
1674 | addrreg
1675 | performancereg
1676 ;
1677
1678 directsrcoperand:
1679 negate abs directgenreg_list region swizzle reg_type
1680 {
1681 $$ = brw_reg($3.file,
1682 $3.nr,
1683 $3.subnr,
1684 $1,
1685 $2,
1686 $6,
1687 $4.vstride,
1688 $4.width,
1689 $4.hstride,
1690 $5.swizzle,
1691 WRITEMASK_X);
1692 }
1693 | srcarcoperandex
1694 ;
1695
1696 /* Address register */
1697 addrparam:
1698 addrreg exp
1699 {
1700 memset(&$$, '\0', sizeof($$));
1701 $$.subnr = $1.subnr;
1702 $$.indirect_offset = $2;
1703 }
1704 | addrreg
1705 ;
1706
1707 /* Register files and register numbers */
1708 exp:
1709 INTEGER { $$ = $1; }
1710 | LONG { $$ = $1; }
1711 ;
1712
1713 subregnum:
1714 DOT exp { $$ = $2; }
1715 | %empty %prec SUBREGNUM { $$ = 0; }
1716 ;
1717
1718 directgenreg:
1719 GENREG subregnum
1720 {
1721 memset(&$$, '\0', sizeof($$));
1722 $$.file = BRW_GENERAL_REGISTER_FILE;
1723 $$.nr = $1;
1724 $$.subnr = $2;
1725 }
1726 ;
1727
1728 indirectgenreg:
1729 GENREGFILE LSQUARE addrparam RSQUARE
1730 {
1731 memset(&$$, '\0', sizeof($$));
1732 $$.file = BRW_GENERAL_REGISTER_FILE;
1733 $$.subnr = $3.subnr;
1734 $$.indirect_offset = $3.indirect_offset;
1735 }
1736 ;
1737
1738 directmsgreg:
1739 MSGREG subregnum
1740 {
1741 $$ = brw_message_reg($1);
1742 $$.subnr = $2;
1743 }
1744 ;
1745
1746 indirectmsgreg:
1747 MSGREGFILE LSQUARE addrparam RSQUARE
1748 {
1749 memset(&$$, '\0', sizeof($$));
1750 $$.file = BRW_MESSAGE_REGISTER_FILE;
1751 $$.subnr = $3.subnr;
1752 $$.indirect_offset = $3.indirect_offset;
1753 }
1754 ;
1755
1756 addrreg:
1757 ADDRREG subregnum
1758 {
1759 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1760
1761 if ($2 > subnr)
1762 error(&@2, "Address sub register number %d"
1763 "out of range\n", $2);
1764
1765 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1766 $$.nr = BRW_ARF_ADDRESS;
1767 $$.subnr = $2;
1768 }
1769 ;
1770
1771 accreg:
1772 ACCREG subregnum
1773 {
1774 int nr_reg;
1775 if (p->devinfo->gen < 8)
1776 nr_reg = 2;
1777 else
1778 nr_reg = 10;
1779
1780 if ($1 > nr_reg)
1781 error(&@1, "Accumulator register number %d"
1782 " out of range\n", $1);
1783
1784 memset(&$$, '\0', sizeof($$));
1785 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1786 $$.nr = BRW_ARF_ACCUMULATOR;
1787 $$.subnr = $2;
1788 }
1789 ;
1790
1791 flagreg:
1792 FLAGREG subregnum
1793 {
1794 // SNB = 1 flag reg and IVB+ = 2 flag reg
1795 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1796 int subnr = nr_reg;
1797
1798 if ($1 > nr_reg)
1799 error(&@1, "Flag register number %d"
1800 " out of range \n", $1);
1801 if ($2 > subnr)
1802 error(&@2, "Flag subregister number %d"
1803 " out of range\n", $2);
1804
1805 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1806 $$.nr = BRW_ARF_FLAG | $1;
1807 $$.subnr = $2;
1808 }
1809 ;
1810
1811 maskreg:
1812 MASKREG subregnum
1813 {
1814 if ($1 > 0)
1815 error(&@1, "Mask register number %d"
1816 " out of range\n", $1);
1817
1818 $$ = brw_mask_reg($2);
1819 }
1820 ;
1821
1822 notifyreg:
1823 NOTIFYREG subregnum
1824 {
1825 if ($1 > 0)
1826 error(&@1, "Notification register number %d"
1827 " out of range\n", $1);
1828
1829 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1830 if ($2 > subnr)
1831 error(&@2, "Notification sub register number %d"
1832 " out of range\n", $2);
1833
1834 $$ = brw_notification_reg();
1835 $$.subnr = $2;
1836 }
1837 ;
1838
1839 statereg:
1840 STATEREG subregnum
1841 {
1842 if ($1 > 2)
1843 error(&@1, "State register number %d"
1844 " out of range\n", $1);
1845
1846 if ($2 > 4)
1847 error(&@2, "State sub register number %d"
1848 " out of range\n", $2);
1849
1850 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1851 $$.nr = BRW_ARF_STATE;
1852 $$.subnr = $2;
1853 }
1854 ;
1855
1856 controlreg:
1857 CONTROLREG subregnum
1858 {
1859 if ($2 > 3)
1860 error(&@2, "control sub register number %d"
1861 " out of range\n", $2);
1862
1863 $$ = brw_cr0_reg($2);
1864 }
1865 ;
1866
1867 ipreg:
1868 IPREG { $$ = brw_ip_reg(); }
1869 ;
1870
1871 nullreg:
1872 NULL_TOKEN { $$ = brw_null_reg(); }
1873 ;
1874
1875 threadcontrolreg:
1876 THREADREG subregnum
1877 {
1878 if ($1 > 0)
1879 error(&@1, "Thread control register number %d"
1880 " out of range\n", $1);
1881
1882 if ($2 > 7)
1883 error(&@2, "Thread control sub register number %d"
1884 " out of range\n", $2);
1885
1886 $$ = brw_tdr_reg();
1887 $$.subnr = $2;
1888 }
1889 ;
1890
1891 performancereg:
1892 PERFORMANCEREG subregnum
1893 {
1894 int subnr;
1895 if (p->devinfo->gen >= 10)
1896 subnr = 5;
1897 else if (p->devinfo->gen <= 8)
1898 subnr = 3;
1899 else
1900 subnr = 4;
1901
1902 if ($2 > subnr)
1903 error(&@2, "Performance sub register number %d"
1904 " out of range\n", $2);
1905
1906 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1907 $$.nr = BRW_ARF_TIMESTAMP;
1908 }
1909 ;
1910
1911 channelenablereg:
1912 CHANNELENABLEREG subregnum
1913 {
1914 if ($1 > 0)
1915 error(&@1, "Channel enable register number %d"
1916 " out of range\n", $1);
1917
1918 $$ = brw_mask_reg($2);
1919 }
1920 ;
1921
1922 /* Immediate values */
1923 immval:
1924 exp2
1925 {
1926 $$ = $1;
1927 }
1928 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1929 {
1930 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1931 }
1932 ;
1933
1934 /* Regions */
1935 dstregion:
1936 %empty { $$ = -1; }
1937 | LANGLE exp RANGLE
1938 {
1939 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1940 error(&@2, "Invalid Horizontal stride %d\n", $2);
1941
1942 $$ = ffs($2);
1943 }
1944 ;
1945
1946 indirectregion:
1947 region
1948 | region_wh
1949 ;
1950
1951 region:
1952 %empty
1953 {
1954 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1955 }
1956 | LANGLE exp RANGLE
1957 {
1958 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1959 error(&@2, "Invalid VertStride %d\n", $2);
1960
1961 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1962 }
1963 | LANGLE exp COMMA exp COMMA exp RANGLE
1964 {
1965
1966 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1967 error(&@2, "Invalid VertStride %d\n", $2);
1968
1969 if ($4 > 16 || !isPowerofTwo($4))
1970 error(&@4, "Invalid width %d\n", $4);
1971
1972 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1973 error(&@6, "Invalid Horizontal stride in"
1974 " region_wh %d\n", $6);
1975
1976 $$ = stride($$, $2, $4, $6);
1977 }
1978 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1979 {
1980 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1981 error(&@2, "Invalid VertStride %d\n", $2);
1982
1983 if ($4 > 16 || !isPowerofTwo($4))
1984 error(&@4, "Invalid width %d\n", $4);
1985
1986 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1987 error(&@6, "Invalid Horizontal stride in"
1988 " region_wh %d\n", $6);
1989
1990 $$ = stride($$, $2, $4, $6);
1991 }
1992 | LANGLE VxH COMMA exp COMMA exp RANGLE
1993 {
1994 if ($4 > 16 || !isPowerofTwo($4))
1995 error(&@4, "Invalid width %d\n", $4);
1996
1997 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1998 error(&@6, "Invalid Horizontal stride in"
1999 " region_wh %d\n", $6);
2000
2001 $$ = brw_VxH_indirect(0, 0);
2002 }
2003 ;
2004
2005 region_wh:
2006 LANGLE exp COMMA exp RANGLE
2007 {
2008 if ($2 > 16 || !isPowerofTwo($2))
2009 error(&@2, "Invalid width %d\n", $2);
2010
2011 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2012 error(&@4, "Invalid Horizontal stride in"
2013 " region_wh %d\n", $4);
2014
2015 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2016 }
2017 ;
2018
2019 reg_type:
2020 TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
2021 | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
2022 | TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
2023 | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
2024 | TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
2025 | TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
2026 | TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
2027 | TYPE_DF { $$ = BRW_REGISTER_TYPE_DF; }
2028 | TYPE_UQ { $$ = BRW_REGISTER_TYPE_UQ; }
2029 | TYPE_Q { $$ = BRW_REGISTER_TYPE_Q; }
2030 | TYPE_HF { $$ = BRW_REGISTER_TYPE_HF; }
2031 | TYPE_NF { $$ = BRW_REGISTER_TYPE_NF; }
2032 ;
2033
2034 imm_type:
2035 reg_type { $$ = $1; }
2036 | TYPE_V { $$ = BRW_REGISTER_TYPE_V; }
2037 | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; }
2038 | TYPE_UV { $$ = BRW_REGISTER_TYPE_UV; }
2039 ;
2040
2041 writemask:
2042 %empty
2043 {
2044 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2045 }
2046 | DOT writemask_x writemask_y writemask_z writemask_w
2047 {
2048 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2049 }
2050 ;
2051
2052 writemask_x:
2053 %empty { $$ = 0; }
2054 | X { $$ = 1 << BRW_CHANNEL_X; }
2055 ;
2056
2057 writemask_y:
2058 %empty { $$ = 0; }
2059 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2060 ;
2061
2062 writemask_z:
2063 %empty { $$ = 0; }
2064 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2065 ;
2066
2067 writemask_w:
2068 %empty { $$ = 0; }
2069 | W { $$ = 1 << BRW_CHANNEL_W; }
2070 ;
2071
2072 swizzle:
2073 %empty
2074 {
2075 $$.swizzle = BRW_SWIZZLE_NOOP;
2076 }
2077 | DOT chansel
2078 {
2079 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2080 }
2081 | DOT chansel chansel chansel chansel
2082 {
2083 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2084 }
2085 ;
2086
2087 chansel:
2088 X
2089 | Y
2090 | Z
2091 | W
2092 ;
2093
2094 /* Instruction prediction and modifiers */
2095 predicate:
2096 %empty
2097 {
2098 brw_push_insn_state(p);
2099 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2100 brw_set_default_flag_reg(p, 0, 0);
2101 brw_set_default_predicate_inverse(p, false);
2102 }
2103 | LPAREN predstate flagreg predctrl RPAREN
2104 {
2105 brw_push_insn_state(p);
2106 brw_set_default_predicate_inverse(p, $2);
2107 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2108 brw_set_default_predicate_control(p, $4);
2109 }
2110 ;
2111
2112 predstate:
2113 %empty { $$ = 0; }
2114 | PLUS { $$ = 0; }
2115 | MINUS { $$ = 1; }
2116 ;
2117
2118 predctrl:
2119 %empty { $$ = BRW_PREDICATE_NORMAL; }
2120 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2121 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2122 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2123 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2124 | ANYV
2125 | ALLV
2126 | ANY2H
2127 | ALL2H
2128 | ANY4H
2129 | ALL4H
2130 | ANY8H
2131 | ALL8H
2132 | ANY16H
2133 | ALL16H
2134 | ANY32H
2135 | ALL32H
2136 ;
2137
2138 /* Source Modification */
2139 negate:
2140 %empty { $$ = 0; }
2141 | MINUS { $$ = 1; }
2142 ;
2143
2144 abs:
2145 %empty { $$ = 0; }
2146 | ABS { $$ = 1; }
2147 ;
2148
2149 /* Flag (Conditional) Modifier */
2150 cond_mod:
2151 condModifiers
2152 {
2153 $$.cond_modifier = $1;
2154 $$.flag_reg_nr = 0;
2155 $$.flag_subreg_nr = 0;
2156 }
2157 | condModifiers DOT flagreg
2158 {
2159 $$.cond_modifier = $1;
2160 $$.flag_reg_nr = $3.nr;
2161 $$.flag_subreg_nr = $3.subnr;
2162 }
2163 ;
2164
2165 condModifiers:
2166 %empty { $$ = BRW_CONDITIONAL_NONE; }
2167 | ZERO
2168 | EQUAL
2169 | NOT_ZERO
2170 | NOT_EQUAL
2171 | GREATER
2172 | GREATER_EQUAL
2173 | LESS
2174 | LESS_EQUAL
2175 | OVERFLOW
2176 | ROUND_INCREMENT
2177 | UNORDERED
2178 ;
2179
2180 saturate:
2181 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2182 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2183 ;
2184
2185 /* Execution size */
2186 execsize:
2187 %empty %prec EMPTYEXECSIZE
2188 {
2189 $$ = 0;
2190 }
2191 | LPAREN exp2 RPAREN
2192 {
2193 if ($2 > 32 || !isPowerofTwo($2))
2194 error(&@2, "Invalid execution size %d\n", $2);
2195
2196 $$ = cvt($2) - 1;
2197 }
2198 ;
2199
2200 /* Instruction options */
2201 instoptions:
2202 %empty
2203 {
2204 memset(&$$, 0, sizeof($$));
2205 }
2206 | LCURLY instoption_list RCURLY
2207 {
2208 memset(&$$, 0, sizeof($$));
2209 $$ = $2;
2210 }
2211 ;
2212
2213 instoption_list:
2214 instoption_list COMMA instoption
2215 {
2216 memset(&$$, 0, sizeof($$));
2217 $$ = $1;
2218 add_instruction_option(&$$, $3);
2219 }
2220 | instoption_list instoption
2221 {
2222 memset(&$$, 0, sizeof($$));
2223 $$ = $1;
2224 add_instruction_option(&$$, $2);
2225 }
2226 | %empty
2227 {
2228 memset(&$$, 0, sizeof($$));
2229 }
2230 ;
2231
2232 instoption:
2233 ALIGN1 { $$ = ALIGN1;}
2234 | ALIGN16 { $$ = ALIGN16; }
2235 | ACCWREN { $$ = ACCWREN; }
2236 | SECHALF { $$ = SECHALF; }
2237 | COMPR { $$ = COMPR; }
2238 | COMPR4 { $$ = COMPR4; }
2239 | BREAKPOINT { $$ = BREAKPOINT; }
2240 | NODDCLR { $$ = NODDCLR; }
2241 | NODDCHK { $$ = NODDCHK; }
2242 | MASK_DISABLE { $$ = MASK_DISABLE; }
2243 | EOT { $$ = EOT; }
2244 | SWITCH { $$ = SWITCH; }
2245 | ATOMIC { $$ = ATOMIC; }
2246 | CMPTCTRL { $$ = CMPTCTRL; }
2247 | WECTRL { $$ = WECTRL; }
2248 | QTR_2Q { $$ = QTR_2Q; }
2249 | QTR_3Q { $$ = QTR_3Q; }
2250 | QTR_4Q { $$ = QTR_4Q; }
2251 | QTR_2H { $$ = QTR_2H; }
2252 | QTR_2N { $$ = QTR_2N; }
2253 | QTR_3N { $$ = QTR_3N; }
2254 | QTR_4N { $$ = QTR_4N; }
2255 | QTR_5N { $$ = QTR_5N; }
2256 | QTR_6N { $$ = QTR_6N; }
2257 | QTR_7N { $$ = QTR_7N; }
2258 | QTR_8N { $$ = QTR_8N; }
2259 ;
2260
2261 %%
2262
2263 extern int yylineno;
2264
2265 void
2266 yyerror(char *msg)
2267 {
2268 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2269 input_filename, yylineno, msg, lex_text());
2270 ++errors;
2271 }