src/intel/tools/i965_gram.y

   1 %{
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <strings.h>
  29 #include "i965_asm.h"
  30
  31 #define YYLTYPE YYLTYPE
  32 typedef struct YYLTYPE
  33 {
  34         int first_line;
  35         int first_column;
  36         int last_line;
  37         int last_column;
  38 } YYLTYPE;
  39
  40 enum message_level {
  41         WARN,
  42         ERROR,
  43 };
  44
  45 int yydebug = 1;
  46
  47 static void
  48 message(enum message_level level, YYLTYPE *location,
  49         const char *fmt, ...)
  50 {
  51         static const char *level_str[] = { "warning", "error" };
  52         va_list args;
  53
  54         if (location)
  55                 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
  56                         location->first_line,
  57                         location->first_column, level_str[level]);
  58         else
  59                 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
  60
  61         va_start(args, fmt);
  62         vfprintf(stderr, fmt, args);
  63         va_end(args);
  64 }
  65
  66 #define warn(flag, l, fmt, ...)                                  \
  67         do {                                                     \
  68                 if (warning_flags & WARN_ ## flag)               \
  69                         message(WARN, l, fmt, ## __VA_ARGS__);   \
  70         } while (0)
  71
  72 #define error(l, fmt, ...)                                       \
  73         do {                                                     \
  74                 message(ERROR, l, fmt, ## __VA_ARGS__);          \
  75         } while (0)
  76
  77 static bool
  78 isPowerofTwo(unsigned int x)
  79 {
  80         return x && (!(x & (x - 1)));
  81 }
  82
  83 static struct brw_reg
  84 set_direct_src_operand(struct brw_reg *reg, int type)
  85 {
  86         return brw_reg(reg->file,
  87                        reg->nr,
  88                        reg->subnr,
  89                        0,               // negate
  90                        0,               // abs
  91                        type,
  92                        0,               // vstride
  93                        0,               // width
  94                        0,               // hstride
  95                        BRW_SWIZZLE_NOOP,
  96                        WRITEMASK_XYZW);
  97 }
  98
  99 static void
 100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
 101                            struct brw_reg dest, struct brw_reg src0)
 102 {
 103         switch (opcode) {
 104         case BRW_OPCODE_BFREV:
 105                 brw_BFREV(p, dest, src0);
 106                 break;
 107         case BRW_OPCODE_CBIT:
 108                 brw_CBIT(p, dest, src0);
 109                 break;
 110         case BRW_OPCODE_F32TO16:
 111                 brw_F32TO16(p, dest, src0);
 112                 break;
 113         case BRW_OPCODE_F16TO32:
 114                 brw_F16TO32(p, dest, src0);
 115                 break;
 116         case BRW_OPCODE_MOV:
 117                 brw_MOV(p, dest, src0);
 118                 break;
 119         case BRW_OPCODE_FBL:
 120                 brw_FBL(p, dest, src0);
 121                 break;
 122         case BRW_OPCODE_FRC:
 123                 brw_FRC(p, dest, src0);
 124                 break;
 125         case BRW_OPCODE_FBH:
 126                 brw_FBH(p, dest, src0);
 127                 break;
 128         case BRW_OPCODE_NOT:
 129                 brw_NOT(p, dest, src0);
 130                 break;
 131         case BRW_OPCODE_RNDE:
 132                 brw_RNDE(p, dest, src0);
 133                 break;
 134         case BRW_OPCODE_RNDZ:
 135                 brw_RNDZ(p, dest, src0);
 136                 break;
 137         case BRW_OPCODE_RNDD:
 138                 brw_RNDD(p, dest, src0);
 139                 break;
 140         case BRW_OPCODE_LZD:
 141                 brw_LZD(p, dest, src0);
 142                 break;
 143         case BRW_OPCODE_DIM:
 144                 brw_DIM(p, dest, src0);
 145                 break;
 146         case BRW_OPCODE_RNDU:
 147                 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
 148                 break;
 149         default:
 150                 fprintf(stderr, "Unsupported unary opcode\n");
 151         }
 152 }
 153
 154 static void
 155 i965_asm_binary_instruction(int opcode,
 156                             struct brw_codegen *p,
 157                             struct brw_reg dest,
 158                             struct brw_reg src0,
 159                             struct brw_reg src1)
 160 {
 161         switch (opcode) {
 162         case BRW_OPCODE_ADDC:
 163                 brw_ADDC(p, dest, src0, src1);
 164                 break;
 165         case BRW_OPCODE_BFI1:
 166                 brw_BFI1(p, dest, src0, src1);
 167                 break;
 168         case BRW_OPCODE_DP2:
 169                 brw_DP2(p, dest, src0, src1);
 170                 break;
 171         case BRW_OPCODE_DP3:
 172                 brw_DP3(p, dest, src0, src1);
 173                 break;
 174         case BRW_OPCODE_DP4:
 175                 brw_DP4(p, dest, src0, src1);
 176                 break;
 177         case BRW_OPCODE_DPH:
 178                 brw_DPH(p, dest, src0, src1);
 179                 break;
 180         case BRW_OPCODE_LINE:
 181                 brw_LINE(p, dest, src0, src1);
 182                 break;
 183         case BRW_OPCODE_MAC:
 184                 brw_MAC(p, dest, src0, src1);
 185                 break;
 186         case BRW_OPCODE_MACH:
 187                 brw_MACH(p, dest, src0, src1);
 188                 break;
 189         case BRW_OPCODE_PLN:
 190                 brw_PLN(p, dest, src0, src1);
 191                 break;
 192         case BRW_OPCODE_ROL:
 193                 brw_ROL(p, dest, src0, src1);
 194                 break;
 195         case BRW_OPCODE_ROR:
 196                 brw_ROR(p, dest, src0, src1);
 197                 break;
 198         case BRW_OPCODE_SAD2:
 199                 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
 200                 break;
 201         case BRW_OPCODE_SADA2:
 202                 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
 203                 break;
 204         case BRW_OPCODE_SUBB:
 205                 brw_SUBB(p, dest, src0, src1);
 206                 break;
 207         case BRW_OPCODE_ADD:
 208                 brw_ADD(p, dest, src0, src1);
 209                 break;
 210         case BRW_OPCODE_CMP:
 211                 /* Third parameter is conditional modifier
 212                  * which gets updated later
 213                  */
 214                 brw_CMP(p, dest, 0, src0, src1);
 215                 break;
 216         case BRW_OPCODE_AND:
 217                 brw_AND(p, dest, src0, src1);
 218                 break;
 219         case BRW_OPCODE_ASR:
 220                 brw_ASR(p, dest, src0, src1);
 221                 break;
 222         case BRW_OPCODE_AVG:
 223                 brw_AVG(p, dest, src0, src1);
 224                 break;
 225         case BRW_OPCODE_OR:
 226                 brw_OR(p, dest, src0, src1);
 227                 break;
 228         case BRW_OPCODE_SEL:
 229                 brw_SEL(p, dest, src0, src1);
 230                 break;
 231         case BRW_OPCODE_SHL:
 232                 brw_SHL(p, dest, src0, src1);
 233                 break;
 234         case BRW_OPCODE_SHR:
 235                 brw_SHR(p, dest, src0, src1);
 236                 break;
 237         case BRW_OPCODE_XOR:
 238                 brw_XOR(p, dest, src0, src1);
 239                 break;
 240         case BRW_OPCODE_MUL:
 241                 brw_MUL(p, dest, src0, src1);
 242                 break;
 243         default:
 244                 fprintf(stderr, "Unsupported binary opcode\n");
 245         }
 246 }
 247
 248 static void
 249 i965_asm_ternary_instruction(int opcode,
 250                              struct brw_codegen *p,
 251                              struct brw_reg dest,
 252                              struct brw_reg src0,
 253                              struct brw_reg src1,
 254                              struct brw_reg src2)
 255 {
 256         switch (opcode) {
 257         case BRW_OPCODE_MAD:
 258                 brw_MAD(p, dest, src0, src1, src2);
 259                 break;
 260         case BRW_OPCODE_CSEL:
 261                 brw_CSEL(p, dest, src0, src1, src2);
 262                 break;
 263         case BRW_OPCODE_LRP:
 264                 brw_LRP(p, dest, src0, src1, src2);
 265                 break;
 266         case BRW_OPCODE_BFE:
 267                 brw_BFE(p, dest, src0, src1, src2);
 268                 break;
 269         case BRW_OPCODE_BFI2:
 270                 brw_BFI2(p, dest, src0, src1, src2);
 271                 break;
 272         default:
 273                 fprintf(stderr, "Unsupported ternary opcode\n");
 274         }
 275 }
 276
 277 static void
 278 i965_asm_set_instruction_options(struct brw_codegen *p,
 279                                  struct options options)
 280 {
 281         brw_inst_set_access_mode(p->devinfo, brw_last_inst,
 282                                  options.access_mode);
 283         brw_inst_set_mask_control(p->devinfo, brw_last_inst,
 284                                   options.mask_control);
 285         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
 286                                     options.thread_control);
 287         brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
 288                                  options.no_dd_check);
 289         brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 290                                  options.no_dd_clear);
 291         brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 292                                    options.debug_control);
 293         if (p->devinfo->gen >= 6)
 294                 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
 295                                             options.acc_wr_control);
 296         brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
 297                                   options.compaction);
 298 }
 299
 300 static void
 301 i965_asm_set_dst_nr(struct brw_codegen *p,
 302                     struct brw_reg *reg,
 303                     struct options options)
 304 {
 305         if (p->devinfo->gen <= 6) {
 306                 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
 307                     options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
 308                     !options.is_compr)
 309                         reg->nr |= BRW_MRF_COMPR4;
 310         }
 311 }
 312
 313 static void
 314 add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
 315 {
 316         if (!label_name) {
 317                 return;
 318         }
 319
 320         struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
 321
 322         label->name = ralloc_strdup(p->mem_ctx, label_name);
 323         label->offset = p->next_insn_offset;
 324         label->type = type;
 325
 326         list_addtail(&label->link, &instr_labels);
 327 }
 328
 329 %}
 330
 331 %locations
 332
 333 %start ROOT
 334
 335 %union {
 336         char *string;
 337         double number;
 338         int integer;
 339         unsigned long long int llint;
 340         struct brw_reg reg;
 341         enum brw_reg_type reg_type;
 342         struct brw_codegen *program;
 343         struct predicate predicate;
 344         struct condition condition;
 345         struct options options;
 346         brw_inst *instruction;
 347 }
 348
 349 %token ABS
 350 %token COLON
 351 %token COMMA
 352 %token DOT
 353 %token LANGLE RANGLE
 354 %token LCURLY RCURLY
 355 %token LPAREN RPAREN
 356 %token LSQUARE RSQUARE
 357 %token PLUS MINUS
 358 %token SEMICOLON
 359
 360 /* datatypes */
 361 %token <integer> TYPE_B TYPE_UB
 362 %token <integer> TYPE_W TYPE_UW
 363 %token <integer> TYPE_D TYPE_UD
 364 %token <integer> TYPE_Q TYPE_UQ
 365 %token <integer> TYPE_V TYPE_UV
 366 %token <integer> TYPE_F TYPE_HF
 367 %token <integer> TYPE_DF TYPE_NF
 368 %token <integer> TYPE_VF
 369
 370 /* label */
 371 %token <string> JUMP_LABEL
 372 %token <string> JUMP_LABEL_TARGET
 373
 374 /* opcodes */
 375 %token <integer> ADD ADD3 ADDC AND ASR AVG
 376 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 377 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
 378 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
 379 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
 380 %token <integer> GOTO
 381 %token <integer> HALT
 382 %token <integer> IF IFF ILLEGAL
 383 %token <integer> JMPI JOIN
 384 %token <integer> LINE LRP LZD
 385 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
 386 %token <integer> NENOP NOP NOT
 387 %token <integer> OR
 388 %token <integer> PLN POP PUSH
 389 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
 390 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
 391 %token <integer> WAIT WHILE
 392 %token <integer> XOR
 393
 394 /* extended math functions */
 395 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
 396 %token <integer> RSQRTM SIN SINCOS SQRT
 397
 398 /* shared functions for send */
 399 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
 400 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
 401
 402 /* Conditional modifiers */
 403 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
 404 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
 405
 406 /* register Access Modes */
 407 %token ALIGN1 ALIGN16
 408
 409 /* accumulator write control */
 410 %token ACCWREN
 411
 412 /* compaction control */
 413 %token CMPTCTRL
 414
 415 /* compression control */
 416 %token COMPR COMPR4 SECHALF
 417
 418 /* mask control (WeCtrl) */
 419 %token WECTRL
 420
 421 /* debug control */
 422 %token BREAKPOINT
 423
 424 /* dependency control */
 425 %token NODDCLR NODDCHK
 426
 427 /* end of thread */
 428 %token EOT
 429
 430 /* mask control */
 431 %token MASK_DISABLE;
 432
 433 /* predicate control */
 434 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
 435 %token <integer> ANY32H ALL32H
 436
 437 /* round instructions */
 438 %token <integer> ROUND_INCREMENT
 439
 440 /* staturation */
 441 %token SATURATE
 442
 443 /* thread control */
 444 %token ATOMIC SWITCH
 445
 446 /* quater control */
 447 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
 448 %token QTR_6N QTR_7N QTR_8N
 449
 450 /* channels */
 451 %token <integer> X Y Z W
 452
 453 /* reg files */
 454 %token GENREGFILE MSGREGFILE
 455
 456 /* vertical stride in register region */
 457 %token VxH
 458
 459 /* register type */
 460 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
 461 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
 462 %token <integer> MASKREG
 463
 464 %token <integer> INTEGER
 465 %token <llint> LONG
 466 %token NULL_TOKEN
 467
 468 %precedence SUBREGNUM
 469 %left PLUS MINUS
 470 %precedence DOT
 471 %precedence EMPTYEXECSIZE
 472 %precedence LPAREN
 473
 474 %type <integer> execsize simple_int exp
 475 %type <llint> exp2
 476
 477 /* predicate control */
 478 %type <integer> predctrl predstate
 479 %type <predicate> predicate
 480
 481 /* conditional modifier */
 482 %type <condition> cond_mod
 483 %type <integer> condModifiers
 484
 485 /* instruction options  */
 486 %type <options> instoptions instoption_list
 487 %type <integer> instoption
 488
 489 /* writemask */
 490 %type <integer> writemask_x writemask_y writemask_z writemask_w
 491 %type <integer> writemask
 492
 493 /* dst operand */
 494 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
 495 %type <integer> dstregion
 496
 497 %type <integer> saturate relativelocation rellocation
 498 %type <reg> relativelocation2
 499
 500 /* src operand */
 501 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 502 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
 503 %type <reg> indirectgenreg indirectregion
 504 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 505 %type <reg> region_wh directgenreg directmsgreg indirectmsgreg
 506 %type <integer> swizzle
 507
 508 /* registers */
 509 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
 510 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
 511 %type <integer> subregnum
 512
 513 /* register types */
 514 %type <reg_type> reg_type imm_type
 515
 516 /* immediate values */
 517 %type <llint> immval
 518
 519 /* instruction opcodes */
 520 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
 521 %type <integer> sendop
 522 %type <instruction> sendopcode
 523
 524 %type <integer> negate abs chansel math_function sharedfunction
 525
 526 %type <string> jumplabeltarget
 527 %type <string> jumplabel
 528
 529 %code {
 530
 531 static void
 532 add_instruction_option(struct options *options, int option)
 533 {
 534         switch (option) {
 535         case ALIGN1:
 536                 options->access_mode = BRW_ALIGN_1;
 537                 break;
 538         case ALIGN16:
 539                 options->access_mode = BRW_ALIGN_16;
 540                 break;
 541         case SECHALF:
 542                 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
 543                 break;
 544         case COMPR:
 545                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 546                 options->is_compr = true;
 547                 break;
 548         case COMPR4:
 549                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 550                 break;
 551         case SWITCH:
 552                 options->thread_control |= BRW_THREAD_SWITCH;
 553                 break;
 554         case ATOMIC:
 555                 options->thread_control |= BRW_THREAD_ATOMIC;
 556                 break;
 557         case NODDCHK:
 558                 options->no_dd_check = true;
 559                 break;
 560         case NODDCLR:
 561                 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
 562                 break;
 563         case MASK_DISABLE:
 564                 options->mask_control |= BRW_MASK_DISABLE;
 565                 break;
 566         case BREAKPOINT:
 567                 options->debug_control = BRW_DEBUG_BREAKPOINT;
 568                 break;
 569         case WECTRL:
 570                 options->mask_control |= BRW_WE_ALL;
 571                 break;
 572         case CMPTCTRL:
 573                 options->compaction = true;
 574                 break;
 575         case ACCWREN:
 576                 options->acc_wr_control = true;
 577                 break;
 578         case EOT:
 579                 options->end_of_thread = true;
 580                 break;
 581         /* TODO : Figure out how to set instruction group and get rid of
 582          * code below
 583          */
 584         case QTR_2Q:
 585                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 586                 break;
 587         case QTR_3Q:
 588                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 589                 break;
 590         case QTR_4Q:
 591                 options->qtr_ctrl = 3;
 592                 break;
 593         case QTR_2H:
 594                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 595                 break;
 596         case QTR_2N:
 597                 options->qtr_ctrl = BRW_COMPRESSION_NONE;
 598                 options->nib_ctrl = true;
 599                 break;
 600         case QTR_3N:
 601                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 602                 break;
 603         case QTR_4N:
 604                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 605                 options->nib_ctrl = true;
 606                 break;
 607         case QTR_5N:
 608                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 609                 break;
 610         case QTR_6N:
 611                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 612                 options->nib_ctrl = true;
 613                 break;
 614         case QTR_7N:
 615                 options->qtr_ctrl = 3;
 616                 break;
 617         case QTR_8N:
 618                 options->qtr_ctrl = 3;
 619                 options->nib_ctrl = true;
 620                 break;
 621         }
 622 }
 623 }
 624 %%
 625
 626 ROOT:
 627         instrseq
 628         ;
 629
 630 instrseq:
 631         instrseq instruction SEMICOLON
 632         | instrseq relocatableinstruction SEMICOLON
 633         | instruction SEMICOLON
 634         | relocatableinstruction SEMICOLON
 635         | instrseq jumplabeltarget
 636         | jumplabeltarget
 637         ;
 638
 639 /* Instruction Group */
 640 instruction:
 641         unaryinstruction
 642         | binaryinstruction
 643         | binaryaccinstruction
 644         | mathinstruction
 645         | nopinstruction
 646         | syncinstruction
 647         | ternaryinstruction
 648         | sendinstruction
 649         | illegalinstruction
 650         ;
 651
 652 relocatableinstruction:
 653         jumpinstruction
 654         | branchinstruction
 655         | breakinstruction
 656         | loopinstruction
 657         ;
 658
 659 illegalinstruction:
 660         ILLEGAL execsize instoptions
 661         {
 662                 brw_next_insn(p, $1);
 663                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 664                 i965_asm_set_instruction_options(p, $3);
 665         }
 666         ;
 667
 668 /* Unary instruction */
 669 unaryinstruction:
 670         predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
 671         {
 672                 i965_asm_set_dst_nr(p, &$6, $8);
 673                 brw_set_default_access_mode(p, $8.access_mode);
 674                 i965_asm_unary_instruction($2, p, $6, $7);
 675                 brw_pop_insn_state(p);
 676                 i965_asm_set_instruction_options(p, $8);
 677                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 678                                            $4.cond_modifier);
 679
 680                 if (p->devinfo->gen >= 7) {
 681                         if ($2 != BRW_OPCODE_DIM) {
 682                                 brw_inst_set_flag_reg_nr(p->devinfo,
 683                                                          brw_last_inst,
 684                                                          $4.flag_reg_nr);
 685                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 686                                                             brw_last_inst,
 687                                                             $4.flag_subreg_nr);
 688                         }
 689                 }
 690
 691                 if ($7.file != BRW_IMMEDIATE_VALUE) {
 692                         brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
 693                                                   $7.vstride);
 694                 }
 695                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 696                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 697                 // TODO: set instruction group instead of qtr and nib ctrl
 698                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 699                                          $8.qtr_ctrl);
 700
 701                 if (p->devinfo->gen >= 7)
 702                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 703                                                  $8.nib_ctrl);
 704         }
 705         ;
 706
 707 unaryopcodes:
 708         BFREV
 709         | CBIT
 710         | DIM
 711         | F16TO32
 712         | F32TO16
 713         | FBH
 714         | FBL
 715         | FRC
 716         | LZD
 717         | MOV
 718         | NOT
 719         | RNDD
 720         | RNDE
 721         | RNDU
 722         | RNDZ
 723         ;
 724
 725 /* Binary instruction */
 726 binaryinstruction:
 727         predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
 728         {
 729                 i965_asm_set_dst_nr(p, &$6, $9);
 730                 brw_set_default_access_mode(p, $9.access_mode);
 731                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 732                 i965_asm_set_instruction_options(p, $9);
 733                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 734                                            $4.cond_modifier);
 735
 736                 if (p->devinfo->gen >= 7) {
 737                         brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
 738                                                  $4.flag_reg_nr);
 739                         brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
 740                                                     $4.flag_subreg_nr);
 741                 }
 742
 743                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 744                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 745                 // TODO: set instruction group instead of qtr and nib ctrl
 746                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 747                                          $9.qtr_ctrl);
 748
 749                 if (p->devinfo->gen >= 7)
 750                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 751                                                  $9.nib_ctrl);
 752
 753                 brw_pop_insn_state(p);
 754         }
 755         ;
 756
 757 binaryopcodes:
 758         ADDC
 759         | BFI1
 760         | DP2
 761         | DP3
 762         | DP4
 763         | DPH
 764         | LINE
 765         | MAC
 766         | MACH
 767         | MUL
 768         | PLN
 769         | ROL
 770         | ROR
 771         | SAD2
 772         | SADA2
 773         | SUBB
 774         ;
 775
 776 /* Binary acc instruction */
 777 binaryaccinstruction:
 778         predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
 779         {
 780                 i965_asm_set_dst_nr(p, &$6, $9);
 781                 brw_set_default_access_mode(p, $9.access_mode);
 782                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 783                 brw_pop_insn_state(p);
 784                 i965_asm_set_instruction_options(p, $9);
 785                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 786                                            $4.cond_modifier);
 787
 788                 if (p->devinfo->gen >= 7) {
 789                         if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
 790                                 brw_inst_set_flag_reg_nr(p->devinfo,
 791                                                          brw_last_inst,
 792                                                          $4.flag_reg_nr);
 793                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 794                                                             brw_last_inst,
 795                                                             $4.flag_subreg_nr);
 796                         }
 797                 }
 798
 799                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 800                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 801                 // TODO: set instruction group instead of qtr and nib ctrl
 802                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 803                                          $9.qtr_ctrl);
 804
 805                 if (p->devinfo->gen >= 7)
 806                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 807                                                  $9.nib_ctrl);
 808         }
 809         ;
 810
 811 binaryaccopcodes:
 812         ADD
 813         | AND
 814         | ASR
 815         | AVG
 816         | CMP
 817         | CMPN
 818         | OR
 819         | SEL
 820         | SHL
 821         | SHR
 822         | XOR
 823         ;
 824
 825 /* Math instruction */
 826 mathinstruction:
 827         predicate MATH saturate math_function execsize dst src srcimm instoptions
 828         {
 829                 brw_set_default_access_mode(p, $9.access_mode);
 830                 gen6_math(p, $6, $4, $7, $8);
 831                 i965_asm_set_instruction_options(p, $9);
 832                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 833                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 834                 // TODO: set instruction group instead
 835                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 836                                          $9.qtr_ctrl);
 837
 838                 if (p->devinfo->gen >= 7)
 839                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 840                                                  $9.nib_ctrl);
 841
 842                 brw_pop_insn_state(p);
 843         }
 844         ;
 845
 846 math_function:
 847         COS
 848         | EXP
 849         | FDIV
 850         | INV
 851         | INVM
 852         | INTDIV
 853         | INTDIVMOD
 854         | INTMOD
 855         | LOG
 856         | POW
 857         | RSQ
 858         | RSQRTM
 859         | SIN
 860         | SQRT
 861         | SINCOS
 862         ;
 863
 864 /* NOP instruction */
 865 nopinstruction:
 866         NOP
 867         {
 868                 brw_NOP(p);
 869         }
 870         ;
 871
 872 /* Ternary operand instruction */
 873 ternaryinstruction:
 874         predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
 875         {
 876                 brw_set_default_access_mode(p, $10.access_mode);
 877                 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
 878                 brw_pop_insn_state(p);
 879                 i965_asm_set_instruction_options(p, $10);
 880                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 881                                            $4.cond_modifier);
 882
 883                 if (p->devinfo->gen >= 7) {
 884                         brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
 885                                                  $4.flag_reg_nr);
 886                         brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
 887                                                     $4.flag_subreg_nr);
 888                 }
 889
 890                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 891                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 892                 // TODO: set instruction group instead of qtr and nib ctrl
 893                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 894                                          $10.qtr_ctrl);
 895
 896                 if (p->devinfo->gen >= 7)
 897                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 898                                                  $10.nib_ctrl);
 899         }
 900         ;
 901
 902 ternaryopcodes:
 903         CSEL
 904         | BFE
 905         | BFI2
 906         | LRP
 907         | MAD
 908         ;
 909
 910 /* Sync instruction */
 911 syncinstruction:
 912         WAIT execsize dst instoptions
 913         {
 914                 brw_next_insn(p, $1);
 915                 i965_asm_set_instruction_options(p, $4);
 916                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 917                 brw_set_default_access_mode(p, $4.access_mode);
 918                 struct brw_reg dest = $3;
 919                 dest.swizzle = brw_swizzle_for_mask(dest.writemask);
 920                 if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
 921                         error(&@1, "WAIT must use the notification register\n");
 922                 brw_set_dest(p, brw_last_inst, dest);
 923                 brw_set_src0(p, brw_last_inst, dest);
 924                 brw_set_src1(p, brw_last_inst, brw_null_reg());
 925                 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
 926         }
 927         ;
 928
 929 /* Send instruction */
 930 sendinstruction:
 931         predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
 932         {
 933                 i965_asm_set_instruction_options(p, $8);
 934                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 935                 brw_set_dest(p, brw_last_inst, $4);
 936                 brw_set_src0(p, brw_last_inst, $5);
 937                 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
 938                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 939                                             BRW_IMMEDIATE_VALUE,
 940                                             BRW_REGISTER_TYPE_UD);
 941                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
 942                 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
 943                 // TODO: set instruction group instead of qtr and nib ctrl
 944                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 945                                          $8.qtr_ctrl);
 946
 947                 if (p->devinfo->gen >= 7)
 948                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 949                                                  $8.nib_ctrl);
 950
 951                 brw_pop_insn_state(p);
 952         }
 953         | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
 954         {
 955                 i965_asm_set_instruction_options(p, $9);
 956                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 957                 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
 958                 brw_set_dest(p, brw_last_inst, $5);
 959                 brw_set_src0(p, brw_last_inst, $6);
 960                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 961                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 962                                             BRW_IMMEDIATE_VALUE,
 963                                             BRW_REGISTER_TYPE_UD);
 964                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 965                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 966                 // TODO: set instruction group instead of qtr and nib ctrl
 967                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 968                                          $9.qtr_ctrl);
 969
 970                 if (p->devinfo->gen >= 7)
 971                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 972                                                  $9.nib_ctrl);
 973
 974                 brw_pop_insn_state(p);
 975         }
 976         | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
 977         {
 978                 i965_asm_set_instruction_options(p, $9);
 979                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 980                 brw_set_dest(p, brw_last_inst, $4);
 981                 brw_set_src0(p, brw_last_inst, $5);
 982                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 983                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 984                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 985                 // TODO: set instruction group instead of qtr and nib ctrl
 986                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 987                                          $9.qtr_ctrl);
 988
 989                 if (p->devinfo->gen >= 7)
 990                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 991                                                  $9.nib_ctrl);
 992
 993                 brw_pop_insn_state(p);
 994         }
 995         | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
 996         {
 997                 brw_next_insn(p, $2);
 998                 i965_asm_set_instruction_options(p, $10);
 999                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1000                 brw_set_dest(p, brw_last_inst, $4);
1001                 brw_set_src0(p, brw_last_inst, $5);
1002                 brw_set_src1(p, brw_last_inst, $6);
1003
1004                 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
1005                         brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
1006                 } else {
1007                         brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1008                 }
1009
1010                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
1011                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1012                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1013                 // TODO: set instruction group instead of qtr and nib ctrl
1014                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1015                                          $10.qtr_ctrl);
1016
1017                 if (p->devinfo->gen >= 7)
1018                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1019                                                  $10.nib_ctrl);
1020
1021                 brw_pop_insn_state(p);
1022         }
1023         | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
1024         {
1025                 brw_next_insn(p, $2);
1026                 i965_asm_set_instruction_options(p, $10);
1027                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1028                 brw_set_dest(p, brw_last_inst, $4);
1029                 brw_set_src0(p, brw_last_inst, $5);
1030                 brw_set_src1(p, brw_last_inst, $6);
1031
1032                 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1033                 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1034
1035                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1036                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1037                 // TODO: set instruction group instead of qtr and nib ctrl
1038                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1039                                          $10.qtr_ctrl);
1040
1041                 if (p->devinfo->gen >= 7)
1042                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1043                                                  $10.nib_ctrl);
1044
1045                 brw_pop_insn_state(p);
1046         }
1047         ;
1048
1049 sendop:
1050         SEND
1051         | SENDC
1052         ;
1053
1054 sendopcode:
1055         sendop   { $$ = brw_next_insn(p, $1); }
1056         ;
1057
1058 sharedfunction:
1059         NULL_TOKEN              { $$ = BRW_SFID_NULL; }
1060         | MATH                  { $$ = BRW_SFID_MATH; }
1061         | GATEWAY               { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1062         | READ                  { $$ = BRW_SFID_DATAPORT_READ; }
1063         | WRITE                 { $$ = BRW_SFID_DATAPORT_WRITE; }
1064         | URB                   { $$ = BRW_SFID_URB; }
1065         | THREAD_SPAWNER        { $$ = BRW_SFID_THREAD_SPAWNER; }
1066         | VME                   { $$ = BRW_SFID_VME; }
1067         | RENDER                { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1068         | CONST                 { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1069         | DATA                  { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1070         | PIXEL_INTERP          { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1071         | DP_DATA_1             { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1072         | CRE                   { $$ = HSW_SFID_CRE; }
1073         | SAMPLER               { $$ = BRW_SFID_SAMPLER; }
1074         | DP_SAMPLER            { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1075         ;
1076
1077 exp2:
1078         LONG            { $$ = $1; }
1079         | MINUS LONG    { $$ = -$2; }
1080         ;
1081
1082 /* Jump instruction */
1083 jumpinstruction:
1084         predicate JMPI execsize relativelocation2 instoptions
1085         {
1086                 brw_next_insn(p, $2);
1087                 i965_asm_set_instruction_options(p, $5);
1088                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1089                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1090                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1091                 brw_set_src1(p, brw_last_inst, $4);
1092                 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1093                                           brw_inst_pred_control(p->devinfo,
1094                                                                 brw_last_inst));
1095                 brw_pop_insn_state(p);
1096         }
1097         ;
1098
1099 /* branch instruction */
1100 branchinstruction:
1101         predicate ENDIF execsize JUMP_LABEL instoptions
1102         {
1103                 add_label(p, $4, INSTR_LABEL_JIP);
1104
1105                 brw_next_insn(p, $2);
1106                 i965_asm_set_instruction_options(p, $5);
1107                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1108
1109                 if (p->devinfo->gen == 6) {
1110                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1111                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1112                                      BRW_REGISTER_TYPE_D));
1113                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1114                                      BRW_REGISTER_TYPE_D));
1115                 } else if (p->devinfo->gen == 7) {
1116                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1117                                      BRW_REGISTER_TYPE_D));
1118                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1119                                      BRW_REGISTER_TYPE_D));
1120                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1121                 } else {
1122                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1123                 }
1124
1125                 brw_pop_insn_state(p);
1126         }
1127         | predicate ENDIF execsize relativelocation instoptions
1128         {
1129                 brw_next_insn(p, $2);
1130                 i965_asm_set_instruction_options(p, $5);
1131                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1132
1133                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1134                                         BRW_REGISTER_TYPE_D));
1135                 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1136                                         BRW_REGISTER_TYPE_D));
1137                 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1138                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
1139
1140                 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1141                                                 BRW_THREAD_SWITCH);
1142
1143                 brw_pop_insn_state(p);
1144         }
1145         | ELSE execsize JUMP_LABEL jumplabel instoptions
1146         {
1147                 add_label(p, $3, INSTR_LABEL_JIP);
1148                 add_label(p, $4, INSTR_LABEL_UIP);
1149
1150                 brw_next_insn(p, $1);
1151                 i965_asm_set_instruction_options(p, $5);
1152                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1153
1154                 if (p->devinfo->gen == 6) {
1155                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1156                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1157                                      BRW_REGISTER_TYPE_D));
1158                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1159                                      BRW_REGISTER_TYPE_D));
1160                 } else if (p->devinfo->gen == 7) {
1161                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1162                                      BRW_REGISTER_TYPE_D));
1163                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1164                                      BRW_REGISTER_TYPE_D));
1165                         brw_set_src1(p, brw_last_inst, brw_imm_w(0));
1166                 } else {
1167                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1168                                      BRW_REGISTER_TYPE_D));
1169                         if (p->devinfo->gen < 12)
1170                                 brw_set_src0(p, brw_last_inst, brw_imm_d(0));
1171                 }
1172         }
1173         | ELSE execsize relativelocation rellocation instoptions
1174         {
1175                 brw_next_insn(p, $1);
1176                 i965_asm_set_instruction_options(p, $5);
1177                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1178
1179                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1180                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1181                 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1182                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $3);
1183                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
1184
1185                 if (!p->single_program_flow)
1186                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1187                                                     BRW_THREAD_SWITCH);
1188         }
1189         | predicate IF execsize JUMP_LABEL jumplabel instoptions
1190         {
1191                 add_label(p, $4, INSTR_LABEL_JIP);
1192                 add_label(p, $5, INSTR_LABEL_UIP);
1193
1194                 brw_next_insn(p, $2);
1195                 i965_asm_set_instruction_options(p, $6);
1196                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1197
1198                 if (p->devinfo->gen == 6) {
1199                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1200                         brw_set_src0(p, brw_last_inst,
1201                                      vec1(retype(brw_null_reg(),
1202                                      BRW_REGISTER_TYPE_D)));
1203                         brw_set_src1(p, brw_last_inst,
1204                                      vec1(retype(brw_null_reg(),
1205                                      BRW_REGISTER_TYPE_D)));
1206                 } else if (p->devinfo->gen == 7) {
1207                         brw_set_dest(p, brw_last_inst,
1208                                      vec1(retype(brw_null_reg(),
1209                                      BRW_REGISTER_TYPE_D)));
1210                         brw_set_src0(p, brw_last_inst,
1211                                      vec1(retype(brw_null_reg(),
1212                                      BRW_REGISTER_TYPE_D)));
1213                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1214                 } else {
1215                         brw_set_dest(p, brw_last_inst,
1216                                      vec1(retype(brw_null_reg(),
1217                                      BRW_REGISTER_TYPE_D)));
1218                         if (p->devinfo->gen < 12)
1219                                 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1220                 }
1221
1222                 brw_pop_insn_state(p);
1223         }
1224         | predicate IF execsize relativelocation rellocation instoptions
1225         {
1226                 brw_next_insn(p, $2);
1227                 i965_asm_set_instruction_options(p, $6);
1228                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1229
1230                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1231                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1232                 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1233                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1234                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
1235
1236                 if (!p->single_program_flow)
1237                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1238                                                     BRW_THREAD_SWITCH);
1239
1240                 brw_pop_insn_state(p);
1241         }
1242         | predicate IFF execsize JUMP_LABEL instoptions
1243         {
1244                 add_label(p, $4, INSTR_LABEL_JIP);
1245
1246                 brw_next_insn(p, $2);
1247                 i965_asm_set_instruction_options(p, $5);
1248                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1249
1250                 if (p->devinfo->gen == 6) {
1251                         brw_set_src0(p, brw_last_inst,
1252                                      vec1(retype(brw_null_reg(),
1253                                      BRW_REGISTER_TYPE_D)));
1254                         brw_set_src1(p, brw_last_inst,
1255                                      vec1(retype(brw_null_reg(),
1256                                      BRW_REGISTER_TYPE_D)));
1257                 } else if (p->devinfo->gen == 7) {
1258                         brw_set_dest(p, brw_last_inst,
1259                                      vec1(retype(brw_null_reg(),
1260                                      BRW_REGISTER_TYPE_D)));
1261                         brw_set_src0(p, brw_last_inst,
1262                                      vec1(retype(brw_null_reg(),
1263                                      BRW_REGISTER_TYPE_D)));
1264                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1265                 } else {
1266                         brw_set_dest(p, brw_last_inst,
1267                                      vec1(retype(brw_null_reg(),
1268                                      BRW_REGISTER_TYPE_D)));
1269                         if (p->devinfo->gen < 12)
1270                                 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1271                 }
1272
1273                 brw_pop_insn_state(p);
1274         }
1275         | predicate IFF execsize relativelocation instoptions
1276         {
1277                 brw_next_insn(p, $2);
1278                 i965_asm_set_instruction_options(p, $5);
1279                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1280
1281                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1282                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1283                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1284                 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1285
1286                 if (!p->single_program_flow)
1287                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1288                                                     BRW_THREAD_SWITCH);
1289
1290                 brw_pop_insn_state(p);
1291         }
1292         ;
1293
1294 /* break instruction */
1295 breakinstruction:
1296         predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
1297         {
1298                 add_label(p, $4, INSTR_LABEL_JIP);
1299                 add_label(p, $5, INSTR_LABEL_UIP);
1300
1301                 brw_next_insn(p, $2);
1302                 i965_asm_set_instruction_options(p, $6);
1303                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1304
1305                 if (p->devinfo->gen >= 8) {
1306                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1307                                      BRW_REGISTER_TYPE_D));
1308                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1309                 } else {
1310                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1311                                      BRW_REGISTER_TYPE_D));
1312                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1313                                      BRW_REGISTER_TYPE_D));
1314                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1315                 }
1316
1317                 brw_pop_insn_state(p);
1318         }
1319         | predicate BREAK execsize relativelocation relativelocation instoptions
1320         {
1321                 brw_next_insn(p, $2);
1322                 i965_asm_set_instruction_options(p, $6);
1323                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1324
1325                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1326                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1327                 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1328                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1329                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
1330
1331                 brw_pop_insn_state(p);
1332         }
1333         | predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
1334         {
1335                 add_label(p, $4, INSTR_LABEL_JIP);
1336                 add_label(p, $5, INSTR_LABEL_UIP);
1337
1338                 brw_next_insn(p, $2);
1339                 i965_asm_set_instruction_options(p, $6);
1340                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1341
1342                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1343                              BRW_REGISTER_TYPE_D));
1344
1345                 if (p->devinfo->gen >= 8) {
1346                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1347                 } else {
1348                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1349                                      BRW_REGISTER_TYPE_D));
1350                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1351                 }
1352
1353                 brw_pop_insn_state(p);
1354         }
1355         | predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
1356         {
1357                 add_label(p, $4, INSTR_LABEL_JIP);
1358                 add_label(p, $5, INSTR_LABEL_UIP);
1359
1360                 brw_next_insn(p, $2);
1361                 i965_asm_set_instruction_options(p, $6);
1362                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1363                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1364
1365                 if (p->devinfo->gen >= 8) {
1366                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1367                 } else {
1368                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1369                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1370                 }
1371
1372                 brw_pop_insn_state(p);
1373         }
1374         | predicate CONT execsize relativelocation relativelocation instoptions
1375         {
1376                 brw_next_insn(p, $2);
1377                 i965_asm_set_instruction_options(p, $6);
1378                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1379                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1380
1381                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1382                 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1383
1384                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1385                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
1386
1387                 brw_pop_insn_state(p);
1388         }
1389         ;
1390
1391 /* loop instruction */
1392 loopinstruction:
1393         predicate WHILE execsize JUMP_LABEL instoptions
1394         {
1395                 add_label(p, $4, INSTR_LABEL_JIP);
1396
1397                 brw_next_insn(p, $2);
1398                 i965_asm_set_instruction_options(p, $5);
1399                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1400
1401                 if (p->devinfo->gen >= 8) {
1402                         brw_set_dest(p, brw_last_inst,
1403                                                 retype(brw_null_reg(),
1404                                                 BRW_REGISTER_TYPE_D));
1405                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1406                 } else if (p->devinfo->gen == 7) {
1407                         brw_set_dest(p, brw_last_inst,
1408                                                 retype(brw_null_reg(),
1409                                                 BRW_REGISTER_TYPE_D));
1410                         brw_set_src0(p, brw_last_inst,
1411                                                 retype(brw_null_reg(),
1412                                                 BRW_REGISTER_TYPE_D));
1413                         brw_set_src1(p, brw_last_inst,
1414                                                 brw_imm_w(0x0));
1415                 } else {
1416                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1417                         brw_set_src0(p, brw_last_inst,
1418                                                 retype(brw_null_reg(),
1419                                                 BRW_REGISTER_TYPE_D));
1420                         brw_set_src1(p, brw_last_inst,
1421                                                 retype(brw_null_reg(),
1422                                                 BRW_REGISTER_TYPE_D));
1423                 }
1424
1425                 brw_pop_insn_state(p);
1426         }
1427         | predicate WHILE execsize relativelocation instoptions
1428         {
1429                 brw_next_insn(p, $2);
1430                 i965_asm_set_instruction_options(p, $5);
1431                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1432
1433                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1434                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1435                 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1436                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
1437                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, 0);
1438
1439                 brw_pop_insn_state(p);
1440         }
1441         | DO execsize instoptions
1442         {
1443                 brw_next_insn(p, $1);
1444                 if (p->devinfo->gen < 6) {
1445                         brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1446                         i965_asm_set_instruction_options(p, $3);
1447                         brw_set_dest(p, brw_last_inst, brw_null_reg());
1448                         brw_set_src0(p, brw_last_inst, brw_null_reg());
1449                         brw_set_src1(p, brw_last_inst, brw_null_reg());
1450
1451                         brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1452                 }
1453         }
1454         ;
1455
1456 /* Relative location */
1457 relativelocation2:
1458         immreg
1459         | reg32
1460         ;
1461
1462 simple_int:
1463         INTEGER                 { $$ = $1; }
1464         | MINUS INTEGER         { $$ = -$2; }
1465         | LONG                  { $$ = $1; }
1466         | MINUS LONG            { $$ = -$2; }
1467         ;
1468
1469 rellocation:
1470         relativelocation
1471         | %empty { $$ = 0; }
1472         ;
1473
1474 relativelocation:
1475         simple_int
1476         {
1477                 $$ = $1;
1478         }
1479         ;
1480
1481 jumplabel:
1482         JUMP_LABEL      { $$ = $1; }
1483         | %empty        { $$ = NULL; }
1484         ;
1485
1486 jumplabeltarget:
1487         JUMP_LABEL_TARGET
1488         {
1489                 struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
1490
1491                 label->name = ralloc_strdup(p->mem_ctx, $1);
1492                 label->offset = p->next_insn_offset;
1493
1494                 list_addtail(&label->link, &target_labels);
1495         }
1496         ;
1497
1498 /* Destination register */
1499 dst:
1500         dstoperand
1501         | dstoperandex
1502         ;
1503
1504 dstoperand:
1505         dstreg dstregion writemask reg_type
1506         {
1507                 $$ = $1;
1508                 $$.vstride = BRW_VERTICAL_STRIDE_1;
1509                 $$.width = BRW_WIDTH_1;
1510                 $$.hstride = $2;
1511                 $$.type = $4;
1512                 $$.writemask = $3;
1513                 $$.swizzle = BRW_SWIZZLE_NOOP;
1514                 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1515         }
1516         ;
1517
1518 dstoperandex:
1519         dstoperandex_typed dstregion writemask reg_type
1520         {
1521                 $$ = $1;
1522                 $$.hstride = $2;
1523                 $$.type = $4;
1524                 $$.writemask = $3;
1525                 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1526         }
1527         /* BSpec says "When the conditional modifier is present, updates
1528          * to the selected flag register also occur. In this case, the
1529          * register region fields of the ‘null’ operand are valid."
1530          */
1531         | nullreg dstregion writemask reg_type
1532         {
1533                 $$ = $1;
1534                 $$.vstride = BRW_VERTICAL_STRIDE_1;
1535                 $$.width = BRW_WIDTH_1;
1536                 $$.hstride = $2;
1537                 $$.writemask = $3;
1538                 $$.type = $4;
1539         }
1540         | threadcontrolreg
1541         {
1542                 $$ = $1;
1543                 $$.hstride = 1;
1544                 $$.type = BRW_REGISTER_TYPE_UW;
1545         }
1546         ;
1547
1548 dstoperandex_typed:
1549         accreg
1550         | addrreg
1551         | channelenablereg
1552         | controlreg
1553         | flagreg
1554         | ipreg
1555         | maskreg
1556         | notifyreg
1557         | performancereg
1558         | statereg
1559         ;
1560
1561 dstreg:
1562         directgenreg
1563         {
1564                 $$ = $1;
1565                 $$.address_mode = BRW_ADDRESS_DIRECT;
1566         }
1567         | indirectgenreg
1568         {
1569                 $$ = $1;
1570                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1571         }
1572         | directmsgreg
1573         {
1574                 $$ = $1;
1575                 $$.address_mode = BRW_ADDRESS_DIRECT;
1576         }
1577         | indirectmsgreg
1578         {
1579                 $$ = $1;
1580                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1581         }
1582         ;
1583
1584 /* Source register */
1585 srcaccimm:
1586         srcacc
1587         | immreg
1588         ;
1589
1590 immreg:
1591         immval imm_type
1592         {
1593                 switch ($2) {
1594                 case BRW_REGISTER_TYPE_UD:
1595                         $$ = brw_imm_ud($1);
1596                         break;
1597                 case BRW_REGISTER_TYPE_D:
1598                         $$ = brw_imm_d($1);
1599                         break;
1600                 case BRW_REGISTER_TYPE_UW:
1601                         $$ = brw_imm_uw($1 | ($1 << 16));
1602                         break;
1603                 case BRW_REGISTER_TYPE_W:
1604                         $$ = brw_imm_w($1);
1605                         break;
1606                 case BRW_REGISTER_TYPE_F:
1607                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1608                         /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1609                         $$.u64 = $1;
1610                         break;
1611                 case BRW_REGISTER_TYPE_V:
1612                         $$ = brw_imm_v($1);
1613                         break;
1614                 case BRW_REGISTER_TYPE_UV:
1615                         $$ = brw_imm_uv($1);
1616                         break;
1617                 case BRW_REGISTER_TYPE_VF:
1618                         $$ = brw_imm_vf($1);
1619                         break;
1620                 case BRW_REGISTER_TYPE_Q:
1621                         $$ = brw_imm_q($1);
1622                         break;
1623                 case BRW_REGISTER_TYPE_UQ:
1624                         $$ = brw_imm_uq($1);
1625                         break;
1626                 case BRW_REGISTER_TYPE_DF:
1627                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1628                         $$.d64 = $1;
1629                         break;
1630                 default:
1631                         error(&@2, "Unknown immediate type %s\n",
1632                               brw_reg_type_to_letters($2));
1633                 }
1634         }
1635         ;
1636
1637 reg32:
1638         directgenreg region reg_type
1639         {
1640                 $$ = set_direct_src_operand(&$1, $3);
1641                 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1642         }
1643         ;
1644
1645 payload:
1646         directsrcoperand
1647         ;
1648
1649 src:
1650         directsrcoperand
1651         | indirectsrcoperand
1652         ;
1653
1654 srcacc:
1655         directsrcaccoperand
1656         | indirectsrcoperand
1657         ;
1658
1659 srcimm:
1660         directsrcoperand
1661         | indirectsrcoperand
1662         | immreg
1663         ;
1664
1665 directsrcaccoperand:
1666         directsrcoperand
1667         | accreg region reg_type
1668         {
1669                 $$ = set_direct_src_operand(&$1, $3);
1670                 $$.vstride = $2.vstride;
1671                 $$.width = $2.width;
1672                 $$.hstride = $2.hstride;
1673         }
1674         ;
1675
1676 srcarcoperandex:
1677         srcarcoperandex_typed region reg_type
1678         {
1679                 $$ = brw_reg($1.file,
1680                              $1.nr,
1681                              $1.subnr,
1682                              0,
1683                              0,
1684                              $3,
1685                              $2.vstride,
1686                              $2.width,
1687                              $2.hstride,
1688                              BRW_SWIZZLE_NOOP,
1689                              WRITEMASK_XYZW);
1690         }
1691         | nullreg region reg_type
1692         {
1693                 $$ = set_direct_src_operand(&$1, $3);
1694                 $$.vstride = $2.vstride;
1695                 $$.width = $2.width;
1696                 $$.hstride = $2.hstride;
1697         }
1698         | threadcontrolreg
1699         {
1700                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1701         }
1702         ;
1703
1704 srcarcoperandex_typed:
1705         channelenablereg
1706         | controlreg
1707         | flagreg
1708         | ipreg
1709         | maskreg
1710         | statereg
1711         ;
1712
1713 indirectsrcoperand:
1714         negate abs indirectgenreg indirectregion swizzle reg_type
1715         {
1716                 $$ = brw_reg($3.file,
1717                              0,
1718                              $3.subnr,
1719                              $1,  // negate
1720                              $2,  // abs
1721                              $6,
1722                              $4.vstride,
1723                              $4.width,
1724                              $4.hstride,
1725                              $5,
1726                              WRITEMASK_X);
1727
1728                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1729                 // brw_reg set indirect_offset to 0 so set it to valid value
1730                 $$.indirect_offset = $3.indirect_offset;
1731         }
1732         ;
1733
1734 directgenreg_list:
1735         directgenreg
1736         | directmsgreg
1737         | notifyreg
1738         | addrreg
1739         | performancereg
1740         ;
1741
1742 directsrcoperand:
1743         negate abs directgenreg_list region swizzle reg_type
1744         {
1745                 $$ = brw_reg($3.file,
1746                              $3.nr,
1747                              $3.subnr,
1748                              $1,
1749                              $2,
1750                              $6,
1751                              $4.vstride,
1752                              $4.width,
1753                              $4.hstride,
1754                              $5,
1755                              WRITEMASK_X);
1756         }
1757         | srcarcoperandex
1758         ;
1759
1760 /* Address register */
1761 addrparam:
1762         addrreg exp
1763         {
1764                 memset(&$$, '\0', sizeof($$));
1765                 $$.subnr = $1.subnr;
1766                 $$.indirect_offset = $2;
1767         }
1768         | addrreg
1769         ;
1770
1771 /* Register files and register numbers */
1772 exp:
1773         INTEGER         { $$ = $1; }
1774         | LONG          { $$ = $1; }
1775         ;
1776
1777 subregnum:
1778         DOT exp                         { $$ = $2; }
1779         | %empty %prec SUBREGNUM        { $$ = 0; }
1780         ;
1781
1782 directgenreg:
1783         GENREG subregnum
1784         {
1785                 memset(&$$, '\0', sizeof($$));
1786                 $$.file = BRW_GENERAL_REGISTER_FILE;
1787                 $$.nr = $1;
1788                 $$.subnr = $2;
1789         }
1790         ;
1791
1792 indirectgenreg:
1793         GENREGFILE LSQUARE addrparam RSQUARE
1794         {
1795                 memset(&$$, '\0', sizeof($$));
1796                 $$.file = BRW_GENERAL_REGISTER_FILE;
1797                 $$.subnr = $3.subnr;
1798                 $$.indirect_offset = $3.indirect_offset;
1799         }
1800         ;
1801
1802 directmsgreg:
1803         MSGREG subregnum
1804         {
1805                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1806                 $$.nr = $1;
1807                 $$.subnr = $2;
1808         }
1809         ;
1810
1811 indirectmsgreg:
1812         MSGREGFILE LSQUARE addrparam RSQUARE
1813         {
1814                 memset(&$$, '\0', sizeof($$));
1815                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1816                 $$.subnr = $3.subnr;
1817                 $$.indirect_offset = $3.indirect_offset;
1818         }
1819         ;
1820
1821 addrreg:
1822         ADDRREG subregnum
1823         {
1824                 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1825
1826                 if ($2 > subnr)
1827                         error(&@2, "Address sub register number %d"
1828                                    "out of range\n", $2);
1829
1830                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1831                 $$.nr = BRW_ARF_ADDRESS;
1832                 $$.subnr = $2;
1833         }
1834         ;
1835
1836 accreg:
1837         ACCREG subregnum
1838         {
1839                 int nr_reg;
1840                 if (p->devinfo->gen < 8)
1841                         nr_reg = 2;
1842                 else
1843                         nr_reg = 10;
1844
1845                 if ($1 > nr_reg)
1846                         error(&@1, "Accumulator register number %d"
1847                                    " out of range\n", $1);
1848
1849                 memset(&$$, '\0', sizeof($$));
1850                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1851                 $$.nr = BRW_ARF_ACCUMULATOR;
1852                 $$.subnr = $2;
1853         }
1854         ;
1855
1856 flagreg:
1857         FLAGREG subregnum
1858         {
1859                 // SNB = 1 flag reg and IVB+ = 2 flag reg
1860                 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1861                 int subnr = nr_reg;
1862
1863                 if ($1 > nr_reg)
1864                         error(&@1, "Flag register number %d"
1865                                    " out of range \n", $1);
1866                 if ($2 > subnr)
1867                         error(&@2, "Flag subregister number %d"
1868                                    " out of range\n", $2);
1869
1870                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1871                 $$.nr = BRW_ARF_FLAG | $1;
1872                 $$.subnr = $2;
1873         }
1874         ;
1875
1876 maskreg:
1877         MASKREG subregnum
1878         {
1879                 if ($1 > 0)
1880                         error(&@1, "Mask register number %d"
1881                                    " out of range\n", $1);
1882
1883                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1884                 $$.nr = BRW_ARF_MASK;
1885                 $$.subnr = $2;
1886         }
1887         ;
1888
1889 notifyreg:
1890         NOTIFYREG subregnum
1891         {
1892                 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1893                 if ($2 > subnr)
1894                         error(&@2, "Notification sub register number %d"
1895                                    " out of range\n", $2);
1896
1897                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1898                 $$.nr = BRW_ARF_NOTIFICATION_COUNT;
1899                 $$.subnr = $2;
1900         }
1901         ;
1902
1903 statereg:
1904         STATEREG subregnum
1905         {
1906                 if ($1 > 2)
1907                         error(&@1, "State register number %d"
1908                                    " out of range\n", $1);
1909
1910                 if ($2 > 4)
1911                         error(&@2, "State sub register number %d"
1912                                    " out of range\n", $2);
1913
1914                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1915                 $$.nr = BRW_ARF_STATE;
1916                 $$.subnr = $2;
1917         }
1918         ;
1919
1920 controlreg:
1921         CONTROLREG subregnum
1922         {
1923                 if ($2 > 3)
1924                         error(&@2, "control sub register number %d"
1925                                    " out of range\n", $2);
1926
1927                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1928                 $$.nr = BRW_ARF_CONTROL;
1929                 $$.subnr = $2;
1930         }
1931         ;
1932
1933 ipreg:
1934         IPREG           { $$ = brw_ip_reg(); }
1935         ;
1936
1937 nullreg:
1938         NULL_TOKEN      { $$ = brw_null_reg(); }
1939         ;
1940
1941 threadcontrolreg:
1942         THREADREG subregnum
1943         {
1944                 if ($2 > 7)
1945                         error(&@2, "Thread control sub register number %d"
1946                                    " out of range\n", $2);
1947
1948                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1949                 $$.nr = BRW_ARF_TDR;
1950                 $$.subnr = $2;
1951         }
1952         ;
1953
1954 performancereg:
1955         PERFORMANCEREG subregnum
1956         {
1957                 int subnr;
1958                 if (p->devinfo->gen >= 10)
1959                         subnr = 5;
1960                 else if (p->devinfo->gen <= 8)
1961                         subnr = 3;
1962                 else
1963                         subnr = 4;
1964
1965                 if ($2 > subnr)
1966                         error(&@2, "Performance sub register number %d"
1967                                    " out of range\n", $2);
1968
1969                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1970                 $$.nr = BRW_ARF_TIMESTAMP;
1971                 $$.subnr = $2;
1972         }
1973         ;
1974
1975 channelenablereg:
1976         CHANNELENABLEREG subregnum
1977         {
1978                 if ($1 > 0)
1979                         error(&@1, "Channel enable register number %d"
1980                                    " out of range\n", $1);
1981
1982                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1983                 $$.nr = BRW_ARF_MASK;
1984                 $$.subnr = $2;
1985         }
1986         ;
1987
1988 /* Immediate values */
1989 immval:
1990         exp2
1991         {
1992                 $$ = $1;
1993         }
1994         | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1995         {
1996                 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1997         }
1998         ;
1999
2000 /* Regions */
2001 dstregion:
2002         %empty
2003         {
2004                 $$ = BRW_HORIZONTAL_STRIDE_1;
2005         }
2006         | LANGLE exp RANGLE
2007         {
2008                 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
2009                         error(&@2, "Invalid Horizontal stride %d\n", $2);
2010
2011                 $$ = ffs($2);
2012         }
2013         ;
2014
2015 indirectregion:
2016         region
2017         | region_wh
2018         ;
2019
2020 region:
2021         %empty
2022         {
2023                 $$ = stride($$, 0, 1, 0);
2024         }
2025         | LANGLE exp RANGLE
2026         {
2027                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2028                         error(&@2, "Invalid VertStride %d\n", $2);
2029
2030                 $$ = stride($$, $2, 1, 0);
2031         }
2032         | LANGLE exp COMMA exp COMMA exp RANGLE
2033         {
2034
2035                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2036                         error(&@2, "Invalid VertStride %d\n", $2);
2037
2038                 if ($4 > 16 || !isPowerofTwo($4))
2039                         error(&@4, "Invalid width %d\n", $4);
2040
2041                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2042                         error(&@6, "Invalid Horizontal stride in"
2043                                    "  region_wh %d\n", $6);
2044
2045                 $$ = stride($$, $2, $4, $6);
2046         }
2047         | LANGLE exp SEMICOLON exp COMMA exp RANGLE
2048         {
2049                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
2050                         error(&@2, "Invalid VertStride %d\n", $2);
2051
2052                 if ($4 > 16 || !isPowerofTwo($4))
2053                         error(&@4, "Invalid width %d\n", $4);
2054
2055                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2056                         error(&@6, "Invalid Horizontal stride in"
2057                                    " region_wh %d\n", $6);
2058
2059                 $$ = stride($$, $2, $4, $6);
2060         }
2061         | LANGLE VxH COMMA exp COMMA exp RANGLE
2062         {
2063                 if ($4 > 16 || !isPowerofTwo($4))
2064                         error(&@4, "Invalid width %d\n", $4);
2065
2066                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2067                         error(&@6, "Invalid Horizontal stride in"
2068                                    " region_wh %d\n", $6);
2069
2070                 $$ = brw_VxH_indirect(0, 0);
2071         }
2072         ;
2073
2074 region_wh:
2075         LANGLE exp COMMA exp RANGLE
2076         {
2077                 if ($2 > 16 || !isPowerofTwo($2))
2078                         error(&@2, "Invalid width %d\n", $2);
2079
2080                 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2081                         error(&@4, "Invalid Horizontal stride in"
2082                                    " region_wh %d\n", $4);
2083
2084                 $$ = stride($$, 0, $2, $4);
2085                 $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
2086         }
2087         ;
2088
2089 reg_type:
2090           TYPE_F        { $$ = BRW_REGISTER_TYPE_F;  }
2091         | TYPE_UD       { $$ = BRW_REGISTER_TYPE_UD; }
2092         | TYPE_D        { $$ = BRW_REGISTER_TYPE_D;  }
2093         | TYPE_UW       { $$ = BRW_REGISTER_TYPE_UW; }
2094         | TYPE_W        { $$ = BRW_REGISTER_TYPE_W;  }
2095         | TYPE_UB       { $$ = BRW_REGISTER_TYPE_UB; }
2096         | TYPE_B        { $$ = BRW_REGISTER_TYPE_B;  }
2097         | TYPE_DF       { $$ = BRW_REGISTER_TYPE_DF; }
2098         | TYPE_UQ       { $$ = BRW_REGISTER_TYPE_UQ; }
2099         | TYPE_Q        { $$ = BRW_REGISTER_TYPE_Q;  }
2100         | TYPE_HF       { $$ = BRW_REGISTER_TYPE_HF; }
2101         | TYPE_NF       { $$ = BRW_REGISTER_TYPE_NF; }
2102         ;
2103
2104 imm_type:
2105         reg_type        { $$ = $1; }
2106         | TYPE_V        { $$ = BRW_REGISTER_TYPE_V;  }
2107         | TYPE_VF       { $$ = BRW_REGISTER_TYPE_VF; }
2108         | TYPE_UV       { $$ = BRW_REGISTER_TYPE_UV; }
2109         ;
2110
2111 writemask:
2112         %empty
2113         {
2114                 $$ = WRITEMASK_XYZW;
2115         }
2116         | DOT writemask_x writemask_y writemask_z writemask_w
2117         {
2118                 $$ = $2 | $3 | $4 | $5;
2119         }
2120         ;
2121
2122 writemask_x:
2123         %empty  { $$ = 0; }
2124         | X     { $$ = 1 << BRW_CHANNEL_X; }
2125         ;
2126
2127 writemask_y:
2128         %empty  { $$ = 0; }
2129         | Y     { $$ = 1 << BRW_CHANNEL_Y; }
2130         ;
2131
2132 writemask_z:
2133         %empty  { $$ = 0; }
2134         | Z     { $$ = 1 << BRW_CHANNEL_Z; }
2135         ;
2136
2137 writemask_w:
2138         %empty  { $$ = 0; }
2139         | W     { $$ = 1 << BRW_CHANNEL_W; }
2140         ;
2141
2142 swizzle:
2143         %empty
2144         {
2145                 $$ = BRW_SWIZZLE_NOOP;
2146         }
2147         | DOT chansel
2148         {
2149                 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
2150         }
2151         | DOT chansel chansel chansel chansel
2152         {
2153                 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
2154         }
2155         ;
2156
2157 chansel:
2158         X
2159         | Y
2160         | Z
2161         | W
2162         ;
2163
2164 /* Instruction prediction and modifiers */
2165 predicate:
2166         %empty
2167         {
2168                 brw_push_insn_state(p);
2169                 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2170                 brw_set_default_flag_reg(p, 0, 0);
2171                 brw_set_default_predicate_inverse(p, false);
2172         }
2173         | LPAREN predstate flagreg predctrl RPAREN
2174         {
2175                 brw_push_insn_state(p);
2176                 brw_set_default_predicate_inverse(p, $2);
2177                 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2178                 brw_set_default_predicate_control(p, $4);
2179         }
2180         ;
2181
2182 predstate:
2183         %empty          { $$ = 0; }
2184         | PLUS          { $$ = 0; }
2185         | MINUS         { $$ = 1; }
2186         ;
2187
2188 predctrl:
2189         %empty          { $$ = BRW_PREDICATE_NORMAL; }
2190         | DOT X         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2191         | DOT Y         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2192         | DOT Z         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2193         | DOT W         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2194         | ANYV
2195         | ALLV
2196         | ANY2H
2197         | ALL2H
2198         | ANY4H
2199         | ALL4H
2200         | ANY8H
2201         | ALL8H
2202         | ANY16H
2203         | ALL16H
2204         | ANY32H
2205         | ALL32H
2206         ;
2207
2208 /* Source Modification */
2209 negate:
2210         %empty          { $$ = 0; }
2211         | MINUS         { $$ = 1; }
2212         ;
2213
2214 abs:
2215         %empty  { $$ = 0; }
2216         | ABS   { $$ = 1; }
2217         ;
2218
2219 /* Flag (Conditional) Modifier */
2220 cond_mod:
2221         condModifiers
2222         {
2223                 $$.cond_modifier = $1;
2224                 $$.flag_reg_nr = 0;
2225                 $$.flag_subreg_nr = 0;
2226         }
2227         | condModifiers DOT flagreg
2228         {
2229                 $$.cond_modifier = $1;
2230                 $$.flag_reg_nr = $3.nr;
2231                 $$.flag_subreg_nr = $3.subnr;
2232         }
2233         ;
2234
2235 condModifiers:
2236         %empty  { $$ = BRW_CONDITIONAL_NONE; }
2237         | ZERO
2238         | EQUAL
2239         | NOT_ZERO
2240         | NOT_EQUAL
2241         | GREATER
2242         | GREATER_EQUAL
2243         | LESS
2244         | LESS_EQUAL
2245         | OVERFLOW
2246         | ROUND_INCREMENT
2247         | UNORDERED
2248         ;
2249
2250 saturate:
2251         %empty          { $$ = BRW_INSTRUCTION_NORMAL; }
2252         | SATURATE      { $$ = BRW_INSTRUCTION_SATURATE; }
2253         ;
2254
2255 /* Execution size */
2256 execsize:
2257         %empty %prec EMPTYEXECSIZE
2258         {
2259                 $$ = 0;
2260         }
2261         | LPAREN exp2 RPAREN
2262         {
2263                 if ($2 > 32 || !isPowerofTwo($2))
2264                         error(&@2, "Invalid execution size %d\n", $2);
2265
2266                 $$ = cvt($2) - 1;
2267         }
2268         ;
2269
2270 /* Instruction options */
2271 instoptions:
2272         %empty
2273         {
2274                 memset(&$$, 0, sizeof($$));
2275         }
2276         | LCURLY instoption_list RCURLY
2277         {
2278                 memset(&$$, 0, sizeof($$));
2279                 $$ = $2;
2280         }
2281         ;
2282
2283 instoption_list:
2284         instoption_list COMMA instoption
2285         {
2286                 memset(&$$, 0, sizeof($$));
2287                 $$ = $1;
2288                 add_instruction_option(&$$, $3);
2289         }
2290         | instoption_list instoption
2291         {
2292                 memset(&$$, 0, sizeof($$));
2293                 $$ = $1;
2294                 add_instruction_option(&$$, $2);
2295         }
2296         | %empty
2297         {
2298                 memset(&$$, 0, sizeof($$));
2299         }
2300         ;
2301
2302 instoption:
2303         ALIGN1          { $$ = ALIGN1;}
2304         | ALIGN16       { $$ = ALIGN16; }
2305         | ACCWREN       { $$ = ACCWREN; }
2306         | SECHALF       { $$ = SECHALF; }
2307         | COMPR         { $$ = COMPR; }
2308         | COMPR4        { $$ = COMPR4; }
2309         | BREAKPOINT    { $$ = BREAKPOINT; }
2310         | NODDCLR       { $$ = NODDCLR; }
2311         | NODDCHK       { $$ = NODDCHK; }
2312         | MASK_DISABLE  { $$ = MASK_DISABLE; }
2313         | EOT           { $$ = EOT; }
2314         | SWITCH        { $$ = SWITCH; }
2315         | ATOMIC        { $$ = ATOMIC; }
2316         | CMPTCTRL      { $$ = CMPTCTRL; }
2317         | WECTRL        { $$ = WECTRL; }
2318         | QTR_2Q        { $$ = QTR_2Q; }
2319         | QTR_3Q        { $$ = QTR_3Q; }
2320         | QTR_4Q        { $$ = QTR_4Q; }
2321         | QTR_2H        { $$ = QTR_2H; }
2322         | QTR_2N        { $$ = QTR_2N; }
2323         | QTR_3N        { $$ = QTR_3N; }
2324         | QTR_4N        { $$ = QTR_4N; }
2325         | QTR_5N        { $$ = QTR_5N; }
2326         | QTR_6N        { $$ = QTR_6N; }
2327         | QTR_7N        { $$ = QTR_7N; }
2328         | QTR_8N        { $$ = QTR_8N; }
2329         ;
2330
2331 %%
2332
2333 extern int yylineno;
2334
2335 void
2336 yyerror(char *msg)
2337 {
2338         fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2339                 input_filename, yylineno, msg, lex_text());
2340         ++errors;
2341 }