src/intel/tools/i965_gram.y

   1 %{
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <strings.h>
  29 #include "i965_asm.h"
  30
  31 #define YYLTYPE YYLTYPE
  32 typedef struct YYLTYPE
  33 {
  34         int first_line;
  35         int first_column;
  36         int last_line;
  37         int last_column;
  38 } YYLTYPE;
  39
  40 enum message_level {
  41         WARN,
  42         ERROR,
  43 };
  44
  45 int yydebug = 1;
  46
  47 static void
  48 message(enum message_level level, YYLTYPE *location,
  49         const char *fmt, ...)
  50 {
  51         static const char *level_str[] = { "warning", "error" };
  52         va_list args;
  53
  54         if (location)
  55                 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
  56                         location->first_line,
  57                         location->first_column, level_str[level]);
  58         else
  59                 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
  60
  61         va_start(args, fmt);
  62         vfprintf(stderr, fmt, args);
  63         va_end(args);
  64 }
  65
  66 #define warn(flag, l, fmt, ...)                                  \
  67         do {                                                     \
  68                 if (warning_flags & WARN_ ## flag)               \
  69                         message(WARN, l, fmt, ## __VA_ARGS__);   \
  70         } while (0)
  71
  72 #define error(l, fmt, ...)                                       \
  73         do {                                                     \
  74                 message(ERROR, l, fmt, ## __VA_ARGS__);          \
  75         } while (0)
  76
  77 static bool
  78 isPowerofTwo(unsigned int x)
  79 {
  80         return x && (!(x & (x - 1)));
  81 }
  82
  83 static struct brw_reg
  84 set_direct_src_operand(struct brw_reg *reg, int type)
  85 {
  86         return brw_reg(reg->file,
  87                        reg->nr,
  88                        reg->subnr,
  89                        0,               // negate
  90                        0,               // abs
  91                        type,
  92                        0,               // vstride
  93                        0,               // width
  94                        0,               // hstride
  95                        BRW_SWIZZLE_NOOP,
  96                        WRITEMASK_XYZW);
  97 }
  98
  99 static void
 100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
 101                            struct brw_reg dest, struct brw_reg src0)
 102 {
 103         switch (opcode) {
 104         case BRW_OPCODE_BFREV:
 105                 brw_BFREV(p, dest, src0);
 106                 break;
 107         case BRW_OPCODE_CBIT:
 108                 brw_CBIT(p, dest, src0);
 109                 break;
 110         case BRW_OPCODE_F32TO16:
 111                 brw_F32TO16(p, dest, src0);
 112                 break;
 113         case BRW_OPCODE_F16TO32:
 114                 brw_F16TO32(p, dest, src0);
 115                 break;
 116         case BRW_OPCODE_MOV:
 117                 brw_MOV(p, dest, src0);
 118                 break;
 119         case BRW_OPCODE_FBL:
 120                 brw_FBL(p, dest, src0);
 121                 break;
 122         case BRW_OPCODE_FRC:
 123                 brw_FRC(p, dest, src0);
 124                 break;
 125         case BRW_OPCODE_FBH:
 126                 brw_FBH(p, dest, src0);
 127                 break;
 128         case BRW_OPCODE_NOT:
 129                 brw_NOT(p, dest, src0);
 130                 break;
 131         case BRW_OPCODE_RNDE:
 132                 brw_RNDE(p, dest, src0);
 133                 break;
 134         case BRW_OPCODE_RNDZ:
 135                 brw_RNDZ(p, dest, src0);
 136                 break;
 137         case BRW_OPCODE_RNDD:
 138                 brw_RNDD(p, dest, src0);
 139                 break;
 140         case BRW_OPCODE_LZD:
 141                 brw_LZD(p, dest, src0);
 142                 break;
 143         case BRW_OPCODE_DIM:
 144                 brw_DIM(p, dest, src0);
 145                 break;
 146         case BRW_OPCODE_RNDU:
 147                 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
 148                 break;
 149         default:
 150                 fprintf(stderr, "Unsupported unary opcode\n");
 151         }
 152 }
 153
 154 static void
 155 i965_asm_binary_instruction(int opcode,
 156                             struct brw_codegen *p,
 157                             struct brw_reg dest,
 158                             struct brw_reg src0,
 159                             struct brw_reg src1)
 160 {
 161         switch (opcode) {
 162         case BRW_OPCODE_ADDC:
 163                 brw_ADDC(p, dest, src0, src1);
 164                 break;
 165         case BRW_OPCODE_BFI1:
 166                 brw_BFI1(p, dest, src0, src1);
 167                 break;
 168         case BRW_OPCODE_DP2:
 169                 brw_DP2(p, dest, src0, src1);
 170                 break;
 171         case BRW_OPCODE_DP3:
 172                 brw_DP3(p, dest, src0, src1);
 173                 break;
 174         case BRW_OPCODE_DP4:
 175                 brw_DP4(p, dest, src0, src1);
 176                 break;
 177         case BRW_OPCODE_DPH:
 178                 brw_DPH(p, dest, src0, src1);
 179                 break;
 180         case BRW_OPCODE_LINE:
 181                 brw_LINE(p, dest, src0, src1);
 182                 break;
 183         case BRW_OPCODE_MAC:
 184                 brw_MAC(p, dest, src0, src1);
 185                 break;
 186         case BRW_OPCODE_MACH:
 187                 brw_MACH(p, dest, src0, src1);
 188                 break;
 189         case BRW_OPCODE_PLN:
 190                 brw_PLN(p, dest, src0, src1);
 191                 break;
 192         case BRW_OPCODE_ROL:
 193                 brw_ROL(p, dest, src0, src1);
 194                 break;
 195         case BRW_OPCODE_ROR:
 196                 brw_ROR(p, dest, src0, src1);
 197                 break;
 198         case BRW_OPCODE_SAD2:
 199                 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
 200                 break;
 201         case BRW_OPCODE_SADA2:
 202                 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
 203                 break;
 204         case BRW_OPCODE_SUBB:
 205                 brw_SUBB(p, dest, src0, src1);
 206                 break;
 207         case BRW_OPCODE_ADD:
 208                 brw_ADD(p, dest, src0, src1);
 209                 break;
 210         case BRW_OPCODE_CMP:
 211                 /* Third parameter is conditional modifier
 212                  * which gets updated later
 213                  */
 214                 brw_CMP(p, dest, 0, src0, src1);
 215                 break;
 216         case BRW_OPCODE_AND:
 217                 brw_AND(p, dest, src0, src1);
 218                 break;
 219         case BRW_OPCODE_ASR:
 220                 brw_ASR(p, dest, src0, src1);
 221                 break;
 222         case BRW_OPCODE_AVG:
 223                 brw_AVG(p, dest, src0, src1);
 224                 break;
 225         case BRW_OPCODE_OR:
 226                 brw_OR(p, dest, src0, src1);
 227                 break;
 228         case BRW_OPCODE_SEL:
 229                 brw_SEL(p, dest, src0, src1);
 230                 break;
 231         case BRW_OPCODE_SHL:
 232                 brw_SHL(p, dest, src0, src1);
 233                 break;
 234         case BRW_OPCODE_SHR:
 235                 brw_SHR(p, dest, src0, src1);
 236                 break;
 237         case BRW_OPCODE_XOR:
 238                 brw_XOR(p, dest, src0, src1);
 239                 break;
 240         case BRW_OPCODE_MUL:
 241                 brw_MUL(p, dest, src0, src1);
 242                 break;
 243         default:
 244                 fprintf(stderr, "Unsupported binary opcode\n");
 245         }
 246 }
 247
 248 static void
 249 i965_asm_ternary_instruction(int opcode,
 250                              struct brw_codegen *p,
 251                              struct brw_reg dest,
 252                              struct brw_reg src0,
 253                              struct brw_reg src1,
 254                              struct brw_reg src2)
 255 {
 256         switch (opcode) {
 257         case BRW_OPCODE_MAD:
 258                 brw_MAD(p, dest, src0, src1, src2);
 259                 break;
 260         case BRW_OPCODE_CSEL:
 261                 brw_CSEL(p, dest, src0, src1, src2);
 262                 break;
 263         case BRW_OPCODE_LRP:
 264                 brw_LRP(p, dest, src0, src1, src2);
 265                 break;
 266         case BRW_OPCODE_BFE:
 267                 brw_BFE(p, dest, src0, src1, src2);
 268                 break;
 269         case BRW_OPCODE_BFI2:
 270                 brw_BFI2(p, dest, src0, src1, src2);
 271                 break;
 272         default:
 273                 fprintf(stderr, "Unsupported ternary opcode\n");
 274         }
 275 }
 276
 277 static void
 278 i965_asm_set_instruction_options(struct brw_codegen *p,
 279                                  struct options options)
 280 {
 281         brw_inst_set_access_mode(p->devinfo, brw_last_inst,
 282                                  options.access_mode);
 283         brw_inst_set_mask_control(p->devinfo, brw_last_inst,
 284                                   options.mask_control);
 285         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
 286                                     options.thread_control);
 287         brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
 288                                  options.no_dd_check);
 289         brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 290                                  options.no_dd_clear);
 291         brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 292                                    options.debug_control);
 293         if (p->devinfo->gen >= 6)
 294                 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
 295                                             options.acc_wr_control);
 296         brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
 297                                   options.compaction);
 298 }
 299
 300 static void
 301 i965_asm_set_dst_nr(struct brw_codegen *p,
 302                     struct brw_reg *reg,
 303                     struct options options)
 304 {
 305         if (p->devinfo->gen <= 6) {
 306                 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
 307                     options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
 308                     !options.is_compr)
 309                         reg->nr |= BRW_MRF_COMPR4;
 310         }
 311 }
 312
 313 %}
 314
 315 %locations
 316
 317 %start ROOT
 318
 319 %union {
 320         double number;
 321         int integer;
 322         unsigned long long int llint;
 323         struct brw_reg reg;
 324         enum brw_reg_type reg_type;
 325         struct brw_codegen *program;
 326         struct predicate predicate;
 327         struct condition condition;
 328         struct options options;
 329         brw_inst *instruction;
 330 }
 331
 332 %token ABS
 333 %token COLON
 334 %token COMMA
 335 %token DOT
 336 %token LANGLE RANGLE
 337 %token LCURLY RCURLY
 338 %token LPAREN RPAREN
 339 %token LSQUARE RSQUARE
 340 %token PLUS MINUS
 341 %token SEMICOLON
 342
 343 /* datatypes */
 344 %token <integer> TYPE_B TYPE_UB
 345 %token <integer> TYPE_W TYPE_UW
 346 %token <integer> TYPE_D TYPE_UD
 347 %token <integer> TYPE_Q TYPE_UQ
 348 %token <integer> TYPE_V TYPE_UV
 349 %token <integer> TYPE_F TYPE_HF
 350 %token <integer> TYPE_DF TYPE_NF
 351 %token <integer> TYPE_VF
 352
 353 /* opcodes */
 354 %token <integer> ADD ADD3 ADDC AND ASR AVG
 355 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 356 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
 357 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
 358 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
 359 %token <integer> GOTO
 360 %token <integer> HALT
 361 %token <integer> IF IFF ILLEGAL
 362 %token <integer> JMPI JOIN
 363 %token <integer> LINE LRP LZD
 364 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
 365 %token <integer> NENOP NOP NOT
 366 %token <integer> OR
 367 %token <integer> PLN POP PUSH
 368 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
 369 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
 370 %token <integer> WAIT WHILE
 371 %token <integer> XOR
 372
 373 /* extended math functions */
 374 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
 375 %token <integer> RSQRTM SIN SINCOS SQRT
 376
 377 /* shared functions for send */
 378 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
 379 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
 380
 381 /* Conditional modifiers */
 382 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
 383 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
 384
 385 /* register Access Modes */
 386 %token ALIGN1 ALIGN16
 387
 388 /* accumulator write control */
 389 %token ACCWREN
 390
 391 /* compaction control */
 392 %token CMPTCTRL
 393
 394 /* compression control */
 395 %token COMPR COMPR4 SECHALF
 396
 397 /* mask control (WeCtrl) */
 398 %token WECTRL
 399
 400 /* debug control */
 401 %token BREAKPOINT
 402
 403 /* dependency control */
 404 %token NODDCLR NODDCHK
 405
 406 /* end of thread */
 407 %token EOT
 408
 409 /* mask control */
 410 %token MASK_DISABLE;
 411
 412 /* predicate control */
 413 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
 414 %token <integer> ANY32H ALL32H
 415
 416 /* round instructions */
 417 %token <integer> ROUND_INCREMENT
 418
 419 /* staturation */
 420 %token SATURATE
 421
 422 /* thread control */
 423 %token ATOMIC SWITCH
 424
 425 /* quater control */
 426 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
 427 %token QTR_6N QTR_7N QTR_8N
 428
 429 /* channels */
 430 %token <integer> X Y Z W
 431
 432 /* reg files */
 433 %token GENREGFILE MSGREGFILE
 434
 435 /* vertical stride in register region */
 436 %token VxH
 437
 438 /* register type */
 439 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
 440 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
 441 %token <integer> MASKREG
 442
 443 %token <integer> INTEGER
 444 %token <llint> LONG
 445 %token NULL_TOKEN
 446
 447 %precedence SUBREGNUM
 448 %left PLUS MINUS
 449 %precedence DOT
 450 %precedence EMPTYEXECSIZE
 451 %precedence LPAREN
 452
 453 %type <integer> execsize simple_int exp
 454 %type <llint> exp2
 455
 456 /* predicate control */
 457 %type <integer> predctrl predstate
 458 %type <predicate> predicate
 459
 460 /* conditional modifier */
 461 %type <condition> cond_mod
 462 %type <integer> condModifiers
 463
 464 /* instruction options  */
 465 %type <options> instoptions instoption_list
 466 %type <integer> instoption
 467
 468 /* writemask */
 469 %type <integer> writemask_x writemask_y writemask_z writemask_w
 470 %type <integer> writemask
 471
 472 /* dst operand */
 473 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
 474 %type <integer> dstregion
 475
 476 %type <integer> saturate relativelocation rellocation
 477 %type <reg> relativelocation2
 478
 479 /* src operand */
 480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
 482 %type <reg> indirectgenreg indirectregion
 483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 484 %type <reg> region_wh directgenreg directmsgreg indirectmsgreg
 485 %type <integer> swizzle
 486
 487 /* registers */
 488 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
 489 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
 490 %type <integer> subregnum
 491
 492 /* register types */
 493 %type <reg_type> reg_type imm_type
 494
 495 /* immediate values */
 496 %type <llint> immval
 497
 498 /* instruction opcodes */
 499 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
 500 %type <integer> sendop
 501 %type <instruction> sendopcode
 502
 503 %type <integer> negate abs chansel math_function sharedfunction
 504
 505 %code {
 506
 507 static void
 508 add_instruction_option(struct options *options, int option)
 509 {
 510         switch (option) {
 511         case ALIGN1:
 512                 options->access_mode = BRW_ALIGN_1;
 513                 break;
 514         case ALIGN16:
 515                 options->access_mode = BRW_ALIGN_16;
 516                 break;
 517         case SECHALF:
 518                 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
 519                 break;
 520         case COMPR:
 521                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 522                 options->is_compr = true;
 523                 break;
 524         case COMPR4:
 525                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 526                 break;
 527         case SWITCH:
 528                 options->thread_control |= BRW_THREAD_SWITCH;
 529                 break;
 530         case ATOMIC:
 531                 options->thread_control |= BRW_THREAD_ATOMIC;
 532                 break;
 533         case NODDCHK:
 534                 options->no_dd_check = true;
 535                 break;
 536         case NODDCLR:
 537                 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
 538                 break;
 539         case MASK_DISABLE:
 540                 options->mask_control |= BRW_MASK_DISABLE;
 541                 break;
 542         case BREAKPOINT:
 543                 options->debug_control = BRW_DEBUG_BREAKPOINT;
 544                 break;
 545         case WECTRL:
 546                 options->mask_control |= BRW_WE_ALL;
 547                 break;
 548         case CMPTCTRL:
 549                 options->compaction = true;
 550                 break;
 551         case ACCWREN:
 552                 options->acc_wr_control = true;
 553                 break;
 554         case EOT:
 555                 options->end_of_thread = true;
 556                 break;
 557         /* TODO : Figure out how to set instruction group and get rid of
 558          * code below
 559          */
 560         case QTR_2Q:
 561                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 562                 break;
 563         case QTR_3Q:
 564                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 565                 break;
 566         case QTR_4Q:
 567                 options->qtr_ctrl = 3;
 568                 break;
 569         case QTR_2H:
 570                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 571                 break;
 572         case QTR_2N:
 573                 options->qtr_ctrl = BRW_COMPRESSION_NONE;
 574                 options->nib_ctrl = true;
 575                 break;
 576         case QTR_3N:
 577                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 578                 break;
 579         case QTR_4N:
 580                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 581                 options->nib_ctrl = true;
 582                 break;
 583         case QTR_5N:
 584                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 585                 break;
 586         case QTR_6N:
 587                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 588                 options->nib_ctrl = true;
 589                 break;
 590         case QTR_7N:
 591                 options->qtr_ctrl = 3;
 592                 break;
 593         case QTR_8N:
 594                 options->qtr_ctrl = 3;
 595                 options->nib_ctrl = true;
 596                 break;
 597         }
 598 }
 599 }
 600 %%
 601
 602 ROOT:
 603         instrseq
 604         ;
 605
 606 instrseq:
 607         instrseq instruction SEMICOLON
 608         | instrseq relocatableinstruction SEMICOLON
 609         | instruction SEMICOLON
 610         | relocatableinstruction SEMICOLON
 611         ;
 612
 613 /* Instruction Group */
 614 instruction:
 615         unaryinstruction
 616         | binaryinstruction
 617         | binaryaccinstruction
 618         | mathinstruction
 619         | nopinstruction
 620         | syncinstruction
 621         | ternaryinstruction
 622         | sendinstruction
 623         | illegalinstruction
 624         ;
 625
 626 relocatableinstruction:
 627         jumpinstruction
 628         | branchinstruction
 629         | breakinstruction
 630         | loopinstruction
 631         ;
 632
 633 illegalinstruction:
 634         ILLEGAL execsize instoptions
 635         {
 636                 brw_next_insn(p, $1);
 637                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 638                 i965_asm_set_instruction_options(p, $3);
 639         }
 640         ;
 641
 642 /* Unary instruction */
 643 unaryinstruction:
 644         predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
 645         {
 646                 i965_asm_set_dst_nr(p, &$6, $8);
 647                 brw_set_default_access_mode(p, $8.access_mode);
 648                 i965_asm_unary_instruction($2, p, $6, $7);
 649                 brw_pop_insn_state(p);
 650                 i965_asm_set_instruction_options(p, $8);
 651                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 652                                            $4.cond_modifier);
 653
 654                 if (p->devinfo->gen >= 7) {
 655                         if ($2 != BRW_OPCODE_DIM) {
 656                                 brw_inst_set_flag_reg_nr(p->devinfo,
 657                                                          brw_last_inst,
 658                                                          $4.flag_reg_nr);
 659                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 660                                                             brw_last_inst,
 661                                                             $4.flag_subreg_nr);
 662                         }
 663                 }
 664
 665                 if ($7.file != BRW_IMMEDIATE_VALUE) {
 666                         brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
 667                                                   $7.vstride);
 668                 }
 669                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 670                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 671                 // TODO: set instruction group instead of qtr and nib ctrl
 672                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 673                                          $8.qtr_ctrl);
 674
 675                 if (p->devinfo->gen >= 7)
 676                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 677                                                  $8.nib_ctrl);
 678         }
 679         ;
 680
 681 unaryopcodes:
 682         BFREV
 683         | CBIT
 684         | DIM
 685         | F16TO32
 686         | F32TO16
 687         | FBH
 688         | FBL
 689         | FRC
 690         | LZD
 691         | MOV
 692         | NOT
 693         | RNDD
 694         | RNDE
 695         | RNDU
 696         | RNDZ
 697         ;
 698
 699 /* Binary instruction */
 700 binaryinstruction:
 701         predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
 702         {
 703                 i965_asm_set_dst_nr(p, &$6, $9);
 704                 brw_set_default_access_mode(p, $9.access_mode);
 705                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 706                 i965_asm_set_instruction_options(p, $9);
 707                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 708                                            $4.cond_modifier);
 709
 710                 if (p->devinfo->gen >= 7) {
 711                         brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
 712                                                  $4.flag_reg_nr);
 713                         brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
 714                                                     $4.flag_subreg_nr);
 715                 }
 716
 717                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 718                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 719                 // TODO: set instruction group instead of qtr and nib ctrl
 720                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 721                                          $9.qtr_ctrl);
 722
 723                 if (p->devinfo->gen >= 7)
 724                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 725                                                  $9.nib_ctrl);
 726
 727                 brw_pop_insn_state(p);
 728         }
 729         ;
 730
 731 binaryopcodes:
 732         ADDC
 733         | BFI1
 734         | DP2
 735         | DP3
 736         | DP4
 737         | DPH
 738         | LINE
 739         | MAC
 740         | MACH
 741         | MUL
 742         | PLN
 743         | ROL
 744         | ROR
 745         | SAD2
 746         | SADA2
 747         | SUBB
 748         ;
 749
 750 /* Binary acc instruction */
 751 binaryaccinstruction:
 752         predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
 753         {
 754                 i965_asm_set_dst_nr(p, &$6, $9);
 755                 brw_set_default_access_mode(p, $9.access_mode);
 756                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 757                 brw_pop_insn_state(p);
 758                 i965_asm_set_instruction_options(p, $9);
 759                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 760                                            $4.cond_modifier);
 761
 762                 if (p->devinfo->gen >= 7) {
 763                         if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
 764                                 brw_inst_set_flag_reg_nr(p->devinfo,
 765                                                          brw_last_inst,
 766                                                          $4.flag_reg_nr);
 767                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 768                                                             brw_last_inst,
 769                                                             $4.flag_subreg_nr);
 770                         }
 771                 }
 772
 773                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 774                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 775                 // TODO: set instruction group instead of qtr and nib ctrl
 776                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 777                                          $9.qtr_ctrl);
 778
 779                 if (p->devinfo->gen >= 7)
 780                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 781                                                  $9.nib_ctrl);
 782         }
 783         ;
 784
 785 binaryaccopcodes:
 786         ADD
 787         | AND
 788         | ASR
 789         | AVG
 790         | CMP
 791         | CMPN
 792         | OR
 793         | SEL
 794         | SHL
 795         | SHR
 796         | XOR
 797         ;
 798
 799 /* Math instruction */
 800 mathinstruction:
 801         predicate MATH saturate math_function execsize dst src srcimm instoptions
 802         {
 803                 brw_set_default_access_mode(p, $9.access_mode);
 804                 gen6_math(p, $6, $4, $7, $8);
 805                 i965_asm_set_instruction_options(p, $9);
 806                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 807                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 808                 // TODO: set instruction group instead
 809                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 810                                          $9.qtr_ctrl);
 811
 812                 if (p->devinfo->gen >= 7)
 813                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 814                                                  $9.nib_ctrl);
 815
 816                 brw_pop_insn_state(p);
 817         }
 818         ;
 819
 820 math_function:
 821         COS
 822         | EXP
 823         | FDIV
 824         | INV
 825         | INVM
 826         | INTDIV
 827         | INTDIVMOD
 828         | INTMOD
 829         | LOG
 830         | POW
 831         | RSQ
 832         | RSQRTM
 833         | SIN
 834         | SQRT
 835         | SINCOS
 836         ;
 837
 838 /* NOP instruction */
 839 nopinstruction:
 840         NOP
 841         {
 842                 brw_NOP(p);
 843         }
 844         ;
 845
 846 /* Ternary operand instruction */
 847 ternaryinstruction:
 848         predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
 849         {
 850                 brw_set_default_access_mode(p, $10.access_mode);
 851                 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
 852                 brw_pop_insn_state(p);
 853                 i965_asm_set_instruction_options(p, $10);
 854                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 855                                            $4.cond_modifier);
 856
 857                 if (p->devinfo->gen >= 7) {
 858                         brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
 859                                                  $4.flag_reg_nr);
 860                         brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
 861                                                     $4.flag_subreg_nr);
 862                 }
 863
 864                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 865                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 866                 // TODO: set instruction group instead of qtr and nib ctrl
 867                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 868                                          $10.qtr_ctrl);
 869
 870                 if (p->devinfo->gen >= 7)
 871                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 872                                                  $10.nib_ctrl);
 873         }
 874         ;
 875
 876 ternaryopcodes:
 877         CSEL
 878         | BFE
 879         | BFI2
 880         | LRP
 881         | MAD
 882         ;
 883
 884 /* Sync instruction */
 885 syncinstruction:
 886         WAIT execsize src instoptions
 887         {
 888                 brw_next_insn(p, $1);
 889                 i965_asm_set_instruction_options(p, $4);
 890                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 891                 brw_set_default_access_mode(p, $4.access_mode);
 892                 struct brw_reg src = brw_notification_reg();
 893                 brw_set_dest(p, brw_last_inst, src);
 894                 brw_set_src0(p, brw_last_inst, src);
 895                 brw_set_src1(p, brw_last_inst, brw_null_reg());
 896                 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
 897         }
 898         ;
 899
 900 /* Send instruction */
 901 sendinstruction:
 902         predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
 903         {
 904                 i965_asm_set_instruction_options(p, $8);
 905                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 906                 brw_set_dest(p, brw_last_inst, $4);
 907                 brw_set_src0(p, brw_last_inst, $5);
 908                 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
 909                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 910                                             BRW_IMMEDIATE_VALUE,
 911                                             BRW_REGISTER_TYPE_UD);
 912                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
 913                 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
 914                 // TODO: set instruction group instead of qtr and nib ctrl
 915                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 916                                          $8.qtr_ctrl);
 917
 918                 if (p->devinfo->gen >= 7)
 919                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 920                                                  $8.nib_ctrl);
 921
 922                 brw_pop_insn_state(p);
 923         }
 924         | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
 925         {
 926                 i965_asm_set_instruction_options(p, $9);
 927                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 928                 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
 929                 brw_set_dest(p, brw_last_inst, $5);
 930                 brw_set_src0(p, brw_last_inst, $6);
 931                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 932                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 933                                             BRW_IMMEDIATE_VALUE,
 934                                             BRW_REGISTER_TYPE_UD);
 935                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 936                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 937                 // TODO: set instruction group instead of qtr and nib ctrl
 938                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 939                                          $9.qtr_ctrl);
 940
 941                 if (p->devinfo->gen >= 7)
 942                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 943                                                  $9.nib_ctrl);
 944
 945                 brw_pop_insn_state(p);
 946         }
 947         | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
 948         {
 949                 i965_asm_set_instruction_options(p, $9);
 950                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 951                 brw_set_dest(p, brw_last_inst, $4);
 952                 brw_set_src0(p, brw_last_inst, $5);
 953                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 954                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 955                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 956                 // TODO: set instruction group instead of qtr and nib ctrl
 957                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 958                                          $9.qtr_ctrl);
 959
 960                 if (p->devinfo->gen >= 7)
 961                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 962                                                  $9.nib_ctrl);
 963
 964                 brw_pop_insn_state(p);
 965         }
 966         | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
 967         {
 968                 brw_next_insn(p, $2);
 969                 i965_asm_set_instruction_options(p, $10);
 970                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 971                 brw_set_dest(p, brw_last_inst, $4);
 972                 brw_set_src0(p, brw_last_inst, $5);
 973                 brw_set_src1(p, brw_last_inst, $6);
 974
 975                 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
 976                         brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
 977                 } else {
 978                         brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
 979                 }
 980
 981                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 982                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
 983                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
 984                 // TODO: set instruction group instead of qtr and nib ctrl
 985                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 986                                          $10.qtr_ctrl);
 987
 988                 if (p->devinfo->gen >= 7)
 989                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 990                                                  $10.nib_ctrl);
 991
 992                 brw_pop_insn_state(p);
 993         }
 994         | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
 995         {
 996                 brw_next_insn(p, $2);
 997                 i965_asm_set_instruction_options(p, $10);
 998                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 999                 brw_set_dest(p, brw_last_inst, $4);
1000                 brw_set_src0(p, brw_last_inst, $5);
1001                 brw_set_src1(p, brw_last_inst, $6);
1002
1003                 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
1004                 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
1005
1006                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
1007                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
1008                 // TODO: set instruction group instead of qtr and nib ctrl
1009                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
1010                                          $10.qtr_ctrl);
1011
1012                 if (p->devinfo->gen >= 7)
1013                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1014                                                  $10.nib_ctrl);
1015
1016                 brw_pop_insn_state(p);
1017         }
1018         ;
1019
1020 sendop:
1021         SEND
1022         | SENDC
1023         ;
1024
1025 sendopcode:
1026         sendop   { $$ = brw_next_insn(p, $1); }
1027         ;
1028
1029 sharedfunction:
1030         NULL_TOKEN              { $$ = BRW_SFID_NULL; }
1031         | MATH                  { $$ = BRW_SFID_MATH; }
1032         | GATEWAY               { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1033         | READ                  { $$ = BRW_SFID_DATAPORT_READ; }
1034         | WRITE                 { $$ = BRW_SFID_DATAPORT_WRITE; }
1035         | URB                   { $$ = BRW_SFID_URB; }
1036         | THREAD_SPAWNER        { $$ = BRW_SFID_THREAD_SPAWNER; }
1037         | VME                   { $$ = BRW_SFID_VME; }
1038         | RENDER                { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1039         | CONST                 { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1040         | DATA                  { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1041         | PIXEL_INTERP          { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1042         | DP_DATA_1             { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1043         | CRE                   { $$ = HSW_SFID_CRE; }
1044         | SAMPLER               { $$ = BRW_SFID_SAMPLER; }
1045         | DP_SAMPLER            { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1046         ;
1047
1048 exp2:
1049         LONG            { $$ = $1; }
1050         | MINUS LONG    { $$ = -$2; }
1051         ;
1052
1053 /* Jump instruction */
1054 jumpinstruction:
1055         predicate JMPI execsize relativelocation2 instoptions
1056         {
1057                 brw_next_insn(p, $2);
1058                 i965_asm_set_instruction_options(p, $5);
1059                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1060                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1061                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1062                 brw_set_src1(p, brw_last_inst, $4);
1063                 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1064                                           brw_inst_pred_control(p->devinfo,
1065                                                                 brw_last_inst));
1066                 brw_pop_insn_state(p);
1067         }
1068         ;
1069
1070 /* branch instruction */
1071 branchinstruction:
1072         predicate ENDIF execsize relativelocation instoptions
1073         {
1074                 brw_next_insn(p, $2);
1075                 i965_asm_set_instruction_options(p, $5);
1076                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1077
1078                 if (p->devinfo->gen < 6) {
1079                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1080                                      BRW_REGISTER_TYPE_D));
1081                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1082                                      BRW_REGISTER_TYPE_D));
1083                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1084                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1085                                                     $4);
1086                 } else if (p->devinfo->gen == 6) {
1087                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1088                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1089                                                      $4);
1090                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1091                                      BRW_REGISTER_TYPE_D));
1092                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1093                                      BRW_REGISTER_TYPE_D));
1094                 } else if (p->devinfo->gen == 7) {
1095                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1096                                      BRW_REGISTER_TYPE_D));
1097                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1098                                      BRW_REGISTER_TYPE_D));
1099                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1100                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1101                 } else {
1102                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1103                 }
1104
1105                 if (p->devinfo->gen < 6)
1106                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1107                                                     BRW_THREAD_SWITCH);
1108                 brw_pop_insn_state(p);
1109         }
1110         | ELSE execsize relativelocation rellocation instoptions
1111         {
1112                 brw_next_insn(p, $1);
1113                 i965_asm_set_instruction_options(p, $5);
1114                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1115
1116                 if (p->devinfo->gen < 6) {
1117                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1118                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1119                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1120                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1121                                                      $3);
1122                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1123                                                     $4);
1124                 } else if (p->devinfo->gen == 6) {
1125                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1126                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1127                                                      $3);
1128                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1129                                      BRW_REGISTER_TYPE_D));
1130                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1131                                      BRW_REGISTER_TYPE_D));
1132                 } else if (p->devinfo->gen == 7) {
1133                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1134                                      BRW_REGISTER_TYPE_D));
1135                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1136                                      BRW_REGISTER_TYPE_D));
1137                         brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1138                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1139                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1140                 } else {
1141                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1142                                      BRW_REGISTER_TYPE_D));
1143                         brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1144                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1145                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1146                 }
1147
1148                 if (!p->single_program_flow && p->devinfo->gen < 6)
1149                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1150                                                     BRW_THREAD_SWITCH);
1151         }
1152         | predicate IF execsize relativelocation rellocation instoptions
1153         {
1154                 brw_next_insn(p, $2);
1155                 i965_asm_set_instruction_options(p, $6);
1156                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1157
1158                 if (p->devinfo->gen < 6) {
1159                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1160                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1161                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1162                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1163                                                      $4);
1164                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1165                                                     $5);
1166                 } else if (p->devinfo->gen == 6) {
1167                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1168                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1169                                                      $4);
1170                         brw_set_src0(p, brw_last_inst,
1171                                      vec1(retype(brw_null_reg(),
1172                                      BRW_REGISTER_TYPE_D)));
1173                         brw_set_src1(p, brw_last_inst,
1174                                      vec1(retype(brw_null_reg(),
1175                                      BRW_REGISTER_TYPE_D)));
1176                 } else if (p->devinfo->gen == 7) {
1177                         brw_set_dest(p, brw_last_inst,
1178                                      vec1(retype(brw_null_reg(),
1179                                      BRW_REGISTER_TYPE_D)));
1180                         brw_set_src0(p, brw_last_inst,
1181                                      vec1(retype(brw_null_reg(),
1182                                      BRW_REGISTER_TYPE_D)));
1183                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1184                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1185                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1186                 } else {
1187                         brw_set_dest(p, brw_last_inst,
1188                                      vec1(retype(brw_null_reg(),
1189                                      BRW_REGISTER_TYPE_D)));
1190                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1191                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1192                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1193                 }
1194
1195                 if (!p->single_program_flow && p->devinfo->gen < 6)
1196                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1197                                                     BRW_THREAD_SWITCH);
1198
1199                 brw_pop_insn_state(p);
1200         }
1201         | predicate IFF execsize relativelocation instoptions
1202         {
1203                 brw_next_insn(p, $2);
1204                 i965_asm_set_instruction_options(p, $5);
1205                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1206
1207                 if (p->devinfo->gen < 6) {
1208                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1209                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1210                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1211                                                      $4);
1212                         brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1213                 } else if (p->devinfo->gen == 6) {
1214                         brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1215                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1216                                                      $4);
1217                         brw_set_src0(p, brw_last_inst,
1218                                      vec1(retype(brw_null_reg(),
1219                                      BRW_REGISTER_TYPE_D)));
1220                         brw_set_src1(p, brw_last_inst,
1221                                      vec1(retype(brw_null_reg(),
1222                                      BRW_REGISTER_TYPE_D)));
1223                 } else if (p->devinfo->gen == 7) {
1224                         brw_set_dest(p, brw_last_inst,
1225                                      vec1(retype(brw_null_reg(),
1226                                      BRW_REGISTER_TYPE_D)));
1227                         brw_set_src0(p, brw_last_inst,
1228                                      vec1(retype(brw_null_reg(),
1229                                      BRW_REGISTER_TYPE_D)));
1230                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1231                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1232                 } else {
1233                         brw_set_dest(p, brw_last_inst,
1234                                      vec1(retype(brw_null_reg(),
1235                                      BRW_REGISTER_TYPE_D)));
1236                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1237                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1238                 }
1239
1240                 if (!p->single_program_flow && p->devinfo->gen < 6)
1241                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1242                                                     BRW_THREAD_SWITCH);
1243
1244                 brw_pop_insn_state(p);
1245         }
1246         ;
1247
1248 /* break instruction */
1249 breakinstruction:
1250         predicate BREAK execsize relativelocation relativelocation instoptions
1251         {
1252                 brw_next_insn(p, $2);
1253                 i965_asm_set_instruction_options(p, $6);
1254                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1255
1256                 if (p->devinfo->gen >= 8) {
1257                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1258                                      BRW_REGISTER_TYPE_D));
1259                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1260                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1261                 } else if (p->devinfo->gen >= 6) {
1262                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1263                                      BRW_REGISTER_TYPE_D));
1264                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1265                                      BRW_REGISTER_TYPE_D));
1266                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1267                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1268                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1269                 } else {
1270                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1271                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1272                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1273                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1274                                                      $4);
1275                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1276                                                     $5);
1277                 }
1278
1279                 brw_pop_insn_state(p);
1280         }
1281         | predicate HALT execsize relativelocation relativelocation instoptions
1282         {
1283                 brw_next_insn(p, $2);
1284                 i965_asm_set_instruction_options(p, $6);
1285                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1286                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1287                              BRW_REGISTER_TYPE_D));
1288
1289                 if (p->devinfo->gen >= 8) {
1290                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1291                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1292                 } else {
1293                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1294                                      BRW_REGISTER_TYPE_D));
1295                         brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1296                 }
1297
1298                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1299                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1300                 brw_pop_insn_state(p);
1301         }
1302         | predicate CONT execsize relativelocation relativelocation instoptions
1303         {
1304                 brw_next_insn(p, $2);
1305                 i965_asm_set_instruction_options(p, $6);
1306                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1307                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1308
1309                 if (p->devinfo->gen >= 8) {
1310                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1311                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1312                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1313                 } else {
1314                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1315                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1316                         if (p->devinfo->gen >= 6) {
1317                                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1318                                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1319                         } else {
1320                                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1321                                                              $4);
1322                                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1323                                                             $5);
1324                         }
1325                 }
1326
1327                 brw_pop_insn_state(p);
1328         }
1329         ;
1330
1331 /* loop instruction */
1332 loopinstruction:
1333         predicate WHILE execsize relativelocation instoptions
1334         {
1335                 brw_next_insn(p, $2);
1336                 i965_asm_set_instruction_options(p, $5);
1337                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1338
1339                 if (p->devinfo->gen >= 6) {
1340                         if (p->devinfo->gen >= 8) {
1341                                 brw_set_dest(p, brw_last_inst,
1342                                              retype(brw_null_reg(),
1343                                              BRW_REGISTER_TYPE_D));
1344                                 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1345                         } else if (p->devinfo->gen == 7) {
1346                                 brw_set_dest(p, brw_last_inst,
1347                                              retype(brw_null_reg(),
1348                                              BRW_REGISTER_TYPE_D));
1349                                 brw_set_src0(p, brw_last_inst,
1350                                              retype(brw_null_reg(),
1351                                              BRW_REGISTER_TYPE_D));
1352                                 brw_set_src1(p, brw_last_inst,
1353                                              brw_imm_w(0x0));
1354                                 brw_inst_set_jip(p->devinfo, brw_last_inst,
1355                                                  $4);
1356                         } else {
1357                                 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1358                                 brw_inst_set_gen6_jump_count(p->devinfo,
1359                                                              brw_last_inst,
1360                                                              $4);
1361                                 brw_set_src0(p, brw_last_inst,
1362                                              retype(brw_null_reg(),
1363                                              BRW_REGISTER_TYPE_D));
1364                                 brw_set_src1(p, brw_last_inst,
1365                                              retype(brw_null_reg(),
1366                                              BRW_REGISTER_TYPE_D));
1367                         }
1368                 } else {
1369                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1370                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1371                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1372                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1373                                                      $4);
1374                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1375                                                     0);
1376                 }
1377                 brw_pop_insn_state(p);
1378         }
1379         | DO execsize instoptions
1380         {
1381                 brw_next_insn(p, $1);
1382                 if (p->devinfo->gen < 6) {
1383                         brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1384                         i965_asm_set_instruction_options(p, $3);
1385                         brw_set_dest(p, brw_last_inst, brw_null_reg());
1386                         brw_set_src0(p, brw_last_inst, brw_null_reg());
1387                         brw_set_src1(p, brw_last_inst, brw_null_reg());
1388
1389                         brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1390                 }
1391         }
1392         ;
1393
1394 /* Relative location */
1395 relativelocation2:
1396         immreg
1397         | reg32
1398         ;
1399
1400 simple_int:
1401         INTEGER                 { $$ = $1; }
1402         | MINUS INTEGER         { $$ = -$2; }
1403         | LONG                  { $$ = $1; }
1404         | MINUS LONG            { $$ = -$2; }
1405         ;
1406
1407 rellocation:
1408         relativelocation
1409         | %empty { $$ = 0; }
1410         ;
1411
1412 relativelocation:
1413         simple_int
1414         {
1415                 $$ = $1;
1416         }
1417         ;
1418
1419 /* Destination register */
1420 dst:
1421         dstoperand
1422         | dstoperandex
1423         ;
1424
1425 dstoperand:
1426         dstreg dstregion writemask reg_type
1427         {
1428                 $$ = $1;
1429
1430                 if ($2 == -1) {
1431                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1432                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1433                         $$.width = BRW_WIDTH_1;
1434                 } else {
1435                         $$.hstride = $2;
1436                 }
1437                 $$.type = $4;
1438                 $$.writemask = $3;
1439                 $$.swizzle = BRW_SWIZZLE_NOOP;
1440                 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1441         }
1442         ;
1443
1444 dstoperandex:
1445         dstoperandex_typed dstregion writemask reg_type
1446         {
1447                 $$ = $1;
1448                 $$.hstride = $2;
1449                 $$.type = $4;
1450                 $$.writemask = $3;
1451                 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1452         }
1453         /* BSpec says "When the conditional modifier is present, updates
1454          * to the selected flag register also occur. In this case, the
1455          * register region fields of the ‘null’ operand are valid."
1456          */
1457         | nullreg dstregion writemask reg_type
1458         {
1459                 $$ = $1;
1460                 if ($2 == -1) {
1461                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1462                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1463                         $$.width = BRW_WIDTH_1;
1464                 } else {
1465                         $$.hstride = $2;
1466                 }
1467                 $$.writemask = $3;
1468                 $$.type = $4;
1469         }
1470         | threadcontrolreg
1471         {
1472                 $$ = $1;
1473                 $$.hstride = 1;
1474                 $$.type = BRW_REGISTER_TYPE_UW;
1475         }
1476         ;
1477
1478 dstoperandex_typed:
1479         accreg
1480         | addrreg
1481         | channelenablereg
1482         | controlreg
1483         | flagreg
1484         | ipreg
1485         | maskreg
1486         | performancereg
1487         | statereg
1488         ;
1489
1490 dstreg:
1491         directgenreg
1492         {
1493                 $$ = $1;
1494                 $$.address_mode = BRW_ADDRESS_DIRECT;
1495         }
1496         | indirectgenreg
1497         {
1498                 $$ = $1;
1499                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1500         }
1501         | directmsgreg
1502         {
1503                 $$ = $1;
1504                 $$.address_mode = BRW_ADDRESS_DIRECT;
1505         }
1506         | indirectmsgreg
1507         {
1508                 $$ = $1;
1509                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1510         }
1511         ;
1512
1513 /* Source register */
1514 srcaccimm:
1515         srcacc
1516         | immreg
1517         ;
1518
1519 immreg:
1520         immval imm_type
1521         {
1522                 switch ($2) {
1523                 case BRW_REGISTER_TYPE_UD:
1524                         $$ = brw_imm_ud($1);
1525                         break;
1526                 case BRW_REGISTER_TYPE_D:
1527                         $$ = brw_imm_d($1);
1528                         break;
1529                 case BRW_REGISTER_TYPE_UW:
1530                         $$ = brw_imm_uw($1 | ($1 << 16));
1531                         break;
1532                 case BRW_REGISTER_TYPE_W:
1533                         $$ = brw_imm_w($1);
1534                         break;
1535                 case BRW_REGISTER_TYPE_F:
1536                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1537                         /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
1538                         $$.u64 = $1;
1539                         break;
1540                 case BRW_REGISTER_TYPE_V:
1541                         $$ = brw_imm_v($1);
1542                         break;
1543                 case BRW_REGISTER_TYPE_UV:
1544                         $$ = brw_imm_uv($1);
1545                         break;
1546                 case BRW_REGISTER_TYPE_VF:
1547                         $$ = brw_imm_vf($1);
1548                         break;
1549                 case BRW_REGISTER_TYPE_Q:
1550                         $$ = brw_imm_q($1);
1551                         break;
1552                 case BRW_REGISTER_TYPE_UQ:
1553                         $$ = brw_imm_uq($1);
1554                         break;
1555                 case BRW_REGISTER_TYPE_DF:
1556                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1557                         $$.d64 = $1;
1558                         break;
1559                 default:
1560                         error(&@2, "Unknown immediate type %s\n",
1561                               brw_reg_type_to_letters($2));
1562                 }
1563         }
1564         ;
1565
1566 reg32:
1567         directgenreg region reg_type
1568         {
1569                 $$ = set_direct_src_operand(&$1, $3);
1570                 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1571         }
1572         ;
1573
1574 payload:
1575         directsrcoperand
1576         ;
1577
1578 src:
1579         directsrcoperand
1580         | indirectsrcoperand
1581         ;
1582
1583 srcacc:
1584         directsrcaccoperand
1585         | indirectsrcoperand
1586         ;
1587
1588 srcimm:
1589         directsrcoperand
1590         | indirectsrcoperand
1591         | immreg
1592         ;
1593
1594 directsrcaccoperand:
1595         directsrcoperand
1596         | accreg region reg_type
1597         {
1598                 $$ = set_direct_src_operand(&$1, $3);
1599                 $$.vstride = $2.vstride;
1600                 $$.width = $2.width;
1601                 $$.hstride = $2.hstride;
1602         }
1603         ;
1604
1605 srcarcoperandex:
1606         srcarcoperandex_typed region reg_type
1607         {
1608                 $$ = brw_reg($1.file,
1609                              $1.nr,
1610                              $1.subnr,
1611                              0,
1612                              0,
1613                              $3,
1614                              $2.vstride,
1615                              $2.width,
1616                              $2.hstride,
1617                              BRW_SWIZZLE_NOOP,
1618                              WRITEMASK_XYZW);
1619         }
1620         | nullreg region reg_type
1621         {
1622                 $$ = set_direct_src_operand(&$1, $3);
1623                 $$.vstride = $2.vstride;
1624                 $$.width = $2.width;
1625                 $$.hstride = $2.hstride;
1626         }
1627         | threadcontrolreg
1628         {
1629                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1630         }
1631         ;
1632
1633 srcarcoperandex_typed:
1634         channelenablereg
1635         | controlreg
1636         | flagreg
1637         | ipreg
1638         | maskreg
1639         | statereg
1640         ;
1641
1642 indirectsrcoperand:
1643         negate abs indirectgenreg indirectregion swizzle reg_type
1644         {
1645                 $$ = brw_reg($3.file,
1646                              0,
1647                              $3.subnr,
1648                              $1,  // negate
1649                              $2,  // abs
1650                              $6,
1651                              $4.vstride,
1652                              $4.width,
1653                              $4.hstride,
1654                              $5,
1655                              WRITEMASK_X);
1656
1657                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1658                 // brw_reg set indirect_offset to 0 so set it to valid value
1659                 $$.indirect_offset = $3.indirect_offset;
1660         }
1661         ;
1662
1663 directgenreg_list:
1664         directgenreg
1665         | directmsgreg
1666         | notifyreg
1667         | addrreg
1668         | performancereg
1669         ;
1670
1671 directsrcoperand:
1672         negate abs directgenreg_list region swizzle reg_type
1673         {
1674                 $$ = brw_reg($3.file,
1675                              $3.nr,
1676                              $3.subnr,
1677                              $1,
1678                              $2,
1679                              $6,
1680                              $4.vstride,
1681                              $4.width,
1682                              $4.hstride,
1683                              $5,
1684                              WRITEMASK_X);
1685         }
1686         | srcarcoperandex
1687         ;
1688
1689 /* Address register */
1690 addrparam:
1691         addrreg exp
1692         {
1693                 memset(&$$, '\0', sizeof($$));
1694                 $$.subnr = $1.subnr;
1695                 $$.indirect_offset = $2;
1696         }
1697         | addrreg
1698         ;
1699
1700 /* Register files and register numbers */
1701 exp:
1702         INTEGER         { $$ = $1; }
1703         | LONG          { $$ = $1; }
1704         ;
1705
1706 subregnum:
1707         DOT exp                         { $$ = $2; }
1708         | %empty %prec SUBREGNUM        { $$ = 0; }
1709         ;
1710
1711 directgenreg:
1712         GENREG subregnum
1713         {
1714                 memset(&$$, '\0', sizeof($$));
1715                 $$.file = BRW_GENERAL_REGISTER_FILE;
1716                 $$.nr = $1;
1717                 $$.subnr = $2;
1718         }
1719         ;
1720
1721 indirectgenreg:
1722         GENREGFILE LSQUARE addrparam RSQUARE
1723         {
1724                 memset(&$$, '\0', sizeof($$));
1725                 $$.file = BRW_GENERAL_REGISTER_FILE;
1726                 $$.subnr = $3.subnr;
1727                 $$.indirect_offset = $3.indirect_offset;
1728         }
1729         ;
1730
1731 directmsgreg:
1732         MSGREG subregnum
1733         {
1734                 $$ = brw_message_reg($1);
1735                 $$.subnr = $2;
1736         }
1737         ;
1738
1739 indirectmsgreg:
1740         MSGREGFILE LSQUARE addrparam RSQUARE
1741         {
1742                 memset(&$$, '\0', sizeof($$));
1743                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1744                 $$.subnr = $3.subnr;
1745                 $$.indirect_offset = $3.indirect_offset;
1746         }
1747         ;
1748
1749 addrreg:
1750         ADDRREG subregnum
1751         {
1752                 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1753
1754                 if ($2 > subnr)
1755                         error(&@2, "Address sub register number %d"
1756                                    "out of range\n", $2);
1757
1758                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1759                 $$.nr = BRW_ARF_ADDRESS;
1760                 $$.subnr = $2;
1761         }
1762         ;
1763
1764 accreg:
1765         ACCREG subregnum
1766         {
1767                 int nr_reg;
1768                 if (p->devinfo->gen < 8)
1769                         nr_reg = 2;
1770                 else
1771                         nr_reg = 10;
1772
1773                 if ($1 > nr_reg)
1774                         error(&@1, "Accumulator register number %d"
1775                                    " out of range\n", $1);
1776
1777                 memset(&$$, '\0', sizeof($$));
1778                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1779                 $$.nr = BRW_ARF_ACCUMULATOR;
1780                 $$.subnr = $2;
1781         }
1782         ;
1783
1784 flagreg:
1785         FLAGREG subregnum
1786         {
1787                 // SNB = 1 flag reg and IVB+ = 2 flag reg
1788                 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1789                 int subnr = nr_reg;
1790
1791                 if ($1 > nr_reg)
1792                         error(&@1, "Flag register number %d"
1793                                    " out of range \n", $1);
1794                 if ($2 > subnr)
1795                         error(&@2, "Flag subregister number %d"
1796                                    " out of range\n", $2);
1797
1798                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1799                 $$.nr = BRW_ARF_FLAG | $1;
1800                 $$.subnr = $2;
1801         }
1802         ;
1803
1804 maskreg:
1805         MASKREG subregnum
1806         {
1807                 if ($1 > 0)
1808                         error(&@1, "Mask register number %d"
1809                                    " out of range\n", $1);
1810
1811                 $$ = brw_mask_reg($2);
1812         }
1813         ;
1814
1815 notifyreg:
1816         NOTIFYREG subregnum
1817         {
1818                 if ($1 > 0)
1819                         error(&@1, "Notification register number %d"
1820                                    " out of range\n", $1);
1821
1822                 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1823                 if ($2 > subnr)
1824                         error(&@2, "Notification sub register number %d"
1825                                    " out of range\n", $2);
1826
1827                 $$ = brw_notification_reg();
1828                 $$.subnr = $2;
1829         }
1830         ;
1831
1832 statereg:
1833         STATEREG subregnum
1834         {
1835                 if ($1 > 2)
1836                         error(&@1, "State register number %d"
1837                                    " out of range\n", $1);
1838
1839                 if ($2 > 4)
1840                         error(&@2, "State sub register number %d"
1841                                    " out of range\n", $2);
1842
1843                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1844                 $$.nr = BRW_ARF_STATE;
1845                 $$.subnr = $2;
1846         }
1847         ;
1848
1849 controlreg:
1850         CONTROLREG subregnum
1851         {
1852                 if ($2 > 3)
1853                         error(&@2, "control sub register number %d"
1854                                    " out of range\n", $2);
1855
1856                 $$ = brw_cr0_reg($2);
1857         }
1858         ;
1859
1860 ipreg:
1861         IPREG           { $$ = brw_ip_reg(); }
1862         ;
1863
1864 nullreg:
1865         NULL_TOKEN      { $$ = brw_null_reg(); }
1866         ;
1867
1868 threadcontrolreg:
1869         THREADREG subregnum
1870         {
1871                 if ($1 > 0)
1872                         error(&@1, "Thread control register number %d"
1873                                    " out of range\n", $1);
1874
1875                 if ($2 > 7)
1876                         error(&@2, "Thread control sub register number %d"
1877                                    " out of range\n", $2);
1878
1879                 $$ = brw_tdr_reg();
1880                 $$.subnr = $2;
1881         }
1882         ;
1883
1884 performancereg:
1885         PERFORMANCEREG subregnum
1886         {
1887                 int subnr;
1888                 if (p->devinfo->gen >= 10)
1889                         subnr = 5;
1890                 else if (p->devinfo->gen <= 8)
1891                         subnr = 3;
1892                 else
1893                         subnr = 4;
1894
1895                 if ($2 > subnr)
1896                         error(&@2, "Performance sub register number %d"
1897                                    " out of range\n", $2);
1898
1899                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1900                 $$.nr = BRW_ARF_TIMESTAMP;
1901         }
1902         ;
1903
1904 channelenablereg:
1905         CHANNELENABLEREG subregnum
1906         {
1907                 if ($1 > 0)
1908                         error(&@1, "Channel enable register number %d"
1909                                    " out of range\n", $1);
1910
1911                 $$ = brw_mask_reg($2);
1912         }
1913         ;
1914
1915 /* Immediate values */
1916 immval:
1917         exp2
1918         {
1919                 $$ = $1;
1920         }
1921         | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1922         {
1923                 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1924         }
1925         ;
1926
1927 /* Regions */
1928 dstregion:
1929         %empty  { $$ = -1; }
1930         | LANGLE exp RANGLE
1931         {
1932                 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1933                         error(&@2, "Invalid Horizontal stride %d\n", $2);
1934
1935                 $$ = ffs($2);
1936         }
1937         ;
1938
1939 indirectregion:
1940         region
1941         | region_wh
1942         ;
1943
1944 region:
1945         %empty
1946         {
1947                 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1948         }
1949         | LANGLE exp RANGLE
1950         {
1951                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1952                         error(&@2, "Invalid VertStride %d\n", $2);
1953
1954                 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1955         }
1956         | LANGLE exp COMMA exp COMMA exp RANGLE
1957         {
1958
1959                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1960                         error(&@2, "Invalid VertStride %d\n", $2);
1961
1962                 if ($4 > 16 || !isPowerofTwo($4))
1963                         error(&@4, "Invalid width %d\n", $4);
1964
1965                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1966                         error(&@6, "Invalid Horizontal stride in"
1967                                    "  region_wh %d\n", $6);
1968
1969                 $$ = stride($$, $2, $4, $6);
1970         }
1971         | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1972         {
1973                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1974                         error(&@2, "Invalid VertStride %d\n", $2);
1975
1976                 if ($4 > 16 || !isPowerofTwo($4))
1977                         error(&@4, "Invalid width %d\n", $4);
1978
1979                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1980                         error(&@6, "Invalid Horizontal stride in"
1981                                    " region_wh %d\n", $6);
1982
1983                 $$ = stride($$, $2, $4, $6);
1984         }
1985         | LANGLE VxH COMMA exp COMMA exp RANGLE
1986         {
1987                 if ($4 > 16 || !isPowerofTwo($4))
1988                         error(&@4, "Invalid width %d\n", $4);
1989
1990                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1991                         error(&@6, "Invalid Horizontal stride in"
1992                                    " region_wh %d\n", $6);
1993
1994                 $$ = brw_VxH_indirect(0, 0);
1995         }
1996         ;
1997
1998 region_wh:
1999         LANGLE exp COMMA exp RANGLE
2000         {
2001                 if ($2 > 16 || !isPowerofTwo($2))
2002                         error(&@2, "Invalid width %d\n", $2);
2003
2004                 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2005                         error(&@4, "Invalid Horizontal stride in"
2006                                    " region_wh %d\n", $4);
2007
2008                 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2009         }
2010         ;
2011
2012 reg_type:
2013           TYPE_F        { $$ = BRW_REGISTER_TYPE_F;  }
2014         | TYPE_UD       { $$ = BRW_REGISTER_TYPE_UD; }
2015         | TYPE_D        { $$ = BRW_REGISTER_TYPE_D;  }
2016         | TYPE_UW       { $$ = BRW_REGISTER_TYPE_UW; }
2017         | TYPE_W        { $$ = BRW_REGISTER_TYPE_W;  }
2018         | TYPE_UB       { $$ = BRW_REGISTER_TYPE_UB; }
2019         | TYPE_B        { $$ = BRW_REGISTER_TYPE_B;  }
2020         | TYPE_DF       { $$ = BRW_REGISTER_TYPE_DF; }
2021         | TYPE_UQ       { $$ = BRW_REGISTER_TYPE_UQ; }
2022         | TYPE_Q        { $$ = BRW_REGISTER_TYPE_Q;  }
2023         | TYPE_HF       { $$ = BRW_REGISTER_TYPE_HF; }
2024         | TYPE_NF       { $$ = BRW_REGISTER_TYPE_NF; }
2025         ;
2026
2027 imm_type:
2028         reg_type        { $$ = $1; }
2029         | TYPE_V        { $$ = BRW_REGISTER_TYPE_V;  }
2030         | TYPE_VF       { $$ = BRW_REGISTER_TYPE_VF; }
2031         | TYPE_UV       { $$ = BRW_REGISTER_TYPE_UV; }
2032         ;
2033
2034 writemask:
2035         %empty
2036         {
2037                 $$ = WRITEMASK_XYZW;
2038         }
2039         | DOT writemask_x writemask_y writemask_z writemask_w
2040         {
2041                 $$ = $2 | $3 | $4 | $5;
2042         }
2043         ;
2044
2045 writemask_x:
2046         %empty  { $$ = 0; }
2047         | X     { $$ = 1 << BRW_CHANNEL_X; }
2048         ;
2049
2050 writemask_y:
2051         %empty  { $$ = 0; }
2052         | Y     { $$ = 1 << BRW_CHANNEL_Y; }
2053         ;
2054
2055 writemask_z:
2056         %empty  { $$ = 0; }
2057         | Z     { $$ = 1 << BRW_CHANNEL_Z; }
2058         ;
2059
2060 writemask_w:
2061         %empty  { $$ = 0; }
2062         | W     { $$ = 1 << BRW_CHANNEL_W; }
2063         ;
2064
2065 swizzle:
2066         %empty
2067         {
2068                 $$ = BRW_SWIZZLE_NOOP;
2069         }
2070         | DOT chansel
2071         {
2072                 $$ = BRW_SWIZZLE4($2, $2, $2, $2);
2073         }
2074         | DOT chansel chansel chansel chansel
2075         {
2076                 $$ = BRW_SWIZZLE4($2, $3, $4, $5);
2077         }
2078         ;
2079
2080 chansel:
2081         X
2082         | Y
2083         | Z
2084         | W
2085         ;
2086
2087 /* Instruction prediction and modifiers */
2088 predicate:
2089         %empty
2090         {
2091                 brw_push_insn_state(p);
2092                 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2093                 brw_set_default_flag_reg(p, 0, 0);
2094                 brw_set_default_predicate_inverse(p, false);
2095         }
2096         | LPAREN predstate flagreg predctrl RPAREN
2097         {
2098                 brw_push_insn_state(p);
2099                 brw_set_default_predicate_inverse(p, $2);
2100                 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2101                 brw_set_default_predicate_control(p, $4);
2102         }
2103         ;
2104
2105 predstate:
2106         %empty          { $$ = 0; }
2107         | PLUS          { $$ = 0; }
2108         | MINUS         { $$ = 1; }
2109         ;
2110
2111 predctrl:
2112         %empty          { $$ = BRW_PREDICATE_NORMAL; }
2113         | DOT X         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2114         | DOT Y         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2115         | DOT Z         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2116         | DOT W         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2117         | ANYV
2118         | ALLV
2119         | ANY2H
2120         | ALL2H
2121         | ANY4H
2122         | ALL4H
2123         | ANY8H
2124         | ALL8H
2125         | ANY16H
2126         | ALL16H
2127         | ANY32H
2128         | ALL32H
2129         ;
2130
2131 /* Source Modification */
2132 negate:
2133         %empty          { $$ = 0; }
2134         | MINUS         { $$ = 1; }
2135         ;
2136
2137 abs:
2138         %empty  { $$ = 0; }
2139         | ABS   { $$ = 1; }
2140         ;
2141
2142 /* Flag (Conditional) Modifier */
2143 cond_mod:
2144         condModifiers
2145         {
2146                 $$.cond_modifier = $1;
2147                 $$.flag_reg_nr = 0;
2148                 $$.flag_subreg_nr = 0;
2149         }
2150         | condModifiers DOT flagreg
2151         {
2152                 $$.cond_modifier = $1;
2153                 $$.flag_reg_nr = $3.nr;
2154                 $$.flag_subreg_nr = $3.subnr;
2155         }
2156         ;
2157
2158 condModifiers:
2159         %empty  { $$ = BRW_CONDITIONAL_NONE; }
2160         | ZERO
2161         | EQUAL
2162         | NOT_ZERO
2163         | NOT_EQUAL
2164         | GREATER
2165         | GREATER_EQUAL
2166         | LESS
2167         | LESS_EQUAL
2168         | OVERFLOW
2169         | ROUND_INCREMENT
2170         | UNORDERED
2171         ;
2172
2173 saturate:
2174         %empty          { $$ = BRW_INSTRUCTION_NORMAL; }
2175         | SATURATE      { $$ = BRW_INSTRUCTION_SATURATE; }
2176         ;
2177
2178 /* Execution size */
2179 execsize:
2180         %empty %prec EMPTYEXECSIZE
2181         {
2182                 $$ = 0;
2183         }
2184         | LPAREN exp2 RPAREN
2185         {
2186                 if ($2 > 32 || !isPowerofTwo($2))
2187                         error(&@2, "Invalid execution size %d\n", $2);
2188
2189                 $$ = cvt($2) - 1;
2190         }
2191         ;
2192
2193 /* Instruction options */
2194 instoptions:
2195         %empty
2196         {
2197                 memset(&$$, 0, sizeof($$));
2198         }
2199         | LCURLY instoption_list RCURLY
2200         {
2201                 memset(&$$, 0, sizeof($$));
2202                 $$ = $2;
2203         }
2204         ;
2205
2206 instoption_list:
2207         instoption_list COMMA instoption
2208         {
2209                 memset(&$$, 0, sizeof($$));
2210                 $$ = $1;
2211                 add_instruction_option(&$$, $3);
2212         }
2213         | instoption_list instoption
2214         {
2215                 memset(&$$, 0, sizeof($$));
2216                 $$ = $1;
2217                 add_instruction_option(&$$, $2);
2218         }
2219         | %empty
2220         {
2221                 memset(&$$, 0, sizeof($$));
2222         }
2223         ;
2224
2225 instoption:
2226         ALIGN1          { $$ = ALIGN1;}
2227         | ALIGN16       { $$ = ALIGN16; }
2228         | ACCWREN       { $$ = ACCWREN; }
2229         | SECHALF       { $$ = SECHALF; }
2230         | COMPR         { $$ = COMPR; }
2231         | COMPR4        { $$ = COMPR4; }
2232         | BREAKPOINT    { $$ = BREAKPOINT; }
2233         | NODDCLR       { $$ = NODDCLR; }
2234         | NODDCHK       { $$ = NODDCHK; }
2235         | MASK_DISABLE  { $$ = MASK_DISABLE; }
2236         | EOT           { $$ = EOT; }
2237         | SWITCH        { $$ = SWITCH; }
2238         | ATOMIC        { $$ = ATOMIC; }
2239         | CMPTCTRL      { $$ = CMPTCTRL; }
2240         | WECTRL        { $$ = WECTRL; }
2241         | QTR_2Q        { $$ = QTR_2Q; }
2242         | QTR_3Q        { $$ = QTR_3Q; }
2243         | QTR_4Q        { $$ = QTR_4Q; }
2244         | QTR_2H        { $$ = QTR_2H; }
2245         | QTR_2N        { $$ = QTR_2N; }
2246         | QTR_3N        { $$ = QTR_3N; }
2247         | QTR_4N        { $$ = QTR_4N; }
2248         | QTR_5N        { $$ = QTR_5N; }
2249         | QTR_6N        { $$ = QTR_6N; }
2250         | QTR_7N        { $$ = QTR_7N; }
2251         | QTR_8N        { $$ = QTR_8N; }
2252         ;
2253
2254 %%
2255
2256 extern int yylineno;
2257
2258 void
2259 yyerror(char *msg)
2260 {
2261         fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2262                 input_filename, yylineno, msg, lex_text());
2263         ++errors;
2264 }