3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
192 case BRW_OPCODE_SAD2:
193 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
195 case BRW_OPCODE_SADA2:
196 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
198 case BRW_OPCODE_SUBB:
199 brw_SUBB(p, dest, src0, src1);
202 brw_ADD(p, dest, src0, src1);
205 /* Third parameter is conditional modifier
206 * which gets updated later
208 brw_CMP(p, dest, 0, src0, src1);
211 brw_AND(p, dest, src0, src1);
214 brw_ASR(p, dest, src0, src1);
217 brw_AVG(p, dest, src0, src1);
220 brw_OR(p, dest, src0, src1);
223 brw_SEL(p, dest, src0, src1);
226 brw_SHL(p, dest, src0, src1);
229 brw_SHR(p, dest, src0, src1);
232 brw_XOR(p, dest, src0, src1);
235 brw_MUL(p, dest, src0, src1);
238 fprintf(stderr, "Unsupported binary opcode\n");
243 i965_asm_ternary_instruction(int opcode,
244 struct brw_codegen *p,
252 brw_MAD(p, dest, src0, src1, src2);
254 case BRW_OPCODE_CSEL:
255 brw_CSEL(p, dest, src0, src1, src2);
258 brw_LRP(p, dest, src0, src1, src2);
261 brw_BFE(p, dest, src0, src1, src2);
263 case BRW_OPCODE_BFI2:
264 brw_BFI2(p, dest, src0, src1, src2);
267 fprintf(stderr, "Unsupported ternary opcode\n");
272 i965_asm_set_instruction_options(struct brw_codegen *p,
273 struct options options)
275 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
276 options.access_mode);
277 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
278 options.mask_control);
279 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
280 options.thread_control);
281 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
282 options.no_dd_check);
283 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
284 options.no_dd_clear);
285 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
286 options.debug_control);
287 if (p->devinfo->gen >= 6)
288 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
289 options.acc_wr_control);
290 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
295 i965_asm_set_dst_nr(struct brw_codegen *p,
297 struct options options)
299 if (p->devinfo->gen <= 6) {
300 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
301 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
303 reg->nr |= BRW_MRF_COMPR4;
316 unsigned long long int llint;
318 struct brw_codegen *program;
319 struct predicate predicate;
320 struct condition condition;
321 struct options options;
322 brw_inst *instruction;
332 %token LSQUARE RSQUARE
337 %token <integer> TYPE_B TYPE_UB
338 %token <integer> TYPE_W TYPE_UW
339 %token <integer> TYPE_D TYPE_UD
340 %token <integer> TYPE_Q TYPE_UQ
341 %token <integer> TYPE_V TYPE_UV
342 %token <integer> TYPE_F TYPE_HF
343 %token <integer> TYPE_DF TYPE_NF
344 %token <integer> TYPE_VF
347 %token <integer> ADD ADD3 ADDC AND ASR AVG
348 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
349 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
350 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
351 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
352 %token <integer> GOTO
353 %token <integer> HALT
354 %token <integer> IF IFF ILLEGAL
355 %token <integer> JMPI JOIN
356 %token <integer> LINE LRP LZD
357 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
358 %token <integer> NENOP NOP NOT
360 %token <integer> PLN POP PUSH
361 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
362 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
363 %token <integer> WAIT WHILE
366 /* extended math functions */
367 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
368 %token <integer> RSQRTM SIN SINCOS SQRT
370 /* shared functions for send */
371 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
372 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
374 /* Conditional modifiers */
375 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
376 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
378 /* register Access Modes */
379 %token ALIGN1 ALIGN16
381 /* accumulator write control */
384 /* compaction control */
387 /* compression control */
388 %token COMPR COMPR4 SECHALF
390 /* mask control (WeCtrl) */
396 /* dependency control */
397 %token NODDCLR NODDCHK
405 /* predicate control */
406 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
407 %token <integer> ANY32H ALL32H
409 /* round instructions */
410 %token <integer> ROUND_INCREMENT
419 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
420 %token QTR_6N QTR_7N QTR_8N
423 %token <integer> X Y Z W
426 %token GENREGFILE MSGREGFILE
428 /* vertical stride in register region */
432 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
433 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
434 %token <integer> MASKREG
436 %token <integer> INTEGER
440 %precedence SUBREGNUM
443 %precedence EMPTYEXECSIZE
446 %type <integer> execsize simple_int exp
449 /* predicate control */
450 %type <integer> predctrl predstate
451 %type <predicate> predicate
453 /* conditional modifier */
454 %type <condition> cond_mod
455 %type <integer> condModifiers
457 /* instruction options */
458 %type <options> instoptions instoption_list
459 %type <integer> instoption
462 %type <integer> writemask_x writemask_y writemask_z writemask_w
463 %type <reg> writemask
466 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
467 %type <reg> dstoperandex_ud_typed
468 %type <integer> dstregion
470 %type <integer> saturate relativelocation rellocation
471 %type <reg> relativelocation2
474 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
475 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
476 %type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
477 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
478 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
481 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
482 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
483 %type <integer> subregnum
485 /* immediate values */
488 /* instruction opcodes */
489 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
490 %type <integer> sendop
491 %type <instruction> sendopcode
493 %type <integer> negate abs chansel math_function sharedfunction
498 add_instruction_option(struct options *options, int option)
502 options->access_mode = BRW_ALIGN_1;
505 options->access_mode = BRW_ALIGN_16;
508 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
511 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
512 options->is_compr = true;
515 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
518 options->thread_control |= BRW_THREAD_SWITCH;
521 options->thread_control |= BRW_THREAD_ATOMIC;
524 options->no_dd_check = true;
527 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
530 options->mask_control |= BRW_MASK_DISABLE;
533 options->debug_control = BRW_DEBUG_BREAKPOINT;
536 options->mask_control |= BRW_WE_ALL;
539 options->compaction = true;
542 options->acc_wr_control = true;
545 options->end_of_thread = true;
547 /* TODO : Figure out how to set instruction group and get rid of
551 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
554 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
557 options->qtr_ctrl = 3;
560 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
563 options->qtr_ctrl = BRW_COMPRESSION_NONE;
564 options->nib_ctrl = true;
567 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
570 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
571 options->nib_ctrl = true;
574 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
577 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
578 options->nib_ctrl = true;
581 options->qtr_ctrl = 3;
584 options->qtr_ctrl = 3;
585 options->nib_ctrl = true;
597 instrseq instruction SEMICOLON
598 | instrseq relocatableinstruction SEMICOLON
599 | instruction SEMICOLON
600 | relocatableinstruction SEMICOLON
603 /* Instruction Group */
607 | binaryaccinstruction
615 relocatableinstruction:
622 /* Unary instruction */
624 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
626 i965_asm_set_dst_nr(p, &$6, $8);
627 brw_set_default_access_mode(p, $8.access_mode);
628 i965_asm_unary_instruction($2, p, $6, $7);
629 brw_pop_insn_state(p);
630 i965_asm_set_instruction_options(p, $8);
631 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
634 if (p->devinfo->gen >= 7) {
635 if ($2 != BRW_OPCODE_DIM) {
636 brw_inst_set_flag_reg_nr(p->devinfo,
639 brw_inst_set_flag_subreg_nr(p->devinfo,
645 if ($7.file != BRW_IMMEDIATE_VALUE) {
646 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
649 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
650 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
651 // TODO: set instruction group instead of qtr and nib ctrl
652 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
655 if (p->devinfo->gen >= 7)
656 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
679 /* Binary instruction */
681 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
683 i965_asm_set_dst_nr(p, &$6, $9);
684 brw_set_default_access_mode(p, $9.access_mode);
685 i965_asm_binary_instruction($2, p, $6, $7, $8);
686 i965_asm_set_instruction_options(p, $9);
687 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
690 if (p->devinfo->gen >= 7) {
691 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
693 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
697 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
698 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
699 // TODO: set instruction group instead of qtr and nib ctrl
700 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
703 if (p->devinfo->gen >= 7)
704 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
707 brw_pop_insn_state(p);
728 /* Binary acc instruction */
729 binaryaccinstruction:
730 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
732 i965_asm_set_dst_nr(p, &$6, $9);
733 brw_set_default_access_mode(p, $9.access_mode);
734 i965_asm_binary_instruction($2, p, $6, $7, $8);
735 brw_pop_insn_state(p);
736 i965_asm_set_instruction_options(p, $9);
737 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
740 if (p->devinfo->gen >= 7) {
741 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
742 brw_inst_set_flag_reg_nr(p->devinfo,
745 brw_inst_set_flag_subreg_nr(p->devinfo,
751 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
752 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
753 // TODO: set instruction group instead of qtr and nib ctrl
754 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
757 if (p->devinfo->gen >= 7)
758 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
778 /* Math instruction */
780 predicate MATH saturate math_function execsize dst src srcimm instoptions
782 brw_set_default_access_mode(p, $9.access_mode);
783 gen6_math(p, $6, $4, $7, $8);
784 i965_asm_set_instruction_options(p, $9);
785 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
786 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
787 // TODO: set instruction group instead
788 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
791 if (p->devinfo->gen >= 7)
792 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
795 brw_pop_insn_state(p);
817 /* NOP instruction */
825 /* Ternary operand instruction */
827 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
829 brw_set_default_access_mode(p, $10.access_mode);
830 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
831 brw_pop_insn_state(p);
832 i965_asm_set_instruction_options(p, $10);
833 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
836 if (p->devinfo->gen >= 7) {
837 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
839 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
843 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
844 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
845 // TODO: set instruction group instead of qtr and nib ctrl
846 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
849 if (p->devinfo->gen >= 7)
850 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
863 /* Sync instruction */
865 WAIT execsize src instoptions
867 brw_next_insn(p, $1);
868 i965_asm_set_instruction_options(p, $4);
869 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
870 brw_set_default_access_mode(p, $4.access_mode);
871 struct brw_reg src = brw_notification_reg();
872 brw_set_dest(p, brw_last_inst, src);
873 brw_set_src0(p, brw_last_inst, src);
874 brw_set_src1(p, brw_last_inst, brw_null_reg());
875 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
879 /* Send instruction */
881 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
883 i965_asm_set_instruction_options(p, $8);
884 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
885 brw_set_dest(p, brw_last_inst, $4);
886 brw_set_src0(p, brw_last_inst, $5);
887 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
888 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
890 BRW_REGISTER_TYPE_UD);
891 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
892 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
893 // TODO: set instruction group instead of qtr and nib ctrl
894 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
897 if (p->devinfo->gen >= 7)
898 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
901 brw_pop_insn_state(p);
903 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
905 i965_asm_set_instruction_options(p, $9);
906 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
907 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
908 brw_set_dest(p, brw_last_inst, $5);
909 brw_set_src0(p, brw_last_inst, $6);
910 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
911 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
913 BRW_REGISTER_TYPE_UD);
914 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
915 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
916 // TODO: set instruction group instead of qtr and nib ctrl
917 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
920 if (p->devinfo->gen >= 7)
921 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
924 brw_pop_insn_state(p);
926 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
928 i965_asm_set_instruction_options(p, $9);
929 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
930 brw_set_dest(p, brw_last_inst, $4);
931 brw_set_src0(p, brw_last_inst, $5);
932 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
933 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
934 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
935 // TODO: set instruction group instead of qtr and nib ctrl
936 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
939 if (p->devinfo->gen >= 7)
940 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
943 brw_pop_insn_state(p);
945 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
947 brw_next_insn(p, $2);
948 i965_asm_set_instruction_options(p, $10);
949 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
950 brw_set_dest(p, brw_last_inst, $4);
951 brw_set_src0(p, brw_last_inst, $5);
952 brw_set_src1(p, brw_last_inst, $6);
954 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
955 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
957 brw_inst_set_send_ex_desc(p->devinfo, brw_last_inst, $8);
960 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
961 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
962 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
963 // TODO: set instruction group instead of qtr and nib ctrl
964 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
967 if (p->devinfo->gen >= 7)
968 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
971 brw_pop_insn_state(p);
973 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
975 brw_next_insn(p, $2);
976 i965_asm_set_instruction_options(p, $10);
977 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
978 brw_set_dest(p, brw_last_inst, $4);
979 brw_set_src0(p, brw_last_inst, $5);
980 brw_set_src1(p, brw_last_inst, $6);
982 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
983 brw_inst_set_send_ex_desc(p->devinfo, brw_last_inst, $8);
985 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
986 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
987 // TODO: set instruction group instead of qtr and nib ctrl
988 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
991 if (p->devinfo->gen >= 7)
992 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
995 brw_pop_insn_state(p);
1005 sendop { $$ = brw_next_insn(p, $1); }
1009 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1010 | MATH { $$ = BRW_SFID_MATH; }
1011 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1012 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1013 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1014 | URB { $$ = BRW_SFID_URB; }
1015 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1016 | VME { $$ = BRW_SFID_VME; }
1017 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1018 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1019 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1020 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1021 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1022 | CRE { $$ = HSW_SFID_CRE; }
1023 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1024 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1029 | MINUS LONG { $$ = -$2; }
1032 /* Jump instruction */
1034 predicate JMPI execsize relativelocation2 instoptions
1036 brw_next_insn(p, $2);
1037 i965_asm_set_instruction_options(p, $5);
1038 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1039 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1040 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1041 brw_set_src1(p, brw_last_inst, $4);
1042 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1043 brw_inst_pred_control(p->devinfo,
1045 brw_pop_insn_state(p);
1049 /* branch instruction */
1051 predicate ENDIF execsize relativelocation instoptions
1053 brw_next_insn(p, $2);
1054 i965_asm_set_instruction_options(p, $5);
1055 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1057 if (p->devinfo->gen < 6) {
1058 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1059 BRW_REGISTER_TYPE_D));
1060 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1061 BRW_REGISTER_TYPE_D));
1062 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1063 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1065 } else if (p->devinfo->gen == 6) {
1066 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1067 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1069 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1070 BRW_REGISTER_TYPE_D));
1071 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1072 BRW_REGISTER_TYPE_D));
1073 } else if (p->devinfo->gen == 7) {
1074 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1075 BRW_REGISTER_TYPE_D));
1076 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1077 BRW_REGISTER_TYPE_D));
1078 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1079 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1081 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1084 if (p->devinfo->gen < 6)
1085 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1087 brw_pop_insn_state(p);
1089 | ELSE execsize relativelocation rellocation instoptions
1091 brw_next_insn(p, $1);
1092 i965_asm_set_instruction_options(p, $5);
1093 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1095 if (p->devinfo->gen < 6) {
1096 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1097 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1098 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1099 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1101 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1103 } else if (p->devinfo->gen == 6) {
1104 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1105 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1107 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1108 BRW_REGISTER_TYPE_D));
1109 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1110 BRW_REGISTER_TYPE_D));
1111 } else if (p->devinfo->gen == 7) {
1112 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1113 BRW_REGISTER_TYPE_D));
1114 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1115 BRW_REGISTER_TYPE_D));
1116 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1117 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1118 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1120 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1121 BRW_REGISTER_TYPE_D));
1122 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1123 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1124 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1127 if (!p->single_program_flow && p->devinfo->gen < 6)
1128 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1131 | predicate IF execsize relativelocation rellocation instoptions
1133 brw_next_insn(p, $2);
1134 i965_asm_set_instruction_options(p, $6);
1135 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1137 if (p->devinfo->gen < 6) {
1138 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1139 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1140 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1141 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1143 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1145 } else if (p->devinfo->gen == 6) {
1146 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1147 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1149 brw_set_src0(p, brw_last_inst,
1150 vec1(retype(brw_null_reg(),
1151 BRW_REGISTER_TYPE_D)));
1152 brw_set_src1(p, brw_last_inst,
1153 vec1(retype(brw_null_reg(),
1154 BRW_REGISTER_TYPE_D)));
1155 } else if (p->devinfo->gen == 7) {
1156 brw_set_dest(p, brw_last_inst,
1157 vec1(retype(brw_null_reg(),
1158 BRW_REGISTER_TYPE_D)));
1159 brw_set_src0(p, brw_last_inst,
1160 vec1(retype(brw_null_reg(),
1161 BRW_REGISTER_TYPE_D)));
1162 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1163 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1164 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1166 brw_set_dest(p, brw_last_inst,
1167 vec1(retype(brw_null_reg(),
1168 BRW_REGISTER_TYPE_D)));
1169 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1170 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1171 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1174 if (!p->single_program_flow && p->devinfo->gen < 6)
1175 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1178 brw_pop_insn_state(p);
1180 | predicate IFF execsize relativelocation instoptions
1182 brw_next_insn(p, $2);
1183 i965_asm_set_instruction_options(p, $5);
1184 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1186 if (p->devinfo->gen < 6) {
1187 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1188 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1189 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1191 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1192 } else if (p->devinfo->gen == 6) {
1193 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1194 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1196 brw_set_src0(p, brw_last_inst,
1197 vec1(retype(brw_null_reg(),
1198 BRW_REGISTER_TYPE_D)));
1199 brw_set_src1(p, brw_last_inst,
1200 vec1(retype(brw_null_reg(),
1201 BRW_REGISTER_TYPE_D)));
1202 } else if (p->devinfo->gen == 7) {
1203 brw_set_dest(p, brw_last_inst,
1204 vec1(retype(brw_null_reg(),
1205 BRW_REGISTER_TYPE_D)));
1206 brw_set_src0(p, brw_last_inst,
1207 vec1(retype(brw_null_reg(),
1208 BRW_REGISTER_TYPE_D)));
1209 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1210 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1212 brw_set_dest(p, brw_last_inst,
1213 vec1(retype(brw_null_reg(),
1214 BRW_REGISTER_TYPE_D)));
1215 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1216 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1219 if (!p->single_program_flow && p->devinfo->gen < 6)
1220 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1223 brw_pop_insn_state(p);
1227 /* break instruction */
1229 predicate BREAK execsize relativelocation relativelocation instoptions
1231 brw_next_insn(p, $2);
1232 i965_asm_set_instruction_options(p, $6);
1233 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1235 if (p->devinfo->gen >= 8) {
1236 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1237 BRW_REGISTER_TYPE_D));
1238 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1239 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1240 } else if (p->devinfo->gen >= 6) {
1241 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1242 BRW_REGISTER_TYPE_D));
1243 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1244 BRW_REGISTER_TYPE_D));
1245 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1246 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1247 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1249 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1250 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1251 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1252 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1254 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1258 brw_pop_insn_state(p);
1260 | predicate HALT execsize relativelocation relativelocation instoptions
1262 brw_next_insn(p, $2);
1263 i965_asm_set_instruction_options(p, $6);
1264 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1265 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1266 BRW_REGISTER_TYPE_D));
1268 if (p->devinfo->gen >= 8) {
1269 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1270 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1272 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1273 BRW_REGISTER_TYPE_D));
1274 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1277 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1278 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1279 brw_pop_insn_state(p);
1281 | predicate CONT execsize relativelocation relativelocation instoptions
1283 brw_next_insn(p, $2);
1284 i965_asm_set_instruction_options(p, $6);
1285 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1286 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1288 if (p->devinfo->gen >= 8) {
1289 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1290 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1291 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1293 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1294 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1295 if (p->devinfo->gen >= 6) {
1296 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1297 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1299 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1301 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1306 brw_pop_insn_state(p);
1310 /* loop instruction */
1312 predicate WHILE execsize relativelocation instoptions
1314 brw_next_insn(p, $2);
1315 i965_asm_set_instruction_options(p, $5);
1316 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1318 if (p->devinfo->gen >= 6) {
1319 if (p->devinfo->gen >= 8) {
1320 brw_set_dest(p, brw_last_inst,
1321 retype(brw_null_reg(),
1322 BRW_REGISTER_TYPE_D));
1323 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1324 } else if (p->devinfo->gen == 7) {
1325 brw_set_dest(p, brw_last_inst,
1326 retype(brw_null_reg(),
1327 BRW_REGISTER_TYPE_D));
1328 brw_set_src0(p, brw_last_inst,
1329 retype(brw_null_reg(),
1330 BRW_REGISTER_TYPE_D));
1331 brw_set_src1(p, brw_last_inst,
1333 brw_inst_set_jip(p->devinfo, brw_last_inst,
1336 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1337 brw_inst_set_gen6_jump_count(p->devinfo,
1340 brw_set_src0(p, brw_last_inst,
1341 retype(brw_null_reg(),
1342 BRW_REGISTER_TYPE_D));
1343 brw_set_src1(p, brw_last_inst,
1344 retype(brw_null_reg(),
1345 BRW_REGISTER_TYPE_D));
1348 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1349 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1350 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1351 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1353 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1356 brw_pop_insn_state(p);
1358 | DO execsize instoptions
1360 brw_next_insn(p, $1);
1361 if (p->devinfo->gen < 6) {
1362 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1363 i965_asm_set_instruction_options(p, $3);
1364 brw_set_dest(p, brw_last_inst, brw_null_reg());
1365 brw_set_src0(p, brw_last_inst, brw_null_reg());
1366 brw_set_src1(p, brw_last_inst, brw_null_reg());
1368 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1373 /* Relative location */
1380 INTEGER { $$ = $1; }
1381 | MINUS INTEGER { $$ = -$2; }
1383 | MINUS LONG { $$ = -$2; }
1388 | %empty { $$ = 0; }
1398 /* Destination register */
1405 dstreg dstregion writemask dsttype
1410 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1411 $$.vstride = BRW_VERTICAL_STRIDE_1;
1412 $$.width = BRW_WIDTH_1;
1417 $$.writemask = $3.writemask;
1418 $$.swizzle = BRW_SWIZZLE_NOOP;
1419 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1424 dstoperandex_typed dstregion writemask dsttype
1429 $$.writemask = $3.writemask;
1430 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1432 | dstoperandex_ud_typed
1436 $$.type = BRW_REGISTER_TYPE_UD;
1438 /* BSpec says "When the conditional modifier is present, updates
1439 * to the selected flag register also occur. In this case, the
1440 * register region fields of the ‘null’ operand are valid."
1442 | nullreg dstregion writemask dsttype
1446 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1447 $$.vstride = BRW_VERTICAL_STRIDE_1;
1448 $$.width = BRW_WIDTH_1;
1452 $$.writemask = $3.writemask;
1459 $$.type = BRW_REGISTER_TYPE_UW;
1463 dstoperandex_ud_typed:
1482 $$.address_mode = BRW_ADDRESS_DIRECT;
1487 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1492 $$.address_mode = BRW_ADDRESS_DIRECT;
1497 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1501 /* Source register */
1513 case BRW_REGISTER_TYPE_UD:
1515 $$ = brw_imm_ud(u32);
1517 case BRW_REGISTER_TYPE_D:
1520 case BRW_REGISTER_TYPE_UW:
1521 u32 = $1 | ($1 << 16);
1522 $$ = brw_imm_uw(u32);
1524 case BRW_REGISTER_TYPE_W:
1526 $$ = brw_imm_w(u32);
1528 case BRW_REGISTER_TYPE_F:
1529 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1533 case BRW_REGISTER_TYPE_V:
1536 case BRW_REGISTER_TYPE_UV:
1537 $$ = brw_imm_uv($1);
1539 case BRW_REGISTER_TYPE_VF:
1540 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1543 case BRW_REGISTER_TYPE_Q:
1545 $$ = brw_imm_q(u64);
1547 case BRW_REGISTER_TYPE_UQ:
1549 $$ = brw_imm_uq(u64);
1551 case BRW_REGISTER_TYPE_DF:
1552 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1556 error(&@2, "Unkown immdediate type %s\n",
1557 brw_reg_type_to_letters($2.type));
1563 directgenreg region srctype
1565 $$ = set_direct_src_operand(&$1, $3.type);
1566 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1576 | indirectsrcoperand
1581 | indirectsrcoperand
1586 | indirectsrcoperand
1590 directsrcaccoperand:
1592 | accreg region srctype
1594 $$ = set_direct_src_operand(&$1, $3.type);
1595 $$.vstride = $2.vstride;
1596 $$.width = $2.width;
1597 $$.hstride = $2.hstride;
1602 srcarcoperandex_typed region srctype
1604 $$ = brw_reg($1.file,
1616 | srcarcoperandex_ud_typed
1618 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
1620 | nullreg region srctype
1622 $$ = set_direct_src_operand(&$1, $3.type);
1623 $$.vstride = $2.vstride;
1624 $$.width = $2.width;
1625 $$.hstride = $2.hstride;
1629 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1633 srcarcoperandex_ud_typed:
1640 srcarcoperandex_typed:
1646 negate abs indirectgenreg indirectregion swizzle srctype
1648 $$ = brw_reg($3.file,
1660 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1661 // brw_reg set indirect_offset to 0 so set it to valid value
1662 $$.indirect_offset = $3.indirect_offset;
1675 negate abs directgenreg_list region swizzle srctype
1677 $$ = brw_reg($3.file,
1692 /* Address register */
1696 memset(&$$, '\0', sizeof($$));
1697 $$.subnr = $1.subnr;
1698 $$.indirect_offset = $2;
1703 /* Register files and register numbers */
1705 INTEGER { $$ = $1; }
1710 DOT exp { $$ = $2; }
1711 | %empty %prec SUBREGNUM { $$ = 0; }
1717 memset(&$$, '\0', sizeof($$));
1718 $$.file = BRW_GENERAL_REGISTER_FILE;
1725 GENREGFILE LSQUARE addrparam RSQUARE
1727 memset(&$$, '\0', sizeof($$));
1728 $$.file = BRW_GENERAL_REGISTER_FILE;
1729 $$.subnr = $3.subnr;
1730 $$.indirect_offset = $3.indirect_offset;
1737 $$ = brw_message_reg($1);
1743 MSGREGFILE LSQUARE addrparam RSQUARE
1745 memset(&$$, '\0', sizeof($$));
1746 $$.file = BRW_MESSAGE_REGISTER_FILE;
1747 $$.subnr = $3.subnr;
1748 $$.indirect_offset = $3.indirect_offset;
1756 error(&@1, "Address register number %d"
1757 "out of range\n", $1);
1759 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1762 error(&@2, "Address sub resgister number %d"
1763 "out of range\n", $2);
1765 $$ = brw_address_reg($2);
1773 if (p->devinfo->gen < 8)
1779 error(&@1, "Accumulator register number %d"
1780 " out of range\n", $1);
1782 memset(&$$, '\0', sizeof($$));
1783 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1784 $$.nr = BRW_ARF_ACCUMULATOR;
1792 // SNB = 1 flag reg and IVB+ = 2 flag reg
1793 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1797 error(&@1, "Flag register number %d"
1798 " out of range \n", $1);
1800 error(&@2, "Flag subregister number %d"
1801 " out of range\n", $2);
1803 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1804 $$.nr = BRW_ARF_FLAG | $1;
1813 error(&@1, "Mask register number %d"
1814 " out of range\n", $1);
1816 $$ = brw_mask_reg($2);
1824 error(&@1, "Notification register number %d"
1825 " out of range\n", $1);
1827 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1829 error(&@2, "Notification sub register number %d"
1830 " out of range\n", $2);
1832 $$ = brw_notification_reg();
1841 error(&@1, "State register number %d"
1842 " out of range\n", $1);
1845 error(&@2, "State sub register number %d"
1846 " out of range\n", $2);
1848 $$ = brw_sr0_reg($2);
1854 CONTROLREG subregnum
1857 error(&@1, "Control register number %d"
1858 " out of range\n", $1);
1861 error(&@2, "control sub register number %d"
1862 " out of range\n", $2);
1864 $$ = brw_cr0_reg($2);
1870 IPREG srctype { $$ = brw_ip_reg(); }
1874 NULL_TOKEN { $$ = brw_null_reg(); }
1881 error(&@1, "Thread control register number %d"
1882 " out of range\n", $1);
1885 error(&@2, "Thread control sub register number %d"
1886 " out of range\n", $2);
1894 PERFORMANCEREG subregnum
1897 if (p->devinfo->gen >= 10)
1899 else if (p->devinfo->gen <= 8)
1905 error(&@2, "Performance sub register number %d"
1906 " out of range\n", $2);
1908 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1909 $$.nr = BRW_ARF_TIMESTAMP;
1914 CHANNELENABLEREG subregnum
1917 error(&@1, "Channel enable register number %d"
1918 " out of range\n", $1);
1920 $$ = brw_mask_reg($2);
1924 /* Immediate values */
1930 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1932 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1941 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1942 error(&@2, "Invalid Horizontal stride %d\n", $2);
1956 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1960 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1961 error(&@2, "Invalid VertStride %d\n", $2);
1963 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1965 | LANGLE exp COMMA exp COMMA exp RANGLE
1968 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1969 error(&@2, "Invalid VertStride %d\n", $2);
1971 if ($4 > 16 || !isPowerofTwo($4))
1972 error(&@4, "Invalid width %d\n", $4);
1974 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1975 error(&@6, "Invalid Horizontal stride in"
1976 " region_wh %d\n", $6);
1978 $$ = stride($$, $2, $4, $6);
1980 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1982 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1983 error(&@2, "Invalid VertStride %d\n", $2);
1985 if ($4 > 16 || !isPowerofTwo($4))
1986 error(&@4, "Invalid width %d\n", $4);
1988 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1989 error(&@6, "Invalid Horizontal stride in"
1990 " region_wh %d\n", $6);
1992 $$ = stride($$, $2, $4, $6);
1994 | LANGLE VxH COMMA exp COMMA exp RANGLE
1996 if ($4 > 16 || !isPowerofTwo($4))
1997 error(&@4, "Invalid width %d\n", $4);
1999 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2000 error(&@6, "Invalid Horizontal stride in"
2001 " region_wh %d\n", $6);
2003 $$ = brw_VxH_indirect(0, 0);
2008 LANGLE exp COMMA exp RANGLE
2010 if ($2 > 16 || !isPowerofTwo($2))
2011 error(&@2, "Invalid width %d\n", $2);
2013 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2014 error(&@4, "Invalid Horizontal stride in"
2015 " region_wh %d\n", $4);
2017 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2022 %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2023 | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2024 | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2025 | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2026 | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2027 | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2028 | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2029 | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2030 | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2031 | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2032 | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2033 | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2034 | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2038 srctype { $$ = $1; }
2039 | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2040 | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2041 | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2045 srctype { $$ = $1; }
2051 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2053 | DOT writemask_x writemask_y writemask_z writemask_w
2055 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2061 | X { $$ = 1 << BRW_CHANNEL_X; }
2066 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2071 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2076 | W { $$ = 1 << BRW_CHANNEL_W; }
2082 $$.swizzle = BRW_SWIZZLE_NOOP;
2086 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2088 | DOT chansel chansel chansel chansel
2090 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2101 /* Instruction prediction and modifiers */
2105 brw_push_insn_state(p);
2106 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2107 brw_set_default_flag_reg(p, 0, 0);
2108 brw_set_default_predicate_inverse(p, false);
2110 | LPAREN predstate flagreg predctrl RPAREN
2112 brw_push_insn_state(p);
2113 brw_set_default_predicate_inverse(p, $2);
2114 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2115 brw_set_default_predicate_control(p, $4);
2126 %empty { $$ = BRW_PREDICATE_NORMAL; }
2127 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2128 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2129 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2130 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2145 /* Source Modification */
2156 /* Flag (Conditional) Modifier */
2160 $$.cond_modifier = $1;
2162 $$.flag_subreg_nr = 0;
2164 | condModifiers DOT flagreg
2166 $$.cond_modifier = $1;
2167 $$.flag_reg_nr = $3.nr;
2168 $$.flag_subreg_nr = $3.subnr;
2173 %empty { $$ = BRW_CONDITIONAL_NONE; }
2188 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2189 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2192 /* Execution size */
2194 %empty %prec EMPTYEXECSIZE
2198 | LPAREN exp2 RPAREN
2200 if ($2 > 32 || !isPowerofTwo($2))
2201 error(&@2, "Invalid execution size %d\n", $2);
2207 /* Instruction options */
2211 memset(&$$, 0, sizeof($$));
2213 | LCURLY instoption_list RCURLY
2215 memset(&$$, 0, sizeof($$));
2221 instoption_list COMMA instoption
2223 memset(&$$, 0, sizeof($$));
2225 add_instruction_option(&$$, $3);
2227 | instoption_list instoption
2229 memset(&$$, 0, sizeof($$));
2231 add_instruction_option(&$$, $2);
2235 memset(&$$, 0, sizeof($$));
2240 ALIGN1 { $$ = ALIGN1;}
2241 | ALIGN16 { $$ = ALIGN16; }
2242 | ACCWREN { $$ = ACCWREN; }
2243 | SECHALF { $$ = SECHALF; }
2244 | COMPR { $$ = COMPR; }
2245 | COMPR4 { $$ = COMPR4; }
2246 | BREAKPOINT { $$ = BREAKPOINT; }
2247 | NODDCLR { $$ = NODDCLR; }
2248 | NODDCHK { $$ = NODDCHK; }
2249 | MASK_DISABLE { $$ = MASK_DISABLE; }
2251 | SWITCH { $$ = SWITCH; }
2252 | ATOMIC { $$ = ATOMIC; }
2253 | CMPTCTRL { $$ = CMPTCTRL; }
2254 | WECTRL { $$ = WECTRL; }
2255 | QTR_2Q { $$ = QTR_2Q; }
2256 | QTR_3Q { $$ = QTR_3Q; }
2257 | QTR_4Q { $$ = QTR_4Q; }
2258 | QTR_2H { $$ = QTR_2H; }
2259 | QTR_2N { $$ = QTR_2N; }
2260 | QTR_3N { $$ = QTR_3N; }
2261 | QTR_4N { $$ = QTR_4N; }
2262 | QTR_5N { $$ = QTR_5N; }
2263 | QTR_6N { $$ = QTR_6N; }
2264 | QTR_7N { $$ = QTR_7N; }
2265 | QTR_8N { $$ = QTR_8N; }
2270 extern int yylineno;
2275 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2276 input_filename, yylineno, msg, lex_text());