src/intel/tools/i965_gram.y

   1 %{
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <strings.h>
  29 #include "i965_asm.h"
  30
  31 #define YYLTYPE YYLTYPE
  32 typedef struct YYLTYPE
  33 {
  34         int first_line;
  35         int first_column;
  36         int last_line;
  37         int last_column;
  38 } YYLTYPE;
  39
  40 enum message_level {
  41         WARN,
  42         ERROR,
  43 };
  44
  45 int yydebug = 1;
  46
  47 static void
  48 message(enum message_level level, YYLTYPE *location,
  49         const char *fmt, ...)
  50 {
  51         static const char *level_str[] = { "warning", "error" };
  52         va_list args;
  53
  54         if (location)
  55                 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
  56                         location->first_line,
  57                         location->first_column, level_str[level]);
  58         else
  59                 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
  60
  61         va_start(args, fmt);
  62         vfprintf(stderr, fmt, args);
  63         va_end(args);
  64 }
  65
  66 #define warn(flag, l, fmt, ...)                                  \
  67         do {                                                     \
  68                 if (warning_flags & WARN_ ## flag)               \
  69                         message(WARN, l, fmt, ## __VA_ARGS__);   \
  70         } while (0)
  71
  72 #define error(l, fmt, ...)                                       \
  73         do {                                                     \
  74                 message(ERROR, l, fmt, ## __VA_ARGS__);          \
  75         } while (0)
  76
  77 static bool
  78 isPowerofTwo(unsigned int x)
  79 {
  80         return x && (!(x & (x - 1)));
  81 }
  82
  83 static struct brw_reg
  84 set_direct_src_operand(struct brw_reg *reg, int type)
  85 {
  86         return brw_reg(reg->file,
  87                        reg->nr,
  88                        reg->subnr,
  89                        0,               // negate
  90                        0,               // abs
  91                        type,
  92                        0,               // vstride
  93                        0,               // width
  94                        0,               // hstride
  95                        BRW_SWIZZLE_NOOP,
  96                        WRITEMASK_XYZW);
  97 }
  98
  99 static void
 100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
 101                            struct brw_reg dest, struct brw_reg src0)
 102 {
 103         switch (opcode) {
 104         case BRW_OPCODE_BFREV:
 105                 brw_BFREV(p, dest, src0);
 106                 break;
 107         case BRW_OPCODE_CBIT:
 108                 brw_CBIT(p, dest, src0);
 109                 break;
 110         case BRW_OPCODE_F32TO16:
 111                 brw_F32TO16(p, dest, src0);
 112                 break;
 113         case BRW_OPCODE_F16TO32:
 114                 brw_F16TO32(p, dest, src0);
 115                 break;
 116         case BRW_OPCODE_MOV:
 117                 brw_MOV(p, dest, src0);
 118                 break;
 119         case BRW_OPCODE_FBL:
 120                 brw_FBL(p, dest, src0);
 121                 break;
 122         case BRW_OPCODE_FRC:
 123                 brw_FRC(p, dest, src0);
 124                 break;
 125         case BRW_OPCODE_FBH:
 126                 brw_FBH(p, dest, src0);
 127                 break;
 128         case BRW_OPCODE_NOT:
 129                 brw_NOT(p, dest, src0);
 130                 break;
 131         case BRW_OPCODE_RNDE:
 132                 brw_RNDE(p, dest, src0);
 133                 break;
 134         case BRW_OPCODE_RNDZ:
 135                 brw_RNDZ(p, dest, src0);
 136                 break;
 137         case BRW_OPCODE_RNDD:
 138                 brw_RNDD(p, dest, src0);
 139                 break;
 140         case BRW_OPCODE_LZD:
 141                 brw_LZD(p, dest, src0);
 142                 break;
 143         case BRW_OPCODE_DIM:
 144                 brw_DIM(p, dest, src0);
 145                 break;
 146         case BRW_OPCODE_RNDU:
 147                 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
 148                 break;
 149         default:
 150                 fprintf(stderr, "Unsupported unary opcode\n");
 151         }
 152 }
 153
 154 static void
 155 i965_asm_binary_instruction(int opcode,
 156                             struct brw_codegen *p,
 157                             struct brw_reg dest,
 158                             struct brw_reg src0,
 159                             struct brw_reg src1)
 160 {
 161         switch (opcode) {
 162         case BRW_OPCODE_ADDC:
 163                 brw_ADDC(p, dest, src0, src1);
 164                 break;
 165         case BRW_OPCODE_BFI1:
 166                 brw_BFI1(p, dest, src0, src1);
 167                 break;
 168         case BRW_OPCODE_DP2:
 169                 brw_DP2(p, dest, src0, src1);
 170                 break;
 171         case BRW_OPCODE_DP3:
 172                 brw_DP3(p, dest, src0, src1);
 173                 break;
 174         case BRW_OPCODE_DP4:
 175                 brw_DP4(p, dest, src0, src1);
 176                 break;
 177         case BRW_OPCODE_DPH:
 178                 brw_DPH(p, dest, src0, src1);
 179                 break;
 180         case BRW_OPCODE_LINE:
 181                 brw_LINE(p, dest, src0, src1);
 182                 break;
 183         case BRW_OPCODE_MAC:
 184                 brw_MAC(p, dest, src0, src1);
 185                 break;
 186         case BRW_OPCODE_MACH:
 187                 brw_MACH(p, dest, src0, src1);
 188                 break;
 189         case BRW_OPCODE_PLN:
 190                 brw_PLN(p, dest, src0, src1);
 191                 break;
 192         case BRW_OPCODE_ROL:
 193                 brw_ROL(p, dest, src0, src1);
 194                 break;
 195         case BRW_OPCODE_ROR:
 196                 brw_ROR(p, dest, src0, src1);
 197                 break;
 198         case BRW_OPCODE_SAD2:
 199                 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
 200                 break;
 201         case BRW_OPCODE_SADA2:
 202                 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
 203                 break;
 204         case BRW_OPCODE_SUBB:
 205                 brw_SUBB(p, dest, src0, src1);
 206                 break;
 207         case BRW_OPCODE_ADD:
 208                 brw_ADD(p, dest, src0, src1);
 209                 break;
 210         case BRW_OPCODE_CMP:
 211                 /* Third parameter is conditional modifier
 212                  * which gets updated later
 213                  */
 214                 brw_CMP(p, dest, 0, src0, src1);
 215                 break;
 216         case BRW_OPCODE_AND:
 217                 brw_AND(p, dest, src0, src1);
 218                 break;
 219         case BRW_OPCODE_ASR:
 220                 brw_ASR(p, dest, src0, src1);
 221                 break;
 222         case BRW_OPCODE_AVG:
 223                 brw_AVG(p, dest, src0, src1);
 224                 break;
 225         case BRW_OPCODE_OR:
 226                 brw_OR(p, dest, src0, src1);
 227                 break;
 228         case BRW_OPCODE_SEL:
 229                 brw_SEL(p, dest, src0, src1);
 230                 break;
 231         case BRW_OPCODE_SHL:
 232                 brw_SHL(p, dest, src0, src1);
 233                 break;
 234         case BRW_OPCODE_SHR:
 235                 brw_SHR(p, dest, src0, src1);
 236                 break;
 237         case BRW_OPCODE_XOR:
 238                 brw_XOR(p, dest, src0, src1);
 239                 break;
 240         case BRW_OPCODE_MUL:
 241                 brw_MUL(p, dest, src0, src1);
 242                 break;
 243         default:
 244                 fprintf(stderr, "Unsupported binary opcode\n");
 245         }
 246 }
 247
 248 static void
 249 i965_asm_ternary_instruction(int opcode,
 250                              struct brw_codegen *p,
 251                              struct brw_reg dest,
 252                              struct brw_reg src0,
 253                              struct brw_reg src1,
 254                              struct brw_reg src2)
 255 {
 256         switch (opcode) {
 257         case BRW_OPCODE_MAD:
 258                 brw_MAD(p, dest, src0, src1, src2);
 259                 break;
 260         case BRW_OPCODE_CSEL:
 261                 brw_CSEL(p, dest, src0, src1, src2);
 262                 break;
 263         case BRW_OPCODE_LRP:
 264                 brw_LRP(p, dest, src0, src1, src2);
 265                 break;
 266         case BRW_OPCODE_BFE:
 267                 brw_BFE(p, dest, src0, src1, src2);
 268                 break;
 269         case BRW_OPCODE_BFI2:
 270                 brw_BFI2(p, dest, src0, src1, src2);
 271                 break;
 272         default:
 273                 fprintf(stderr, "Unsupported ternary opcode\n");
 274         }
 275 }
 276
 277 static void
 278 i965_asm_set_instruction_options(struct brw_codegen *p,
 279                                  struct options options)
 280 {
 281         brw_inst_set_access_mode(p->devinfo, brw_last_inst,
 282                                  options.access_mode);
 283         brw_inst_set_mask_control(p->devinfo, brw_last_inst,
 284                                   options.mask_control);
 285         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
 286                                     options.thread_control);
 287         brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
 288                                  options.no_dd_check);
 289         brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
 290                                  options.no_dd_clear);
 291         brw_inst_set_debug_control(p->devinfo, brw_last_inst,
 292                                    options.debug_control);
 293         if (p->devinfo->gen >= 6)
 294                 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
 295                                             options.acc_wr_control);
 296         brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
 297                                   options.compaction);
 298 }
 299
 300 static void
 301 i965_asm_set_dst_nr(struct brw_codegen *p,
 302                     struct brw_reg *reg,
 303                     struct options options)
 304 {
 305         if (p->devinfo->gen <= 6) {
 306                 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
 307                     options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
 308                     !options.is_compr)
 309                         reg->nr |= BRW_MRF_COMPR4;
 310         }
 311 }
 312
 313 %}
 314
 315 %locations
 316
 317 %start ROOT
 318
 319 %union {
 320         double number;
 321         int integer;
 322         unsigned long long int llint;
 323         struct brw_reg reg;
 324         struct brw_codegen *program;
 325         struct predicate predicate;
 326         struct condition condition;
 327         struct options options;
 328         brw_inst *instruction;
 329 }
 330
 331 %token ABS
 332 %token COLON
 333 %token COMMA
 334 %token DOT
 335 %token LANGLE RANGLE
 336 %token LCURLY RCURLY
 337 %token LPAREN RPAREN
 338 %token LSQUARE RSQUARE
 339 %token PLUS MINUS
 340 %token SEMICOLON
 341
 342 /* datatypes */
 343 %token <integer> TYPE_B TYPE_UB
 344 %token <integer> TYPE_W TYPE_UW
 345 %token <integer> TYPE_D TYPE_UD
 346 %token <integer> TYPE_Q TYPE_UQ
 347 %token <integer> TYPE_V TYPE_UV
 348 %token <integer> TYPE_F TYPE_HF
 349 %token <integer> TYPE_DF TYPE_NF
 350 %token <integer> TYPE_VF
 351
 352 /* opcodes */
 353 %token <integer> ADD ADD3 ADDC AND ASR AVG
 354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
 355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
 356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
 357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
 358 %token <integer> GOTO
 359 %token <integer> HALT
 360 %token <integer> IF IFF ILLEGAL
 361 %token <integer> JMPI JOIN
 362 %token <integer> LINE LRP LZD
 363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
 364 %token <integer> NENOP NOP NOT
 365 %token <integer> OR
 366 %token <integer> PLN POP PUSH
 367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
 368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
 369 %token <integer> WAIT WHILE
 370 %token <integer> XOR
 371
 372 /* extended math functions */
 373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
 374 %token <integer> RSQRTM SIN SINCOS SQRT
 375
 376 /* shared functions for send */
 377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
 378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
 379
 380 /* Conditional modifiers */
 381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
 382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
 383
 384 /* register Access Modes */
 385 %token ALIGN1 ALIGN16
 386
 387 /* accumulator write control */
 388 %token ACCWREN
 389
 390 /* compaction control */
 391 %token CMPTCTRL
 392
 393 /* compression control */
 394 %token COMPR COMPR4 SECHALF
 395
 396 /* mask control (WeCtrl) */
 397 %token WECTRL
 398
 399 /* debug control */
 400 %token BREAKPOINT
 401
 402 /* dependency control */
 403 %token NODDCLR NODDCHK
 404
 405 /* end of thread */
 406 %token EOT
 407
 408 /* mask control */
 409 %token MASK_DISABLE;
 410
 411 /* predicate control */
 412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
 413 %token <integer> ANY32H ALL32H
 414
 415 /* round instructions */
 416 %token <integer> ROUND_INCREMENT
 417
 418 /* staturation */
 419 %token SATURATE
 420
 421 /* thread control */
 422 %token ATOMIC SWITCH
 423
 424 /* quater control */
 425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
 426 %token QTR_6N QTR_7N QTR_8N
 427
 428 /* channels */
 429 %token <integer> X Y Z W
 430
 431 /* reg files */
 432 %token GENREGFILE MSGREGFILE
 433
 434 /* vertical stride in register region */
 435 %token VxH
 436
 437 /* register type */
 438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
 439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
 440 %token <integer> MASKREG
 441
 442 %token <integer> INTEGER
 443 %token <llint> LONG
 444 %token NULL_TOKEN
 445
 446 %precedence SUBREGNUM
 447 %left PLUS MINUS
 448 %precedence DOT
 449 %precedence EMPTYEXECSIZE
 450 %precedence LPAREN
 451
 452 %type <integer> execsize simple_int exp
 453 %type <llint> exp2
 454
 455 /* predicate control */
 456 %type <integer> predctrl predstate
 457 %type <predicate> predicate
 458
 459 /* conditional modifier */
 460 %type <condition> cond_mod
 461 %type <integer> condModifiers
 462
 463 /* instruction options  */
 464 %type <options> instoptions instoption_list
 465 %type <integer> instoption
 466
 467 /* writemask */
 468 %type <integer> writemask_x writemask_y writemask_z writemask_w
 469 %type <reg> writemask
 470
 471 /* dst operand */
 472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
 473 %type <reg> dstoperandex_ud_typed
 474 %type <integer> dstregion
 475
 476 %type <integer> saturate relativelocation rellocation
 477 %type <reg> relativelocation2
 478
 479 /* src operand */
 480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
 481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
 482 %type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
 483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
 484 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
 485
 486 /* registers */
 487 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
 488 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
 489 %type <integer> subregnum
 490
 491 /* immediate values */
 492 %type <llint> immval
 493
 494 /* instruction opcodes */
 495 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
 496 %type <integer> sendop
 497 %type <instruction> sendopcode
 498
 499 %type <integer> negate abs chansel math_function sharedfunction
 500
 501 %code {
 502
 503 static void
 504 add_instruction_option(struct options *options, int option)
 505 {
 506         switch (option) {
 507         case ALIGN1:
 508                 options->access_mode = BRW_ALIGN_1;
 509                 break;
 510         case ALIGN16:
 511                 options->access_mode = BRW_ALIGN_16;
 512                 break;
 513         case SECHALF:
 514                 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
 515                 break;
 516         case COMPR:
 517                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 518                 options->is_compr = true;
 519                 break;
 520         case COMPR4:
 521                 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
 522                 break;
 523         case SWITCH:
 524                 options->thread_control |= BRW_THREAD_SWITCH;
 525                 break;
 526         case ATOMIC:
 527                 options->thread_control |= BRW_THREAD_ATOMIC;
 528                 break;
 529         case NODDCHK:
 530                 options->no_dd_check = true;
 531                 break;
 532         case NODDCLR:
 533                 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
 534                 break;
 535         case MASK_DISABLE:
 536                 options->mask_control |= BRW_MASK_DISABLE;
 537                 break;
 538         case BREAKPOINT:
 539                 options->debug_control = BRW_DEBUG_BREAKPOINT;
 540                 break;
 541         case WECTRL:
 542                 options->mask_control |= BRW_WE_ALL;
 543                 break;
 544         case CMPTCTRL:
 545                 options->compaction = true;
 546                 break;
 547         case ACCWREN:
 548                 options->acc_wr_control = true;
 549                 break;
 550         case EOT:
 551                 options->end_of_thread = true;
 552                 break;
 553         /* TODO : Figure out how to set instruction group and get rid of
 554          * code below
 555          */
 556         case QTR_2Q:
 557                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 558                 break;
 559         case QTR_3Q:
 560                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 561                 break;
 562         case QTR_4Q:
 563                 options->qtr_ctrl = 3;
 564                 break;
 565         case QTR_2H:
 566                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 567                 break;
 568         case QTR_2N:
 569                 options->qtr_ctrl = BRW_COMPRESSION_NONE;
 570                 options->nib_ctrl = true;
 571                 break;
 572         case QTR_3N:
 573                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 574                 break;
 575         case QTR_4N:
 576                 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
 577                 options->nib_ctrl = true;
 578                 break;
 579         case QTR_5N:
 580                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 581                 break;
 582         case QTR_6N:
 583                 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
 584                 options->nib_ctrl = true;
 585                 break;
 586         case QTR_7N:
 587                 options->qtr_ctrl = 3;
 588                 break;
 589         case QTR_8N:
 590                 options->qtr_ctrl = 3;
 591                 options->nib_ctrl = true;
 592                 break;
 593         }
 594 }
 595 }
 596 %%
 597
 598 ROOT:
 599         instrseq
 600         ;
 601
 602 instrseq:
 603         instrseq instruction SEMICOLON
 604         | instrseq relocatableinstruction SEMICOLON
 605         | instruction SEMICOLON
 606         | relocatableinstruction SEMICOLON
 607         ;
 608
 609 /* Instruction Group */
 610 instruction:
 611         unaryinstruction
 612         | binaryinstruction
 613         | binaryaccinstruction
 614         | mathinstruction
 615         | nopinstruction
 616         | syncinstruction
 617         | ternaryinstruction
 618         | sendinstruction
 619         ;
 620
 621 relocatableinstruction:
 622         jumpinstruction
 623         | branchinstruction
 624         | breakinstruction
 625         | loopinstruction
 626         ;
 627
 628 /* Unary instruction */
 629 unaryinstruction:
 630         predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
 631         {
 632                 i965_asm_set_dst_nr(p, &$6, $8);
 633                 brw_set_default_access_mode(p, $8.access_mode);
 634                 i965_asm_unary_instruction($2, p, $6, $7);
 635                 brw_pop_insn_state(p);
 636                 i965_asm_set_instruction_options(p, $8);
 637                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 638                                            $4.cond_modifier);
 639
 640                 if (p->devinfo->gen >= 7) {
 641                         if ($2 != BRW_OPCODE_DIM) {
 642                                 brw_inst_set_flag_reg_nr(p->devinfo,
 643                                                          brw_last_inst,
 644                                                          $4.flag_reg_nr);
 645                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 646                                                             brw_last_inst,
 647                                                             $4.flag_subreg_nr);
 648                         }
 649                 }
 650
 651                 if ($7.file != BRW_IMMEDIATE_VALUE) {
 652                         brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
 653                                                   $7.vstride);
 654                 }
 655                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 656                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 657                 // TODO: set instruction group instead of qtr and nib ctrl
 658                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 659                                          $8.qtr_ctrl);
 660
 661                 if (p->devinfo->gen >= 7)
 662                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 663                                                  $8.nib_ctrl);
 664         }
 665         ;
 666
 667 unaryopcodes:
 668         BFREV
 669         | CBIT
 670         | DIM
 671         | F16TO32
 672         | F32TO16
 673         | FBH
 674         | FBL
 675         | FRC
 676         | LZD
 677         | MOV
 678         | NOT
 679         | RNDD
 680         | RNDE
 681         | RNDU
 682         | RNDZ
 683         ;
 684
 685 /* Binary instruction */
 686 binaryinstruction:
 687         predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
 688         {
 689                 i965_asm_set_dst_nr(p, &$6, $9);
 690                 brw_set_default_access_mode(p, $9.access_mode);
 691                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 692                 i965_asm_set_instruction_options(p, $9);
 693                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 694                                            $4.cond_modifier);
 695
 696                 if (p->devinfo->gen >= 7) {
 697                         brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
 698                                                  $4.flag_reg_nr);
 699                         brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
 700                                                     $4.flag_subreg_nr);
 701                 }
 702
 703                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 704                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 705                 // TODO: set instruction group instead of qtr and nib ctrl
 706                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 707                                          $9.qtr_ctrl);
 708
 709                 if (p->devinfo->gen >= 7)
 710                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 711                                                  $9.nib_ctrl);
 712
 713                 brw_pop_insn_state(p);
 714         }
 715         ;
 716
 717 binaryopcodes:
 718         ADDC
 719         | BFI1
 720         | DP2
 721         | DP3
 722         | DP4
 723         | DPH
 724         | LINE
 725         | MAC
 726         | MACH
 727         | MUL
 728         | PLN
 729         | ROL
 730         | ROR
 731         | SAD2
 732         | SADA2
 733         | SUBB
 734         ;
 735
 736 /* Binary acc instruction */
 737 binaryaccinstruction:
 738         predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
 739         {
 740                 i965_asm_set_dst_nr(p, &$6, $9);
 741                 brw_set_default_access_mode(p, $9.access_mode);
 742                 i965_asm_binary_instruction($2, p, $6, $7, $8);
 743                 brw_pop_insn_state(p);
 744                 i965_asm_set_instruction_options(p, $9);
 745                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 746                                            $4.cond_modifier);
 747
 748                 if (p->devinfo->gen >= 7) {
 749                         if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
 750                                 brw_inst_set_flag_reg_nr(p->devinfo,
 751                                                          brw_last_inst,
 752                                                          $4.flag_reg_nr);
 753                                 brw_inst_set_flag_subreg_nr(p->devinfo,
 754                                                             brw_last_inst,
 755                                                             $4.flag_subreg_nr);
 756                         }
 757                 }
 758
 759                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 760                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 761                 // TODO: set instruction group instead of qtr and nib ctrl
 762                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 763                                          $9.qtr_ctrl);
 764
 765                 if (p->devinfo->gen >= 7)
 766                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 767                                                  $9.nib_ctrl);
 768
 769         }
 770         ;
 771
 772 binaryaccopcodes:
 773         ADD
 774         | AND
 775         | ASR
 776         | AVG
 777         | CMP
 778         | CMPN
 779         | OR
 780         | SEL
 781         | SHL
 782         | SHR
 783         | XOR
 784         ;
 785
 786 /* Math instruction */
 787 mathinstruction:
 788         predicate MATH saturate math_function execsize dst src srcimm instoptions
 789         {
 790                 brw_set_default_access_mode(p, $9.access_mode);
 791                 gen6_math(p, $6, $4, $7, $8);
 792                 i965_asm_set_instruction_options(p, $9);
 793                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 794                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 795                 // TODO: set instruction group instead
 796                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 797                                          $9.qtr_ctrl);
 798
 799                 if (p->devinfo->gen >= 7)
 800                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 801                                                  $9.nib_ctrl);
 802
 803                 brw_pop_insn_state(p);
 804         }
 805         ;
 806
 807 math_function:
 808         COS
 809         | EXP
 810         | FDIV
 811         | INV
 812         | INVM
 813         | INTDIV
 814         | INTDIVMOD
 815         | INTMOD
 816         | LOG
 817         | POW
 818         | RSQ
 819         | RSQRTM
 820         | SIN
 821         | SQRT
 822         | SINCOS
 823         ;
 824
 825 /* NOP instruction */
 826 nopinstruction:
 827         NOP
 828         {
 829                 brw_NOP(p);
 830         }
 831         ;
 832
 833 /* Ternary operand instruction */
 834 ternaryinstruction:
 835         predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
 836         {
 837                 brw_set_default_access_mode(p, $10.access_mode);
 838                 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
 839                 brw_pop_insn_state(p);
 840                 i965_asm_set_instruction_options(p, $10);
 841                 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
 842                                            $4.cond_modifier);
 843
 844                 if (p->devinfo->gen >= 7) {
 845                         brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
 846                                                  $4.flag_reg_nr);
 847                         brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
 848                                                     $4.flag_subreg_nr);
 849                 }
 850
 851                 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
 852                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
 853                 // TODO: set instruction group instead of qtr and nib ctrl
 854                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 855                                          $10.qtr_ctrl);
 856
 857                 if (p->devinfo->gen >= 7)
 858                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 859                                                  $10.nib_ctrl);
 860         }
 861         ;
 862
 863 ternaryopcodes:
 864         CSEL
 865         | BFE
 866         | BFI2
 867         | LRP
 868         | MAD
 869         ;
 870
 871 /* Sync instruction */
 872 syncinstruction:
 873         WAIT execsize src instoptions
 874         {
 875                 brw_next_insn(p, $1);
 876                 i965_asm_set_instruction_options(p, $4);
 877                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 878                 brw_set_default_access_mode(p, $4.access_mode);
 879                 struct brw_reg src = brw_notification_reg();
 880                 brw_set_dest(p, brw_last_inst, src);
 881                 brw_set_src0(p, brw_last_inst, src);
 882                 brw_set_src1(p, brw_last_inst, brw_null_reg());
 883                 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
 884         }
 885         ;
 886
 887 /* Send instruction */
 888 sendinstruction:
 889         predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
 890         {
 891                 i965_asm_set_instruction_options(p, $8);
 892                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 893                 brw_set_dest(p, brw_last_inst, $4);
 894                 brw_set_src0(p, brw_last_inst, $5);
 895                 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
 896                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 897                                             BRW_IMMEDIATE_VALUE,
 898                                             BRW_REGISTER_TYPE_UD);
 899                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
 900                 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
 901                 // TODO: set instruction group instead of qtr and nib ctrl
 902                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 903                                          $8.qtr_ctrl);
 904
 905                 if (p->devinfo->gen >= 7)
 906                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 907                                                  $8.nib_ctrl);
 908
 909                 brw_pop_insn_state(p);
 910         }
 911         | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
 912         {
 913                 i965_asm_set_instruction_options(p, $9);
 914                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 915                 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
 916                 brw_set_dest(p, brw_last_inst, $5);
 917                 brw_set_src0(p, brw_last_inst, $6);
 918                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 919                 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
 920                                             BRW_IMMEDIATE_VALUE,
 921                                             BRW_REGISTER_TYPE_UD);
 922                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 923                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 924                 // TODO: set instruction group instead of qtr and nib ctrl
 925                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 926                                          $9.qtr_ctrl);
 927
 928                 if (p->devinfo->gen >= 7)
 929                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 930                                                  $9.nib_ctrl);
 931
 932                 brw_pop_insn_state(p);
 933         }
 934         | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
 935         {
 936                 i965_asm_set_instruction_options(p, $9);
 937                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 938                 brw_set_dest(p, brw_last_inst, $4);
 939                 brw_set_src0(p, brw_last_inst, $5);
 940                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 941                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
 942                 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
 943                 // TODO: set instruction group instead of qtr and nib ctrl
 944                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 945                                          $9.qtr_ctrl);
 946
 947                 if (p->devinfo->gen >= 7)
 948                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 949                                                  $9.nib_ctrl);
 950
 951                 brw_pop_insn_state(p);
 952         }
 953         | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
 954         {
 955                 brw_next_insn(p, $2);
 956                 i965_asm_set_instruction_options(p, $10);
 957                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 958                 brw_set_dest(p, brw_last_inst, $4);
 959                 brw_set_src0(p, brw_last_inst, $5);
 960                 brw_set_src1(p, brw_last_inst, $6);
 961
 962                 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
 963                         brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
 964                 } else {
 965                         brw_inst_set_send_ex_desc(p->devinfo, brw_last_inst, $8);
 966                 }
 967
 968                 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
 969                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
 970                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
 971                 // TODO: set instruction group instead of qtr and nib ctrl
 972                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 973                                          $10.qtr_ctrl);
 974
 975                 if (p->devinfo->gen >= 7)
 976                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
 977                                                  $10.nib_ctrl);
 978
 979                 brw_pop_insn_state(p);
 980         }
 981         | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
 982         {
 983                 brw_next_insn(p, $2);
 984                 i965_asm_set_instruction_options(p, $10);
 985                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 986                 brw_set_dest(p, brw_last_inst, $4);
 987                 brw_set_src0(p, brw_last_inst, $5);
 988                 brw_set_src1(p, brw_last_inst, $6);
 989
 990                 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
 991                 brw_inst_set_send_ex_desc(p->devinfo, brw_last_inst, $8);
 992
 993                 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
 994                 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
 995                 // TODO: set instruction group instead of qtr and nib ctrl
 996                 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
 997                                          $10.qtr_ctrl);
 998
 999                 if (p->devinfo->gen >= 7)
1000                         brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1001                                                  $10.nib_ctrl);
1002
1003                 brw_pop_insn_state(p);
1004         }
1005         ;
1006
1007 sendop:
1008         SEND
1009         | SENDC
1010         ;
1011
1012 sendopcode:
1013         sendop   { $$ = brw_next_insn(p, $1); }
1014         ;
1015
1016 sharedfunction:
1017         NULL_TOKEN              { $$ = BRW_SFID_NULL; }
1018         | MATH                  { $$ = BRW_SFID_MATH; }
1019         | GATEWAY               { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1020         | READ                  { $$ = BRW_SFID_DATAPORT_READ; }
1021         | WRITE                 { $$ = BRW_SFID_DATAPORT_WRITE; }
1022         | URB                   { $$ = BRW_SFID_URB; }
1023         | THREAD_SPAWNER        { $$ = BRW_SFID_THREAD_SPAWNER; }
1024         | VME                   { $$ = BRW_SFID_VME; }
1025         | RENDER                { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1026         | CONST                 { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1027         | DATA                  { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1028         | PIXEL_INTERP          { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1029         | DP_DATA_1             { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1030         | CRE                   { $$ = HSW_SFID_CRE; }
1031         | SAMPLER               { $$ = BRW_SFID_SAMPLER; }
1032         | DP_SAMPLER            { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1033         ;
1034
1035 exp2:
1036         LONG            { $$ = $1; }
1037         | MINUS LONG    { $$ = -$2; }
1038         ;
1039
1040 /* Jump instruction */
1041 jumpinstruction:
1042         predicate JMPI execsize relativelocation2 instoptions
1043         {
1044                 brw_next_insn(p, $2);
1045                 i965_asm_set_instruction_options(p, $5);
1046                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1047                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1048                 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1049                 brw_set_src1(p, brw_last_inst, $4);
1050                 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1051                                           brw_inst_pred_control(p->devinfo,
1052                                                                 brw_last_inst));
1053                 brw_pop_insn_state(p);
1054         }
1055         ;
1056
1057 /* branch instruction */
1058 branchinstruction:
1059         predicate ENDIF execsize relativelocation instoptions
1060         {
1061                 brw_next_insn(p, $2);
1062                 i965_asm_set_instruction_options(p, $5);
1063                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1064
1065                 if (p->devinfo->gen < 6) {
1066                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1067                                      BRW_REGISTER_TYPE_D));
1068                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1069                                      BRW_REGISTER_TYPE_D));
1070                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1071                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1072                                                     $4);
1073                 } else if (p->devinfo->gen == 6) {
1074                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1075                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1076                                                      $4);
1077                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1078                                      BRW_REGISTER_TYPE_D));
1079                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1080                                      BRW_REGISTER_TYPE_D));
1081                 } else if (p->devinfo->gen == 7) {
1082                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1083                                      BRW_REGISTER_TYPE_D));
1084                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1085                                      BRW_REGISTER_TYPE_D));
1086                         brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1087                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1088                 } else {
1089                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1090                 }
1091
1092                 if (p->devinfo->gen < 6)
1093                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1094                                                     BRW_THREAD_SWITCH);
1095                 brw_pop_insn_state(p);
1096         }
1097         | ELSE execsize relativelocation rellocation instoptions
1098         {
1099                 brw_next_insn(p, $1);
1100                 i965_asm_set_instruction_options(p, $5);
1101                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1102
1103                 if (p->devinfo->gen < 6) {
1104                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1105                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1106                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1107                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1108                                                      $3);
1109                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1110                                                     $4);
1111                 } else if (p->devinfo->gen == 6) {
1112                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1113                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1114                                                      $3);
1115                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1116                                      BRW_REGISTER_TYPE_D));
1117                         brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1118                                      BRW_REGISTER_TYPE_D));
1119                 } else if (p->devinfo->gen == 7) {
1120                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1121                                      BRW_REGISTER_TYPE_D));
1122                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1123                                      BRW_REGISTER_TYPE_D));
1124                         brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1125                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1126                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1127                 } else {
1128                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1129                                      BRW_REGISTER_TYPE_D));
1130                         brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1131                         brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1132                         brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1133                 }
1134
1135                 if (!p->single_program_flow && p->devinfo->gen < 6)
1136                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1137                                                     BRW_THREAD_SWITCH);
1138         }
1139         | predicate IF execsize relativelocation rellocation instoptions
1140         {
1141                 brw_next_insn(p, $2);
1142                 i965_asm_set_instruction_options(p, $6);
1143                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1144
1145                 if (p->devinfo->gen < 6) {
1146                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1147                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1148                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1149                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1150                                                      $4);
1151                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1152                                                     $5);
1153                 } else if (p->devinfo->gen == 6) {
1154                         brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1155                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1156                                                      $4);
1157                         brw_set_src0(p, brw_last_inst,
1158                                      vec1(retype(brw_null_reg(),
1159                                      BRW_REGISTER_TYPE_D)));
1160                         brw_set_src1(p, brw_last_inst,
1161                                      vec1(retype(brw_null_reg(),
1162                                      BRW_REGISTER_TYPE_D)));
1163                 } else if (p->devinfo->gen == 7) {
1164                         brw_set_dest(p, brw_last_inst,
1165                                      vec1(retype(brw_null_reg(),
1166                                      BRW_REGISTER_TYPE_D)));
1167                         brw_set_src0(p, brw_last_inst,
1168                                      vec1(retype(brw_null_reg(),
1169                                      BRW_REGISTER_TYPE_D)));
1170                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1171                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1172                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1173                 } else {
1174                         brw_set_dest(p, brw_last_inst,
1175                                      vec1(retype(brw_null_reg(),
1176                                      BRW_REGISTER_TYPE_D)));
1177                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1178                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1179                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1180                 }
1181
1182                 if (!p->single_program_flow && p->devinfo->gen < 6)
1183                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1184                                                     BRW_THREAD_SWITCH);
1185
1186                 brw_pop_insn_state(p);
1187         }
1188         | predicate IFF execsize relativelocation instoptions
1189         {
1190                 brw_next_insn(p, $2);
1191                 i965_asm_set_instruction_options(p, $5);
1192                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1193
1194                 if (p->devinfo->gen < 6) {
1195                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1196                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1197                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1198                                                      $4);
1199                         brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1200                 } else if (p->devinfo->gen == 6) {
1201                         brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1202                         brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1203                                                      $4);
1204                         brw_set_src0(p, brw_last_inst,
1205                                      vec1(retype(brw_null_reg(),
1206                                      BRW_REGISTER_TYPE_D)));
1207                         brw_set_src1(p, brw_last_inst,
1208                                      vec1(retype(brw_null_reg(),
1209                                      BRW_REGISTER_TYPE_D)));
1210                 } else if (p->devinfo->gen == 7) {
1211                         brw_set_dest(p, brw_last_inst,
1212                                      vec1(retype(brw_null_reg(),
1213                                      BRW_REGISTER_TYPE_D)));
1214                         brw_set_src0(p, brw_last_inst,
1215                                      vec1(retype(brw_null_reg(),
1216                                      BRW_REGISTER_TYPE_D)));
1217                         brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1218                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1219                 } else {
1220                         brw_set_dest(p, brw_last_inst,
1221                                      vec1(retype(brw_null_reg(),
1222                                      BRW_REGISTER_TYPE_D)));
1223                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1224                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1225                 }
1226
1227                 if (!p->single_program_flow && p->devinfo->gen < 6)
1228                         brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1229                                                     BRW_THREAD_SWITCH);
1230
1231                 brw_pop_insn_state(p);
1232         }
1233         ;
1234
1235 /* break instruction */
1236 breakinstruction:
1237         predicate BREAK execsize relativelocation relativelocation instoptions
1238         {
1239                 brw_next_insn(p, $2);
1240                 i965_asm_set_instruction_options(p, $6);
1241                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1242
1243                 if (p->devinfo->gen >= 8) {
1244                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1245                                      BRW_REGISTER_TYPE_D));
1246                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1247                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1248                 } else if (p->devinfo->gen >= 6) {
1249                         brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1250                                      BRW_REGISTER_TYPE_D));
1251                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1252                                      BRW_REGISTER_TYPE_D));
1253                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1254                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1255                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1256                 } else {
1257                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1258                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1259                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1260                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1261                                                      $4);
1262                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1263                                                     $5);
1264                 }
1265
1266                 brw_pop_insn_state(p);
1267         }
1268         | predicate HALT execsize relativelocation relativelocation instoptions
1269         {
1270                 brw_next_insn(p, $2);
1271                 i965_asm_set_instruction_options(p, $6);
1272                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1273                 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1274                              BRW_REGISTER_TYPE_D));
1275
1276                 if (p->devinfo->gen >= 8) {
1277                         brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1278                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1279                 } else {
1280                         brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1281                                      BRW_REGISTER_TYPE_D));
1282                         brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1283                 }
1284
1285                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1286                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1287                 brw_pop_insn_state(p);
1288         }
1289         | predicate CONT execsize relativelocation relativelocation instoptions
1290         {
1291                 brw_next_insn(p, $2);
1292                 i965_asm_set_instruction_options(p, $6);
1293                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1294                 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1295
1296                 if (p->devinfo->gen >= 8) {
1297                         brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1298                         brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1299                         brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1300                 } else {
1301                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1302                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1303                         if (p->devinfo->gen >= 6) {
1304                                 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1305                                 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1306                         } else {
1307                                 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1308                                                              $4);
1309                                 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1310                                                             $5);
1311                         }
1312                 }
1313
1314                 brw_pop_insn_state(p);
1315         }
1316         ;
1317
1318 /* loop instruction */
1319 loopinstruction:
1320         predicate WHILE execsize relativelocation instoptions
1321         {
1322                 brw_next_insn(p, $2);
1323                 i965_asm_set_instruction_options(p, $5);
1324                 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1325
1326                 if (p->devinfo->gen >= 6) {
1327                         if (p->devinfo->gen >= 8) {
1328                                 brw_set_dest(p, brw_last_inst,
1329                                              retype(brw_null_reg(),
1330                                              BRW_REGISTER_TYPE_D));
1331                                 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1332                         } else if (p->devinfo->gen == 7) {
1333                                 brw_set_dest(p, brw_last_inst,
1334                                              retype(brw_null_reg(),
1335                                              BRW_REGISTER_TYPE_D));
1336                                 brw_set_src0(p, brw_last_inst,
1337                                              retype(brw_null_reg(),
1338                                              BRW_REGISTER_TYPE_D));
1339                                 brw_set_src1(p, brw_last_inst,
1340                                              brw_imm_w(0x0));
1341                                 brw_inst_set_jip(p->devinfo, brw_last_inst,
1342                                                  $4);
1343                         } else {
1344                                 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1345                                 brw_inst_set_gen6_jump_count(p->devinfo,
1346                                                              brw_last_inst,
1347                                                              $4);
1348                                 brw_set_src0(p, brw_last_inst,
1349                                              retype(brw_null_reg(),
1350                                              BRW_REGISTER_TYPE_D));
1351                                 brw_set_src1(p, brw_last_inst,
1352                                              retype(brw_null_reg(),
1353                                              BRW_REGISTER_TYPE_D));
1354                         }
1355                 } else {
1356                         brw_set_dest(p, brw_last_inst, brw_ip_reg());
1357                         brw_set_src0(p, brw_last_inst, brw_ip_reg());
1358                         brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1359                         brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1360                                                      $4);
1361                         brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1362                                                     0);
1363                 }
1364                 brw_pop_insn_state(p);
1365         }
1366         | DO execsize instoptions
1367         {
1368                 brw_next_insn(p, $1);
1369                 if (p->devinfo->gen < 6) {
1370                         brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1371                         i965_asm_set_instruction_options(p, $3);
1372                         brw_set_dest(p, brw_last_inst, brw_null_reg());
1373                         brw_set_src0(p, brw_last_inst, brw_null_reg());
1374                         brw_set_src1(p, brw_last_inst, brw_null_reg());
1375
1376                         brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1377                 }
1378         }
1379         ;
1380
1381 /* Relative location */
1382 relativelocation2:
1383         immreg
1384         | reg32
1385         ;
1386
1387 simple_int:
1388         INTEGER                 { $$ = $1; }
1389         | MINUS INTEGER         { $$ = -$2; }
1390         | LONG                  { $$ = $1; }
1391         | MINUS LONG            { $$ = -$2; }
1392         ;
1393
1394 rellocation:
1395         relativelocation
1396         | %empty { $$ = 0; }
1397         ;
1398
1399 relativelocation:
1400         simple_int
1401         {
1402                 $$ = $1;
1403         }
1404         ;
1405
1406 /* Destination register */
1407 dst:
1408         dstoperand
1409         | dstoperandex
1410         ;
1411
1412 dstoperand:
1413         dstreg dstregion writemask dsttype
1414         {
1415                 $$ = $1;
1416
1417                 if ($2 == -1) {
1418                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1419                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1420                         $$.width = BRW_WIDTH_1;
1421                 } else {
1422                         $$.hstride = $2;
1423                 }
1424                 $$.type = $4.type;
1425                 $$.writemask = $3.writemask;
1426                 $$.swizzle = BRW_SWIZZLE_NOOP;
1427                 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1428         }
1429         ;
1430
1431 dstoperandex:
1432         dstoperandex_typed dstregion writemask dsttype
1433         {
1434                 $$ = $1;
1435                 $$.hstride = $2;
1436                 $$.type = $4.type;
1437                 $$.writemask = $3.writemask;
1438                 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1439         }
1440         | dstoperandex_ud_typed
1441         {
1442                 $$ = $1;
1443                 $$.hstride = 1;
1444                 $$.type = BRW_REGISTER_TYPE_UD;
1445         }
1446         /* BSpec says "When the conditional modifier is present, updates
1447          * to the selected flag register also occur. In this case, the
1448          * register region fields of the ‘null’ operand are valid."
1449          */
1450         | nullreg dstregion writemask dsttype
1451         {
1452                 $$ = $1;
1453                 if ($2 == -1) {
1454                         $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1455                         $$.vstride = BRW_VERTICAL_STRIDE_1;
1456                         $$.width = BRW_WIDTH_1;
1457                 } else {
1458                         $$.hstride = $2;
1459                 }
1460                 $$.writemask = $3.writemask;
1461                 $$.type = $4.type;
1462         }
1463         | threadcontrolreg
1464         {
1465                 $$ = $1;
1466                 $$.hstride = 1;
1467                 $$.type = BRW_REGISTER_TYPE_UW;
1468         }
1469         ;
1470
1471 dstoperandex_ud_typed:
1472         controlreg
1473         | ipreg
1474         | channelenablereg
1475         | performancereg
1476         ;
1477
1478 dstoperandex_typed:
1479         accreg
1480         | flagreg
1481         | addrreg
1482         | maskreg
1483         | statereg
1484         ;
1485
1486 dstreg:
1487         directgenreg
1488         {
1489                 $$ = $1;
1490                 $$.address_mode = BRW_ADDRESS_DIRECT;
1491         }
1492         | indirectgenreg
1493         {
1494                 $$ = $1;
1495                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1496         }
1497         | directmsgreg
1498         {
1499                 $$ = $1;
1500                 $$.address_mode = BRW_ADDRESS_DIRECT;
1501         }
1502         | indirectmsgreg
1503         {
1504                 $$ = $1;
1505                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1506         }
1507         ;
1508
1509 /* Source register */
1510 srcaccimm:
1511         srcacc
1512         | immreg
1513         ;
1514
1515 immreg:
1516         immval srcimmtype
1517         {
1518                 uint32_t u32;
1519                 uint64_t u64;
1520                 switch ($2.type) {
1521                 case BRW_REGISTER_TYPE_UD:
1522                         u32 = $1;
1523                         $$ = brw_imm_ud(u32);
1524                         break;
1525                 case BRW_REGISTER_TYPE_D:
1526                         $$ = brw_imm_d($1);
1527                         break;
1528                 case BRW_REGISTER_TYPE_UW:
1529                         u32 = $1 | ($1 << 16);
1530                         $$ = brw_imm_uw(u32);
1531                         break;
1532                 case BRW_REGISTER_TYPE_W:
1533                         u32 = $1;
1534                         $$ = brw_imm_w(u32);
1535                         break;
1536                 case BRW_REGISTER_TYPE_F:
1537                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1538                         $$.u64 = $1;
1539                         $$.ud = $1;
1540                         break;
1541                 case BRW_REGISTER_TYPE_V:
1542                         $$ = brw_imm_v($1);
1543                         break;
1544                 case BRW_REGISTER_TYPE_UV:
1545                         $$ = brw_imm_uv($1);
1546                         break;
1547                 case BRW_REGISTER_TYPE_VF:
1548                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1549                         $$.d = $1;
1550                         break;
1551                 case BRW_REGISTER_TYPE_Q:
1552                         u64 = $1;
1553                         $$ = brw_imm_q(u64);
1554                         break;
1555                 case BRW_REGISTER_TYPE_UQ:
1556                         u64 = $1;
1557                         $$ = brw_imm_uq(u64);
1558                         break;
1559                 case BRW_REGISTER_TYPE_DF:
1560                         $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1561                         $$.d64 = $1;
1562                         break;
1563                 default:
1564                         error(&@2, "Unkown immdediate type %s\n",
1565                               brw_reg_type_to_letters($2.type));
1566                 }
1567         }
1568         ;
1569
1570 reg32:
1571         directgenreg region srctype
1572         {
1573                 $$ = set_direct_src_operand(&$1, $3.type);
1574                 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1575         }
1576         ;
1577
1578 payload:
1579         directsrcoperand
1580         ;
1581
1582 src:
1583         directsrcoperand
1584         | indirectsrcoperand
1585         ;
1586
1587 srcacc:
1588         directsrcaccoperand
1589         | indirectsrcoperand
1590         ;
1591
1592 srcimm:
1593         directsrcoperand
1594         | indirectsrcoperand
1595         | immreg
1596         ;
1597
1598 directsrcaccoperand:
1599         directsrcoperand
1600         | accreg region srctype
1601         {
1602                 $$ = set_direct_src_operand(&$1, $3.type);
1603                 $$.vstride = $2.vstride;
1604                 $$.width = $2.width;
1605                 $$.hstride = $2.hstride;
1606         }
1607         ;
1608
1609 srcarcoperandex:
1610         srcarcoperandex_typed region srctype
1611         {
1612                 $$ = brw_reg($1.file,
1613                              $1.nr,
1614                              $1.subnr,
1615                              0,
1616                              0,
1617                              $3.type,
1618                              $2.vstride,
1619                              $2.width,
1620                              $2.hstride,
1621                              BRW_SWIZZLE_NOOP,
1622                              WRITEMASK_XYZW);
1623         }
1624         | srcarcoperandex_ud_typed
1625         {
1626                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
1627         }
1628         | nullreg region srctype
1629         {
1630                 $$ = set_direct_src_operand(&$1, $3.type);
1631                 $$.vstride = $2.vstride;
1632                 $$.width = $2.width;
1633                 $$.hstride = $2.hstride;
1634         }
1635         | threadcontrolreg
1636         {
1637                 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1638         }
1639         ;
1640
1641 srcarcoperandex_ud_typed:
1642         controlreg
1643         | statereg
1644         | ipreg
1645         | channelenablereg
1646         ;
1647
1648 srcarcoperandex_typed:
1649         flagreg
1650         | maskreg
1651         ;
1652
1653 indirectsrcoperand:
1654         negate abs indirectgenreg indirectregion swizzle srctype
1655         {
1656                 $$ = brw_reg($3.file,
1657                              0,
1658                              $3.subnr,
1659                              $1,  // negate
1660                              $2,  // abs
1661                              $6.type,
1662                              $4.vstride,
1663                              $4.width,
1664                              $4.hstride,
1665                              $5.swizzle,
1666                              WRITEMASK_X);
1667
1668                 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1669                 // brw_reg set indirect_offset to 0 so set it to valid value
1670                 $$.indirect_offset = $3.indirect_offset;
1671         }
1672         ;
1673
1674 directgenreg_list:
1675         directgenreg
1676         | directmsgreg
1677         | notifyreg
1678         | addrreg
1679         | performancereg
1680         ;
1681
1682 directsrcoperand:
1683         negate abs directgenreg_list region swizzle srctype
1684         {
1685                 $$ = brw_reg($3.file,
1686                              $3.nr,
1687                              $3.subnr,
1688                              $1,
1689                              $2,
1690                              $6.type,
1691                              $4.vstride,
1692                              $4.width,
1693                              $4.hstride,
1694                              $5.swizzle,
1695                              WRITEMASK_X);
1696         }
1697         | srcarcoperandex
1698         ;
1699
1700 /* Address register */
1701 addrparam:
1702         addrreg exp
1703         {
1704                 memset(&$$, '\0', sizeof($$));
1705                 $$.subnr = $1.subnr;
1706                 $$.indirect_offset = $2;
1707         }
1708         | addrreg
1709         ;
1710
1711 /* Register files and register numbers */
1712 exp:
1713         INTEGER         { $$ = $1; }
1714         | LONG          { $$ = $1; }
1715         ;
1716
1717 subregnum:
1718         DOT exp                         { $$ = $2; }
1719         | %empty %prec SUBREGNUM        { $$ = 0; }
1720         ;
1721
1722 directgenreg:
1723         GENREG subregnum
1724         {
1725                 memset(&$$, '\0', sizeof($$));
1726                 $$.file = BRW_GENERAL_REGISTER_FILE;
1727                 $$.nr = $1;
1728                 $$.subnr = $2;
1729         }
1730         ;
1731
1732 indirectgenreg:
1733         GENREGFILE LSQUARE addrparam RSQUARE
1734         {
1735                 memset(&$$, '\0', sizeof($$));
1736                 $$.file = BRW_GENERAL_REGISTER_FILE;
1737                 $$.subnr = $3.subnr;
1738                 $$.indirect_offset = $3.indirect_offset;
1739         }
1740         ;
1741
1742 directmsgreg:
1743         MSGREG subregnum
1744         {
1745                 $$ = brw_message_reg($1);
1746                 $$.subnr = $2;
1747         }
1748         ;
1749
1750 indirectmsgreg:
1751         MSGREGFILE LSQUARE addrparam RSQUARE
1752         {
1753                 memset(&$$, '\0', sizeof($$));
1754                 $$.file = BRW_MESSAGE_REGISTER_FILE;
1755                 $$.subnr = $3.subnr;
1756                 $$.indirect_offset = $3.indirect_offset;
1757         }
1758         ;
1759
1760 addrreg:
1761         ADDRREG subregnum
1762         {
1763                 if ($1 != 0)
1764                         error(&@1, "Address register number %d"
1765                                    "out of range\n", $1);
1766
1767                 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1768
1769                 if ($2 > subnr)
1770                         error(&@2, "Address sub resgister number %d"
1771                                    "out of range\n", $2);
1772
1773                 $$ = brw_address_reg($2);
1774         }
1775         ;
1776
1777 accreg:
1778         ACCREG subregnum
1779         {
1780                 int nr_reg;
1781                 if (p->devinfo->gen < 8)
1782                         nr_reg = 2;
1783                 else
1784                         nr_reg = 10;
1785
1786                 if ($1 > nr_reg)
1787                         error(&@1, "Accumulator register number %d"
1788                                    " out of range\n", $1);
1789
1790                 memset(&$$, '\0', sizeof($$));
1791                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1792                 $$.nr = BRW_ARF_ACCUMULATOR;
1793                 $$.subnr = $2;
1794         }
1795         ;
1796
1797 flagreg:
1798         FLAGREG subregnum
1799         {
1800                 // SNB = 1 flag reg and IVB+ = 2 flag reg
1801                 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1802                 int subnr = nr_reg;
1803
1804                 if ($1 > nr_reg)
1805                         error(&@1, "Flag register number %d"
1806                                    " out of range \n", $1);
1807                 if ($2 > subnr)
1808                         error(&@2, "Flag subregister number %d"
1809                                    " out of range\n", $2);
1810
1811                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1812                 $$.nr = BRW_ARF_FLAG | $1;
1813                 $$.subnr = $2;
1814         }
1815         ;
1816
1817 maskreg:
1818         MASKREG subregnum
1819         {
1820                 if ($1 > 0)
1821                         error(&@1, "Mask register number %d"
1822                                    " out of range\n", $1);
1823
1824                 $$ = brw_mask_reg($2);
1825         }
1826         ;
1827
1828 notifyreg:
1829         NOTIFYREG subregnum
1830         {
1831                 if ($1 > 0)
1832                         error(&@1, "Notification register number %d"
1833                                    " out of range\n", $1);
1834
1835                 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1836                 if ($2 > subnr)
1837                         error(&@2, "Notification sub register number %d"
1838                                    " out of range\n", $2);
1839
1840                 $$ = brw_notification_reg();
1841                 $$.subnr = $2;
1842         }
1843         ;
1844
1845 statereg:
1846         STATEREG subregnum
1847         {
1848                 if ($1 > 2)
1849                         error(&@1, "State register number %d"
1850                                    " out of range\n", $1);
1851
1852                 if ($2 > 4)
1853                         error(&@2, "State sub register number %d"
1854                                    " out of range\n", $2);
1855
1856                 $$ = brw_sr0_reg($2);
1857                 $$.nr = $1;
1858         }
1859         ;
1860
1861 controlreg:
1862         CONTROLREG subregnum
1863         {
1864                 if ($1 > 0)
1865                         error(&@1, "Control register number %d"
1866                                    " out of range\n", $1);
1867
1868                 if ($2 > 4)
1869                         error(&@2, "control sub register number %d"
1870                                    " out of range\n", $2);
1871
1872                 $$ = brw_cr0_reg($2);
1873                 $$.nr = $1;
1874         }
1875         ;
1876
1877 ipreg:
1878         IPREG srctype   { $$ = brw_ip_reg(); }
1879         ;
1880
1881 nullreg:
1882         NULL_TOKEN      { $$ = brw_null_reg(); }
1883         ;
1884
1885 threadcontrolreg:
1886         THREADREG subregnum
1887         {
1888                 if ($1 > 0)
1889                         error(&@1, "Thread control register number %d"
1890                                    " out of range\n", $1);
1891
1892                 if ($2 > 7)
1893                         error(&@2, "Thread control sub register number %d"
1894                                    " out of range\n", $2);
1895
1896                 $$ = brw_tdr_reg();
1897                 $$.subnr = $2;
1898         }
1899         ;
1900
1901 performancereg:
1902         PERFORMANCEREG subregnum
1903         {
1904                 int subnr;
1905                 if (p->devinfo->gen >= 10)
1906                         subnr = 5;
1907                 else if (p->devinfo->gen <= 8)
1908                         subnr = 3;
1909                 else
1910                         subnr = 4;
1911
1912                 if ($2 > subnr)
1913                         error(&@2, "Performance sub register number %d"
1914                                    " out of range\n", $2);
1915
1916                 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1917                 $$.nr = BRW_ARF_TIMESTAMP;
1918         }
1919         ;
1920
1921 channelenablereg:
1922         CHANNELENABLEREG subregnum
1923         {
1924                 if ($1 > 0)
1925                         error(&@1, "Channel enable register number %d"
1926                                    " out of range\n", $1);
1927
1928                 $$ = brw_mask_reg($2);
1929         }
1930         ;
1931
1932 /* Immediate values */
1933 immval:
1934         exp2
1935         {
1936                 $$ = $1;
1937         }
1938         | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1939         {
1940                 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1941         }
1942         ;
1943
1944 /* Regions */
1945 dstregion:
1946         %empty  { $$ = -1; }
1947         | LANGLE exp RANGLE
1948         {
1949                 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1950                         error(&@2, "Invalid Horizontal stride %d\n", $2);
1951
1952                 $$ = ffs($2);
1953         }
1954         ;
1955
1956 indirectregion:
1957         region
1958         | region_wh
1959         ;
1960
1961 region:
1962         %empty
1963         {
1964                 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1965         }
1966         | LANGLE exp RANGLE
1967         {
1968                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1969                         error(&@2, "Invalid VertStride %d\n", $2);
1970
1971                 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1972         }
1973         | LANGLE exp COMMA exp COMMA exp RANGLE
1974         {
1975
1976                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1977                         error(&@2, "Invalid VertStride %d\n", $2);
1978
1979                 if ($4 > 16 || !isPowerofTwo($4))
1980                         error(&@4, "Invalid width %d\n", $4);
1981
1982                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1983                         error(&@6, "Invalid Horizontal stride in"
1984                                    "  region_wh %d\n", $6);
1985
1986                 $$ = stride($$, $2, $4, $6);
1987         }
1988         | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1989         {
1990                 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1991                         error(&@2, "Invalid VertStride %d\n", $2);
1992
1993                 if ($4 > 16 || !isPowerofTwo($4))
1994                         error(&@4, "Invalid width %d\n", $4);
1995
1996                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1997                         error(&@6, "Invalid Horizontal stride in"
1998                                    " region_wh %d\n", $6);
1999
2000                 $$ = stride($$, $2, $4, $6);
2001         }
2002         | LANGLE VxH COMMA exp COMMA exp RANGLE
2003         {
2004                 if ($4 > 16 || !isPowerofTwo($4))
2005                         error(&@4, "Invalid width %d\n", $4);
2006
2007                 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2008                         error(&@6, "Invalid Horizontal stride in"
2009                                    " region_wh %d\n", $6);
2010
2011                 $$ = brw_VxH_indirect(0, 0);
2012         }
2013         ;
2014
2015 region_wh:
2016         LANGLE exp COMMA exp RANGLE
2017         {
2018                 if ($2 > 16 || !isPowerofTwo($2))
2019                         error(&@2, "Invalid width %d\n", $2);
2020
2021                 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2022                         error(&@4, "Invalid Horizontal stride in"
2023                                    " region_wh %d\n", $4);
2024
2025                 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2026         }
2027         ;
2028
2029 srctype:
2030         %empty          { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2031         | TYPE_F        { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2032         | TYPE_UD       { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2033         | TYPE_D        { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2034         | TYPE_UW       { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2035         | TYPE_W        { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2036         | TYPE_UB       { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2037         | TYPE_B        { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2038         | TYPE_DF       { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2039         | TYPE_UQ       { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2040         | TYPE_Q        { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2041         | TYPE_HF       { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2042         | TYPE_NF       { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2043         ;
2044
2045 srcimmtype:
2046         srctype         { $$ = $1; }
2047         | TYPE_V        { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2048         | TYPE_VF       { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2049         | TYPE_UV       { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2050         ;
2051
2052 dsttype:
2053         srctype         { $$ = $1; }
2054         ;
2055
2056 writemask:
2057         %empty
2058         {
2059                 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2060         }
2061         | DOT writemask_x writemask_y writemask_z writemask_w
2062         {
2063                 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2064         }
2065         ;
2066
2067 writemask_x:
2068         %empty  { $$ = 0; }
2069         | X     { $$ = 1 << BRW_CHANNEL_X; }
2070         ;
2071
2072 writemask_y:
2073         %empty  { $$ = 0; }
2074         | Y     { $$ = 1 << BRW_CHANNEL_Y; }
2075         ;
2076
2077 writemask_z:
2078         %empty  { $$ = 0; }
2079         | Z     { $$ = 1 << BRW_CHANNEL_Z; }
2080         ;
2081
2082 writemask_w:
2083         %empty  { $$ = 0; }
2084         | W     { $$ = 1 << BRW_CHANNEL_W; }
2085         ;
2086
2087 swizzle:
2088         %empty
2089         {
2090                 $$.swizzle = BRW_SWIZZLE_NOOP;
2091         }
2092         | DOT chansel
2093         {
2094                 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2095         }
2096         | DOT chansel chansel chansel chansel
2097         {
2098                 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2099         }
2100         ;
2101
2102 chansel:
2103         X
2104         | Y
2105         | Z
2106         | W
2107         ;
2108
2109 /* Instruction prediction and modifiers */
2110 predicate:
2111         %empty
2112         {
2113                 brw_push_insn_state(p);
2114                 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2115                 brw_set_default_flag_reg(p, 0, 0);
2116                 brw_set_default_predicate_inverse(p, false);
2117         }
2118         | LPAREN predstate flagreg predctrl RPAREN
2119         {
2120                 brw_push_insn_state(p);
2121                 brw_set_default_predicate_inverse(p, $2);
2122                 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2123                 brw_set_default_predicate_control(p, $4);
2124         }
2125         ;
2126
2127 predstate:
2128         %empty          { $$ = 0; }
2129         | PLUS          { $$ = 0; }
2130         | MINUS         { $$ = 1; }
2131         ;
2132
2133 predctrl:
2134         %empty          { $$ = BRW_PREDICATE_NORMAL; }
2135         | DOT X         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2136         | DOT Y         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2137         | DOT Z         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2138         | DOT W         { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2139         | ANYV
2140         | ALLV
2141         | ANY2H
2142         | ALL2H
2143         | ANY4H
2144         | ALL4H
2145         | ANY8H
2146         | ALL8H
2147         | ANY16H
2148         | ALL16H
2149         | ANY32H
2150         | ALL32H
2151         ;
2152
2153 /* Source Modification */
2154 negate:
2155         %empty          { $$ = 0; }
2156         | MINUS         { $$ = 1; }
2157         ;
2158
2159 abs:
2160         %empty  { $$ = 0; }
2161         | ABS   { $$ = 1; }
2162         ;
2163
2164 /* Flag (Conditional) Modifier */
2165 cond_mod:
2166         condModifiers
2167         {
2168                 $$.cond_modifier = $1;
2169                 $$.flag_reg_nr = 0;
2170                 $$.flag_subreg_nr = 0;
2171         }
2172         | condModifiers DOT flagreg
2173         {
2174                 $$.cond_modifier = $1;
2175                 $$.flag_reg_nr = $3.nr;
2176                 $$.flag_subreg_nr = $3.subnr;
2177         }
2178         ;
2179
2180 condModifiers:
2181         %empty  { $$ = BRW_CONDITIONAL_NONE; }
2182         | ZERO
2183         | EQUAL
2184         | NOT_ZERO
2185         | NOT_EQUAL
2186         | GREATER
2187         | GREATER_EQUAL
2188         | LESS
2189         | LESS_EQUAL
2190         | OVERFLOW
2191         | ROUND_INCREMENT
2192         | UNORDERED
2193         ;
2194
2195 saturate:
2196         %empty          { $$ = BRW_INSTRUCTION_NORMAL; }
2197         | SATURATE      { $$ = BRW_INSTRUCTION_SATURATE; }
2198         ;
2199
2200 /* Execution size */
2201 execsize:
2202         %empty %prec EMPTYEXECSIZE
2203         {
2204                 $$ = 0;
2205         }
2206         | LPAREN exp2 RPAREN
2207         {
2208                 if ($2 > 32 || !isPowerofTwo($2))
2209                         error(&@2, "Invalid execution size %d\n", $2);
2210
2211                 $$ = cvt($2) - 1;
2212         }
2213         ;
2214
2215 /* Instruction options */
2216 instoptions:
2217         %empty
2218         {
2219                 memset(&$$, 0, sizeof($$));
2220         }
2221         | LCURLY instoption_list RCURLY
2222         {
2223                 memset(&$$, 0, sizeof($$));
2224                 $$ = $2;
2225         }
2226         ;
2227
2228 instoption_list:
2229         instoption_list COMMA instoption
2230         {
2231                 memset(&$$, 0, sizeof($$));
2232                 $$ = $1;
2233                 add_instruction_option(&$$, $3);
2234         }
2235         | instoption_list instoption
2236         {
2237                 memset(&$$, 0, sizeof($$));
2238                 $$ = $1;
2239                 add_instruction_option(&$$, $2);
2240         }
2241         | %empty
2242         {
2243                 memset(&$$, 0, sizeof($$));
2244         }
2245         ;
2246
2247 instoption:
2248         ALIGN1          { $$ = ALIGN1;}
2249         | ALIGN16       { $$ = ALIGN16; }
2250         | ACCWREN       { $$ = ACCWREN; }
2251         | SECHALF       { $$ = SECHALF; }
2252         | COMPR         { $$ = COMPR; }
2253         | COMPR4        { $$ = COMPR4; }
2254         | BREAKPOINT    { $$ = BREAKPOINT; }
2255         | NODDCLR       { $$ = NODDCLR; }
2256         | NODDCHK       { $$ = NODDCHK; }
2257         | MASK_DISABLE  { $$ = MASK_DISABLE; }
2258         | EOT           { $$ = EOT; }
2259         | SWITCH        { $$ = SWITCH; }
2260         | ATOMIC        { $$ = ATOMIC; }
2261         | CMPTCTRL      { $$ = CMPTCTRL; }
2262         | WECTRL        { $$ = WECTRL; }
2263         | QTR_2Q        { $$ = QTR_2Q; }
2264         | QTR_3Q        { $$ = QTR_3Q; }
2265         | QTR_4Q        { $$ = QTR_4Q; }
2266         | QTR_2H        { $$ = QTR_2H; }
2267         | QTR_2N        { $$ = QTR_2N; }
2268         | QTR_3N        { $$ = QTR_3N; }
2269         | QTR_4N        { $$ = QTR_4N; }
2270         | QTR_5N        { $$ = QTR_5N; }
2271         | QTR_6N        { $$ = QTR_6N; }
2272         | QTR_7N        { $$ = QTR_7N; }
2273         | QTR_8N        { $$ = QTR_8N; }
2274         ;
2275
2276 %%
2277
2278 extern int yylineno;
2279
2280 void
2281 yyerror(char *msg)
2282 {
2283         fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2284                 input_filename, yylineno, msg, lex_text());
2285         ++errors;
2286 }