anv: Flatten descriptor bindings in anv_nir_apply_pipeline_layout
[mesa.git] / src / intel / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "vk_format_info.h"
33 #include "vk_util.h"
34
35 /** \file anv_cmd_buffer.c
36 *
37 * This file contains all of the stuff for emitting commands into a command
38 * buffer. This includes implementations of most of the vkCmd*
39 * entrypoints. This file is concerned entirely with state emission and
40 * not with the command buffer data structure itself. As far as this file
41 * is concerned, most of anv_cmd_buffer is magic.
42 */
43
44 /* TODO: These are taken from GLES. We should check the Vulkan spec */
45 const struct anv_dynamic_state default_dynamic_state = {
46 .viewport = {
47 .count = 0,
48 },
49 .scissor = {
50 .count = 0,
51 },
52 .line_width = 1.0f,
53 .depth_bias = {
54 .bias = 0.0f,
55 .clamp = 0.0f,
56 .slope = 0.0f,
57 },
58 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
59 .depth_bounds = {
60 .min = 0.0f,
61 .max = 1.0f,
62 },
63 .stencil_compare_mask = {
64 .front = ~0u,
65 .back = ~0u,
66 },
67 .stencil_write_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_reference = {
72 .front = 0u,
73 .back = 0u,
74 },
75 .line_stipple = {
76 .factor = 0u,
77 .pattern = 0u,
78 },
79 };
80
81 /**
82 * Copy the dynamic state from src to dest based on the copy_mask.
83 *
84 * Avoid copying states that have not changed, except for VIEWPORT, SCISSOR and
85 * BLEND_CONSTANTS (always copy them if they are in the copy_mask).
86 *
87 * Returns a mask of the states which changed.
88 */
89 anv_cmd_dirty_mask_t
90 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
91 const struct anv_dynamic_state *src,
92 anv_cmd_dirty_mask_t copy_mask)
93 {
94 anv_cmd_dirty_mask_t changed = 0;
95
96 if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT) {
97 dest->viewport.count = src->viewport.count;
98 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
99 src->viewport.count);
100 changed |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
101 }
102
103 if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_SCISSOR) {
104 dest->scissor.count = src->scissor.count;
105 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
106 src->scissor.count);
107 changed |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
108 }
109
110 if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
111 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
112 changed |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
113 }
114
115 #define ANV_CMP_COPY(field, flag) \
116 if (copy_mask & flag) { \
117 if (dest->field != src->field) { \
118 dest->field = src->field; \
119 changed |= flag; \
120 } \
121 }
122
123 ANV_CMP_COPY(line_width, ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH);
124
125 ANV_CMP_COPY(depth_bias.bias, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS);
126 ANV_CMP_COPY(depth_bias.clamp, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS);
127 ANV_CMP_COPY(depth_bias.slope, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS);
128
129 ANV_CMP_COPY(depth_bounds.min, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS);
130 ANV_CMP_COPY(depth_bounds.max, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS);
131
132 ANV_CMP_COPY(stencil_compare_mask.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK);
133 ANV_CMP_COPY(stencil_compare_mask.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK);
134
135 ANV_CMP_COPY(stencil_write_mask.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK);
136 ANV_CMP_COPY(stencil_write_mask.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK);
137
138 ANV_CMP_COPY(stencil_reference.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE);
139 ANV_CMP_COPY(stencil_reference.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE);
140
141 ANV_CMP_COPY(line_stipple.factor, ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE);
142 ANV_CMP_COPY(line_stipple.pattern, ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE);
143
144 #undef ANV_CMP_COPY
145
146 return changed;
147 }
148
149 static void
150 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
151 {
152 struct anv_cmd_state *state = &cmd_buffer->state;
153
154 memset(state, 0, sizeof(*state));
155
156 state->current_pipeline = UINT32_MAX;
157 state->restart_index = UINT32_MAX;
158 state->gfx.dynamic = default_dynamic_state;
159 }
160
161 static void
162 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
163 struct anv_cmd_pipeline_state *pipe_state)
164 {
165 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++) {
166 if (pipe_state->push_descriptors[i]) {
167 anv_descriptor_set_layout_unref(cmd_buffer->device,
168 pipe_state->push_descriptors[i]->set.layout);
169 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
170 }
171 }
172 }
173
174 static void
175 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
176 {
177 struct anv_cmd_state *state = &cmd_buffer->state;
178
179 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
180 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
181
182 vk_free(&cmd_buffer->pool->alloc, state->attachments);
183 }
184
185 static void
186 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
187 {
188 anv_cmd_state_finish(cmd_buffer);
189 anv_cmd_state_init(cmd_buffer);
190 }
191
192 static VkResult anv_create_cmd_buffer(
193 struct anv_device * device,
194 struct anv_cmd_pool * pool,
195 VkCommandBufferLevel level,
196 VkCommandBuffer* pCommandBuffer)
197 {
198 struct anv_cmd_buffer *cmd_buffer;
199 VkResult result;
200
201 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 cmd_buffer->batch.status = VK_SUCCESS;
207
208 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
209 cmd_buffer->device = device;
210 cmd_buffer->pool = pool;
211 cmd_buffer->level = level;
212
213 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
214 if (result != VK_SUCCESS)
215 goto fail;
216
217 anv_state_stream_init(&cmd_buffer->surface_state_stream,
218 &device->surface_state_pool, 4096);
219 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
220 &device->dynamic_state_pool, 16384);
221
222 anv_cmd_state_init(cmd_buffer);
223
224 if (pool) {
225 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
226 } else {
227 /* Init the pool_link so we can safefly call list_del when we destroy
228 * the command buffer
229 */
230 list_inithead(&cmd_buffer->pool_link);
231 }
232
233 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
234
235 return VK_SUCCESS;
236
237 fail:
238 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
239
240 return result;
241 }
242
243 VkResult anv_AllocateCommandBuffers(
244 VkDevice _device,
245 const VkCommandBufferAllocateInfo* pAllocateInfo,
246 VkCommandBuffer* pCommandBuffers)
247 {
248 ANV_FROM_HANDLE(anv_device, device, _device);
249 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
250
251 VkResult result = VK_SUCCESS;
252 uint32_t i;
253
254 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
255 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
256 &pCommandBuffers[i]);
257 if (result != VK_SUCCESS)
258 break;
259 }
260
261 if (result != VK_SUCCESS) {
262 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
263 i, pCommandBuffers);
264 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
265 pCommandBuffers[i] = VK_NULL_HANDLE;
266 }
267
268 return result;
269 }
270
271 static void
272 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
273 {
274 list_del(&cmd_buffer->pool_link);
275
276 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
277
278 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
279 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
280
281 anv_cmd_state_finish(cmd_buffer);
282
283 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
284 }
285
286 void anv_FreeCommandBuffers(
287 VkDevice device,
288 VkCommandPool commandPool,
289 uint32_t commandBufferCount,
290 const VkCommandBuffer* pCommandBuffers)
291 {
292 for (uint32_t i = 0; i < commandBufferCount; i++) {
293 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
294
295 if (!cmd_buffer)
296 continue;
297
298 anv_cmd_buffer_destroy(cmd_buffer);
299 }
300 }
301
302 VkResult
303 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
304 {
305 cmd_buffer->usage_flags = 0;
306 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
307 anv_cmd_state_reset(cmd_buffer);
308
309 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
310 anv_state_stream_init(&cmd_buffer->surface_state_stream,
311 &cmd_buffer->device->surface_state_pool, 4096);
312
313 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
314 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
315 &cmd_buffer->device->dynamic_state_pool, 16384);
316 return VK_SUCCESS;
317 }
318
319 VkResult anv_ResetCommandBuffer(
320 VkCommandBuffer commandBuffer,
321 VkCommandBufferResetFlags flags)
322 {
323 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
324 return anv_cmd_buffer_reset(cmd_buffer);
325 }
326
327 #define anv_genX_call(devinfo, func, ...) \
328 switch ((devinfo)->gen) { \
329 case 7: \
330 if ((devinfo)->is_haswell) { \
331 gen75_##func(__VA_ARGS__); \
332 } else { \
333 gen7_##func(__VA_ARGS__); \
334 } \
335 break; \
336 case 8: \
337 gen8_##func(__VA_ARGS__); \
338 break; \
339 case 9: \
340 gen9_##func(__VA_ARGS__); \
341 break; \
342 case 10: \
343 gen10_##func(__VA_ARGS__); \
344 break; \
345 case 11: \
346 gen11_##func(__VA_ARGS__); \
347 break; \
348 default: \
349 assert(!"Unknown hardware generation"); \
350 }
351
352 void
353 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
354 {
355 anv_genX_call(&cmd_buffer->device->info,
356 cmd_buffer_emit_state_base_address,
357 cmd_buffer);
358 }
359
360 void
361 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
362 const struct anv_image *image,
363 VkImageAspectFlagBits aspect,
364 enum isl_aux_usage aux_usage,
365 uint32_t level,
366 uint32_t base_layer,
367 uint32_t layer_count)
368 {
369 anv_genX_call(&cmd_buffer->device->info,
370 cmd_buffer_mark_image_written,
371 cmd_buffer, image, aspect, aux_usage,
372 level, base_layer, layer_count);
373 }
374
375 void
376 anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer)
377 {
378 anv_genX_call(&cmd_buffer->device->info,
379 cmd_emit_conditional_render_predicate,
380 cmd_buffer);
381 }
382
383 void anv_CmdBindPipeline(
384 VkCommandBuffer commandBuffer,
385 VkPipelineBindPoint pipelineBindPoint,
386 VkPipeline _pipeline)
387 {
388 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
389 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
390
391 switch (pipelineBindPoint) {
392 case VK_PIPELINE_BIND_POINT_COMPUTE:
393 cmd_buffer->state.compute.base.pipeline = pipeline;
394 cmd_buffer->state.compute.pipeline_dirty = true;
395 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
396 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
397 break;
398
399 case VK_PIPELINE_BIND_POINT_GRAPHICS:
400 cmd_buffer->state.gfx.base.pipeline = pipeline;
401 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
402 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
403 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
404 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
405
406 /* Apply the dynamic state from the pipeline */
407 cmd_buffer->state.gfx.dirty |=
408 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
409 &pipeline->dynamic_state,
410 pipeline->dynamic_state_mask);
411 break;
412
413 default:
414 assert(!"invalid bind point");
415 break;
416 }
417 }
418
419 void anv_CmdSetViewport(
420 VkCommandBuffer commandBuffer,
421 uint32_t firstViewport,
422 uint32_t viewportCount,
423 const VkViewport* pViewports)
424 {
425 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
426
427 const uint32_t total_count = firstViewport + viewportCount;
428 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
429 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
430
431 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
432 pViewports, viewportCount * sizeof(*pViewports));
433
434 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
435 }
436
437 void anv_CmdSetScissor(
438 VkCommandBuffer commandBuffer,
439 uint32_t firstScissor,
440 uint32_t scissorCount,
441 const VkRect2D* pScissors)
442 {
443 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
444
445 const uint32_t total_count = firstScissor + scissorCount;
446 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
447 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
448
449 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
450 pScissors, scissorCount * sizeof(*pScissors));
451
452 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
453 }
454
455 void anv_CmdSetLineWidth(
456 VkCommandBuffer commandBuffer,
457 float lineWidth)
458 {
459 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
460
461 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
462 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
463 }
464
465 void anv_CmdSetDepthBias(
466 VkCommandBuffer commandBuffer,
467 float depthBiasConstantFactor,
468 float depthBiasClamp,
469 float depthBiasSlopeFactor)
470 {
471 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
472
473 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
474 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
475 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
476
477 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
478 }
479
480 void anv_CmdSetBlendConstants(
481 VkCommandBuffer commandBuffer,
482 const float blendConstants[4])
483 {
484 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
485
486 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
487 blendConstants, sizeof(float) * 4);
488
489 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
490 }
491
492 void anv_CmdSetDepthBounds(
493 VkCommandBuffer commandBuffer,
494 float minDepthBounds,
495 float maxDepthBounds)
496 {
497 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
498
499 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
500 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
501
502 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
503 }
504
505 void anv_CmdSetStencilCompareMask(
506 VkCommandBuffer commandBuffer,
507 VkStencilFaceFlags faceMask,
508 uint32_t compareMask)
509 {
510 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
511
512 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
513 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
514 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
515 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
516
517 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
518 }
519
520 void anv_CmdSetStencilWriteMask(
521 VkCommandBuffer commandBuffer,
522 VkStencilFaceFlags faceMask,
523 uint32_t writeMask)
524 {
525 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
526
527 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
528 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
529 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
530 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
531
532 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
533 }
534
535 void anv_CmdSetStencilReference(
536 VkCommandBuffer commandBuffer,
537 VkStencilFaceFlags faceMask,
538 uint32_t reference)
539 {
540 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
541
542 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
543 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
544 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
545 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
546
547 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
548 }
549
550 void anv_CmdSetLineStippleEXT(
551 VkCommandBuffer commandBuffer,
552 uint32_t lineStippleFactor,
553 uint16_t lineStipplePattern)
554 {
555 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
556
557 cmd_buffer->state.gfx.dynamic.line_stipple.factor = lineStippleFactor;
558 cmd_buffer->state.gfx.dynamic.line_stipple.pattern = lineStipplePattern;
559
560 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
561 }
562
563 static void
564 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
565 VkPipelineBindPoint bind_point,
566 struct anv_pipeline_layout *layout,
567 uint32_t set_index,
568 struct anv_descriptor_set *set,
569 uint32_t *dynamic_offset_count,
570 const uint32_t **dynamic_offsets)
571 {
572 struct anv_descriptor_set_layout *set_layout =
573 layout->set[set_index].layout;
574
575 struct anv_cmd_pipeline_state *pipe_state;
576 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
577 pipe_state = &cmd_buffer->state.compute.base;
578 } else {
579 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
580 pipe_state = &cmd_buffer->state.gfx.base;
581 }
582 pipe_state->descriptors[set_index] = set;
583
584 if (dynamic_offsets) {
585 if (set_layout->dynamic_offset_count > 0) {
586 uint32_t dynamic_offset_start =
587 layout->set[set_index].dynamic_offset_start;
588
589 /* Assert that everything is in range */
590 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
591 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
592 ARRAY_SIZE(pipe_state->dynamic_offsets));
593
594 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
595 *dynamic_offsets, set_layout->dynamic_offset_count);
596
597 *dynamic_offsets += set_layout->dynamic_offset_count;
598 *dynamic_offset_count -= set_layout->dynamic_offset_count;
599
600 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
601 cmd_buffer->state.push_constants_dirty |=
602 VK_SHADER_STAGE_COMPUTE_BIT;
603 } else {
604 cmd_buffer->state.push_constants_dirty |=
605 VK_SHADER_STAGE_ALL_GRAPHICS;
606 }
607 }
608 }
609
610 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
611 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
612 } else {
613 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
614 cmd_buffer->state.descriptors_dirty |=
615 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
616 }
617 }
618
619 void anv_CmdBindDescriptorSets(
620 VkCommandBuffer commandBuffer,
621 VkPipelineBindPoint pipelineBindPoint,
622 VkPipelineLayout _layout,
623 uint32_t firstSet,
624 uint32_t descriptorSetCount,
625 const VkDescriptorSet* pDescriptorSets,
626 uint32_t dynamicOffsetCount,
627 const uint32_t* pDynamicOffsets)
628 {
629 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
630 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
631
632 assert(firstSet + descriptorSetCount <= MAX_SETS);
633
634 for (uint32_t i = 0; i < descriptorSetCount; i++) {
635 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
636 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
637 layout, firstSet + i, set,
638 &dynamicOffsetCount,
639 &pDynamicOffsets);
640 }
641 }
642
643 void anv_CmdBindVertexBuffers(
644 VkCommandBuffer commandBuffer,
645 uint32_t firstBinding,
646 uint32_t bindingCount,
647 const VkBuffer* pBuffers,
648 const VkDeviceSize* pOffsets)
649 {
650 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
651 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
652
653 /* We have to defer setting up vertex buffer since we need the buffer
654 * stride from the pipeline. */
655
656 assert(firstBinding + bindingCount <= MAX_VBS);
657 for (uint32_t i = 0; i < bindingCount; i++) {
658 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
659 vb[firstBinding + i].offset = pOffsets[i];
660 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
661 }
662 }
663
664 void anv_CmdBindTransformFeedbackBuffersEXT(
665 VkCommandBuffer commandBuffer,
666 uint32_t firstBinding,
667 uint32_t bindingCount,
668 const VkBuffer* pBuffers,
669 const VkDeviceSize* pOffsets,
670 const VkDeviceSize* pSizes)
671 {
672 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
673 struct anv_xfb_binding *xfb = cmd_buffer->state.xfb_bindings;
674
675 /* We have to defer setting up vertex buffer since we need the buffer
676 * stride from the pipeline. */
677
678 assert(firstBinding + bindingCount <= MAX_XFB_BUFFERS);
679 for (uint32_t i = 0; i < bindingCount; i++) {
680 if (pBuffers[i] == VK_NULL_HANDLE) {
681 xfb[firstBinding + i].buffer = NULL;
682 } else {
683 ANV_FROM_HANDLE(anv_buffer, buffer, pBuffers[i]);
684 xfb[firstBinding + i].buffer = buffer;
685 xfb[firstBinding + i].offset = pOffsets[i];
686 xfb[firstBinding + i].size =
687 anv_buffer_get_range(buffer, pOffsets[i],
688 pSizes ? pSizes[i] : VK_WHOLE_SIZE);
689 }
690 }
691 }
692
693 enum isl_format
694 anv_isl_format_for_descriptor_type(VkDescriptorType type)
695 {
696 switch (type) {
697 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
698 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
699 return ISL_FORMAT_R32G32B32A32_FLOAT;
700
701 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
702 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
703 return ISL_FORMAT_RAW;
704
705 default:
706 unreachable("Invalid descriptor type");
707 }
708 }
709
710 struct anv_state
711 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
712 const void *data, uint32_t size, uint32_t alignment)
713 {
714 struct anv_state state;
715
716 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
717 memcpy(state.map, data, size);
718
719 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
720
721 return state;
722 }
723
724 struct anv_state
725 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
726 uint32_t *a, uint32_t *b,
727 uint32_t dwords, uint32_t alignment)
728 {
729 struct anv_state state;
730 uint32_t *p;
731
732 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
733 dwords * 4, alignment);
734 p = state.map;
735 for (uint32_t i = 0; i < dwords; i++)
736 p[i] = a[i] | b[i];
737
738 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
739
740 return state;
741 }
742
743 static uint32_t
744 anv_push_constant_value(const struct anv_cmd_pipeline_state *state,
745 const struct anv_push_constants *data, uint32_t param)
746 {
747 if (BRW_PARAM_IS_BUILTIN(param)) {
748 switch (param) {
749 case BRW_PARAM_BUILTIN_ZERO:
750 return 0;
751 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X:
752 return data->base_work_group_id[0];
753 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y:
754 return data->base_work_group_id[1];
755 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z:
756 return data->base_work_group_id[2];
757 default:
758 unreachable("Invalid param builtin");
759 }
760 } else if (ANV_PARAM_IS_PUSH(param)) {
761 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
762 assert(offset % sizeof(uint32_t) == 0);
763 if (offset < sizeof(data->client_data))
764 return *(uint32_t *)((uint8_t *)data + offset);
765 else
766 return 0;
767 } else if (ANV_PARAM_IS_DYN_OFFSET(param)) {
768 unsigned idx = ANV_PARAM_DYN_OFFSET_IDX(param);
769 assert(idx < MAX_DYNAMIC_BUFFERS);
770 return state->dynamic_offsets[idx];
771 }
772
773 assert(!"Invalid param");
774 return 0;
775 }
776
777 struct anv_state
778 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
779 gl_shader_stage stage)
780 {
781 struct anv_cmd_pipeline_state *pipeline_state = &cmd_buffer->state.gfx.base;
782 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
783
784 /* If we don't have this stage, bail. */
785 if (!anv_pipeline_has_stage(pipeline, stage))
786 return (struct anv_state) { .offset = 0 };
787
788 struct anv_push_constants *data =
789 &cmd_buffer->state.push_constants[stage];
790 const struct brw_stage_prog_data *prog_data =
791 pipeline->shaders[stage]->prog_data;
792
793 /* If we don't actually have any push constants, bail. */
794 if (prog_data == NULL || prog_data->nr_params == 0)
795 return (struct anv_state) { .offset = 0 };
796
797 struct anv_state state =
798 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
799 prog_data->nr_params * sizeof(float),
800 32 /* bottom 5 bits MBZ */);
801
802 /* Walk through the param array and fill the buffer with data */
803 uint32_t *u32_map = state.map;
804 for (unsigned i = 0; i < prog_data->nr_params; i++) {
805 u32_map[i] = anv_push_constant_value(pipeline_state, data,
806 prog_data->param[i]);
807 }
808
809 return state;
810 }
811
812 struct anv_state
813 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
814 {
815 struct anv_cmd_pipeline_state *pipeline_state = &cmd_buffer->state.compute.base;
816 struct anv_push_constants *data =
817 &cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
818 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
819 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
820 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
821
822 /* If we don't actually have any push constants, bail. */
823 if (cs_prog_data->push.total.size == 0)
824 return (struct anv_state) { .offset = 0 };
825
826 const unsigned push_constant_alignment =
827 cmd_buffer->device->info.gen < 8 ? 32 : 64;
828 const unsigned aligned_total_push_constants_size =
829 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
830 struct anv_state state =
831 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
832 aligned_total_push_constants_size,
833 push_constant_alignment);
834
835 /* Walk through the param array and fill the buffer with data */
836 uint32_t *u32_map = state.map;
837
838 if (cs_prog_data->push.cross_thread.size > 0) {
839 for (unsigned i = 0;
840 i < cs_prog_data->push.cross_thread.dwords;
841 i++) {
842 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
843 u32_map[i] = anv_push_constant_value(pipeline_state, data,
844 prog_data->param[i]);
845 }
846 }
847
848 if (cs_prog_data->push.per_thread.size > 0) {
849 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
850 unsigned dst =
851 8 * (cs_prog_data->push.per_thread.regs * t +
852 cs_prog_data->push.cross_thread.regs);
853 unsigned src = cs_prog_data->push.cross_thread.dwords;
854 for ( ; src < prog_data->nr_params; src++, dst++) {
855 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
856 u32_map[dst] = t;
857 } else {
858 u32_map[dst] = anv_push_constant_value(pipeline_state, data,
859 prog_data->param[src]);
860 }
861 }
862 }
863 }
864
865 return state;
866 }
867
868 void anv_CmdPushConstants(
869 VkCommandBuffer commandBuffer,
870 VkPipelineLayout layout,
871 VkShaderStageFlags stageFlags,
872 uint32_t offset,
873 uint32_t size,
874 const void* pValues)
875 {
876 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
877
878 anv_foreach_stage(stage, stageFlags) {
879 memcpy(cmd_buffer->state.push_constants[stage].client_data + offset,
880 pValues, size);
881 }
882
883 cmd_buffer->state.push_constants_dirty |= stageFlags;
884 }
885
886 VkResult anv_CreateCommandPool(
887 VkDevice _device,
888 const VkCommandPoolCreateInfo* pCreateInfo,
889 const VkAllocationCallbacks* pAllocator,
890 VkCommandPool* pCmdPool)
891 {
892 ANV_FROM_HANDLE(anv_device, device, _device);
893 struct anv_cmd_pool *pool;
894
895 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
896 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
897 if (pool == NULL)
898 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
899
900 if (pAllocator)
901 pool->alloc = *pAllocator;
902 else
903 pool->alloc = device->alloc;
904
905 list_inithead(&pool->cmd_buffers);
906
907 *pCmdPool = anv_cmd_pool_to_handle(pool);
908
909 return VK_SUCCESS;
910 }
911
912 void anv_DestroyCommandPool(
913 VkDevice _device,
914 VkCommandPool commandPool,
915 const VkAllocationCallbacks* pAllocator)
916 {
917 ANV_FROM_HANDLE(anv_device, device, _device);
918 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
919
920 if (!pool)
921 return;
922
923 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
924 &pool->cmd_buffers, pool_link) {
925 anv_cmd_buffer_destroy(cmd_buffer);
926 }
927
928 vk_free2(&device->alloc, pAllocator, pool);
929 }
930
931 VkResult anv_ResetCommandPool(
932 VkDevice device,
933 VkCommandPool commandPool,
934 VkCommandPoolResetFlags flags)
935 {
936 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
937
938 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
939 &pool->cmd_buffers, pool_link) {
940 anv_cmd_buffer_reset(cmd_buffer);
941 }
942
943 return VK_SUCCESS;
944 }
945
946 void anv_TrimCommandPool(
947 VkDevice device,
948 VkCommandPool commandPool,
949 VkCommandPoolTrimFlags flags)
950 {
951 /* Nothing for us to do here. Our pools stay pretty tidy. */
952 }
953
954 /**
955 * Return NULL if the current subpass has no depthstencil attachment.
956 */
957 const struct anv_image_view *
958 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
959 {
960 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
961
962 if (subpass->depth_stencil_attachment == NULL)
963 return NULL;
964
965 const struct anv_image_view *iview =
966 cmd_buffer->state.attachments[subpass->depth_stencil_attachment->attachment].image_view;
967
968 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
969 VK_IMAGE_ASPECT_STENCIL_BIT));
970
971 return iview;
972 }
973
974 static struct anv_descriptor_set *
975 anv_cmd_buffer_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
976 VkPipelineBindPoint bind_point,
977 struct anv_descriptor_set_layout *layout,
978 uint32_t _set)
979 {
980 struct anv_cmd_pipeline_state *pipe_state;
981 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
982 pipe_state = &cmd_buffer->state.compute.base;
983 } else {
984 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
985 pipe_state = &cmd_buffer->state.gfx.base;
986 }
987
988 struct anv_push_descriptor_set **push_set =
989 &pipe_state->push_descriptors[_set];
990
991 if (*push_set == NULL) {
992 *push_set = vk_zalloc(&cmd_buffer->pool->alloc,
993 sizeof(struct anv_push_descriptor_set), 8,
994 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
995 if (*push_set == NULL) {
996 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
997 return NULL;
998 }
999 }
1000
1001 struct anv_descriptor_set *set = &(*push_set)->set;
1002
1003 if (set->layout != layout) {
1004 if (set->layout)
1005 anv_descriptor_set_layout_unref(cmd_buffer->device, set->layout);
1006 anv_descriptor_set_layout_ref(layout);
1007 set->layout = layout;
1008 }
1009 set->size = anv_descriptor_set_layout_size(layout);
1010 set->buffer_view_count = layout->buffer_view_count;
1011 set->buffer_views = (*push_set)->buffer_views;
1012
1013 if (layout->descriptor_buffer_size &&
1014 ((*push_set)->set_used_on_gpu ||
1015 set->desc_mem.alloc_size < layout->descriptor_buffer_size)) {
1016 /* The previous buffer is either actively used by some GPU command (so
1017 * we can't modify it) or is too small. Allocate a new one.
1018 */
1019 struct anv_state desc_mem =
1020 anv_state_stream_alloc(&cmd_buffer->dynamic_state_stream,
1021 layout->descriptor_buffer_size, 32);
1022 if (set->desc_mem.alloc_size) {
1023 /* TODO: Do we really need to copy all the time? */
1024 memcpy(desc_mem.map, set->desc_mem.map,
1025 MIN2(desc_mem.alloc_size, set->desc_mem.alloc_size));
1026 }
1027 set->desc_mem = desc_mem;
1028
1029 struct anv_address addr = {
1030 .bo = cmd_buffer->dynamic_state_stream.state_pool->block_pool.bo,
1031 .offset = set->desc_mem.offset,
1032 };
1033
1034 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1035 set->desc_surface_state =
1036 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
1037 isl_dev->ss.size, isl_dev->ss.align);
1038 anv_fill_buffer_surface_state(cmd_buffer->device,
1039 set->desc_surface_state,
1040 ISL_FORMAT_R32G32B32A32_FLOAT,
1041 addr, layout->descriptor_buffer_size, 1);
1042 }
1043
1044 return set;
1045 }
1046
1047 void anv_CmdPushDescriptorSetKHR(
1048 VkCommandBuffer commandBuffer,
1049 VkPipelineBindPoint pipelineBindPoint,
1050 VkPipelineLayout _layout,
1051 uint32_t _set,
1052 uint32_t descriptorWriteCount,
1053 const VkWriteDescriptorSet* pDescriptorWrites)
1054 {
1055 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1056 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1057
1058 assert(_set < MAX_SETS);
1059
1060 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1061
1062 struct anv_descriptor_set *set =
1063 anv_cmd_buffer_push_descriptor_set(cmd_buffer, pipelineBindPoint,
1064 set_layout, _set);
1065 if (!set)
1066 return;
1067
1068 /* Go through the user supplied descriptors. */
1069 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
1070 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
1071
1072 switch (write->descriptorType) {
1073 case VK_DESCRIPTOR_TYPE_SAMPLER:
1074 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
1075 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
1076 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
1077 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
1078 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1079 anv_descriptor_set_write_image_view(cmd_buffer->device, set,
1080 write->pImageInfo + j,
1081 write->descriptorType,
1082 write->dstBinding,
1083 write->dstArrayElement + j);
1084 }
1085 break;
1086
1087 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
1088 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
1089 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1090 ANV_FROM_HANDLE(anv_buffer_view, bview,
1091 write->pTexelBufferView[j]);
1092
1093 anv_descriptor_set_write_buffer_view(cmd_buffer->device, set,
1094 write->descriptorType,
1095 bview,
1096 write->dstBinding,
1097 write->dstArrayElement + j);
1098 }
1099 break;
1100
1101 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1102 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1103 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1104 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1105 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1106 assert(write->pBufferInfo[j].buffer);
1107 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1108 assert(buffer);
1109
1110 anv_descriptor_set_write_buffer(cmd_buffer->device, set,
1111 &cmd_buffer->surface_state_stream,
1112 write->descriptorType,
1113 buffer,
1114 write->dstBinding,
1115 write->dstArrayElement + j,
1116 write->pBufferInfo[j].offset,
1117 write->pBufferInfo[j].range);
1118 }
1119 break;
1120
1121 default:
1122 break;
1123 }
1124 }
1125
1126 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1127 layout, _set, set, NULL, NULL);
1128 }
1129
1130 void anv_CmdPushDescriptorSetWithTemplateKHR(
1131 VkCommandBuffer commandBuffer,
1132 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1133 VkPipelineLayout _layout,
1134 uint32_t _set,
1135 const void* pData)
1136 {
1137 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1138 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1139 descriptorUpdateTemplate);
1140 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1141
1142 assert(_set < MAX_PUSH_DESCRIPTORS);
1143
1144 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1145
1146 struct anv_descriptor_set *set =
1147 anv_cmd_buffer_push_descriptor_set(cmd_buffer, template->bind_point,
1148 set_layout, _set);
1149 if (!set)
1150 return;
1151
1152 anv_descriptor_set_write_template(cmd_buffer->device, set,
1153 &cmd_buffer->surface_state_stream,
1154 template,
1155 pData);
1156
1157 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1158 layout, _set, set, NULL, NULL);
1159 }
1160
1161 void anv_CmdSetDeviceMask(
1162 VkCommandBuffer commandBuffer,
1163 uint32_t deviceMask)
1164 {
1165 /* No-op */
1166 }