anv: Stop storing the shader constant data side-band
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
36 #include "anv_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
43
44 // Shader functions
45
46 VkResult anv_CreateShaderModule(
47 VkDevice _device,
48 const VkShaderModuleCreateInfo* pCreateInfo,
49 const VkAllocationCallbacks* pAllocator,
50 VkShaderModule* pShaderModule)
51 {
52 ANV_FROM_HANDLE(anv_device, device, _device);
53 struct anv_shader_module *module;
54
55 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
56 assert(pCreateInfo->flags == 0);
57
58 module = vk_alloc2(&device->vk.alloc, pAllocator,
59 sizeof(*module) + pCreateInfo->codeSize, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
61 if (module == NULL)
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
63
64 vk_object_base_init(&device->vk, &module->base,
65 VK_OBJECT_TYPE_SHADER_MODULE);
66 module->size = pCreateInfo->codeSize;
67 memcpy(module->data, pCreateInfo->pCode, module->size);
68
69 _mesa_sha1_compute(module->data, module->size, module->sha1);
70
71 *pShaderModule = anv_shader_module_to_handle(module);
72
73 return VK_SUCCESS;
74 }
75
76 void anv_DestroyShaderModule(
77 VkDevice _device,
78 VkShaderModule _module,
79 const VkAllocationCallbacks* pAllocator)
80 {
81 ANV_FROM_HANDLE(anv_device, device, _device);
82 ANV_FROM_HANDLE(anv_shader_module, module, _module);
83
84 if (!module)
85 return;
86
87 vk_object_base_finish(&module->base);
88 vk_free2(&device->vk.alloc, pAllocator, module);
89 }
90
91 #define SPIR_V_MAGIC_NUMBER 0x07230203
92
93 struct anv_spirv_debug_data {
94 struct anv_device *device;
95 const struct anv_shader_module *module;
96 };
97
98 static void anv_spirv_nir_debug(void *private_data,
99 enum nir_spirv_debug_level level,
100 size_t spirv_offset,
101 const char *message)
102 {
103 struct anv_spirv_debug_data *debug_data = private_data;
104 struct anv_instance *instance = debug_data->device->physical->instance;
105
106 static const VkDebugReportFlagsEXT vk_flags[] = {
107 [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
108 [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
109 [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
110 };
111 char buffer[256];
112
113 snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset, message);
114
115 vk_debug_report(&instance->debug_report_callbacks,
116 vk_flags[level],
117 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
118 (uint64_t) (uintptr_t) debug_data->module,
119 0, 0, "anv", buffer);
120 }
121
122 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
123 * we can't do that yet because we don't have the ability to copy nir.
124 */
125 static nir_shader *
126 anv_shader_compile_to_nir(struct anv_device *device,
127 void *mem_ctx,
128 const struct anv_shader_module *module,
129 const char *entrypoint_name,
130 gl_shader_stage stage,
131 const VkSpecializationInfo *spec_info)
132 {
133 const struct anv_physical_device *pdevice = device->physical;
134 const struct brw_compiler *compiler = pdevice->compiler;
135 const nir_shader_compiler_options *nir_options =
136 compiler->glsl_compiler_options[stage].NirOptions;
137
138 uint32_t *spirv = (uint32_t *) module->data;
139 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
140 assert(module->size % 4 == 0);
141
142 uint32_t num_spec_entries = 0;
143 struct nir_spirv_specialization *spec_entries = NULL;
144 if (spec_info && spec_info->mapEntryCount > 0) {
145 num_spec_entries = spec_info->mapEntryCount;
146 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
147 for (uint32_t i = 0; i < num_spec_entries; i++) {
148 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
149 const void *data = spec_info->pData + entry.offset;
150 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
151
152 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
153 switch (entry.size) {
154 case 8:
155 spec_entries[i].value.u64 = *(const uint64_t *)data;
156 break;
157 case 4:
158 spec_entries[i].value.u32 = *(const uint32_t *)data;
159 break;
160 case 2:
161 spec_entries[i].value.u16 = *(const uint16_t *)data;
162 break;
163 case 1:
164 spec_entries[i].value.u8 = *(const uint8_t *)data;
165 break;
166 default:
167 assert(!"Invalid spec constant size");
168 break;
169 }
170 }
171 }
172
173 struct anv_spirv_debug_data spirv_debug_data = {
174 .device = device,
175 .module = module,
176 };
177 struct spirv_to_nir_options spirv_options = {
178 .frag_coord_is_sysval = true,
179 .caps = {
180 .demote_to_helper_invocation = true,
181 .derivative_group = true,
182 .descriptor_array_dynamic_indexing = true,
183 .descriptor_array_non_uniform_indexing = true,
184 .descriptor_indexing = true,
185 .device_group = true,
186 .draw_parameters = true,
187 .float16 = pdevice->info.gen >= 8,
188 .float64 = pdevice->info.gen >= 8,
189 .fragment_shader_sample_interlock = pdevice->info.gen >= 9,
190 .fragment_shader_pixel_interlock = pdevice->info.gen >= 9,
191 .geometry_streams = true,
192 .image_write_without_format = true,
193 .int8 = pdevice->info.gen >= 8,
194 .int16 = pdevice->info.gen >= 8,
195 .int64 = pdevice->info.gen >= 8,
196 .int64_atomics = pdevice->info.gen >= 9 && pdevice->use_softpin,
197 .integer_functions2 = pdevice->info.gen >= 8,
198 .min_lod = true,
199 .multiview = true,
200 .physical_storage_buffer_address = pdevice->has_a64_buffer_access,
201 .post_depth_coverage = pdevice->info.gen >= 9,
202 .runtime_descriptor_array = true,
203 .float_controls = pdevice->info.gen >= 8,
204 .shader_clock = true,
205 .shader_viewport_index_layer = true,
206 .stencil_export = pdevice->info.gen >= 9,
207 .storage_8bit = pdevice->info.gen >= 8,
208 .storage_16bit = pdevice->info.gen >= 8,
209 .subgroup_arithmetic = true,
210 .subgroup_basic = true,
211 .subgroup_ballot = true,
212 .subgroup_quad = true,
213 .subgroup_shuffle = true,
214 .subgroup_vote = true,
215 .tessellation = true,
216 .transform_feedback = pdevice->info.gen >= 8,
217 .variable_pointers = true,
218 .vk_memory_model = true,
219 .vk_memory_model_device_scope = true,
220 },
221 .ubo_addr_format = nir_address_format_32bit_index_offset,
222 .ssbo_addr_format =
223 anv_nir_ssbo_addr_format(pdevice, device->robust_buffer_access),
224 .phys_ssbo_addr_format = nir_address_format_64bit_global,
225 .push_const_addr_format = nir_address_format_logical,
226
227 /* TODO: Consider changing this to an address format that has the NULL
228 * pointer equals to 0. That might be a better format to play nice
229 * with certain code / code generators.
230 */
231 .shared_addr_format = nir_address_format_32bit_offset,
232 .debug = {
233 .func = anv_spirv_nir_debug,
234 .private_data = &spirv_debug_data,
235 },
236 };
237
238
239 nir_shader *nir =
240 spirv_to_nir(spirv, module->size / 4,
241 spec_entries, num_spec_entries,
242 stage, entrypoint_name, &spirv_options, nir_options);
243 assert(nir->info.stage == stage);
244 nir_validate_shader(nir, "after spirv_to_nir");
245 ralloc_steal(mem_ctx, nir);
246
247 free(spec_entries);
248
249 if (unlikely(INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage))) {
250 fprintf(stderr, "NIR (from SPIR-V) for %s shader:\n",
251 gl_shader_stage_name(stage));
252 nir_print_shader(nir, stderr);
253 }
254
255 /* We have to lower away local constant initializers right before we
256 * inline functions. That way they get properly initialized at the top
257 * of the function and not at the top of its caller.
258 */
259 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
260 NIR_PASS_V(nir, nir_lower_returns);
261 NIR_PASS_V(nir, nir_inline_functions);
262 NIR_PASS_V(nir, nir_copy_prop);
263 NIR_PASS_V(nir, nir_opt_deref);
264
265 /* Pick off the single entrypoint that we want */
266 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
267 if (!func->is_entrypoint)
268 exec_node_remove(&func->node);
269 }
270 assert(exec_list_length(&nir->functions) == 1);
271
272 /* Now that we've deleted all but the main function, we can go ahead and
273 * lower the rest of the constant initializers. We do this here so that
274 * nir_remove_dead_variables and split_per_member_structs below see the
275 * corresponding stores.
276 */
277 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
278
279 /* Split member structs. We do this before lower_io_to_temporaries so that
280 * it doesn't lower system values to temporaries by accident.
281 */
282 NIR_PASS_V(nir, nir_split_var_copies);
283 NIR_PASS_V(nir, nir_split_per_member_structs);
284
285 NIR_PASS_V(nir, nir_remove_dead_variables,
286 nir_var_shader_in | nir_var_shader_out | nir_var_system_value,
287 NULL);
288
289 NIR_PASS_V(nir, nir_propagate_invariant);
290 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
291 nir_shader_get_entrypoint(nir), true, false);
292
293 NIR_PASS_V(nir, nir_lower_frexp);
294
295 /* Vulkan uses the separate-shader linking model */
296 nir->info.separate_shader = true;
297
298 brw_preprocess_nir(compiler, nir, NULL);
299
300 return nir;
301 }
302
303 VkResult
304 anv_pipeline_init(struct anv_pipeline *pipeline,
305 struct anv_device *device,
306 enum anv_pipeline_type type,
307 VkPipelineCreateFlags flags,
308 const VkAllocationCallbacks *pAllocator)
309 {
310 VkResult result;
311
312 memset(pipeline, 0, sizeof(*pipeline));
313
314 vk_object_base_init(&device->vk, &pipeline->base,
315 VK_OBJECT_TYPE_PIPELINE);
316 pipeline->device = device;
317
318 /* It's the job of the child class to provide actual backing storage for
319 * the batch by setting batch.start, batch.next, and batch.end.
320 */
321 pipeline->batch.alloc = pAllocator ? pAllocator : &device->vk.alloc;
322 pipeline->batch.relocs = &pipeline->batch_relocs;
323 pipeline->batch.status = VK_SUCCESS;
324
325 result = anv_reloc_list_init(&pipeline->batch_relocs,
326 pipeline->batch.alloc);
327 if (result != VK_SUCCESS)
328 return result;
329
330 pipeline->mem_ctx = ralloc_context(NULL);
331
332 pipeline->type = type;
333 pipeline->flags = flags;
334
335 util_dynarray_init(&pipeline->executables, pipeline->mem_ctx);
336
337 return VK_SUCCESS;
338 }
339
340 void
341 anv_pipeline_finish(struct anv_pipeline *pipeline,
342 struct anv_device *device,
343 const VkAllocationCallbacks *pAllocator)
344 {
345 anv_reloc_list_finish(&pipeline->batch_relocs,
346 pAllocator ? pAllocator : &device->vk.alloc);
347 ralloc_free(pipeline->mem_ctx);
348 vk_object_base_finish(&pipeline->base);
349 }
350
351 void anv_DestroyPipeline(
352 VkDevice _device,
353 VkPipeline _pipeline,
354 const VkAllocationCallbacks* pAllocator)
355 {
356 ANV_FROM_HANDLE(anv_device, device, _device);
357 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
358
359 if (!pipeline)
360 return;
361
362 switch (pipeline->type) {
363 case ANV_PIPELINE_GRAPHICS: {
364 struct anv_graphics_pipeline *gfx_pipeline =
365 anv_pipeline_to_graphics(pipeline);
366
367 if (gfx_pipeline->blend_state.map)
368 anv_state_pool_free(&device->dynamic_state_pool, gfx_pipeline->blend_state);
369
370 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
371 if (gfx_pipeline->shaders[s])
372 anv_shader_bin_unref(device, gfx_pipeline->shaders[s]);
373 }
374 break;
375 }
376
377 case ANV_PIPELINE_COMPUTE: {
378 struct anv_compute_pipeline *compute_pipeline =
379 anv_pipeline_to_compute(pipeline);
380
381 if (compute_pipeline->cs)
382 anv_shader_bin_unref(device, compute_pipeline->cs);
383
384 break;
385 }
386
387 default:
388 unreachable("invalid pipeline type");
389 }
390
391 anv_pipeline_finish(pipeline, device, pAllocator);
392 vk_free2(&device->vk.alloc, pAllocator, pipeline);
393 }
394
395 static const uint32_t vk_to_gen_primitive_type[] = {
396 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
397 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
398 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
399 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
400 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
401 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
402 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
403 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
404 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
405 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
406 };
407
408 static void
409 populate_sampler_prog_key(const struct gen_device_info *devinfo,
410 struct brw_sampler_prog_key_data *key)
411 {
412 /* Almost all multisampled textures are compressed. The only time when we
413 * don't compress a multisampled texture is for 16x MSAA with a surface
414 * width greater than 8k which is a bit of an edge case. Since the sampler
415 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
416 * to tell the compiler to always assume compression.
417 */
418 key->compressed_multisample_layout_mask = ~0;
419
420 /* SkyLake added support for 16x MSAA. With this came a new message for
421 * reading from a 16x MSAA surface with compression. The new message was
422 * needed because now the MCS data is 64 bits instead of 32 or lower as is
423 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
424 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
425 * so we can just use it unconditionally. This may not be quite as
426 * efficient but it saves us from recompiling.
427 */
428 if (devinfo->gen >= 9)
429 key->msaa_16 = ~0;
430
431 /* XXX: Handle texture swizzle on HSW- */
432 for (int i = 0; i < MAX_SAMPLERS; i++) {
433 /* Assume color sampler, no swizzling. (Works for BDW+) */
434 key->swizzles[i] = SWIZZLE_XYZW;
435 }
436 }
437
438 static void
439 populate_base_prog_key(const struct gen_device_info *devinfo,
440 VkPipelineShaderStageCreateFlags flags,
441 struct brw_base_prog_key *key)
442 {
443 if (flags & VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT)
444 key->subgroup_size_type = BRW_SUBGROUP_SIZE_VARYING;
445 else
446 key->subgroup_size_type = BRW_SUBGROUP_SIZE_API_CONSTANT;
447
448 populate_sampler_prog_key(devinfo, &key->tex);
449 }
450
451 static void
452 populate_vs_prog_key(const struct gen_device_info *devinfo,
453 VkPipelineShaderStageCreateFlags flags,
454 struct brw_vs_prog_key *key)
455 {
456 memset(key, 0, sizeof(*key));
457
458 populate_base_prog_key(devinfo, flags, &key->base);
459
460 /* XXX: Handle vertex input work-arounds */
461
462 /* XXX: Handle sampler_prog_key */
463 }
464
465 static void
466 populate_tcs_prog_key(const struct gen_device_info *devinfo,
467 VkPipelineShaderStageCreateFlags flags,
468 unsigned input_vertices,
469 struct brw_tcs_prog_key *key)
470 {
471 memset(key, 0, sizeof(*key));
472
473 populate_base_prog_key(devinfo, flags, &key->base);
474
475 key->input_vertices = input_vertices;
476 }
477
478 static void
479 populate_tes_prog_key(const struct gen_device_info *devinfo,
480 VkPipelineShaderStageCreateFlags flags,
481 struct brw_tes_prog_key *key)
482 {
483 memset(key, 0, sizeof(*key));
484
485 populate_base_prog_key(devinfo, flags, &key->base);
486 }
487
488 static void
489 populate_gs_prog_key(const struct gen_device_info *devinfo,
490 VkPipelineShaderStageCreateFlags flags,
491 struct brw_gs_prog_key *key)
492 {
493 memset(key, 0, sizeof(*key));
494
495 populate_base_prog_key(devinfo, flags, &key->base);
496 }
497
498 static void
499 populate_wm_prog_key(const struct gen_device_info *devinfo,
500 VkPipelineShaderStageCreateFlags flags,
501 const struct anv_subpass *subpass,
502 const VkPipelineMultisampleStateCreateInfo *ms_info,
503 struct brw_wm_prog_key *key)
504 {
505 memset(key, 0, sizeof(*key));
506
507 populate_base_prog_key(devinfo, flags, &key->base);
508
509 /* We set this to 0 here and set to the actual value before we call
510 * brw_compile_fs.
511 */
512 key->input_slots_valid = 0;
513
514 /* Vulkan doesn't specify a default */
515 key->high_quality_derivatives = false;
516
517 /* XXX Vulkan doesn't appear to specify */
518 key->clamp_fragment_color = false;
519
520 key->ignore_sample_mask_out = false;
521
522 assert(subpass->color_count <= MAX_RTS);
523 for (uint32_t i = 0; i < subpass->color_count; i++) {
524 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
525 key->color_outputs_valid |= (1 << i);
526 }
527
528 key->nr_color_regions = subpass->color_count;
529
530 /* To reduce possible shader recompilations we would need to know if
531 * there is a SampleMask output variable to compute if we should emit
532 * code to workaround the issue that hardware disables alpha to coverage
533 * when there is SampleMask output.
534 */
535 key->alpha_to_coverage = ms_info && ms_info->alphaToCoverageEnable;
536
537 /* Vulkan doesn't support fixed-function alpha test */
538 key->alpha_test_replicate_alpha = false;
539
540 if (ms_info) {
541 /* We should probably pull this out of the shader, but it's fairly
542 * harmless to compute it and then let dead-code take care of it.
543 */
544 if (ms_info->rasterizationSamples > 1) {
545 key->persample_interp = ms_info->sampleShadingEnable &&
546 (ms_info->minSampleShading * ms_info->rasterizationSamples) > 1;
547 key->multisample_fbo = true;
548 }
549
550 key->frag_coord_adds_sample_pos = key->persample_interp;
551 }
552 }
553
554 static void
555 populate_cs_prog_key(const struct gen_device_info *devinfo,
556 VkPipelineShaderStageCreateFlags flags,
557 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *rss_info,
558 struct brw_cs_prog_key *key)
559 {
560 memset(key, 0, sizeof(*key));
561
562 populate_base_prog_key(devinfo, flags, &key->base);
563
564 if (rss_info) {
565 assert(key->base.subgroup_size_type != BRW_SUBGROUP_SIZE_VARYING);
566
567 /* These enum values are expressly chosen to be equal to the subgroup
568 * size that they require.
569 */
570 assert(rss_info->requiredSubgroupSize == 8 ||
571 rss_info->requiredSubgroupSize == 16 ||
572 rss_info->requiredSubgroupSize == 32);
573 key->base.subgroup_size_type = rss_info->requiredSubgroupSize;
574 } else if (flags & VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT) {
575 /* If the client expressly requests full subgroups and they don't
576 * specify a subgroup size, we need to pick one. If they're requested
577 * varying subgroup sizes, we set it to UNIFORM and let the back-end
578 * compiler pick. Otherwise, we specify the API value of 32.
579 * Performance will likely be terrible in this case but there's nothing
580 * we can do about that. The client should have chosen a size.
581 */
582 if (flags & VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT)
583 key->base.subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM;
584 else
585 key->base.subgroup_size_type = BRW_SUBGROUP_SIZE_REQUIRE_32;
586 }
587 }
588
589 struct anv_pipeline_stage {
590 gl_shader_stage stage;
591
592 const struct anv_shader_module *module;
593 const char *entrypoint;
594 const VkSpecializationInfo *spec_info;
595
596 unsigned char shader_sha1[20];
597
598 union brw_any_prog_key key;
599
600 struct {
601 gl_shader_stage stage;
602 unsigned char sha1[20];
603 } cache_key;
604
605 nir_shader *nir;
606
607 struct anv_pipeline_binding surface_to_descriptor[256];
608 struct anv_pipeline_binding sampler_to_descriptor[256];
609 struct anv_pipeline_bind_map bind_map;
610
611 union brw_any_prog_data prog_data;
612
613 uint32_t num_stats;
614 struct brw_compile_stats stats[3];
615 char *disasm[3];
616
617 VkPipelineCreationFeedbackEXT feedback;
618
619 const unsigned *code;
620 };
621
622 static void
623 anv_pipeline_hash_shader(const struct anv_shader_module *module,
624 const char *entrypoint,
625 gl_shader_stage stage,
626 const VkSpecializationInfo *spec_info,
627 unsigned char *sha1_out)
628 {
629 struct mesa_sha1 ctx;
630 _mesa_sha1_init(&ctx);
631
632 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
633 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
634 _mesa_sha1_update(&ctx, &stage, sizeof(stage));
635 if (spec_info) {
636 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
637 spec_info->mapEntryCount *
638 sizeof(*spec_info->pMapEntries));
639 _mesa_sha1_update(&ctx, spec_info->pData,
640 spec_info->dataSize);
641 }
642
643 _mesa_sha1_final(&ctx, sha1_out);
644 }
645
646 static void
647 anv_pipeline_hash_graphics(struct anv_graphics_pipeline *pipeline,
648 struct anv_pipeline_layout *layout,
649 struct anv_pipeline_stage *stages,
650 unsigned char *sha1_out)
651 {
652 struct mesa_sha1 ctx;
653 _mesa_sha1_init(&ctx);
654
655 _mesa_sha1_update(&ctx, &pipeline->subpass->view_mask,
656 sizeof(pipeline->subpass->view_mask));
657
658 if (layout)
659 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
660
661 const bool rba = pipeline->base.device->robust_buffer_access;
662 _mesa_sha1_update(&ctx, &rba, sizeof(rba));
663
664 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
665 if (stages[s].entrypoint) {
666 _mesa_sha1_update(&ctx, stages[s].shader_sha1,
667 sizeof(stages[s].shader_sha1));
668 _mesa_sha1_update(&ctx, &stages[s].key, brw_prog_key_size(s));
669 }
670 }
671
672 _mesa_sha1_final(&ctx, sha1_out);
673 }
674
675 static void
676 anv_pipeline_hash_compute(struct anv_compute_pipeline *pipeline,
677 struct anv_pipeline_layout *layout,
678 struct anv_pipeline_stage *stage,
679 unsigned char *sha1_out)
680 {
681 struct mesa_sha1 ctx;
682 _mesa_sha1_init(&ctx);
683
684 if (layout)
685 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
686
687 const bool rba = pipeline->base.device->robust_buffer_access;
688 _mesa_sha1_update(&ctx, &rba, sizeof(rba));
689
690 _mesa_sha1_update(&ctx, stage->shader_sha1,
691 sizeof(stage->shader_sha1));
692 _mesa_sha1_update(&ctx, &stage->key.cs, sizeof(stage->key.cs));
693
694 _mesa_sha1_final(&ctx, sha1_out);
695 }
696
697 static nir_shader *
698 anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
699 struct anv_pipeline_cache *cache,
700 void *mem_ctx,
701 struct anv_pipeline_stage *stage)
702 {
703 const struct brw_compiler *compiler =
704 pipeline->device->physical->compiler;
705 const nir_shader_compiler_options *nir_options =
706 compiler->glsl_compiler_options[stage->stage].NirOptions;
707 nir_shader *nir;
708
709 nir = anv_device_search_for_nir(pipeline->device, cache,
710 nir_options,
711 stage->shader_sha1,
712 mem_ctx);
713 if (nir) {
714 assert(nir->info.stage == stage->stage);
715 return nir;
716 }
717
718 nir = anv_shader_compile_to_nir(pipeline->device,
719 mem_ctx,
720 stage->module,
721 stage->entrypoint,
722 stage->stage,
723 stage->spec_info);
724 if (nir) {
725 anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_sha1);
726 return nir;
727 }
728
729 return NULL;
730 }
731
732 static void
733 anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
734 void *mem_ctx,
735 struct anv_pipeline_stage *stage,
736 struct anv_pipeline_layout *layout)
737 {
738 const struct anv_physical_device *pdevice = pipeline->device->physical;
739 const struct brw_compiler *compiler = pdevice->compiler;
740
741 struct brw_stage_prog_data *prog_data = &stage->prog_data.base;
742 nir_shader *nir = stage->nir;
743
744 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
745 NIR_PASS_V(nir, nir_lower_wpos_center,
746 anv_pipeline_to_graphics(pipeline)->sample_shading_enable);
747 NIR_PASS_V(nir, nir_lower_input_attachments,
748 &(nir_input_attachment_options) {
749 .use_fragcoord_sysval = true,
750 .use_layer_id_sysval = true,
751 });
752 }
753
754 NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);
755
756 if (pipeline->type == ANV_PIPELINE_GRAPHICS) {
757 NIR_PASS_V(nir, anv_nir_lower_multiview,
758 anv_pipeline_to_graphics(pipeline));
759 }
760
761 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
762
763 NIR_PASS_V(nir, brw_nir_lower_image_load_store, compiler->devinfo, NULL);
764
765 NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
766 nir_address_format_64bit_global);
767
768 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
769 anv_nir_apply_pipeline_layout(pdevice,
770 pipeline->device->robust_buffer_access,
771 layout, nir, &stage->bind_map);
772
773 NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ubo,
774 nir_address_format_32bit_index_offset);
775 NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ssbo,
776 anv_nir_ssbo_addr_format(pdevice,
777 pipeline->device->robust_buffer_access));
778
779 NIR_PASS_V(nir, nir_opt_constant_folding);
780
781 /* We don't support non-uniform UBOs and non-uniform SSBO access is
782 * handled naturally by falling back to A64 messages.
783 */
784 NIR_PASS_V(nir, nir_lower_non_uniform_access,
785 nir_lower_non_uniform_texture_access |
786 nir_lower_non_uniform_image_access);
787
788 anv_nir_compute_push_layout(pdevice, pipeline->device->robust_buffer_access,
789 nir, prog_data, &stage->bind_map, mem_ctx);
790
791 stage->nir = nir;
792 }
793
794 static void
795 anv_pipeline_link_vs(const struct brw_compiler *compiler,
796 struct anv_pipeline_stage *vs_stage,
797 struct anv_pipeline_stage *next_stage)
798 {
799 if (next_stage)
800 brw_nir_link_shaders(compiler, vs_stage->nir, next_stage->nir);
801 }
802
803 static void
804 anv_pipeline_compile_vs(const struct brw_compiler *compiler,
805 void *mem_ctx,
806 struct anv_graphics_pipeline *pipeline,
807 struct anv_pipeline_stage *vs_stage)
808 {
809 /* When using Primitive Replication for multiview, each view gets its own
810 * position slot.
811 */
812 uint32_t pos_slots = pipeline->use_primitive_replication ?
813 anv_subpass_view_count(pipeline->subpass) : 1;
814
815 brw_compute_vue_map(compiler->devinfo,
816 &vs_stage->prog_data.vs.base.vue_map,
817 vs_stage->nir->info.outputs_written,
818 vs_stage->nir->info.separate_shader,
819 pos_slots);
820
821 vs_stage->num_stats = 1;
822 vs_stage->code = brw_compile_vs(compiler, pipeline->base.device, mem_ctx,
823 &vs_stage->key.vs,
824 &vs_stage->prog_data.vs,
825 vs_stage->nir, -1,
826 vs_stage->stats, NULL);
827 }
828
829 static void
830 merge_tess_info(struct shader_info *tes_info,
831 const struct shader_info *tcs_info)
832 {
833 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
834 *
835 * "PointMode. Controls generation of points rather than triangles
836 * or lines. This functionality defaults to disabled, and is
837 * enabled if either shader stage includes the execution mode.
838 *
839 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
840 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
841 * and OutputVertices, it says:
842 *
843 * "One mode must be set in at least one of the tessellation
844 * shader stages."
845 *
846 * So, the fields can be set in either the TCS or TES, but they must
847 * agree if set in both. Our backend looks at TES, so bitwise-or in
848 * the values from the TCS.
849 */
850 assert(tcs_info->tess.tcs_vertices_out == 0 ||
851 tes_info->tess.tcs_vertices_out == 0 ||
852 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
853 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
854
855 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
856 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
857 tcs_info->tess.spacing == tes_info->tess.spacing);
858 tes_info->tess.spacing |= tcs_info->tess.spacing;
859
860 assert(tcs_info->tess.primitive_mode == 0 ||
861 tes_info->tess.primitive_mode == 0 ||
862 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
863 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
864 tes_info->tess.ccw |= tcs_info->tess.ccw;
865 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
866 }
867
868 static void
869 anv_pipeline_link_tcs(const struct brw_compiler *compiler,
870 struct anv_pipeline_stage *tcs_stage,
871 struct anv_pipeline_stage *tes_stage)
872 {
873 assert(tes_stage && tes_stage->stage == MESA_SHADER_TESS_EVAL);
874
875 brw_nir_link_shaders(compiler, tcs_stage->nir, tes_stage->nir);
876
877 nir_lower_patch_vertices(tes_stage->nir,
878 tcs_stage->nir->info.tess.tcs_vertices_out,
879 NULL);
880
881 /* Copy TCS info into the TES info */
882 merge_tess_info(&tes_stage->nir->info, &tcs_stage->nir->info);
883
884 /* Whacking the key after cache lookup is a bit sketchy, but all of
885 * this comes from the SPIR-V, which is part of the hash used for the
886 * pipeline cache. So it should be safe.
887 */
888 tcs_stage->key.tcs.tes_primitive_mode =
889 tes_stage->nir->info.tess.primitive_mode;
890 tcs_stage->key.tcs.quads_workaround =
891 compiler->devinfo->gen < 9 &&
892 tes_stage->nir->info.tess.primitive_mode == 7 /* GL_QUADS */ &&
893 tes_stage->nir->info.tess.spacing == TESS_SPACING_EQUAL;
894 }
895
896 static void
897 anv_pipeline_compile_tcs(const struct brw_compiler *compiler,
898 void *mem_ctx,
899 struct anv_device *device,
900 struct anv_pipeline_stage *tcs_stage,
901 struct anv_pipeline_stage *prev_stage)
902 {
903 tcs_stage->key.tcs.outputs_written =
904 tcs_stage->nir->info.outputs_written;
905 tcs_stage->key.tcs.patch_outputs_written =
906 tcs_stage->nir->info.patch_outputs_written;
907
908 tcs_stage->num_stats = 1;
909 tcs_stage->code = brw_compile_tcs(compiler, device, mem_ctx,
910 &tcs_stage->key.tcs,
911 &tcs_stage->prog_data.tcs,
912 tcs_stage->nir, -1,
913 tcs_stage->stats, NULL);
914 }
915
916 static void
917 anv_pipeline_link_tes(const struct brw_compiler *compiler,
918 struct anv_pipeline_stage *tes_stage,
919 struct anv_pipeline_stage *next_stage)
920 {
921 if (next_stage)
922 brw_nir_link_shaders(compiler, tes_stage->nir, next_stage->nir);
923 }
924
925 static void
926 anv_pipeline_compile_tes(const struct brw_compiler *compiler,
927 void *mem_ctx,
928 struct anv_device *device,
929 struct anv_pipeline_stage *tes_stage,
930 struct anv_pipeline_stage *tcs_stage)
931 {
932 tes_stage->key.tes.inputs_read =
933 tcs_stage->nir->info.outputs_written;
934 tes_stage->key.tes.patch_inputs_read =
935 tcs_stage->nir->info.patch_outputs_written;
936
937 tes_stage->num_stats = 1;
938 tes_stage->code = brw_compile_tes(compiler, device, mem_ctx,
939 &tes_stage->key.tes,
940 &tcs_stage->prog_data.tcs.base.vue_map,
941 &tes_stage->prog_data.tes,
942 tes_stage->nir, -1,
943 tes_stage->stats, NULL);
944 }
945
946 static void
947 anv_pipeline_link_gs(const struct brw_compiler *compiler,
948 struct anv_pipeline_stage *gs_stage,
949 struct anv_pipeline_stage *next_stage)
950 {
951 if (next_stage)
952 brw_nir_link_shaders(compiler, gs_stage->nir, next_stage->nir);
953 }
954
955 static void
956 anv_pipeline_compile_gs(const struct brw_compiler *compiler,
957 void *mem_ctx,
958 struct anv_device *device,
959 struct anv_pipeline_stage *gs_stage,
960 struct anv_pipeline_stage *prev_stage)
961 {
962 brw_compute_vue_map(compiler->devinfo,
963 &gs_stage->prog_data.gs.base.vue_map,
964 gs_stage->nir->info.outputs_written,
965 gs_stage->nir->info.separate_shader, 1);
966
967 gs_stage->num_stats = 1;
968 gs_stage->code = brw_compile_gs(compiler, device, mem_ctx,
969 &gs_stage->key.gs,
970 &gs_stage->prog_data.gs,
971 gs_stage->nir, NULL, -1,
972 gs_stage->stats, NULL);
973 }
974
975 static void
976 anv_pipeline_link_fs(const struct brw_compiler *compiler,
977 struct anv_pipeline_stage *stage)
978 {
979 unsigned num_rt_bindings;
980 struct anv_pipeline_binding rt_bindings[MAX_RTS];
981 if (stage->key.wm.nr_color_regions > 0) {
982 assert(stage->key.wm.nr_color_regions <= MAX_RTS);
983 for (unsigned rt = 0; rt < stage->key.wm.nr_color_regions; rt++) {
984 if (stage->key.wm.color_outputs_valid & BITFIELD_BIT(rt)) {
985 rt_bindings[rt] = (struct anv_pipeline_binding) {
986 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
987 .index = rt,
988 };
989 } else {
990 /* Setup a null render target */
991 rt_bindings[rt] = (struct anv_pipeline_binding) {
992 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
993 .index = UINT32_MAX,
994 };
995 }
996 }
997 num_rt_bindings = stage->key.wm.nr_color_regions;
998 } else {
999 /* Setup a null render target */
1000 rt_bindings[0] = (struct anv_pipeline_binding) {
1001 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
1002 .index = UINT32_MAX,
1003 };
1004 num_rt_bindings = 1;
1005 }
1006
1007 assert(num_rt_bindings <= MAX_RTS);
1008 assert(stage->bind_map.surface_count == 0);
1009 typed_memcpy(stage->bind_map.surface_to_descriptor,
1010 rt_bindings, num_rt_bindings);
1011 stage->bind_map.surface_count += num_rt_bindings;
1012
1013 /* Now that we've set up the color attachments, we can go through and
1014 * eliminate any shader outputs that map to VK_ATTACHMENT_UNUSED in the
1015 * hopes that dead code can clean them up in this and any earlier shader
1016 * stages.
1017 */
1018 nir_function_impl *impl = nir_shader_get_entrypoint(stage->nir);
1019 bool deleted_output = false;
1020 nir_foreach_shader_out_variable_safe(var, stage->nir) {
1021 /* TODO: We don't delete depth/stencil writes. We probably could if the
1022 * subpass doesn't have a depth/stencil attachment.
1023 */
1024 if (var->data.location < FRAG_RESULT_DATA0)
1025 continue;
1026
1027 const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
1028
1029 /* If this is the RT at location 0 and we have alpha to coverage
1030 * enabled we still need that write because it will affect the coverage
1031 * mask even if it's never written to a color target.
1032 */
1033 if (rt == 0 && stage->key.wm.alpha_to_coverage)
1034 continue;
1035
1036 const unsigned array_len =
1037 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
1038 assert(rt + array_len <= MAX_RTS);
1039
1040 if (rt >= MAX_RTS || !(stage->key.wm.color_outputs_valid &
1041 BITFIELD_RANGE(rt, array_len))) {
1042 deleted_output = true;
1043 var->data.mode = nir_var_function_temp;
1044 exec_node_remove(&var->node);
1045 exec_list_push_tail(&impl->locals, &var->node);
1046 }
1047 }
1048
1049 if (deleted_output)
1050 nir_fixup_deref_modes(stage->nir);
1051
1052 /* We stored the number of subpass color attachments in nr_color_regions
1053 * when calculating the key for caching. Now that we've computed the bind
1054 * map, we can reduce this to the actual max before we go into the back-end
1055 * compiler.
1056 */
1057 stage->key.wm.nr_color_regions =
1058 util_last_bit(stage->key.wm.color_outputs_valid);
1059 }
1060
1061 static void
1062 anv_pipeline_compile_fs(const struct brw_compiler *compiler,
1063 void *mem_ctx,
1064 struct anv_device *device,
1065 struct anv_pipeline_stage *fs_stage,
1066 struct anv_pipeline_stage *prev_stage)
1067 {
1068 /* TODO: we could set this to 0 based on the information in nir_shader, but
1069 * we need this before we call spirv_to_nir.
1070 */
1071 assert(prev_stage);
1072 fs_stage->key.wm.input_slots_valid =
1073 prev_stage->prog_data.vue.vue_map.slots_valid;
1074
1075 fs_stage->code = brw_compile_fs(compiler, device, mem_ctx,
1076 &fs_stage->key.wm,
1077 &fs_stage->prog_data.wm,
1078 fs_stage->nir, -1, -1, -1,
1079 true, false, NULL,
1080 fs_stage->stats, NULL);
1081
1082 fs_stage->num_stats = (uint32_t)fs_stage->prog_data.wm.dispatch_8 +
1083 (uint32_t)fs_stage->prog_data.wm.dispatch_16 +
1084 (uint32_t)fs_stage->prog_data.wm.dispatch_32;
1085
1086 if (fs_stage->key.wm.color_outputs_valid == 0 &&
1087 !fs_stage->prog_data.wm.has_side_effects &&
1088 !fs_stage->prog_data.wm.uses_omask &&
1089 !fs_stage->key.wm.alpha_to_coverage &&
1090 !fs_stage->prog_data.wm.uses_kill &&
1091 fs_stage->prog_data.wm.computed_depth_mode == BRW_PSCDEPTH_OFF &&
1092 !fs_stage->prog_data.wm.computed_stencil) {
1093 /* This fragment shader has no outputs and no side effects. Go ahead
1094 * and return the code pointer so we don't accidentally think the
1095 * compile failed but zero out prog_data which will set program_size to
1096 * zero and disable the stage.
1097 */
1098 memset(&fs_stage->prog_data, 0, sizeof(fs_stage->prog_data));
1099 }
1100 }
1101
1102 static void
1103 anv_pipeline_add_executable(struct anv_pipeline *pipeline,
1104 struct anv_pipeline_stage *stage,
1105 struct brw_compile_stats *stats,
1106 uint32_t code_offset)
1107 {
1108 char *nir = NULL;
1109 if (stage->nir &&
1110 (pipeline->flags &
1111 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR)) {
1112 char *stream_data = NULL;
1113 size_t stream_size = 0;
1114 FILE *stream = open_memstream(&stream_data, &stream_size);
1115
1116 nir_print_shader(stage->nir, stream);
1117
1118 fclose(stream);
1119
1120 /* Copy it to a ralloc'd thing */
1121 nir = ralloc_size(pipeline->mem_ctx, stream_size + 1);
1122 memcpy(nir, stream_data, stream_size);
1123 nir[stream_size] = 0;
1124
1125 free(stream_data);
1126 }
1127
1128 char *disasm = NULL;
1129 if (stage->code &&
1130 (pipeline->flags &
1131 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR)) {
1132 char *stream_data = NULL;
1133 size_t stream_size = 0;
1134 FILE *stream = open_memstream(&stream_data, &stream_size);
1135
1136 uint32_t push_size = 0;
1137 for (unsigned i = 0; i < 4; i++)
1138 push_size += stage->bind_map.push_ranges[i].length;
1139 if (push_size > 0) {
1140 fprintf(stream, "Push constant ranges:\n");
1141 for (unsigned i = 0; i < 4; i++) {
1142 if (stage->bind_map.push_ranges[i].length == 0)
1143 continue;
1144
1145 fprintf(stream, " RANGE%d (%dB): ", i,
1146 stage->bind_map.push_ranges[i].length * 32);
1147
1148 switch (stage->bind_map.push_ranges[i].set) {
1149 case ANV_DESCRIPTOR_SET_NULL:
1150 fprintf(stream, "NULL");
1151 break;
1152
1153 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS:
1154 fprintf(stream, "Vulkan push constants and API params");
1155 break;
1156
1157 case ANV_DESCRIPTOR_SET_DESCRIPTORS:
1158 fprintf(stream, "Descriptor buffer for set %d (start=%dB)",
1159 stage->bind_map.push_ranges[i].index,
1160 stage->bind_map.push_ranges[i].start * 32);
1161 break;
1162
1163 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS:
1164 unreachable("gl_NumWorkgroups is never pushed");
1165
1166 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS:
1167 fprintf(stream, "Inline shader constant data (start=%dB)",
1168 stage->bind_map.push_ranges[i].start * 32);
1169 break;
1170
1171 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS:
1172 unreachable("Color attachments can't be pushed");
1173
1174 default:
1175 fprintf(stream, "UBO (set=%d binding=%d start=%dB)",
1176 stage->bind_map.push_ranges[i].set,
1177 stage->bind_map.push_ranges[i].index,
1178 stage->bind_map.push_ranges[i].start * 32);
1179 break;
1180 }
1181 fprintf(stream, "\n");
1182 }
1183 fprintf(stream, "\n");
1184 }
1185
1186 /* Creating this is far cheaper than it looks. It's perfectly fine to
1187 * do it for every binary.
1188 */
1189 gen_disassemble(&pipeline->device->info,
1190 stage->code, code_offset, stream);
1191
1192 fclose(stream);
1193
1194 /* Copy it to a ralloc'd thing */
1195 disasm = ralloc_size(pipeline->mem_ctx, stream_size + 1);
1196 memcpy(disasm, stream_data, stream_size);
1197 disasm[stream_size] = 0;
1198
1199 free(stream_data);
1200 }
1201
1202 const struct anv_pipeline_executable exe = {
1203 .stage = stage->stage,
1204 .stats = *stats,
1205 .nir = nir,
1206 .disasm = disasm,
1207 };
1208 util_dynarray_append(&pipeline->executables,
1209 struct anv_pipeline_executable, exe);
1210 }
1211
1212 static void
1213 anv_pipeline_add_executables(struct anv_pipeline *pipeline,
1214 struct anv_pipeline_stage *stage,
1215 struct anv_shader_bin *bin)
1216 {
1217 if (stage->stage == MESA_SHADER_FRAGMENT) {
1218 /* We pull the prog data and stats out of the anv_shader_bin because
1219 * the anv_pipeline_stage may not be fully populated if we successfully
1220 * looked up the shader in a cache.
1221 */
1222 const struct brw_wm_prog_data *wm_prog_data =
1223 (const struct brw_wm_prog_data *)bin->prog_data;
1224 struct brw_compile_stats *stats = bin->stats;
1225
1226 if (wm_prog_data->dispatch_8) {
1227 anv_pipeline_add_executable(pipeline, stage, stats++, 0);
1228 }
1229
1230 if (wm_prog_data->dispatch_16) {
1231 anv_pipeline_add_executable(pipeline, stage, stats++,
1232 wm_prog_data->prog_offset_16);
1233 }
1234
1235 if (wm_prog_data->dispatch_32) {
1236 anv_pipeline_add_executable(pipeline, stage, stats++,
1237 wm_prog_data->prog_offset_32);
1238 }
1239 } else {
1240 anv_pipeline_add_executable(pipeline, stage, bin->stats, 0);
1241 }
1242 }
1243
1244 static void
1245 anv_pipeline_init_from_cached_graphics(struct anv_graphics_pipeline *pipeline)
1246 {
1247 /* TODO: Cache this pipeline-wide information. */
1248
1249 /* Primitive replication depends on information from all the shaders.
1250 * Recover this bit from the fact that we have more than one position slot
1251 * in the vertex shader when using it.
1252 */
1253 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1254 int pos_slots = 0;
1255 const struct brw_vue_prog_data *vue_prog_data =
1256 (const void *) pipeline->shaders[MESA_SHADER_VERTEX]->prog_data;
1257 const struct brw_vue_map *vue_map = &vue_prog_data->vue_map;
1258 for (int i = 0; i < vue_map->num_slots; i++) {
1259 if (vue_map->slot_to_varying[i] == VARYING_SLOT_POS)
1260 pos_slots++;
1261 }
1262 pipeline->use_primitive_replication = pos_slots > 1;
1263 }
1264
1265 static VkResult
1266 anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
1267 struct anv_pipeline_cache *cache,
1268 const VkGraphicsPipelineCreateInfo *info)
1269 {
1270 VkPipelineCreationFeedbackEXT pipeline_feedback = {
1271 .flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT,
1272 };
1273 int64_t pipeline_start = os_time_get_nano();
1274
1275 const struct brw_compiler *compiler = pipeline->base.device->physical->compiler;
1276 struct anv_pipeline_stage stages[MESA_SHADER_STAGES] = {};
1277
1278 pipeline->active_stages = 0;
1279
1280 VkResult result;
1281 for (uint32_t i = 0; i < info->stageCount; i++) {
1282 const VkPipelineShaderStageCreateInfo *sinfo = &info->pStages[i];
1283 gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
1284
1285 pipeline->active_stages |= sinfo->stage;
1286
1287 int64_t stage_start = os_time_get_nano();
1288
1289 stages[stage].stage = stage;
1290 stages[stage].module = anv_shader_module_from_handle(sinfo->module);
1291 stages[stage].entrypoint = sinfo->pName;
1292 stages[stage].spec_info = sinfo->pSpecializationInfo;
1293 anv_pipeline_hash_shader(stages[stage].module,
1294 stages[stage].entrypoint,
1295 stage,
1296 stages[stage].spec_info,
1297 stages[stage].shader_sha1);
1298
1299 const struct gen_device_info *devinfo = &pipeline->base.device->info;
1300 switch (stage) {
1301 case MESA_SHADER_VERTEX:
1302 populate_vs_prog_key(devinfo, sinfo->flags, &stages[stage].key.vs);
1303 break;
1304 case MESA_SHADER_TESS_CTRL:
1305 populate_tcs_prog_key(devinfo, sinfo->flags,
1306 info->pTessellationState->patchControlPoints,
1307 &stages[stage].key.tcs);
1308 break;
1309 case MESA_SHADER_TESS_EVAL:
1310 populate_tes_prog_key(devinfo, sinfo->flags, &stages[stage].key.tes);
1311 break;
1312 case MESA_SHADER_GEOMETRY:
1313 populate_gs_prog_key(devinfo, sinfo->flags, &stages[stage].key.gs);
1314 break;
1315 case MESA_SHADER_FRAGMENT: {
1316 const bool raster_enabled =
1317 !info->pRasterizationState->rasterizerDiscardEnable;
1318 populate_wm_prog_key(devinfo, sinfo->flags,
1319 pipeline->subpass,
1320 raster_enabled ? info->pMultisampleState : NULL,
1321 &stages[stage].key.wm);
1322 break;
1323 }
1324 default:
1325 unreachable("Invalid graphics shader stage");
1326 }
1327
1328 stages[stage].feedback.duration += os_time_get_nano() - stage_start;
1329 stages[stage].feedback.flags |= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
1330 }
1331
1332 if (pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)
1333 pipeline->active_stages |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
1334
1335 assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT);
1336
1337 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1338
1339 unsigned char sha1[20];
1340 anv_pipeline_hash_graphics(pipeline, layout, stages, sha1);
1341
1342 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1343 if (!stages[s].entrypoint)
1344 continue;
1345
1346 stages[s].cache_key.stage = s;
1347 memcpy(stages[s].cache_key.sha1, sha1, sizeof(sha1));
1348 }
1349
1350 const bool skip_cache_lookup =
1351 (pipeline->base.flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR);
1352
1353 if (!skip_cache_lookup) {
1354 unsigned found = 0;
1355 unsigned cache_hits = 0;
1356 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1357 if (!stages[s].entrypoint)
1358 continue;
1359
1360 int64_t stage_start = os_time_get_nano();
1361
1362 bool cache_hit;
1363 struct anv_shader_bin *bin =
1364 anv_device_search_for_kernel(pipeline->base.device, cache,
1365 &stages[s].cache_key,
1366 sizeof(stages[s].cache_key), &cache_hit);
1367 if (bin) {
1368 found++;
1369 pipeline->shaders[s] = bin;
1370 }
1371
1372 if (cache_hit) {
1373 cache_hits++;
1374 stages[s].feedback.flags |=
1375 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT;
1376 }
1377 stages[s].feedback.duration += os_time_get_nano() - stage_start;
1378 }
1379
1380 if (found == __builtin_popcount(pipeline->active_stages)) {
1381 if (cache_hits == found) {
1382 pipeline_feedback.flags |=
1383 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT;
1384 }
1385 /* We found all our shaders in the cache. We're done. */
1386 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1387 if (!stages[s].entrypoint)
1388 continue;
1389
1390 anv_pipeline_add_executables(&pipeline->base, &stages[s],
1391 pipeline->shaders[s]);
1392 }
1393 anv_pipeline_init_from_cached_graphics(pipeline);
1394 goto done;
1395 } else if (found > 0) {
1396 /* We found some but not all of our shaders. This shouldn't happen
1397 * most of the time but it can if we have a partially populated
1398 * pipeline cache.
1399 */
1400 assert(found < __builtin_popcount(pipeline->active_stages));
1401
1402 vk_debug_report(&pipeline->base.device->physical->instance->debug_report_callbacks,
1403 VK_DEBUG_REPORT_WARNING_BIT_EXT |
1404 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT,
1405 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT,
1406 (uint64_t)(uintptr_t)cache,
1407 0, 0, "anv",
1408 "Found a partial pipeline in the cache. This is "
1409 "most likely caused by an incomplete pipeline cache "
1410 "import or export");
1411
1412 /* We're going to have to recompile anyway, so just throw away our
1413 * references to the shaders in the cache. We'll get them out of the
1414 * cache again as part of the compilation process.
1415 */
1416 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1417 stages[s].feedback.flags = 0;
1418 if (pipeline->shaders[s]) {
1419 anv_shader_bin_unref(pipeline->base.device, pipeline->shaders[s]);
1420 pipeline->shaders[s] = NULL;
1421 }
1422 }
1423 }
1424 }
1425
1426 if (info->flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT)
1427 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
1428
1429 void *pipeline_ctx = ralloc_context(NULL);
1430
1431 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1432 if (!stages[s].entrypoint)
1433 continue;
1434
1435 int64_t stage_start = os_time_get_nano();
1436
1437 assert(stages[s].stage == s);
1438 assert(pipeline->shaders[s] == NULL);
1439
1440 stages[s].bind_map = (struct anv_pipeline_bind_map) {
1441 .surface_to_descriptor = stages[s].surface_to_descriptor,
1442 .sampler_to_descriptor = stages[s].sampler_to_descriptor
1443 };
1444
1445 stages[s].nir = anv_pipeline_stage_get_nir(&pipeline->base, cache,
1446 pipeline_ctx,
1447 &stages[s]);
1448 if (stages[s].nir == NULL) {
1449 result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1450 goto fail;
1451 }
1452
1453 stages[s].feedback.duration += os_time_get_nano() - stage_start;
1454 }
1455
1456 /* Walk backwards to link */
1457 struct anv_pipeline_stage *next_stage = NULL;
1458 for (int s = MESA_SHADER_STAGES - 1; s >= 0; s--) {
1459 if (!stages[s].entrypoint)
1460 continue;
1461
1462 switch (s) {
1463 case MESA_SHADER_VERTEX:
1464 anv_pipeline_link_vs(compiler, &stages[s], next_stage);
1465 break;
1466 case MESA_SHADER_TESS_CTRL:
1467 anv_pipeline_link_tcs(compiler, &stages[s], next_stage);
1468 break;
1469 case MESA_SHADER_TESS_EVAL:
1470 anv_pipeline_link_tes(compiler, &stages[s], next_stage);
1471 break;
1472 case MESA_SHADER_GEOMETRY:
1473 anv_pipeline_link_gs(compiler, &stages[s], next_stage);
1474 break;
1475 case MESA_SHADER_FRAGMENT:
1476 anv_pipeline_link_fs(compiler, &stages[s]);
1477 break;
1478 default:
1479 unreachable("Invalid graphics shader stage");
1480 }
1481
1482 next_stage = &stages[s];
1483 }
1484
1485 if (pipeline->base.device->info.gen >= 12 &&
1486 pipeline->subpass->view_mask != 0) {
1487 /* For some pipelines HW Primitive Replication can be used instead of
1488 * instancing to implement Multiview. This depend on how viewIndex is
1489 * used in all the active shaders, so this check can't be done per
1490 * individual shaders.
1491 */
1492 nir_shader *shaders[MESA_SHADER_STAGES] = {};
1493 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++)
1494 shaders[s] = stages[s].nir;
1495
1496 pipeline->use_primitive_replication =
1497 anv_check_for_primitive_replication(shaders, pipeline);
1498 } else {
1499 pipeline->use_primitive_replication = false;
1500 }
1501
1502 struct anv_pipeline_stage *prev_stage = NULL;
1503 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1504 if (!stages[s].entrypoint)
1505 continue;
1506
1507 int64_t stage_start = os_time_get_nano();
1508
1509 void *stage_ctx = ralloc_context(NULL);
1510
1511 anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
1512
1513 if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) {
1514 prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
1515 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
1516 stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &
1517 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
1518 prev_stage->nir->info.patch_outputs_written |= stages[s].nir->info.patch_inputs_read;
1519 stages[s].nir->info.patch_inputs_read |= prev_stage->nir->info.patch_outputs_written;
1520 }
1521
1522 ralloc_free(stage_ctx);
1523
1524 stages[s].feedback.duration += os_time_get_nano() - stage_start;
1525
1526 prev_stage = &stages[s];
1527 }
1528
1529 prev_stage = NULL;
1530 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1531 if (!stages[s].entrypoint)
1532 continue;
1533
1534 int64_t stage_start = os_time_get_nano();
1535
1536 void *stage_ctx = ralloc_context(NULL);
1537
1538 nir_xfb_info *xfb_info = NULL;
1539 if (s == MESA_SHADER_VERTEX ||
1540 s == MESA_SHADER_TESS_EVAL ||
1541 s == MESA_SHADER_GEOMETRY)
1542 xfb_info = nir_gather_xfb_info(stages[s].nir, stage_ctx);
1543
1544 switch (s) {
1545 case MESA_SHADER_VERTEX:
1546 anv_pipeline_compile_vs(compiler, stage_ctx, pipeline,
1547 &stages[s]);
1548 break;
1549 case MESA_SHADER_TESS_CTRL:
1550 anv_pipeline_compile_tcs(compiler, stage_ctx, pipeline->base.device,
1551 &stages[s], prev_stage);
1552 break;
1553 case MESA_SHADER_TESS_EVAL:
1554 anv_pipeline_compile_tes(compiler, stage_ctx, pipeline->base.device,
1555 &stages[s], prev_stage);
1556 break;
1557 case MESA_SHADER_GEOMETRY:
1558 anv_pipeline_compile_gs(compiler, stage_ctx, pipeline->base.device,
1559 &stages[s], prev_stage);
1560 break;
1561 case MESA_SHADER_FRAGMENT:
1562 anv_pipeline_compile_fs(compiler, stage_ctx, pipeline->base.device,
1563 &stages[s], prev_stage);
1564 break;
1565 default:
1566 unreachable("Invalid graphics shader stage");
1567 }
1568 if (stages[s].code == NULL) {
1569 ralloc_free(stage_ctx);
1570 result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1571 goto fail;
1572 }
1573
1574 anv_nir_validate_push_layout(&stages[s].prog_data.base,
1575 &stages[s].bind_map);
1576
1577 struct anv_shader_bin *bin =
1578 anv_device_upload_kernel(pipeline->base.device, cache, s,
1579 &stages[s].cache_key,
1580 sizeof(stages[s].cache_key),
1581 stages[s].code,
1582 stages[s].prog_data.base.program_size,
1583 &stages[s].prog_data.base,
1584 brw_prog_data_size(s),
1585 stages[s].stats, stages[s].num_stats,
1586 xfb_info, &stages[s].bind_map);
1587 if (!bin) {
1588 ralloc_free(stage_ctx);
1589 result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1590 goto fail;
1591 }
1592
1593 anv_pipeline_add_executables(&pipeline->base, &stages[s], bin);
1594
1595 pipeline->shaders[s] = bin;
1596 ralloc_free(stage_ctx);
1597
1598 stages[s].feedback.duration += os_time_get_nano() - stage_start;
1599
1600 prev_stage = &stages[s];
1601 }
1602
1603 ralloc_free(pipeline_ctx);
1604
1605 done:
1606
1607 if (pipeline->shaders[MESA_SHADER_FRAGMENT] &&
1608 pipeline->shaders[MESA_SHADER_FRAGMENT]->prog_data->program_size == 0) {
1609 /* This can happen if we decided to implicitly disable the fragment
1610 * shader. See anv_pipeline_compile_fs().
1611 */
1612 anv_shader_bin_unref(pipeline->base.device,
1613 pipeline->shaders[MESA_SHADER_FRAGMENT]);
1614 pipeline->shaders[MESA_SHADER_FRAGMENT] = NULL;
1615 pipeline->active_stages &= ~VK_SHADER_STAGE_FRAGMENT_BIT;
1616 }
1617
1618 pipeline_feedback.duration = os_time_get_nano() - pipeline_start;
1619
1620 const VkPipelineCreationFeedbackCreateInfoEXT *create_feedback =
1621 vk_find_struct_const(info->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
1622 if (create_feedback) {
1623 *create_feedback->pPipelineCreationFeedback = pipeline_feedback;
1624
1625 assert(info->stageCount == create_feedback->pipelineStageCreationFeedbackCount);
1626 for (uint32_t i = 0; i < info->stageCount; i++) {
1627 gl_shader_stage s = vk_to_mesa_shader_stage(info->pStages[i].stage);
1628 create_feedback->pPipelineStageCreationFeedbacks[i] = stages[s].feedback;
1629 }
1630 }
1631
1632 return VK_SUCCESS;
1633
1634 fail:
1635 ralloc_free(pipeline_ctx);
1636
1637 for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
1638 if (pipeline->shaders[s])
1639 anv_shader_bin_unref(pipeline->base.device, pipeline->shaders[s]);
1640 }
1641
1642 return result;
1643 }
1644
1645 static void
1646 shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align)
1647 {
1648 assert(glsl_type_is_vector_or_scalar(type));
1649
1650 uint32_t comp_size = glsl_type_is_boolean(type)
1651 ? 4 : glsl_get_bit_size(type) / 8;
1652 unsigned length = glsl_get_vector_elements(type);
1653 *size = comp_size * length,
1654 *align = comp_size * (length == 3 ? 4 : length);
1655 }
1656
1657 VkResult
1658 anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
1659 struct anv_pipeline_cache *cache,
1660 const VkComputePipelineCreateInfo *info,
1661 const struct anv_shader_module *module,
1662 const char *entrypoint,
1663 const VkSpecializationInfo *spec_info)
1664 {
1665 VkPipelineCreationFeedbackEXT pipeline_feedback = {
1666 .flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT,
1667 };
1668 int64_t pipeline_start = os_time_get_nano();
1669
1670 const struct brw_compiler *compiler = pipeline->base.device->physical->compiler;
1671
1672 struct anv_pipeline_stage stage = {
1673 .stage = MESA_SHADER_COMPUTE,
1674 .module = module,
1675 .entrypoint = entrypoint,
1676 .spec_info = spec_info,
1677 .cache_key = {
1678 .stage = MESA_SHADER_COMPUTE,
1679 },
1680 .feedback = {
1681 .flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT,
1682 },
1683 };
1684 anv_pipeline_hash_shader(stage.module,
1685 stage.entrypoint,
1686 MESA_SHADER_COMPUTE,
1687 stage.spec_info,
1688 stage.shader_sha1);
1689
1690 struct anv_shader_bin *bin = NULL;
1691
1692 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *rss_info =
1693 vk_find_struct_const(info->stage.pNext,
1694 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
1695
1696 populate_cs_prog_key(&pipeline->base.device->info, info->stage.flags,
1697 rss_info, &stage.key.cs);
1698
1699 ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
1700
1701 const bool skip_cache_lookup =
1702 (pipeline->base.flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR);
1703
1704 anv_pipeline_hash_compute(pipeline, layout, &stage, stage.cache_key.sha1);
1705
1706 bool cache_hit = false;
1707 if (!skip_cache_lookup) {
1708 bin = anv_device_search_for_kernel(pipeline->base.device, cache,
1709 &stage.cache_key,
1710 sizeof(stage.cache_key),
1711 &cache_hit);
1712 }
1713
1714 if (bin == NULL &&
1715 (info->flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT))
1716 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
1717
1718 void *mem_ctx = ralloc_context(NULL);
1719 if (bin == NULL) {
1720 int64_t stage_start = os_time_get_nano();
1721
1722 stage.bind_map = (struct anv_pipeline_bind_map) {
1723 .surface_to_descriptor = stage.surface_to_descriptor,
1724 .sampler_to_descriptor = stage.sampler_to_descriptor
1725 };
1726
1727 /* Set up a binding for the gl_NumWorkGroups */
1728 stage.bind_map.surface_count = 1;
1729 stage.bind_map.surface_to_descriptor[0] = (struct anv_pipeline_binding) {
1730 .set = ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS,
1731 };
1732
1733 stage.nir = anv_pipeline_stage_get_nir(&pipeline->base, cache, mem_ctx, &stage);
1734 if (stage.nir == NULL) {
1735 ralloc_free(mem_ctx);
1736 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1737 }
1738
1739 NIR_PASS_V(stage.nir, anv_nir_add_base_work_group_id);
1740
1741 anv_pipeline_lower_nir(&pipeline->base, mem_ctx, &stage, layout);
1742
1743 NIR_PASS_V(stage.nir, nir_lower_vars_to_explicit_types,
1744 nir_var_mem_shared, shared_type_info);
1745 NIR_PASS_V(stage.nir, nir_lower_explicit_io,
1746 nir_var_mem_shared, nir_address_format_32bit_offset);
1747 NIR_PASS_V(stage.nir, brw_nir_lower_cs_intrinsics);
1748
1749 stage.num_stats = 1;
1750 stage.code = brw_compile_cs(compiler, pipeline->base.device, mem_ctx,
1751 &stage.key.cs, &stage.prog_data.cs,
1752 stage.nir, -1, stage.stats, NULL);
1753 if (stage.code == NULL) {
1754 ralloc_free(mem_ctx);
1755 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1756 }
1757
1758 anv_nir_validate_push_layout(&stage.prog_data.base, &stage.bind_map);
1759
1760 if (!stage.prog_data.cs.uses_num_work_groups) {
1761 assert(stage.bind_map.surface_to_descriptor[0].set ==
1762 ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS);
1763 stage.bind_map.surface_to_descriptor[0].set = ANV_DESCRIPTOR_SET_NULL;
1764 }
1765
1766 const unsigned code_size = stage.prog_data.base.program_size;
1767 bin = anv_device_upload_kernel(pipeline->base.device, cache,
1768 MESA_SHADER_COMPUTE,
1769 &stage.cache_key, sizeof(stage.cache_key),
1770 stage.code, code_size,
1771 &stage.prog_data.base,
1772 sizeof(stage.prog_data.cs),
1773 stage.stats, stage.num_stats,
1774 NULL, &stage.bind_map);
1775 if (!bin) {
1776 ralloc_free(mem_ctx);
1777 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1778 }
1779
1780 stage.feedback.duration = os_time_get_nano() - stage_start;
1781 }
1782
1783 anv_pipeline_add_executables(&pipeline->base, &stage, bin);
1784
1785 ralloc_free(mem_ctx);
1786
1787 if (cache_hit) {
1788 stage.feedback.flags |=
1789 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT;
1790 pipeline_feedback.flags |=
1791 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT;
1792 }
1793 pipeline_feedback.duration = os_time_get_nano() - pipeline_start;
1794
1795 const VkPipelineCreationFeedbackCreateInfoEXT *create_feedback =
1796 vk_find_struct_const(info->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
1797 if (create_feedback) {
1798 *create_feedback->pPipelineCreationFeedback = pipeline_feedback;
1799
1800 assert(create_feedback->pipelineStageCreationFeedbackCount == 1);
1801 create_feedback->pPipelineStageCreationFeedbacks[0] = stage.feedback;
1802 }
1803
1804 pipeline->cs = bin;
1805
1806 return VK_SUCCESS;
1807 }
1808
1809 struct anv_cs_parameters
1810 anv_cs_parameters(const struct anv_compute_pipeline *pipeline)
1811 {
1812 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
1813
1814 struct anv_cs_parameters cs_params = {};
1815
1816 cs_params.group_size = cs_prog_data->local_size[0] *
1817 cs_prog_data->local_size[1] *
1818 cs_prog_data->local_size[2];
1819 cs_params.simd_size =
1820 brw_cs_simd_size_for_group_size(&pipeline->base.device->info,
1821 cs_prog_data, cs_params.group_size);
1822 cs_params.threads = DIV_ROUND_UP(cs_params.group_size, cs_params.simd_size);
1823
1824 return cs_params;
1825 }
1826
1827 /**
1828 * Copy pipeline state not marked as dynamic.
1829 * Dynamic state is pipeline state which hasn't been provided at pipeline
1830 * creation time, but is dynamically provided afterwards using various
1831 * vkCmdSet* functions.
1832 *
1833 * The set of state considered "non_dynamic" is determined by the pieces of
1834 * state that have their corresponding VkDynamicState enums omitted from
1835 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1836 *
1837 * @param[out] pipeline Destination non_dynamic state.
1838 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1839 */
1840 static void
1841 copy_non_dynamic_state(struct anv_graphics_pipeline *pipeline,
1842 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1843 {
1844 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
1845 struct anv_subpass *subpass = pipeline->subpass;
1846
1847 pipeline->dynamic_state = default_dynamic_state;
1848
1849 if (pCreateInfo->pDynamicState) {
1850 /* Remove all of the states that are marked as dynamic */
1851 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1852 for (uint32_t s = 0; s < count; s++) {
1853 states &= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1854 pCreateInfo->pDynamicState->pDynamicStates[s]);
1855 }
1856 }
1857
1858 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
1859
1860 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1861 *
1862 * pViewportState is [...] NULL if the pipeline
1863 * has rasterization disabled.
1864 */
1865 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1866 assert(pCreateInfo->pViewportState);
1867
1868 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1869 if (states & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT) {
1870 typed_memcpy(dynamic->viewport.viewports,
1871 pCreateInfo->pViewportState->pViewports,
1872 pCreateInfo->pViewportState->viewportCount);
1873 }
1874
1875 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1876 if (states & ANV_CMD_DIRTY_DYNAMIC_SCISSOR) {
1877 typed_memcpy(dynamic->scissor.scissors,
1878 pCreateInfo->pViewportState->pScissors,
1879 pCreateInfo->pViewportState->scissorCount);
1880 }
1881 }
1882
1883 if (states & ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
1884 assert(pCreateInfo->pRasterizationState);
1885 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1886 }
1887
1888 if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS) {
1889 assert(pCreateInfo->pRasterizationState);
1890 dynamic->depth_bias.bias =
1891 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1892 dynamic->depth_bias.clamp =
1893 pCreateInfo->pRasterizationState->depthBiasClamp;
1894 dynamic->depth_bias.slope =
1895 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1896 }
1897
1898 if (states & ANV_CMD_DIRTY_DYNAMIC_CULL_MODE) {
1899 assert(pCreateInfo->pRasterizationState);
1900 dynamic->cull_mode =
1901 pCreateInfo->pRasterizationState->cullMode;
1902 }
1903
1904 if (states & ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE) {
1905 assert(pCreateInfo->pRasterizationState);
1906 dynamic->front_face =
1907 pCreateInfo->pRasterizationState->frontFace;
1908 }
1909
1910 if (states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1911 assert(pCreateInfo->pInputAssemblyState);
1912 bool has_tess = false;
1913 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1914 const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i];
1915 gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
1916 if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_TESS_EVAL)
1917 has_tess = true;
1918 }
1919 if (has_tess) {
1920 const VkPipelineTessellationStateCreateInfo *tess_info =
1921 pCreateInfo->pTessellationState;
1922 dynamic->primitive_topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1923 } else {
1924 dynamic->primitive_topology = pCreateInfo->pInputAssemblyState->topology;
1925 }
1926 }
1927
1928 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1929 *
1930 * pColorBlendState is [...] NULL if the pipeline has rasterization
1931 * disabled or if the subpass of the render pass the pipeline is
1932 * created against does not use any color attachments.
1933 */
1934 bool uses_color_att = false;
1935 for (unsigned i = 0; i < subpass->color_count; ++i) {
1936 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1937 uses_color_att = true;
1938 break;
1939 }
1940 }
1941
1942 if (uses_color_att &&
1943 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1944 assert(pCreateInfo->pColorBlendState);
1945
1946 if (states & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1947 typed_memcpy(dynamic->blend_constants,
1948 pCreateInfo->pColorBlendState->blendConstants, 4);
1949 }
1950
1951 /* If there is no depthstencil attachment, then don't read
1952 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1953 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1954 * no need to override the depthstencil defaults in
1955 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1956 *
1957 * Section 9.2 of the Vulkan 1.0.15 spec says:
1958 *
1959 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1960 * disabled or if the subpass of the render pass the pipeline is created
1961 * against does not use a depth/stencil attachment.
1962 */
1963 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1964 subpass->depth_stencil_attachment) {
1965 assert(pCreateInfo->pDepthStencilState);
1966
1967 if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS) {
1968 dynamic->depth_bounds.min =
1969 pCreateInfo->pDepthStencilState->minDepthBounds;
1970 dynamic->depth_bounds.max =
1971 pCreateInfo->pDepthStencilState->maxDepthBounds;
1972 }
1973
1974 if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) {
1975 dynamic->stencil_compare_mask.front =
1976 pCreateInfo->pDepthStencilState->front.compareMask;
1977 dynamic->stencil_compare_mask.back =
1978 pCreateInfo->pDepthStencilState->back.compareMask;
1979 }
1980
1981 if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) {
1982 dynamic->stencil_write_mask.front =
1983 pCreateInfo->pDepthStencilState->front.writeMask;
1984 dynamic->stencil_write_mask.back =
1985 pCreateInfo->pDepthStencilState->back.writeMask;
1986 }
1987
1988 if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) {
1989 dynamic->stencil_reference.front =
1990 pCreateInfo->pDepthStencilState->front.reference;
1991 dynamic->stencil_reference.back =
1992 pCreateInfo->pDepthStencilState->back.reference;
1993 }
1994
1995 if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE) {
1996 dynamic->depth_test_enable =
1997 pCreateInfo->pDepthStencilState->depthTestEnable;
1998 }
1999
2000 if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE) {
2001 dynamic->depth_write_enable =
2002 pCreateInfo->pDepthStencilState->depthWriteEnable;
2003 }
2004
2005 if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP) {
2006 dynamic->depth_compare_op =
2007 pCreateInfo->pDepthStencilState->depthCompareOp;
2008 }
2009
2010 if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
2011 dynamic->depth_bounds_test_enable =
2012 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
2013 }
2014
2015 if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE) {
2016 dynamic->stencil_test_enable =
2017 pCreateInfo->pDepthStencilState->stencilTestEnable;
2018 }
2019
2020 if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP) {
2021 const VkPipelineDepthStencilStateCreateInfo *info =
2022 pCreateInfo->pDepthStencilState;
2023 memcpy(&dynamic->stencil_op.front, &info->front,
2024 sizeof(dynamic->stencil_op.front));
2025 memcpy(&dynamic->stencil_op.back, &info->back,
2026 sizeof(dynamic->stencil_op.back));
2027 }
2028 }
2029
2030 const VkPipelineRasterizationLineStateCreateInfoEXT *line_state =
2031 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
2032 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
2033 if (line_state) {
2034 if (states & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
2035 dynamic->line_stipple.factor = line_state->lineStippleFactor;
2036 dynamic->line_stipple.pattern = line_state->lineStipplePattern;
2037 }
2038 }
2039
2040 pipeline->dynamic_state_mask = states;
2041 }
2042
2043 static void
2044 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
2045 {
2046 #ifdef DEBUG
2047 struct anv_render_pass *renderpass = NULL;
2048 struct anv_subpass *subpass = NULL;
2049
2050 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
2051 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
2052 */
2053 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
2054
2055 renderpass = anv_render_pass_from_handle(info->renderPass);
2056 assert(renderpass);
2057
2058 assert(info->subpass < renderpass->subpass_count);
2059 subpass = &renderpass->subpasses[info->subpass];
2060
2061 assert(info->stageCount >= 1);
2062 assert(info->pVertexInputState);
2063 assert(info->pInputAssemblyState);
2064 assert(info->pRasterizationState);
2065 if (!info->pRasterizationState->rasterizerDiscardEnable) {
2066 assert(info->pViewportState);
2067 assert(info->pMultisampleState);
2068
2069 if (subpass && subpass->depth_stencil_attachment)
2070 assert(info->pDepthStencilState);
2071
2072 if (subpass && subpass->color_count > 0) {
2073 bool all_color_unused = true;
2074 for (int i = 0; i < subpass->color_count; i++) {
2075 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2076 all_color_unused = false;
2077 }
2078 /* pColorBlendState is ignored if the pipeline has rasterization
2079 * disabled or if the subpass of the render pass the pipeline is
2080 * created against does not use any color attachments.
2081 */
2082 assert(info->pColorBlendState || all_color_unused);
2083 }
2084 }
2085
2086 for (uint32_t i = 0; i < info->stageCount; ++i) {
2087 switch (info->pStages[i].stage) {
2088 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
2089 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
2090 assert(info->pTessellationState);
2091 break;
2092 default:
2093 break;
2094 }
2095 }
2096 #endif
2097 }
2098
2099 /**
2100 * Calculate the desired L3 partitioning based on the current state of the
2101 * pipeline. For now this simply returns the conservative defaults calculated
2102 * by get_default_l3_weights(), but we could probably do better by gathering
2103 * more statistics from the pipeline state (e.g. guess of expected URB usage
2104 * and bound surfaces), or by using feed-back from performance counters.
2105 */
2106 void
2107 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
2108 {
2109 const struct gen_device_info *devinfo = &pipeline->device->info;
2110
2111 const struct gen_l3_weights w =
2112 gen_get_default_l3_weights(devinfo, true, needs_slm);
2113
2114 pipeline->l3_config = gen_get_l3_config(devinfo, w);
2115 }
2116
2117 VkResult
2118 anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline,
2119 struct anv_device *device,
2120 struct anv_pipeline_cache *cache,
2121 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2122 const VkAllocationCallbacks *alloc)
2123 {
2124 VkResult result;
2125
2126 anv_pipeline_validate_create_info(pCreateInfo);
2127
2128 result = anv_pipeline_init(&pipeline->base, device,
2129 ANV_PIPELINE_GRAPHICS, pCreateInfo->flags,
2130 alloc);
2131 if (result != VK_SUCCESS)
2132 return result;
2133
2134 anv_batch_set_storage(&pipeline->base.batch, ANV_NULL_ADDRESS,
2135 pipeline->batch_data, sizeof(pipeline->batch_data));
2136
2137 ANV_FROM_HANDLE(anv_render_pass, render_pass, pCreateInfo->renderPass);
2138 assert(pCreateInfo->subpass < render_pass->subpass_count);
2139 pipeline->subpass = &render_pass->subpasses[pCreateInfo->subpass];
2140
2141 assert(pCreateInfo->pRasterizationState);
2142
2143 copy_non_dynamic_state(pipeline, pCreateInfo);
2144 pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState->depthClampEnable;
2145
2146 /* Previously we enabled depth clipping when !depthClampEnable.
2147 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
2148 * clipping info is available, use its enable value to determine clipping,
2149 * otherwise fallback to the previous !depthClampEnable logic.
2150 */
2151 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *clip_info =
2152 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
2153 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
2154 pipeline->depth_clip_enable = clip_info ? clip_info->depthClipEnable : !pipeline->depth_clamp_enable;
2155
2156 pipeline->sample_shading_enable =
2157 !pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
2158 pCreateInfo->pMultisampleState &&
2159 pCreateInfo->pMultisampleState->sampleShadingEnable;
2160
2161 /* When we free the pipeline, we detect stages based on the NULL status
2162 * of various prog_data pointers. Make them NULL by default.
2163 */
2164 memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
2165
2166 result = anv_pipeline_compile_graphics(pipeline, cache, pCreateInfo);
2167 if (result != VK_SUCCESS) {
2168 anv_pipeline_finish(&pipeline->base, device, alloc);
2169 return result;
2170 }
2171
2172 assert(pipeline->shaders[MESA_SHADER_VERTEX]);
2173
2174 anv_pipeline_setup_l3_config(&pipeline->base, false);
2175
2176 const VkPipelineVertexInputStateCreateInfo *vi_info =
2177 pCreateInfo->pVertexInputState;
2178
2179 const uint64_t inputs_read = get_vs_prog_data(pipeline)->inputs_read;
2180
2181 pipeline->vb_used = 0;
2182 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2183 const VkVertexInputAttributeDescription *desc =
2184 &vi_info->pVertexAttributeDescriptions[i];
2185
2186 if (inputs_read & (1ull << (VERT_ATTRIB_GENERIC0 + desc->location)))
2187 pipeline->vb_used |= 1 << desc->binding;
2188 }
2189
2190 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2191 const VkVertexInputBindingDescription *desc =
2192 &vi_info->pVertexBindingDescriptions[i];
2193
2194 pipeline->vb[desc->binding].stride = desc->stride;
2195
2196 /* Step rate is programmed per vertex element (attribute), not
2197 * binding. Set up a map of which bindings step per instance, for
2198 * reference by vertex element setup. */
2199 switch (desc->inputRate) {
2200 default:
2201 case VK_VERTEX_INPUT_RATE_VERTEX:
2202 pipeline->vb[desc->binding].instanced = false;
2203 break;
2204 case VK_VERTEX_INPUT_RATE_INSTANCE:
2205 pipeline->vb[desc->binding].instanced = true;
2206 break;
2207 }
2208
2209 pipeline->vb[desc->binding].instance_divisor = 1;
2210 }
2211
2212 const VkPipelineVertexInputDivisorStateCreateInfoEXT *vi_div_state =
2213 vk_find_struct_const(vi_info->pNext,
2214 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2215 if (vi_div_state) {
2216 for (uint32_t i = 0; i < vi_div_state->vertexBindingDivisorCount; i++) {
2217 const VkVertexInputBindingDivisorDescriptionEXT *desc =
2218 &vi_div_state->pVertexBindingDivisors[i];
2219
2220 pipeline->vb[desc->binding].instance_divisor = desc->divisor;
2221 }
2222 }
2223
2224 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2225 * different views. If the client asks for instancing, we need to multiply
2226 * the instance divisor by the number of views ensure that we repeat the
2227 * client's per-instance data once for each view.
2228 */
2229 if (pipeline->subpass->view_mask && !pipeline->use_primitive_replication) {
2230 const uint32_t view_count = anv_subpass_view_count(pipeline->subpass);
2231 for (uint32_t vb = 0; vb < MAX_VBS; vb++) {
2232 if (pipeline->vb[vb].instanced)
2233 pipeline->vb[vb].instance_divisor *= view_count;
2234 }
2235 }
2236
2237 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2238 pCreateInfo->pInputAssemblyState;
2239 const VkPipelineTessellationStateCreateInfo *tess_info =
2240 pCreateInfo->pTessellationState;
2241 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
2242
2243 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2244 pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
2245 else
2246 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
2247
2248 return VK_SUCCESS;
2249 }
2250
2251 #define WRITE_STR(field, ...) ({ \
2252 memset(field, 0, sizeof(field)); \
2253 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
2254 assert(i > 0 && i < sizeof(field)); \
2255 })
2256
2257 VkResult anv_GetPipelineExecutablePropertiesKHR(
2258 VkDevice device,
2259 const VkPipelineInfoKHR* pPipelineInfo,
2260 uint32_t* pExecutableCount,
2261 VkPipelineExecutablePropertiesKHR* pProperties)
2262 {
2263 ANV_FROM_HANDLE(anv_pipeline, pipeline, pPipelineInfo->pipeline);
2264 VK_OUTARRAY_MAKE(out, pProperties, pExecutableCount);
2265
2266 util_dynarray_foreach (&pipeline->executables, struct anv_pipeline_executable, exe) {
2267 vk_outarray_append(&out, props) {
2268 gl_shader_stage stage = exe->stage;
2269 props->stages = mesa_to_vk_shader_stage(stage);
2270
2271 unsigned simd_width = exe->stats.dispatch_width;
2272 if (stage == MESA_SHADER_FRAGMENT) {
2273 WRITE_STR(props->name, "%s%d %s",
2274 simd_width ? "SIMD" : "vec",
2275 simd_width ? simd_width : 4,
2276 _mesa_shader_stage_to_string(stage));
2277 } else {
2278 WRITE_STR(props->name, "%s", _mesa_shader_stage_to_string(stage));
2279 }
2280 WRITE_STR(props->description, "%s%d %s shader",
2281 simd_width ? "SIMD" : "vec",
2282 simd_width ? simd_width : 4,
2283 _mesa_shader_stage_to_string(stage));
2284
2285 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2286 * wants a subgroup size of 1.
2287 */
2288 props->subgroupSize = MAX2(simd_width, 1);
2289 }
2290 }
2291
2292 return vk_outarray_status(&out);
2293 }
2294
2295 static const struct anv_pipeline_executable *
2296 anv_pipeline_get_executable(struct anv_pipeline *pipeline, uint32_t index)
2297 {
2298 assert(index < util_dynarray_num_elements(&pipeline->executables,
2299 struct anv_pipeline_executable));
2300 return util_dynarray_element(
2301 &pipeline->executables, struct anv_pipeline_executable, index);
2302 }
2303
2304 VkResult anv_GetPipelineExecutableStatisticsKHR(
2305 VkDevice device,
2306 const VkPipelineExecutableInfoKHR* pExecutableInfo,
2307 uint32_t* pStatisticCount,
2308 VkPipelineExecutableStatisticKHR* pStatistics)
2309 {
2310 ANV_FROM_HANDLE(anv_pipeline, pipeline, pExecutableInfo->pipeline);
2311 VK_OUTARRAY_MAKE(out, pStatistics, pStatisticCount);
2312
2313 const struct anv_pipeline_executable *exe =
2314 anv_pipeline_get_executable(pipeline, pExecutableInfo->executableIndex);
2315
2316 const struct brw_stage_prog_data *prog_data;
2317 switch (pipeline->type) {
2318 case ANV_PIPELINE_GRAPHICS: {
2319 prog_data = anv_pipeline_to_graphics(pipeline)->shaders[exe->stage]->prog_data;
2320 break;
2321 }
2322 case ANV_PIPELINE_COMPUTE: {
2323 prog_data = anv_pipeline_to_compute(pipeline)->cs->prog_data;
2324 break;
2325 }
2326 default:
2327 unreachable("invalid pipeline type");
2328 }
2329
2330 vk_outarray_append(&out, stat) {
2331 WRITE_STR(stat->name, "Instruction Count");
2332 WRITE_STR(stat->description,
2333 "Number of GEN instructions in the final generated "
2334 "shader executable.");
2335 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2336 stat->value.u64 = exe->stats.instructions;
2337 }
2338
2339 vk_outarray_append(&out, stat) {
2340 WRITE_STR(stat->name, "SEND Count");
2341 WRITE_STR(stat->description,
2342 "Number of instructions in the final generated shader "
2343 "executable which access external units such as the "
2344 "constant cache or the sampler.");
2345 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2346 stat->value.u64 = exe->stats.sends;
2347 }
2348
2349 vk_outarray_append(&out, stat) {
2350 WRITE_STR(stat->name, "Loop Count");
2351 WRITE_STR(stat->description,
2352 "Number of loops (not unrolled) in the final generated "
2353 "shader executable.");
2354 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2355 stat->value.u64 = exe->stats.loops;
2356 }
2357
2358 vk_outarray_append(&out, stat) {
2359 WRITE_STR(stat->name, "Cycle Count");
2360 WRITE_STR(stat->description,
2361 "Estimate of the number of EU cycles required to execute "
2362 "the final generated executable. This is an estimate only "
2363 "and may vary greatly from actual run-time performance.");
2364 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2365 stat->value.u64 = exe->stats.cycles;
2366 }
2367
2368 vk_outarray_append(&out, stat) {
2369 WRITE_STR(stat->name, "Spill Count");
2370 WRITE_STR(stat->description,
2371 "Number of scratch spill operations. This gives a rough "
2372 "estimate of the cost incurred due to spilling temporary "
2373 "values to memory. If this is non-zero, you may want to "
2374 "adjust your shader to reduce register pressure.");
2375 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2376 stat->value.u64 = exe->stats.spills;
2377 }
2378
2379 vk_outarray_append(&out, stat) {
2380 WRITE_STR(stat->name, "Fill Count");
2381 WRITE_STR(stat->description,
2382 "Number of scratch fill operations. This gives a rough "
2383 "estimate of the cost incurred due to spilling temporary "
2384 "values to memory. If this is non-zero, you may want to "
2385 "adjust your shader to reduce register pressure.");
2386 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2387 stat->value.u64 = exe->stats.fills;
2388 }
2389
2390 vk_outarray_append(&out, stat) {
2391 WRITE_STR(stat->name, "Scratch Memory Size");
2392 WRITE_STR(stat->description,
2393 "Number of bytes of scratch memory required by the "
2394 "generated shader executable. If this is non-zero, you "
2395 "may want to adjust your shader to reduce register "
2396 "pressure.");
2397 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2398 stat->value.u64 = prog_data->total_scratch;
2399 }
2400
2401 if (exe->stage == MESA_SHADER_COMPUTE) {
2402 vk_outarray_append(&out, stat) {
2403 WRITE_STR(stat->name, "Workgroup Memory Size");
2404 WRITE_STR(stat->description,
2405 "Number of bytes of workgroup shared memory used by this "
2406 "compute shader including any padding.");
2407 stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
2408 stat->value.u64 = brw_cs_prog_data_const(prog_data)->slm_size;
2409 }
2410 }
2411
2412 return vk_outarray_status(&out);
2413 }
2414
2415 static bool
2416 write_ir_text(VkPipelineExecutableInternalRepresentationKHR* ir,
2417 const char *data)
2418 {
2419 ir->isText = VK_TRUE;
2420
2421 size_t data_len = strlen(data) + 1;
2422
2423 if (ir->pData == NULL) {
2424 ir->dataSize = data_len;
2425 return true;
2426 }
2427
2428 strncpy(ir->pData, data, ir->dataSize);
2429 if (ir->dataSize < data_len)
2430 return false;
2431
2432 ir->dataSize = data_len;
2433 return true;
2434 }
2435
2436 VkResult anv_GetPipelineExecutableInternalRepresentationsKHR(
2437 VkDevice device,
2438 const VkPipelineExecutableInfoKHR* pExecutableInfo,
2439 uint32_t* pInternalRepresentationCount,
2440 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
2441 {
2442 ANV_FROM_HANDLE(anv_pipeline, pipeline, pExecutableInfo->pipeline);
2443 VK_OUTARRAY_MAKE(out, pInternalRepresentations,
2444 pInternalRepresentationCount);
2445 bool incomplete_text = false;
2446
2447 const struct anv_pipeline_executable *exe =
2448 anv_pipeline_get_executable(pipeline, pExecutableInfo->executableIndex);
2449
2450 if (exe->nir) {
2451 vk_outarray_append(&out, ir) {
2452 WRITE_STR(ir->name, "Final NIR");
2453 WRITE_STR(ir->description,
2454 "Final NIR before going into the back-end compiler");
2455
2456 if (!write_ir_text(ir, exe->nir))
2457 incomplete_text = true;
2458 }
2459 }
2460
2461 if (exe->disasm) {
2462 vk_outarray_append(&out, ir) {
2463 WRITE_STR(ir->name, "GEN Assembly");
2464 WRITE_STR(ir->description,
2465 "Final GEN assembly for the generated shader binary");
2466
2467 if (!write_ir_text(ir, exe->disasm))
2468 incomplete_text = true;
2469 }
2470 }
2471
2472 return incomplete_text ? VK_INCOMPLETE : vk_outarray_status(&out);
2473 }