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Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / intel / vulkan / anv_pipeline.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "util/mesa-sha1.h"
31 #include "anv_private.h"
32 #include "brw_nir.h"
33 #include "anv_nir.h"
34 #include "spirv/nir_spirv.h"
35
36 /* Needed for SWIZZLE macros */
37 #include "program/prog_instruction.h"
38
39 // Shader functions
40
41 VkResult anv_CreateShaderModule(
42 VkDevice _device,
43 const VkShaderModuleCreateInfo* pCreateInfo,
44 const VkAllocationCallbacks* pAllocator,
45 VkShaderModule* pShaderModule)
46 {
47 ANV_FROM_HANDLE(anv_device, device, _device);
48 struct anv_shader_module *module;
49
50 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
51 assert(pCreateInfo->flags == 0);
52
53 module = anv_alloc2(&device->alloc, pAllocator,
54 sizeof(*module) + pCreateInfo->codeSize, 8,
55 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
56 if (module == NULL)
57 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
58
59 module->nir = NULL;
60 module->size = pCreateInfo->codeSize;
61 memcpy(module->data, pCreateInfo->pCode, module->size);
62
63 _mesa_sha1_compute(module->data, module->size, module->sha1);
64
65 *pShaderModule = anv_shader_module_to_handle(module);
66
67 return VK_SUCCESS;
68 }
69
70 void anv_DestroyShaderModule(
71 VkDevice _device,
72 VkShaderModule _module,
73 const VkAllocationCallbacks* pAllocator)
74 {
75 ANV_FROM_HANDLE(anv_device, device, _device);
76 ANV_FROM_HANDLE(anv_shader_module, module, _module);
77
78 anv_free2(&device->alloc, pAllocator, module);
79 }
80
81 #define SPIR_V_MAGIC_NUMBER 0x07230203
82
83 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
84 * we can't do that yet because we don't have the ability to copy nir.
85 */
86 static nir_shader *
87 anv_shader_compile_to_nir(struct anv_device *device,
88 struct anv_shader_module *module,
89 const char *entrypoint_name,
90 gl_shader_stage stage,
91 const VkSpecializationInfo *spec_info)
92 {
93 if (strcmp(entrypoint_name, "main") != 0) {
94 anv_finishme("Multiple shaders per module not really supported");
95 }
96
97 const struct brw_compiler *compiler =
98 device->instance->physicalDevice.compiler;
99 const nir_shader_compiler_options *nir_options =
100 compiler->glsl_compiler_options[stage].NirOptions;
101
102 nir_shader *nir;
103 nir_function *entry_point;
104 if (module->nir) {
105 /* Some things such as our meta clear/blit code will give us a NIR
106 * shader directly. In that case, we just ignore the SPIR-V entirely
107 * and just use the NIR shader */
108 nir = module->nir;
109 nir->options = nir_options;
110 nir_validate_shader(nir);
111
112 assert(exec_list_length(&nir->functions) == 1);
113 struct exec_node *node = exec_list_get_head(&nir->functions);
114 entry_point = exec_node_data(nir_function, node, node);
115 } else {
116 uint32_t *spirv = (uint32_t *) module->data;
117 assert(spirv[0] == SPIR_V_MAGIC_NUMBER);
118 assert(module->size % 4 == 0);
119
120 uint32_t num_spec_entries = 0;
121 struct nir_spirv_specialization *spec_entries = NULL;
122 if (spec_info && spec_info->mapEntryCount > 0) {
123 num_spec_entries = spec_info->mapEntryCount;
124 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
125 for (uint32_t i = 0; i < num_spec_entries; i++) {
126 const uint32_t *data =
127 spec_info->pData + spec_info->pMapEntries[i].offset;
128 assert((const void *)(data + 1) <=
129 spec_info->pData + spec_info->dataSize);
130
131 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
132 spec_entries[i].data = *data;
133 }
134 }
135
136 entry_point = spirv_to_nir(spirv, module->size / 4,
137 spec_entries, num_spec_entries,
138 stage, entrypoint_name, nir_options);
139 nir = entry_point->shader;
140 assert(nir->stage == stage);
141 nir_validate_shader(nir);
142
143 free(spec_entries);
144
145 nir_lower_returns(nir);
146 nir_validate_shader(nir);
147
148 nir_inline_functions(nir);
149 nir_validate_shader(nir);
150
151 /* Pick off the single entrypoint that we want */
152 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
153 if (func != entry_point)
154 exec_node_remove(&func->node);
155 }
156 assert(exec_list_length(&nir->functions) == 1);
157 entry_point->name = ralloc_strdup(entry_point, "main");
158
159 nir_remove_dead_variables(nir, nir_var_shader_in);
160 nir_remove_dead_variables(nir, nir_var_shader_out);
161 nir_remove_dead_variables(nir, nir_var_system_value);
162 nir_validate_shader(nir);
163
164 nir_lower_outputs_to_temporaries(entry_point->shader, entry_point);
165
166 nir_lower_system_values(nir);
167 nir_validate_shader(nir);
168 }
169
170 /* Vulkan uses the separate-shader linking model */
171 nir->info.separate_shader = true;
172
173 nir = brw_preprocess_nir(compiler, nir);
174
175 nir_shader_gather_info(nir, entry_point->impl);
176
177 nir_variable_mode indirect_mask = 0;
178 if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
179 indirect_mask |= nir_var_shader_in;
180 if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
181 indirect_mask |= nir_var_local;
182
183 nir_lower_indirect_derefs(nir, indirect_mask);
184
185 return nir;
186 }
187
188 void anv_DestroyPipeline(
189 VkDevice _device,
190 VkPipeline _pipeline,
191 const VkAllocationCallbacks* pAllocator)
192 {
193 ANV_FROM_HANDLE(anv_device, device, _device);
194 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
195
196 anv_reloc_list_finish(&pipeline->batch_relocs,
197 pAllocator ? pAllocator : &device->alloc);
198 if (pipeline->blend_state.map)
199 anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
200 anv_free2(&device->alloc, pAllocator, pipeline);
201 }
202
203 static const uint32_t vk_to_gen_primitive_type[] = {
204 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
205 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
206 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
207 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
208 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
209 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
210 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY] = _3DPRIM_LINELIST_ADJ,
211 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
212 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
213 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
214 /* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
215 };
216
217 static void
218 populate_sampler_prog_key(const struct brw_device_info *devinfo,
219 struct brw_sampler_prog_key_data *key)
220 {
221 /* XXX: Handle texture swizzle on HSW- */
222 for (int i = 0; i < MAX_SAMPLERS; i++) {
223 /* Assume color sampler, no swizzling. (Works for BDW+) */
224 key->swizzles[i] = SWIZZLE_XYZW;
225 }
226 }
227
228 static void
229 populate_vs_prog_key(const struct brw_device_info *devinfo,
230 struct brw_vs_prog_key *key)
231 {
232 memset(key, 0, sizeof(*key));
233
234 populate_sampler_prog_key(devinfo, &key->tex);
235
236 /* XXX: Handle vertex input work-arounds */
237
238 /* XXX: Handle sampler_prog_key */
239 }
240
241 static void
242 populate_gs_prog_key(const struct brw_device_info *devinfo,
243 struct brw_gs_prog_key *key)
244 {
245 memset(key, 0, sizeof(*key));
246
247 populate_sampler_prog_key(devinfo, &key->tex);
248 }
249
250 static void
251 populate_wm_prog_key(const struct brw_device_info *devinfo,
252 const VkGraphicsPipelineCreateInfo *info,
253 const struct anv_graphics_pipeline_create_info *extra,
254 struct brw_wm_prog_key *key)
255 {
256 ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
257
258 memset(key, 0, sizeof(*key));
259
260 populate_sampler_prog_key(devinfo, &key->tex);
261
262 /* TODO: Fill out key->input_slots_valid */
263
264 /* Vulkan doesn't specify a default */
265 key->high_quality_derivatives = false;
266
267 /* XXX Vulkan doesn't appear to specify */
268 key->clamp_fragment_color = false;
269
270 /* Vulkan always specifies upper-left coordinates */
271 key->drawable_height = 0;
272 key->render_to_fbo = false;
273
274 if (extra && extra->color_attachment_count >= 0) {
275 key->nr_color_regions = extra->color_attachment_count;
276 } else {
277 key->nr_color_regions =
278 render_pass->subpasses[info->subpass].color_count;
279 }
280
281 key->replicate_alpha = key->nr_color_regions > 1 &&
282 info->pMultisampleState &&
283 info->pMultisampleState->alphaToCoverageEnable;
284
285 if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
286 /* We should probably pull this out of the shader, but it's fairly
287 * harmless to compute it and then let dead-code take care of it.
288 */
289 key->persample_shading = info->pMultisampleState->sampleShadingEnable;
290 if (key->persample_shading)
291 key->persample_2x = info->pMultisampleState->rasterizationSamples == 2;
292
293 key->compute_pos_offset = info->pMultisampleState->sampleShadingEnable;
294 key->compute_sample_id = info->pMultisampleState->sampleShadingEnable;
295 }
296 }
297
298 static void
299 populate_cs_prog_key(const struct brw_device_info *devinfo,
300 struct brw_cs_prog_key *key)
301 {
302 memset(key, 0, sizeof(*key));
303
304 populate_sampler_prog_key(devinfo, &key->tex);
305 }
306
307 static nir_shader *
308 anv_pipeline_compile(struct anv_pipeline *pipeline,
309 struct anv_shader_module *module,
310 const char *entrypoint,
311 gl_shader_stage stage,
312 const VkSpecializationInfo *spec_info,
313 struct brw_stage_prog_data *prog_data,
314 struct anv_pipeline_bind_map *map)
315 {
316 const struct brw_compiler *compiler =
317 pipeline->device->instance->physicalDevice.compiler;
318
319 nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
320 module, entrypoint, stage,
321 spec_info);
322 if (nir == NULL)
323 return NULL;
324
325 anv_nir_lower_push_constants(nir, compiler->scalar_stage[stage]);
326
327 /* Figure out the number of parameters */
328 prog_data->nr_params = 0;
329
330 if (nir->num_uniforms > 0) {
331 /* If the shader uses any push constants at all, we'll just give
332 * them the maximum possible number
333 */
334 prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
335 }
336
337 if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
338 prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
339
340 if (nir->info.num_images > 0)
341 prog_data->nr_params += nir->info.num_images * BRW_IMAGE_PARAM_SIZE;
342
343 if (prog_data->nr_params > 0) {
344 /* XXX: I think we're leaking this */
345 prog_data->param = (const union gl_constant_value **)
346 malloc(prog_data->nr_params * sizeof(union gl_constant_value *));
347
348 /* We now set the param values to be offsets into a
349 * anv_push_constant_data structure. Since the compiler doesn't
350 * actually dereference any of the gl_constant_value pointers in the
351 * params array, it doesn't really matter what we put here.
352 */
353 struct anv_push_constants *null_data = NULL;
354 if (nir->num_uniforms > 0) {
355 /* Fill out the push constants section of the param array */
356 for (unsigned i = 0; i < MAX_PUSH_CONSTANTS_SIZE / sizeof(float); i++)
357 prog_data->param[i] = (const union gl_constant_value *)
358 &null_data->client_data[i * sizeof(float)];
359 }
360 }
361
362 /* Set up dynamic offsets */
363 anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
364
365 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
366 if (pipeline->layout)
367 anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
368
369 /* nir_lower_io will only handle the push constants; we need to set this
370 * to the full number of possible uniforms.
371 */
372 nir->num_uniforms = prog_data->nr_params * 4;
373
374 return nir;
375 }
376
377 static void
378 anv_fill_binding_table(struct brw_stage_prog_data *prog_data, unsigned bias)
379 {
380 prog_data->binding_table.size_bytes = 0;
381 prog_data->binding_table.texture_start = bias;
382 prog_data->binding_table.ubo_start = bias;
383 prog_data->binding_table.ssbo_start = bias;
384 prog_data->binding_table.image_start = bias;
385 }
386
387 static void
388 anv_pipeline_add_compiled_stage(struct anv_pipeline *pipeline,
389 gl_shader_stage stage,
390 const struct brw_stage_prog_data *prog_data,
391 struct anv_pipeline_bind_map *map)
392 {
393 struct brw_device_info *devinfo = &pipeline->device->info;
394 uint32_t max_threads[] = {
395 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
396 [MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
397 [MESA_SHADER_TESS_EVAL] = devinfo->max_ds_threads,
398 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
399 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
400 [MESA_SHADER_COMPUTE] = devinfo->max_cs_threads,
401 };
402
403 pipeline->prog_data[stage] = prog_data;
404 pipeline->active_stages |= mesa_to_vk_shader_stage(stage);
405 pipeline->scratch_start[stage] = pipeline->total_scratch;
406 pipeline->total_scratch =
407 align_u32(pipeline->total_scratch, 1024) +
408 prog_data->total_scratch * max_threads[stage];
409 pipeline->bindings[stage] = *map;
410 }
411
412 static VkResult
413 anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
414 struct anv_pipeline_cache *cache,
415 const VkGraphicsPipelineCreateInfo *info,
416 struct anv_shader_module *module,
417 const char *entrypoint,
418 const VkSpecializationInfo *spec_info)
419 {
420 const struct brw_compiler *compiler =
421 pipeline->device->instance->physicalDevice.compiler;
422 const struct brw_stage_prog_data *stage_prog_data;
423 struct anv_pipeline_bind_map map;
424 struct brw_vs_prog_key key;
425 uint32_t kernel = NO_KERNEL;
426 unsigned char sha1[20];
427
428 populate_vs_prog_key(&pipeline->device->info, &key);
429
430 if (module->size > 0) {
431 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
432 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
433 }
434
435 if (kernel == NO_KERNEL) {
436 struct brw_vs_prog_data prog_data = { 0, };
437 struct anv_pipeline_binding surface_to_descriptor[256];
438 struct anv_pipeline_binding sampler_to_descriptor[256];
439
440 map = (struct anv_pipeline_bind_map) {
441 .surface_to_descriptor = surface_to_descriptor,
442 .sampler_to_descriptor = sampler_to_descriptor
443 };
444
445 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
446 MESA_SHADER_VERTEX, spec_info,
447 &prog_data.base.base, &map);
448 if (nir == NULL)
449 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
450
451 anv_fill_binding_table(&prog_data.base.base, 0);
452
453 void *mem_ctx = ralloc_context(NULL);
454
455 if (module->nir == NULL)
456 ralloc_steal(mem_ctx, nir);
457
458 prog_data.inputs_read = nir->info.inputs_read;
459
460 brw_compute_vue_map(&pipeline->device->info,
461 &prog_data.base.vue_map,
462 nir->info.outputs_written,
463 nir->info.separate_shader);
464
465 unsigned code_size;
466 const unsigned *shader_code =
467 brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
468 NULL, false, -1, &code_size, NULL);
469 if (shader_code == NULL) {
470 ralloc_free(mem_ctx);
471 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
472 }
473
474 stage_prog_data = &prog_data.base.base;
475 kernel = anv_pipeline_cache_upload_kernel(cache,
476 module->size > 0 ? sha1 : NULL,
477 shader_code, code_size,
478 &stage_prog_data, sizeof(prog_data),
479 &map);
480 ralloc_free(mem_ctx);
481 }
482
483 const struct brw_vs_prog_data *vs_prog_data =
484 (const struct brw_vs_prog_data *) stage_prog_data;
485
486 if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
487 pipeline->vs_simd8 = kernel;
488 pipeline->vs_vec4 = NO_KERNEL;
489 } else {
490 pipeline->vs_simd8 = NO_KERNEL;
491 pipeline->vs_vec4 = kernel;
492 }
493
494 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX,
495 stage_prog_data, &map);
496
497 return VK_SUCCESS;
498 }
499
500 static VkResult
501 anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
502 struct anv_pipeline_cache *cache,
503 const VkGraphicsPipelineCreateInfo *info,
504 struct anv_shader_module *module,
505 const char *entrypoint,
506 const VkSpecializationInfo *spec_info)
507 {
508 const struct brw_compiler *compiler =
509 pipeline->device->instance->physicalDevice.compiler;
510 const struct brw_stage_prog_data *stage_prog_data;
511 struct anv_pipeline_bind_map map;
512 struct brw_gs_prog_key key;
513 uint32_t kernel = NO_KERNEL;
514 unsigned char sha1[20];
515
516 populate_gs_prog_key(&pipeline->device->info, &key);
517
518 if (module->size > 0) {
519 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
520 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
521 }
522
523 if (kernel == NO_KERNEL) {
524 struct brw_gs_prog_data prog_data = { 0, };
525 struct anv_pipeline_binding surface_to_descriptor[256];
526 struct anv_pipeline_binding sampler_to_descriptor[256];
527
528 map = (struct anv_pipeline_bind_map) {
529 .surface_to_descriptor = surface_to_descriptor,
530 .sampler_to_descriptor = sampler_to_descriptor
531 };
532
533 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
534 MESA_SHADER_GEOMETRY, spec_info,
535 &prog_data.base.base, &map);
536 if (nir == NULL)
537 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
538
539 anv_fill_binding_table(&prog_data.base.base, 0);
540
541 void *mem_ctx = ralloc_context(NULL);
542
543 if (module->nir == NULL)
544 ralloc_steal(mem_ctx, nir);
545
546 brw_compute_vue_map(&pipeline->device->info,
547 &prog_data.base.vue_map,
548 nir->info.outputs_written,
549 nir->info.separate_shader);
550
551 unsigned code_size;
552 const unsigned *shader_code =
553 brw_compile_gs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
554 NULL, -1, &code_size, NULL);
555 if (shader_code == NULL) {
556 ralloc_free(mem_ctx);
557 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
558 }
559
560 /* TODO: SIMD8 GS */
561 stage_prog_data = &prog_data.base.base;
562 kernel = anv_pipeline_cache_upload_kernel(cache,
563 module->size > 0 ? sha1 : NULL,
564 shader_code, code_size,
565 &stage_prog_data, sizeof(prog_data),
566 &map);
567
568 ralloc_free(mem_ctx);
569 }
570
571 pipeline->gs_kernel = kernel;
572
573 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY,
574 stage_prog_data, &map);
575
576 return VK_SUCCESS;
577 }
578
579 static VkResult
580 anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
581 struct anv_pipeline_cache *cache,
582 const VkGraphicsPipelineCreateInfo *info,
583 const struct anv_graphics_pipeline_create_info *extra,
584 struct anv_shader_module *module,
585 const char *entrypoint,
586 const VkSpecializationInfo *spec_info)
587 {
588 const struct brw_compiler *compiler =
589 pipeline->device->instance->physicalDevice.compiler;
590 const struct brw_stage_prog_data *stage_prog_data;
591 struct anv_pipeline_bind_map map;
592 struct brw_wm_prog_key key;
593 uint32_t kernel = NO_KERNEL;
594 unsigned char sha1[20];
595
596 populate_wm_prog_key(&pipeline->device->info, info, extra, &key);
597
598 if (module->size > 0) {
599 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
600 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
601 }
602
603 if (kernel == NO_KERNEL) {
604 struct brw_wm_prog_data prog_data = { 0, };
605 struct anv_pipeline_binding surface_to_descriptor[256];
606 struct anv_pipeline_binding sampler_to_descriptor[256];
607
608 map = (struct anv_pipeline_bind_map) {
609 .surface_to_descriptor = surface_to_descriptor + 8,
610 .sampler_to_descriptor = sampler_to_descriptor
611 };
612
613 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
614 MESA_SHADER_FRAGMENT, spec_info,
615 &prog_data.base, &map);
616 if (nir == NULL)
617 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
618
619 unsigned num_rts = 0;
620 struct anv_pipeline_binding rt_bindings[8];
621 nir_function_impl *impl = nir_shader_get_entrypoint(nir)->impl;
622 nir_foreach_variable_safe(var, &nir->outputs) {
623 if (var->data.location < FRAG_RESULT_DATA0)
624 continue;
625
626 unsigned rt = var->data.location - FRAG_RESULT_DATA0;
627 if (rt >= key.nr_color_regions) {
628 /* Out-of-bounds, throw it away */
629 var->data.mode = nir_var_local;
630 exec_node_remove(&var->node);
631 exec_list_push_tail(&impl->locals, &var->node);
632 continue;
633 }
634
635 /* Give it a new, compacted, location */
636 var->data.location = FRAG_RESULT_DATA0 + num_rts;
637
638 unsigned array_len =
639 glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
640 assert(num_rts + array_len <= 8);
641
642 for (unsigned i = 0; i < array_len; i++) {
643 rt_bindings[num_rts] = (struct anv_pipeline_binding) {
644 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
645 .offset = rt + i,
646 };
647 }
648
649 num_rts += array_len;
650 }
651
652 if (pipeline->use_repclear) {
653 assert(num_rts == 1);
654 key.nr_color_regions = 1;
655 }
656
657 if (num_rts == 0) {
658 /* If we have no render targets, we need a null render target */
659 rt_bindings[0] = (struct anv_pipeline_binding) {
660 .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
661 .offset = UINT16_MAX,
662 };
663 num_rts = 1;
664 }
665
666 assert(num_rts <= 8);
667 map.surface_to_descriptor -= num_rts;
668 map.surface_count += num_rts;
669 assert(map.surface_count <= 256);
670 memcpy(map.surface_to_descriptor, rt_bindings,
671 num_rts * sizeof(*rt_bindings));
672
673 anv_fill_binding_table(&prog_data.base, num_rts);
674
675 void *mem_ctx = ralloc_context(NULL);
676
677 if (module->nir == NULL)
678 ralloc_steal(mem_ctx, nir);
679
680 unsigned code_size;
681 const unsigned *shader_code =
682 brw_compile_fs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
683 NULL, -1, -1, pipeline->use_repclear, &code_size, NULL);
684 if (shader_code == NULL) {
685 ralloc_free(mem_ctx);
686 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
687 }
688
689 stage_prog_data = &prog_data.base;
690 kernel = anv_pipeline_cache_upload_kernel(cache,
691 module->size > 0 ? sha1 : NULL,
692 shader_code, code_size,
693 &stage_prog_data, sizeof(prog_data),
694 &map);
695
696 ralloc_free(mem_ctx);
697 }
698
699 const struct brw_wm_prog_data *wm_prog_data =
700 (const struct brw_wm_prog_data *) stage_prog_data;
701
702 if (wm_prog_data->no_8)
703 pipeline->ps_simd8 = NO_KERNEL;
704 else
705 pipeline->ps_simd8 = kernel;
706
707 if (wm_prog_data->no_8 || wm_prog_data->prog_offset_16) {
708 pipeline->ps_simd16 = kernel + wm_prog_data->prog_offset_16;
709 } else {
710 pipeline->ps_simd16 = NO_KERNEL;
711 }
712
713 pipeline->ps_ksp2 = 0;
714 pipeline->ps_grf_start2 = 0;
715 if (pipeline->ps_simd8 != NO_KERNEL) {
716 pipeline->ps_ksp0 = pipeline->ps_simd8;
717 pipeline->ps_grf_start0 = wm_prog_data->base.dispatch_grf_start_reg;
718 if (pipeline->ps_simd16 != NO_KERNEL) {
719 pipeline->ps_ksp2 = pipeline->ps_simd16;
720 pipeline->ps_grf_start2 = wm_prog_data->dispatch_grf_start_reg_16;
721 }
722 } else if (pipeline->ps_simd16 != NO_KERNEL) {
723 pipeline->ps_ksp0 = pipeline->ps_simd16;
724 pipeline->ps_grf_start0 = wm_prog_data->dispatch_grf_start_reg_16;
725 }
726
727 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT,
728 stage_prog_data, &map);
729
730 return VK_SUCCESS;
731 }
732
733 VkResult
734 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
735 struct anv_pipeline_cache *cache,
736 const VkComputePipelineCreateInfo *info,
737 struct anv_shader_module *module,
738 const char *entrypoint,
739 const VkSpecializationInfo *spec_info)
740 {
741 const struct brw_compiler *compiler =
742 pipeline->device->instance->physicalDevice.compiler;
743 const struct brw_stage_prog_data *stage_prog_data;
744 struct anv_pipeline_bind_map map;
745 struct brw_cs_prog_key key;
746 uint32_t kernel = NO_KERNEL;
747 unsigned char sha1[20];
748
749 populate_cs_prog_key(&pipeline->device->info, &key);
750
751 if (module->size > 0) {
752 anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint, spec_info);
753 kernel = anv_pipeline_cache_search(cache, sha1, &stage_prog_data, &map);
754 }
755
756 if (module->size == 0 || kernel == NO_KERNEL) {
757 struct brw_cs_prog_data prog_data = { 0, };
758 struct anv_pipeline_binding surface_to_descriptor[256];
759 struct anv_pipeline_binding sampler_to_descriptor[256];
760
761 map = (struct anv_pipeline_bind_map) {
762 .surface_to_descriptor = surface_to_descriptor,
763 .sampler_to_descriptor = sampler_to_descriptor
764 };
765
766 nir_shader *nir = anv_pipeline_compile(pipeline, module, entrypoint,
767 MESA_SHADER_COMPUTE, spec_info,
768 &prog_data.base, &map);
769 if (nir == NULL)
770 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
771
772 anv_fill_binding_table(&prog_data.base, 1);
773
774 void *mem_ctx = ralloc_context(NULL);
775
776 if (module->nir == NULL)
777 ralloc_steal(mem_ctx, nir);
778
779 unsigned code_size;
780 const unsigned *shader_code =
781 brw_compile_cs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
782 -1, &code_size, NULL);
783 if (shader_code == NULL) {
784 ralloc_free(mem_ctx);
785 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
786 }
787
788 stage_prog_data = &prog_data.base;
789 kernel = anv_pipeline_cache_upload_kernel(cache,
790 module->size > 0 ? sha1 : NULL,
791 shader_code, code_size,
792 &stage_prog_data, sizeof(prog_data),
793 &map);
794
795 ralloc_free(mem_ctx);
796 }
797
798 pipeline->cs_simd = kernel;
799
800 anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE,
801 stage_prog_data, &map);
802
803 return VK_SUCCESS;
804 }
805
806 static void
807 gen7_compute_urb_partition(struct anv_pipeline *pipeline)
808 {
809 const struct brw_device_info *devinfo = &pipeline->device->info;
810 bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
811 unsigned vs_size = vs_present ?
812 get_vs_prog_data(pipeline)->base.urb_entry_size : 1;
813 unsigned vs_entry_size_bytes = vs_size * 64;
814 bool gs_present = pipeline->active_stages & VK_SHADER_STAGE_GEOMETRY_BIT;
815 unsigned gs_size = gs_present ?
816 get_gs_prog_data(pipeline)->base.urb_entry_size : 1;
817 unsigned gs_entry_size_bytes = gs_size * 64;
818
819 /* From p35 of the Ivy Bridge PRM (section 1.7.1: 3DSTATE_URB_GS):
820 *
821 * VS Number of URB Entries must be divisible by 8 if the VS URB Entry
822 * Allocation Size is less than 9 512-bit URB entries.
823 *
824 * Similar text exists for GS.
825 */
826 unsigned vs_granularity = (vs_size < 9) ? 8 : 1;
827 unsigned gs_granularity = (gs_size < 9) ? 8 : 1;
828
829 /* URB allocations must be done in 8k chunks. */
830 unsigned chunk_size_bytes = 8192;
831
832 /* Determine the size of the URB in chunks. */
833 unsigned urb_chunks = devinfo->urb.size * 1024 / chunk_size_bytes;
834
835 /* Reserve space for push constants */
836 unsigned push_constant_kb;
837 if (pipeline->device->info.gen >= 8)
838 push_constant_kb = 32;
839 else if (pipeline->device->info.is_haswell)
840 push_constant_kb = pipeline->device->info.gt == 3 ? 32 : 16;
841 else
842 push_constant_kb = 16;
843
844 unsigned push_constant_bytes = push_constant_kb * 1024;
845 unsigned push_constant_chunks =
846 push_constant_bytes / chunk_size_bytes;
847
848 /* Initially, assign each stage the minimum amount of URB space it needs,
849 * and make a note of how much additional space it "wants" (the amount of
850 * additional space it could actually make use of).
851 */
852
853 /* VS has a lower limit on the number of URB entries */
854 unsigned vs_chunks =
855 ALIGN(devinfo->urb.min_vs_entries * vs_entry_size_bytes,
856 chunk_size_bytes) / chunk_size_bytes;
857 unsigned vs_wants =
858 ALIGN(devinfo->urb.max_vs_entries * vs_entry_size_bytes,
859 chunk_size_bytes) / chunk_size_bytes - vs_chunks;
860
861 unsigned gs_chunks = 0;
862 unsigned gs_wants = 0;
863 if (gs_present) {
864 /* There are two constraints on the minimum amount of URB space we can
865 * allocate:
866 *
867 * (1) We need room for at least 2 URB entries, since we always operate
868 * the GS in DUAL_OBJECT mode.
869 *
870 * (2) We can't allocate less than nr_gs_entries_granularity.
871 */
872 gs_chunks = ALIGN(MAX2(gs_granularity, 2) * gs_entry_size_bytes,
873 chunk_size_bytes) / chunk_size_bytes;
874 gs_wants =
875 ALIGN(devinfo->urb.max_gs_entries * gs_entry_size_bytes,
876 chunk_size_bytes) / chunk_size_bytes - gs_chunks;
877 }
878
879 /* There should always be enough URB space to satisfy the minimum
880 * requirements of each stage.
881 */
882 unsigned total_needs = push_constant_chunks + vs_chunks + gs_chunks;
883 assert(total_needs <= urb_chunks);
884
885 /* Mete out remaining space (if any) in proportion to "wants". */
886 unsigned total_wants = vs_wants + gs_wants;
887 unsigned remaining_space = urb_chunks - total_needs;
888 if (remaining_space > total_wants)
889 remaining_space = total_wants;
890 if (remaining_space > 0) {
891 unsigned vs_additional = (unsigned)
892 round(vs_wants * (((double) remaining_space) / total_wants));
893 vs_chunks += vs_additional;
894 remaining_space -= vs_additional;
895 gs_chunks += remaining_space;
896 }
897
898 /* Sanity check that we haven't over-allocated. */
899 assert(push_constant_chunks + vs_chunks + gs_chunks <= urb_chunks);
900
901 /* Finally, compute the number of entries that can fit in the space
902 * allocated to each stage.
903 */
904 unsigned nr_vs_entries = vs_chunks * chunk_size_bytes / vs_entry_size_bytes;
905 unsigned nr_gs_entries = gs_chunks * chunk_size_bytes / gs_entry_size_bytes;
906
907 /* Since we rounded up when computing *_wants, this may be slightly more
908 * than the maximum allowed amount, so correct for that.
909 */
910 nr_vs_entries = MIN2(nr_vs_entries, devinfo->urb.max_vs_entries);
911 nr_gs_entries = MIN2(nr_gs_entries, devinfo->urb.max_gs_entries);
912
913 /* Ensure that we program a multiple of the granularity. */
914 nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, vs_granularity);
915 nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, gs_granularity);
916
917 /* Finally, sanity check to make sure we have at least the minimum number
918 * of entries needed for each stage.
919 */
920 assert(nr_vs_entries >= devinfo->urb.min_vs_entries);
921 if (gs_present)
922 assert(nr_gs_entries >= 2);
923
924 /* Lay out the URB in the following order:
925 * - push constants
926 * - VS
927 * - GS
928 */
929 pipeline->urb.start[MESA_SHADER_VERTEX] = push_constant_chunks;
930 pipeline->urb.size[MESA_SHADER_VERTEX] = vs_size;
931 pipeline->urb.entries[MESA_SHADER_VERTEX] = nr_vs_entries;
932
933 pipeline->urb.start[MESA_SHADER_GEOMETRY] = push_constant_chunks + vs_chunks;
934 pipeline->urb.size[MESA_SHADER_GEOMETRY] = gs_size;
935 pipeline->urb.entries[MESA_SHADER_GEOMETRY] = nr_gs_entries;
936
937 pipeline->urb.start[MESA_SHADER_TESS_CTRL] = push_constant_chunks;
938 pipeline->urb.size[MESA_SHADER_TESS_CTRL] = 1;
939 pipeline->urb.entries[MESA_SHADER_TESS_CTRL] = 0;
940
941 pipeline->urb.start[MESA_SHADER_TESS_EVAL] = push_constant_chunks;
942 pipeline->urb.size[MESA_SHADER_TESS_EVAL] = 1;
943 pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
944
945 const unsigned stages =
946 _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
947 unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
948 unsigned used_kb = 0;
949
950 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
951 * units of 2KB. Incidentally, these are the same platforms that have
952 * 32KB worth of push constant space.
953 */
954 if (push_constant_kb == 32)
955 size_per_stage &= ~1u;
956
957 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
958 pipeline->urb.push_size[i] =
959 (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;
960 used_kb += pipeline->urb.push_size[i];
961 assert(used_kb <= push_constant_kb);
962 }
963
964 pipeline->urb.push_size[MESA_SHADER_FRAGMENT] =
965 push_constant_kb - used_kb;
966 }
967
968 static void
969 anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
970 const VkGraphicsPipelineCreateInfo *pCreateInfo)
971 {
972 anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
973 ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
974 struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
975
976 pipeline->dynamic_state = default_dynamic_state;
977
978 if (pCreateInfo->pDynamicState) {
979 /* Remove all of the states that are marked as dynamic */
980 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
981 for (uint32_t s = 0; s < count; s++)
982 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
983 }
984
985 struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
986
987 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
988 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
989 typed_memcpy(dynamic->viewport.viewports,
990 pCreateInfo->pViewportState->pViewports,
991 pCreateInfo->pViewportState->viewportCount);
992 }
993
994 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
995 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
996 typed_memcpy(dynamic->scissor.scissors,
997 pCreateInfo->pViewportState->pScissors,
998 pCreateInfo->pViewportState->scissorCount);
999 }
1000
1001 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1002 assert(pCreateInfo->pRasterizationState);
1003 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1004 }
1005
1006 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1007 assert(pCreateInfo->pRasterizationState);
1008 dynamic->depth_bias.bias =
1009 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1010 dynamic->depth_bias.clamp =
1011 pCreateInfo->pRasterizationState->depthBiasClamp;
1012 dynamic->depth_bias.slope =
1013 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1014 }
1015
1016 if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1017 assert(pCreateInfo->pColorBlendState);
1018 typed_memcpy(dynamic->blend_constants,
1019 pCreateInfo->pColorBlendState->blendConstants, 4);
1020 }
1021
1022 /* If there is no depthstencil attachment, then don't read
1023 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1024 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1025 * no need to override the depthstencil defaults in
1026 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1027 *
1028 * From the Vulkan spec (20 Oct 2015, git-aa308cb):
1029 *
1030 * pDepthStencilState [...] may only be NULL if renderPass and subpass
1031 * specify a subpass that has no depth/stencil attachment.
1032 */
1033 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1034 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1035 assert(pCreateInfo->pDepthStencilState);
1036 dynamic->depth_bounds.min =
1037 pCreateInfo->pDepthStencilState->minDepthBounds;
1038 dynamic->depth_bounds.max =
1039 pCreateInfo->pDepthStencilState->maxDepthBounds;
1040 }
1041
1042 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1043 assert(pCreateInfo->pDepthStencilState);
1044 dynamic->stencil_compare_mask.front =
1045 pCreateInfo->pDepthStencilState->front.compareMask;
1046 dynamic->stencil_compare_mask.back =
1047 pCreateInfo->pDepthStencilState->back.compareMask;
1048 }
1049
1050 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1051 assert(pCreateInfo->pDepthStencilState);
1052 dynamic->stencil_write_mask.front =
1053 pCreateInfo->pDepthStencilState->front.writeMask;
1054 dynamic->stencil_write_mask.back =
1055 pCreateInfo->pDepthStencilState->back.writeMask;
1056 }
1057
1058 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1059 assert(pCreateInfo->pDepthStencilState);
1060 dynamic->stencil_reference.front =
1061 pCreateInfo->pDepthStencilState->front.reference;
1062 dynamic->stencil_reference.back =
1063 pCreateInfo->pDepthStencilState->back.reference;
1064 }
1065 }
1066
1067 pipeline->dynamic_state_mask = states;
1068 }
1069
1070 static void
1071 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
1072 {
1073 struct anv_render_pass *renderpass = NULL;
1074 struct anv_subpass *subpass = NULL;
1075
1076 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1077 * present, as explained by the Vulkan (20 Oct 2015, git-aa308cb), Section
1078 * 4.2 Graphics Pipeline.
1079 */
1080 assert(info->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
1081
1082 renderpass = anv_render_pass_from_handle(info->renderPass);
1083 assert(renderpass);
1084
1085 if (renderpass != &anv_meta_dummy_renderpass) {
1086 assert(info->subpass < renderpass->subpass_count);
1087 subpass = &renderpass->subpasses[info->subpass];
1088 }
1089
1090 assert(info->stageCount >= 1);
1091 assert(info->pVertexInputState);
1092 assert(info->pInputAssemblyState);
1093 assert(info->pViewportState);
1094 assert(info->pRasterizationState);
1095
1096 if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
1097 assert(info->pDepthStencilState);
1098
1099 if (subpass && subpass->color_count > 0)
1100 assert(info->pColorBlendState);
1101
1102 for (uint32_t i = 0; i < info->stageCount; ++i) {
1103 switch (info->pStages[i].stage) {
1104 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
1105 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
1106 assert(info->pTessellationState);
1107 break;
1108 default:
1109 break;
1110 }
1111 }
1112 }
1113
1114 VkResult
1115 anv_pipeline_init(struct anv_pipeline *pipeline,
1116 struct anv_device *device,
1117 struct anv_pipeline_cache *cache,
1118 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1119 const struct anv_graphics_pipeline_create_info *extra,
1120 const VkAllocationCallbacks *alloc)
1121 {
1122 VkResult result;
1123
1124 anv_validate {
1125 anv_pipeline_validate_create_info(pCreateInfo);
1126 }
1127
1128 if (alloc == NULL)
1129 alloc = &device->alloc;
1130
1131 pipeline->device = device;
1132 pipeline->layout = anv_pipeline_layout_from_handle(pCreateInfo->layout);
1133
1134 result = anv_reloc_list_init(&pipeline->batch_relocs, alloc);
1135 if (result != VK_SUCCESS)
1136 return result;
1137
1138 pipeline->batch.alloc = alloc;
1139 pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
1140 pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
1141 pipeline->batch.relocs = &pipeline->batch_relocs;
1142
1143 anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1144
1145 pipeline->use_repclear = extra && extra->use_repclear;
1146
1147 /* When we free the pipeline, we detect stages based on the NULL status
1148 * of various prog_data pointers. Make them NULL by default.
1149 */
1150 memset(pipeline->prog_data, 0, sizeof(pipeline->prog_data));
1151 memset(pipeline->scratch_start, 0, sizeof(pipeline->scratch_start));
1152 memset(pipeline->bindings, 0, sizeof(pipeline->bindings));
1153
1154 pipeline->vs_simd8 = NO_KERNEL;
1155 pipeline->vs_vec4 = NO_KERNEL;
1156 pipeline->gs_kernel = NO_KERNEL;
1157 pipeline->ps_ksp0 = NO_KERNEL;
1158
1159 pipeline->active_stages = 0;
1160 pipeline->total_scratch = 0;
1161
1162 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1163 struct anv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1164 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1165 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1166 pStages[stage] = &pCreateInfo->pStages[i];
1167 modules[stage] = anv_shader_module_from_handle(pStages[stage]->module);
1168 }
1169
1170 if (modules[MESA_SHADER_VERTEX]) {
1171 anv_pipeline_compile_vs(pipeline, cache, pCreateInfo,
1172 modules[MESA_SHADER_VERTEX],
1173 pStages[MESA_SHADER_VERTEX]->pName,
1174 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo);
1175 }
1176
1177 if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
1178 anv_finishme("no tessellation support");
1179
1180 if (modules[MESA_SHADER_GEOMETRY]) {
1181 anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
1182 modules[MESA_SHADER_GEOMETRY],
1183 pStages[MESA_SHADER_GEOMETRY]->pName,
1184 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo);
1185 }
1186
1187 if (modules[MESA_SHADER_FRAGMENT]) {
1188 anv_pipeline_compile_fs(pipeline, cache, pCreateInfo, extra,
1189 modules[MESA_SHADER_FRAGMENT],
1190 pStages[MESA_SHADER_FRAGMENT]->pName,
1191 pStages[MESA_SHADER_FRAGMENT]->pSpecializationInfo);
1192 }
1193
1194 if (!(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT)) {
1195 /* Vertex is only optional if disable_vs is set */
1196 assert(extra->disable_vs);
1197 }
1198
1199 gen7_compute_urb_partition(pipeline);
1200
1201 const VkPipelineVertexInputStateCreateInfo *vi_info =
1202 pCreateInfo->pVertexInputState;
1203
1204 uint64_t inputs_read;
1205 if (extra && extra->disable_vs) {
1206 /* If the VS is disabled, just assume the user knows what they're
1207 * doing and apply the layout blindly. This can only come from
1208 * meta, so this *should* be safe.
1209 */
1210 inputs_read = ~0ull;
1211 } else {
1212 inputs_read = get_vs_prog_data(pipeline)->inputs_read;
1213 }
1214
1215 pipeline->vb_used = 0;
1216 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1217 const VkVertexInputAttributeDescription *desc =
1218 &vi_info->pVertexAttributeDescriptions[i];
1219
1220 if (inputs_read & (1 << (VERT_ATTRIB_GENERIC0 + desc->location)))
1221 pipeline->vb_used |= 1 << desc->binding;
1222 }
1223
1224 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1225 const VkVertexInputBindingDescription *desc =
1226 &vi_info->pVertexBindingDescriptions[i];
1227
1228 pipeline->binding_stride[desc->binding] = desc->stride;
1229
1230 /* Step rate is programmed per vertex element (attribute), not
1231 * binding. Set up a map of which bindings step per instance, for
1232 * reference by vertex element setup. */
1233 switch (desc->inputRate) {
1234 default:
1235 case VK_VERTEX_INPUT_RATE_VERTEX:
1236 pipeline->instancing_enable[desc->binding] = false;
1237 break;
1238 case VK_VERTEX_INPUT_RATE_INSTANCE:
1239 pipeline->instancing_enable[desc->binding] = true;
1240 break;
1241 }
1242 }
1243
1244 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1245 pCreateInfo->pInputAssemblyState;
1246 pipeline->primitive_restart = ia_info->primitiveRestartEnable;
1247 pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
1248
1249 if (extra && extra->use_rectlist)
1250 pipeline->topology = _3DPRIM_RECTLIST;
1251
1252 while (anv_block_pool_size(&device->scratch_block_pool) <
1253 pipeline->total_scratch)
1254 anv_block_pool_alloc(&device->scratch_block_pool);
1255
1256 return VK_SUCCESS;
1257 }
1258
1259 VkResult
1260 anv_graphics_pipeline_create(
1261 VkDevice _device,
1262 VkPipelineCache _cache,
1263 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1264 const struct anv_graphics_pipeline_create_info *extra,
1265 const VkAllocationCallbacks *pAllocator,
1266 VkPipeline *pPipeline)
1267 {
1268 ANV_FROM_HANDLE(anv_device, device, _device);
1269 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1270
1271 if (cache == NULL)
1272 cache = &device->default_pipeline_cache;
1273
1274 switch (device->info.gen) {
1275 case 7:
1276 if (device->info.is_haswell)
1277 return gen75_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1278 else
1279 return gen7_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1280 case 8:
1281 return gen8_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1282 case 9:
1283 return gen9_graphics_pipeline_create(_device, cache, pCreateInfo, extra, pAllocator, pPipeline);
1284 default:
1285 unreachable("unsupported gen\n");
1286 }
1287 }
1288
1289 VkResult anv_CreateGraphicsPipelines(
1290 VkDevice _device,
1291 VkPipelineCache pipelineCache,
1292 uint32_t count,
1293 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1294 const VkAllocationCallbacks* pAllocator,
1295 VkPipeline* pPipelines)
1296 {
1297 VkResult result = VK_SUCCESS;
1298
1299 unsigned i = 0;
1300 for (; i < count; i++) {
1301 result = anv_graphics_pipeline_create(_device,
1302 pipelineCache,
1303 &pCreateInfos[i],
1304 NULL, pAllocator, &pPipelines[i]);
1305 if (result != VK_SUCCESS) {
1306 for (unsigned j = 0; j < i; j++) {
1307 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1308 }
1309
1310 return result;
1311 }
1312 }
1313
1314 return VK_SUCCESS;
1315 }
1316
1317 static VkResult anv_compute_pipeline_create(
1318 VkDevice _device,
1319 VkPipelineCache _cache,
1320 const VkComputePipelineCreateInfo* pCreateInfo,
1321 const VkAllocationCallbacks* pAllocator,
1322 VkPipeline* pPipeline)
1323 {
1324 ANV_FROM_HANDLE(anv_device, device, _device);
1325 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
1326
1327 if (cache == NULL)
1328 cache = &device->default_pipeline_cache;
1329
1330 switch (device->info.gen) {
1331 case 7:
1332 if (device->info.is_haswell)
1333 return gen75_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1334 else
1335 return gen7_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1336 case 8:
1337 return gen8_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1338 case 9:
1339 return gen9_compute_pipeline_create(_device, cache, pCreateInfo, pAllocator, pPipeline);
1340 default:
1341 unreachable("unsupported gen\n");
1342 }
1343 }
1344
1345 VkResult anv_CreateComputePipelines(
1346 VkDevice _device,
1347 VkPipelineCache pipelineCache,
1348 uint32_t count,
1349 const VkComputePipelineCreateInfo* pCreateInfos,
1350 const VkAllocationCallbacks* pAllocator,
1351 VkPipeline* pPipelines)
1352 {
1353 VkResult result = VK_SUCCESS;
1354
1355 unsigned i = 0;
1356 for (; i < count; i++) {
1357 result = anv_compute_pipeline_create(_device, pipelineCache,
1358 &pCreateInfos[i],
1359 pAllocator, &pPipelines[i]);
1360 if (result != VK_SUCCESS) {
1361 for (unsigned j = 0; j < i; j++) {
1362 anv_DestroyPipeline(_device, pPipelines[j], pAllocator);
1363 }
1364
1365 return result;
1366 }
1367 }
1368
1369 return VK_SUCCESS;
1370 }