2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 struct anv_spirv_debug_data
{
99 struct anv_device
*device
;
100 const struct anv_shader_module
*module
;
103 static void anv_spirv_nir_debug(void *private_data
,
104 enum nir_spirv_debug_level level
,
108 struct anv_spirv_debug_data
*debug_data
= private_data
;
109 static const VkDebugReportFlagsEXT vk_flags
[] = {
110 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
111 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
116 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
118 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
120 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
121 (uint64_t) (uintptr_t) debug_data
->module
,
122 0, 0, "anv", buffer
);
125 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
126 * we can't do that yet because we don't have the ability to copy nir.
129 anv_shader_compile_to_nir(struct anv_device
*device
,
131 const struct anv_shader_module
*module
,
132 const char *entrypoint_name
,
133 gl_shader_stage stage
,
134 const VkSpecializationInfo
*spec_info
)
136 const struct anv_physical_device
*pdevice
=
137 &device
->instance
->physicalDevice
;
138 const struct brw_compiler
*compiler
= pdevice
->compiler
;
139 const nir_shader_compiler_options
*nir_options
=
140 compiler
->glsl_compiler_options
[stage
].NirOptions
;
142 uint32_t *spirv
= (uint32_t *) module
->data
;
143 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
144 assert(module
->size
% 4 == 0);
146 uint32_t num_spec_entries
= 0;
147 struct nir_spirv_specialization
*spec_entries
= NULL
;
148 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
149 num_spec_entries
= spec_info
->mapEntryCount
;
150 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
151 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
152 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
153 const void *data
= spec_info
->pData
+ entry
.offset
;
154 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
156 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
157 if (spec_info
->dataSize
== 8)
158 spec_entries
[i
].data64
= *(const uint64_t *)data
;
160 spec_entries
[i
].data32
= *(const uint32_t *)data
;
164 struct anv_spirv_debug_data spirv_debug_data
= {
168 struct spirv_to_nir_options spirv_options
= {
169 .lower_workgroup_access_to_offsets
= true,
171 .derivative_group
= true,
172 .descriptor_array_dynamic_indexing
= true,
173 .descriptor_array_non_uniform_indexing
= true,
174 .descriptor_indexing
= true,
175 .device_group
= true,
176 .draw_parameters
= true,
177 .float16
= pdevice
->info
.gen
>= 8,
178 .float64
= pdevice
->info
.gen
>= 8,
179 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
180 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
181 .geometry_streams
= true,
182 .image_write_without_format
= true,
183 .int8
= pdevice
->info
.gen
>= 8,
184 .int16
= pdevice
->info
.gen
>= 8,
185 .int64
= pdevice
->info
.gen
>= 8,
186 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
189 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
190 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
191 .runtime_descriptor_array
= true,
192 .shader_viewport_index_layer
= true,
193 .stencil_export
= pdevice
->info
.gen
>= 9,
194 .storage_8bit
= pdevice
->info
.gen
>= 8,
195 .storage_16bit
= pdevice
->info
.gen
>= 8,
196 .subgroup_arithmetic
= true,
197 .subgroup_basic
= true,
198 .subgroup_ballot
= true,
199 .subgroup_quad
= true,
200 .subgroup_shuffle
= true,
201 .subgroup_vote
= true,
202 .tessellation
= true,
203 .transform_feedback
= pdevice
->info
.gen
>= 8,
204 .variable_pointers
= true,
206 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
208 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
209 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
210 .push_const_addr_format
= nir_address_format_logical
,
212 /* TODO: Consider changing this to an address format that has the NULL
213 * pointer equals to 0. That might be a better format to play nice
214 * with certain code / code generators.
216 .shared_addr_format
= nir_address_format_32bit_offset
,
218 .func
= anv_spirv_nir_debug
,
219 .private_data
= &spirv_debug_data
,
225 spirv_to_nir(spirv
, module
->size
/ 4,
226 spec_entries
, num_spec_entries
,
227 stage
, entrypoint_name
, &spirv_options
, nir_options
);
228 assert(nir
->info
.stage
== stage
);
229 nir_validate_shader(nir
, "after spirv_to_nir");
230 ralloc_steal(mem_ctx
, nir
);
234 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
235 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
236 gl_shader_stage_name(stage
));
237 nir_print_shader(nir
, stderr
);
240 /* We have to lower away local constant initializers right before we
241 * inline functions. That way they get properly initialized at the top
242 * of the function and not at the top of its caller.
244 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
245 NIR_PASS_V(nir
, nir_lower_returns
);
246 NIR_PASS_V(nir
, nir_inline_functions
);
247 NIR_PASS_V(nir
, nir_opt_deref
);
249 /* Pick off the single entrypoint that we want */
250 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
251 if (!func
->is_entrypoint
)
252 exec_node_remove(&func
->node
);
254 assert(exec_list_length(&nir
->functions
) == 1);
256 /* Now that we've deleted all but the main function, we can go ahead and
257 * lower the rest of the constant initializers. We do this here so that
258 * nir_remove_dead_variables and split_per_member_structs below see the
259 * corresponding stores.
261 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
263 /* Split member structs. We do this before lower_io_to_temporaries so that
264 * it doesn't lower system values to temporaries by accident.
266 NIR_PASS_V(nir
, nir_split_var_copies
);
267 NIR_PASS_V(nir
, nir_split_per_member_structs
);
269 NIR_PASS_V(nir
, nir_remove_dead_variables
,
270 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
272 NIR_PASS_V(nir
, nir_propagate_invariant
);
273 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
274 nir_shader_get_entrypoint(nir
), true, false);
276 NIR_PASS_V(nir
, nir_lower_frexp
);
278 /* Vulkan uses the separate-shader linking model */
279 nir
->info
.separate_shader
= true;
281 brw_preprocess_nir(compiler
, nir
, NULL
);
286 void anv_DestroyPipeline(
288 VkPipeline _pipeline
,
289 const VkAllocationCallbacks
* pAllocator
)
291 ANV_FROM_HANDLE(anv_device
, device
, _device
);
292 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
297 anv_reloc_list_finish(&pipeline
->batch_relocs
,
298 pAllocator
? pAllocator
: &device
->alloc
);
299 if (pipeline
->blend_state
.map
)
300 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
302 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
303 if (pipeline
->shaders
[s
])
304 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
307 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
310 static const uint32_t vk_to_gen_primitive_type
[] = {
311 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
312 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
313 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
314 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
315 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
316 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
317 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
318 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
319 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
320 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
324 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
325 struct brw_sampler_prog_key_data
*key
)
327 /* Almost all multisampled textures are compressed. The only time when we
328 * don't compress a multisampled texture is for 16x MSAA with a surface
329 * width greater than 8k which is a bit of an edge case. Since the sampler
330 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
331 * to tell the compiler to always assume compression.
333 key
->compressed_multisample_layout_mask
= ~0;
335 /* SkyLake added support for 16x MSAA. With this came a new message for
336 * reading from a 16x MSAA surface with compression. The new message was
337 * needed because now the MCS data is 64 bits instead of 32 or lower as is
338 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
339 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
340 * so we can just use it unconditionally. This may not be quite as
341 * efficient but it saves us from recompiling.
343 if (devinfo
->gen
>= 9)
346 /* XXX: Handle texture swizzle on HSW- */
347 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
348 /* Assume color sampler, no swizzling. (Works for BDW+) */
349 key
->swizzles
[i
] = SWIZZLE_XYZW
;
354 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
355 struct brw_vs_prog_key
*key
)
357 memset(key
, 0, sizeof(*key
));
359 populate_sampler_prog_key(devinfo
, &key
->tex
);
361 /* XXX: Handle vertex input work-arounds */
363 /* XXX: Handle sampler_prog_key */
367 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
368 unsigned input_vertices
,
369 struct brw_tcs_prog_key
*key
)
371 memset(key
, 0, sizeof(*key
));
373 populate_sampler_prog_key(devinfo
, &key
->tex
);
375 key
->input_vertices
= input_vertices
;
379 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
380 struct brw_tes_prog_key
*key
)
382 memset(key
, 0, sizeof(*key
));
384 populate_sampler_prog_key(devinfo
, &key
->tex
);
388 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
389 struct brw_gs_prog_key
*key
)
391 memset(key
, 0, sizeof(*key
));
393 populate_sampler_prog_key(devinfo
, &key
->tex
);
397 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
398 const struct anv_subpass
*subpass
,
399 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
400 struct brw_wm_prog_key
*key
)
402 memset(key
, 0, sizeof(*key
));
404 populate_sampler_prog_key(devinfo
, &key
->tex
);
406 /* We set this to 0 here and set to the actual value before we call
409 key
->input_slots_valid
= 0;
411 /* Vulkan doesn't specify a default */
412 key
->high_quality_derivatives
= false;
414 /* XXX Vulkan doesn't appear to specify */
415 key
->clamp_fragment_color
= false;
417 assert(subpass
->color_count
<= MAX_RTS
);
418 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
419 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
420 key
->color_outputs_valid
|= (1 << i
);
423 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
425 /* To reduce possible shader recompilations we would need to know if
426 * there is a SampleMask output variable to compute if we should emit
427 * code to workaround the issue that hardware disables alpha to coverage
428 * when there is SampleMask output.
430 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
432 /* Vulkan doesn't support fixed-function alpha test */
433 key
->alpha_test_replicate_alpha
= false;
436 /* We should probably pull this out of the shader, but it's fairly
437 * harmless to compute it and then let dead-code take care of it.
439 if (ms_info
->rasterizationSamples
> 1) {
440 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
441 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
442 key
->multisample_fbo
= true;
445 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
450 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
451 struct brw_cs_prog_key
*key
)
453 memset(key
, 0, sizeof(*key
));
455 populate_sampler_prog_key(devinfo
, &key
->tex
);
458 struct anv_pipeline_stage
{
459 gl_shader_stage stage
;
461 const struct anv_shader_module
*module
;
462 const char *entrypoint
;
463 const VkSpecializationInfo
*spec_info
;
465 unsigned char shader_sha1
[20];
467 union brw_any_prog_key key
;
470 gl_shader_stage stage
;
471 unsigned char sha1
[20];
476 struct anv_pipeline_binding surface_to_descriptor
[256];
477 struct anv_pipeline_binding sampler_to_descriptor
[256];
478 struct anv_pipeline_bind_map bind_map
;
480 union brw_any_prog_data prog_data
;
482 VkPipelineCreationFeedbackEXT feedback
;
486 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
487 const char *entrypoint
,
488 gl_shader_stage stage
,
489 const VkSpecializationInfo
*spec_info
,
490 unsigned char *sha1_out
)
492 struct mesa_sha1 ctx
;
493 _mesa_sha1_init(&ctx
);
495 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
496 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
497 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
499 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
500 spec_info
->mapEntryCount
*
501 sizeof(*spec_info
->pMapEntries
));
502 _mesa_sha1_update(&ctx
, spec_info
->pData
,
503 spec_info
->dataSize
);
506 _mesa_sha1_final(&ctx
, sha1_out
);
510 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
511 struct anv_pipeline_layout
*layout
,
512 struct anv_pipeline_stage
*stages
,
513 unsigned char *sha1_out
)
515 struct mesa_sha1 ctx
;
516 _mesa_sha1_init(&ctx
);
518 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
519 sizeof(pipeline
->subpass
->view_mask
));
522 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
524 const bool rba
= pipeline
->device
->robust_buffer_access
;
525 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
527 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
528 if (stages
[s
].entrypoint
) {
529 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
530 sizeof(stages
[s
].shader_sha1
));
531 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
535 _mesa_sha1_final(&ctx
, sha1_out
);
539 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
540 struct anv_pipeline_layout
*layout
,
541 struct anv_pipeline_stage
*stage
,
542 unsigned char *sha1_out
)
544 struct mesa_sha1 ctx
;
545 _mesa_sha1_init(&ctx
);
548 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
550 const bool rba
= pipeline
->device
->robust_buffer_access
;
551 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
553 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
554 sizeof(stage
->shader_sha1
));
555 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
557 _mesa_sha1_final(&ctx
, sha1_out
);
561 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
562 struct anv_pipeline_cache
*cache
,
564 struct anv_pipeline_stage
*stage
)
566 const struct brw_compiler
*compiler
=
567 pipeline
->device
->instance
->physicalDevice
.compiler
;
568 const nir_shader_compiler_options
*nir_options
=
569 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
572 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
577 assert(nir
->info
.stage
== stage
->stage
);
581 nir
= anv_shader_compile_to_nir(pipeline
->device
,
588 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
596 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
598 struct anv_pipeline_stage
*stage
,
599 struct anv_pipeline_layout
*layout
)
601 const struct anv_physical_device
*pdevice
=
602 &pipeline
->device
->instance
->physicalDevice
;
603 const struct brw_compiler
*compiler
= pdevice
->compiler
;
605 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
606 nir_shader
*nir
= stage
->nir
;
608 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
609 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
610 NIR_PASS_V(nir
, nir_lower_input_attachments
, false);
613 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
615 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
617 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
618 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
620 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
621 prog_data
->total_shared
= nir
->num_shared
;
623 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
625 if (nir
->num_uniforms
> 0) {
626 assert(prog_data
->nr_params
== 0);
628 /* If the shader uses any push constants at all, we'll just give
629 * them the maximum possible number
631 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
632 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
633 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
634 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
636 /* We now set the param values to be offsets into a
637 * anv_push_constant_data structure. Since the compiler doesn't
638 * actually dereference any of the gl_constant_value pointers in the
639 * params array, it doesn't really matter what we put here.
641 struct anv_push_constants
*null_data
= NULL
;
642 /* Fill out the push constants section of the param array */
643 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
644 prog_data
->param
[i
] = ANV_PARAM_PUSH(
645 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
649 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
650 pipeline
->needs_data_cache
= true;
652 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
654 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
655 nir_address_format_64bit_global
);
657 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
659 anv_nir_apply_pipeline_layout(pdevice
,
660 pipeline
->device
->robust_buffer_access
,
661 layout
, nir
, prog_data
,
664 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
665 nir_address_format_32bit_index_offset
);
666 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
667 anv_nir_ssbo_addr_format(pdevice
,
668 pipeline
->device
->robust_buffer_access
));
670 NIR_PASS_V(nir
, nir_opt_constant_folding
);
672 /* We don't support non-uniform UBOs and non-uniform SSBO access is
673 * handled naturally by falling back to A64 messages.
675 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
676 nir_lower_non_uniform_texture_access
|
677 nir_lower_non_uniform_image_access
);
680 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
681 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
683 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
689 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
690 struct anv_pipeline_stage
*vs_stage
,
691 struct anv_pipeline_stage
*next_stage
)
694 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
697 static const unsigned *
698 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
700 struct anv_device
*device
,
701 struct anv_pipeline_stage
*vs_stage
)
703 brw_compute_vue_map(compiler
->devinfo
,
704 &vs_stage
->prog_data
.vs
.base
.vue_map
,
705 vs_stage
->nir
->info
.outputs_written
,
706 vs_stage
->nir
->info
.separate_shader
);
708 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
709 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
713 merge_tess_info(struct shader_info
*tes_info
,
714 const struct shader_info
*tcs_info
)
716 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
718 * "PointMode. Controls generation of points rather than triangles
719 * or lines. This functionality defaults to disabled, and is
720 * enabled if either shader stage includes the execution mode.
722 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
723 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
724 * and OutputVertices, it says:
726 * "One mode must be set in at least one of the tessellation
729 * So, the fields can be set in either the TCS or TES, but they must
730 * agree if set in both. Our backend looks at TES, so bitwise-or in
731 * the values from the TCS.
733 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
734 tes_info
->tess
.tcs_vertices_out
== 0 ||
735 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
736 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
738 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
739 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
740 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
741 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
743 assert(tcs_info
->tess
.primitive_mode
== 0 ||
744 tes_info
->tess
.primitive_mode
== 0 ||
745 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
746 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
747 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
748 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
752 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
753 struct anv_pipeline_stage
*tcs_stage
,
754 struct anv_pipeline_stage
*tes_stage
)
756 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
758 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
760 nir_lower_patch_vertices(tes_stage
->nir
,
761 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
764 /* Copy TCS info into the TES info */
765 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
767 /* Whacking the key after cache lookup is a bit sketchy, but all of
768 * this comes from the SPIR-V, which is part of the hash used for the
769 * pipeline cache. So it should be safe.
771 tcs_stage
->key
.tcs
.tes_primitive_mode
=
772 tes_stage
->nir
->info
.tess
.primitive_mode
;
773 tcs_stage
->key
.tcs
.quads_workaround
=
774 compiler
->devinfo
->gen
< 9 &&
775 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
776 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
779 static const unsigned *
780 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
782 struct anv_device
*device
,
783 struct anv_pipeline_stage
*tcs_stage
,
784 struct anv_pipeline_stage
*prev_stage
)
786 tcs_stage
->key
.tcs
.outputs_written
=
787 tcs_stage
->nir
->info
.outputs_written
;
788 tcs_stage
->key
.tcs
.patch_outputs_written
=
789 tcs_stage
->nir
->info
.patch_outputs_written
;
791 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
792 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
797 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
798 struct anv_pipeline_stage
*tes_stage
,
799 struct anv_pipeline_stage
*next_stage
)
802 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
805 static const unsigned *
806 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
808 struct anv_device
*device
,
809 struct anv_pipeline_stage
*tes_stage
,
810 struct anv_pipeline_stage
*tcs_stage
)
812 tes_stage
->key
.tes
.inputs_read
=
813 tcs_stage
->nir
->info
.outputs_written
;
814 tes_stage
->key
.tes
.patch_inputs_read
=
815 tcs_stage
->nir
->info
.patch_outputs_written
;
817 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
818 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
819 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
824 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
825 struct anv_pipeline_stage
*gs_stage
,
826 struct anv_pipeline_stage
*next_stage
)
829 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
832 static const unsigned *
833 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
835 struct anv_device
*device
,
836 struct anv_pipeline_stage
*gs_stage
,
837 struct anv_pipeline_stage
*prev_stage
)
839 brw_compute_vue_map(compiler
->devinfo
,
840 &gs_stage
->prog_data
.gs
.base
.vue_map
,
841 gs_stage
->nir
->info
.outputs_written
,
842 gs_stage
->nir
->info
.separate_shader
);
844 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
845 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
850 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
851 struct anv_pipeline_stage
*stage
)
853 unsigned num_rts
= 0;
854 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
855 struct anv_pipeline_binding rt_bindings
[max_rt
];
856 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
857 int rt_to_bindings
[max_rt
];
858 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
859 bool rt_used
[max_rt
];
860 memset(rt_used
, 0, sizeof(rt_used
));
862 /* Flag used render targets */
863 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
864 if (var
->data
.location
< FRAG_RESULT_DATA0
)
867 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
872 const unsigned array_len
=
873 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
874 assert(rt
+ array_len
<= max_rt
);
877 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
878 /* If this is the RT at location 0 and we have alpha to coverage
879 * enabled we will have to create a null RT for it, so mark it as
882 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
886 for (unsigned i
= 0; i
< array_len
; i
++)
887 rt_used
[rt
+ i
] = true;
890 /* Set new, compacted, location */
891 for (unsigned i
= 0; i
< max_rt
; i
++) {
895 rt_to_bindings
[i
] = num_rts
;
897 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
898 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
899 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
904 /* Setup a null render target */
905 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
906 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
915 bool deleted_output
= false;
916 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
917 if (var
->data
.location
< FRAG_RESULT_DATA0
)
920 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
922 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
923 /* Unused or out-of-bounds, throw it away, unless it is the first
924 * RT and we have alpha to coverage enabled.
926 deleted_output
= true;
927 var
->data
.mode
= nir_var_function_temp
;
928 exec_node_remove(&var
->node
);
929 exec_list_push_tail(&impl
->locals
, &var
->node
);
933 /* Give it the new location */
934 assert(rt_to_bindings
[rt
] != -1);
935 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
939 nir_fixup_deref_modes(stage
->nir
);
942 /* If we have no render targets, we need a null render target */
943 rt_bindings
[0] = (struct anv_pipeline_binding
) {
944 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
951 /* Now that we've determined the actual number of render targets, adjust
952 * the key accordingly.
954 stage
->key
.wm
.nr_color_regions
= num_rts
;
955 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
957 assert(num_rts
<= max_rt
);
958 assert(stage
->bind_map
.surface_count
== 0);
959 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
960 rt_bindings
, num_rts
);
961 stage
->bind_map
.surface_count
+= num_rts
;
964 static const unsigned *
965 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
967 struct anv_device
*device
,
968 struct anv_pipeline_stage
*fs_stage
,
969 struct anv_pipeline_stage
*prev_stage
)
971 /* TODO: we could set this to 0 based on the information in nir_shader, but
972 * we need this before we call spirv_to_nir.
975 fs_stage
->key
.wm
.input_slots_valid
=
976 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
978 const unsigned *code
=
979 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
980 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
981 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
983 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
984 !fs_stage
->prog_data
.wm
.has_side_effects
&&
985 !fs_stage
->prog_data
.wm
.uses_kill
&&
986 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
987 !fs_stage
->prog_data
.wm
.computed_stencil
) {
988 /* This fragment shader has no outputs and no side effects. Go ahead
989 * and return the code pointer so we don't accidentally think the
990 * compile failed but zero out prog_data which will set program_size to
991 * zero and disable the stage.
993 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1000 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1001 struct anv_pipeline_cache
*cache
,
1002 const VkGraphicsPipelineCreateInfo
*info
)
1004 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1005 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1007 int64_t pipeline_start
= os_time_get_nano();
1009 const struct brw_compiler
*compiler
=
1010 pipeline
->device
->instance
->physicalDevice
.compiler
;
1011 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1013 pipeline
->active_stages
= 0;
1016 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1017 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1018 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1020 pipeline
->active_stages
|= sinfo
->stage
;
1022 int64_t stage_start
= os_time_get_nano();
1024 stages
[stage
].stage
= stage
;
1025 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1026 stages
[stage
].entrypoint
= sinfo
->pName
;
1027 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1028 anv_pipeline_hash_shader(stages
[stage
].module
,
1029 stages
[stage
].entrypoint
,
1031 stages
[stage
].spec_info
,
1032 stages
[stage
].shader_sha1
);
1034 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1036 case MESA_SHADER_VERTEX
:
1037 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
1039 case MESA_SHADER_TESS_CTRL
:
1040 populate_tcs_prog_key(devinfo
,
1041 info
->pTessellationState
->patchControlPoints
,
1042 &stages
[stage
].key
.tcs
);
1044 case MESA_SHADER_TESS_EVAL
:
1045 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
1047 case MESA_SHADER_GEOMETRY
:
1048 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
1050 case MESA_SHADER_FRAGMENT
:
1051 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1052 info
->pMultisampleState
,
1053 &stages
[stage
].key
.wm
);
1056 unreachable("Invalid graphics shader stage");
1059 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1060 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1063 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1064 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1066 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1068 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1070 unsigned char sha1
[20];
1071 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1074 unsigned cache_hits
= 0;
1075 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1076 if (!stages
[s
].entrypoint
)
1079 int64_t stage_start
= os_time_get_nano();
1081 stages
[s
].cache_key
.stage
= s
;
1082 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1085 struct anv_shader_bin
*bin
=
1086 anv_device_search_for_kernel(pipeline
->device
, cache
,
1087 &stages
[s
].cache_key
,
1088 sizeof(stages
[s
].cache_key
), &cache_hit
);
1091 pipeline
->shaders
[s
] = bin
;
1096 stages
[s
].feedback
.flags
|=
1097 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1099 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1102 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1103 if (cache_hits
== found
) {
1104 pipeline_feedback
.flags
|=
1105 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1107 /* We found all our shaders in the cache. We're done. */
1109 } else if (found
> 0) {
1110 /* We found some but not all of our shaders. This shouldn't happen
1111 * most of the time but it can if we have a partially populated
1114 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1116 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1117 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1118 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1119 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1120 (uint64_t)(uintptr_t)cache
,
1122 "Found a partial pipeline in the cache. This is "
1123 "most likely caused by an incomplete pipeline cache "
1124 "import or export");
1126 /* We're going to have to recompile anyway, so just throw away our
1127 * references to the shaders in the cache. We'll get them out of the
1128 * cache again as part of the compilation process.
1130 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1131 stages
[s
].feedback
.flags
= 0;
1132 if (pipeline
->shaders
[s
]) {
1133 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1134 pipeline
->shaders
[s
] = NULL
;
1139 void *pipeline_ctx
= ralloc_context(NULL
);
1141 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1142 if (!stages
[s
].entrypoint
)
1145 int64_t stage_start
= os_time_get_nano();
1147 assert(stages
[s
].stage
== s
);
1148 assert(pipeline
->shaders
[s
] == NULL
);
1150 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1151 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1152 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1155 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1158 if (stages
[s
].nir
== NULL
) {
1159 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1163 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1166 /* Walk backwards to link */
1167 struct anv_pipeline_stage
*next_stage
= NULL
;
1168 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1169 if (!stages
[s
].entrypoint
)
1173 case MESA_SHADER_VERTEX
:
1174 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1176 case MESA_SHADER_TESS_CTRL
:
1177 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1179 case MESA_SHADER_TESS_EVAL
:
1180 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1182 case MESA_SHADER_GEOMETRY
:
1183 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1185 case MESA_SHADER_FRAGMENT
:
1186 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1189 unreachable("Invalid graphics shader stage");
1192 next_stage
= &stages
[s
];
1195 struct anv_pipeline_stage
*prev_stage
= NULL
;
1196 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1197 if (!stages
[s
].entrypoint
)
1200 int64_t stage_start
= os_time_get_nano();
1202 void *stage_ctx
= ralloc_context(NULL
);
1204 nir_xfb_info
*xfb_info
= NULL
;
1205 if (s
== MESA_SHADER_VERTEX
||
1206 s
== MESA_SHADER_TESS_EVAL
||
1207 s
== MESA_SHADER_GEOMETRY
)
1208 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1210 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1212 const unsigned *code
;
1214 case MESA_SHADER_VERTEX
:
1215 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1218 case MESA_SHADER_TESS_CTRL
:
1219 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1220 &stages
[s
], prev_stage
);
1222 case MESA_SHADER_TESS_EVAL
:
1223 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1224 &stages
[s
], prev_stage
);
1226 case MESA_SHADER_GEOMETRY
:
1227 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1228 &stages
[s
], prev_stage
);
1230 case MESA_SHADER_FRAGMENT
:
1231 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1232 &stages
[s
], prev_stage
);
1235 unreachable("Invalid graphics shader stage");
1238 ralloc_free(stage_ctx
);
1239 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1243 struct anv_shader_bin
*bin
=
1244 anv_device_upload_kernel(pipeline
->device
, cache
,
1245 &stages
[s
].cache_key
,
1246 sizeof(stages
[s
].cache_key
),
1247 code
, stages
[s
].prog_data
.base
.program_size
,
1248 stages
[s
].nir
->constant_data
,
1249 stages
[s
].nir
->constant_data_size
,
1250 &stages
[s
].prog_data
.base
,
1251 brw_prog_data_size(s
),
1252 xfb_info
, &stages
[s
].bind_map
);
1254 ralloc_free(stage_ctx
);
1255 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1259 pipeline
->shaders
[s
] = bin
;
1260 ralloc_free(stage_ctx
);
1262 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1264 prev_stage
= &stages
[s
];
1267 ralloc_free(pipeline_ctx
);
1271 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1272 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1273 /* This can happen if we decided to implicitly disable the fragment
1274 * shader. See anv_pipeline_compile_fs().
1276 anv_shader_bin_unref(pipeline
->device
,
1277 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1278 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1279 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1282 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1284 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1285 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1286 if (create_feedback
) {
1287 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1289 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1290 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1291 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1292 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1299 ralloc_free(pipeline_ctx
);
1301 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1302 if (pipeline
->shaders
[s
])
1303 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1310 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1311 struct anv_pipeline_cache
*cache
,
1312 const VkComputePipelineCreateInfo
*info
,
1313 const struct anv_shader_module
*module
,
1314 const char *entrypoint
,
1315 const VkSpecializationInfo
*spec_info
)
1317 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1318 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1320 int64_t pipeline_start
= os_time_get_nano();
1322 const struct brw_compiler
*compiler
=
1323 pipeline
->device
->instance
->physicalDevice
.compiler
;
1325 struct anv_pipeline_stage stage
= {
1326 .stage
= MESA_SHADER_COMPUTE
,
1328 .entrypoint
= entrypoint
,
1329 .spec_info
= spec_info
,
1331 .stage
= MESA_SHADER_COMPUTE
,
1334 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1337 anv_pipeline_hash_shader(stage
.module
,
1339 MESA_SHADER_COMPUTE
,
1343 struct anv_shader_bin
*bin
= NULL
;
1345 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1347 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1349 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1351 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1352 sizeof(stage
.cache_key
), &cache_hit
);
1355 int64_t stage_start
= os_time_get_nano();
1357 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1358 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1359 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1362 /* Set up a binding for the gl_NumWorkGroups */
1363 stage
.bind_map
.surface_count
= 1;
1364 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1365 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1368 void *mem_ctx
= ralloc_context(NULL
);
1370 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1371 if (stage
.nir
== NULL
) {
1372 ralloc_free(mem_ctx
);
1373 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1376 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1378 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1379 &stage
.prog_data
.cs
);
1381 const unsigned *shader_code
=
1382 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1383 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1384 if (shader_code
== NULL
) {
1385 ralloc_free(mem_ctx
);
1386 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1389 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1390 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1391 &stage
.cache_key
, sizeof(stage
.cache_key
),
1392 shader_code
, code_size
,
1393 stage
.nir
->constant_data
,
1394 stage
.nir
->constant_data_size
,
1395 &stage
.prog_data
.base
,
1396 sizeof(stage
.prog_data
.cs
),
1397 NULL
, &stage
.bind_map
);
1399 ralloc_free(mem_ctx
);
1400 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1403 ralloc_free(mem_ctx
);
1405 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1409 stage
.feedback
.flags
|=
1410 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1411 pipeline_feedback
.flags
|=
1412 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1414 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1416 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1417 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1418 if (create_feedback
) {
1419 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1421 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1422 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1425 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1426 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1432 * Copy pipeline state not marked as dynamic.
1433 * Dynamic state is pipeline state which hasn't been provided at pipeline
1434 * creation time, but is dynamically provided afterwards using various
1435 * vkCmdSet* functions.
1437 * The set of state considered "non_dynamic" is determined by the pieces of
1438 * state that have their corresponding VkDynamicState enums omitted from
1439 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1441 * @param[out] pipeline Destination non_dynamic state.
1442 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1445 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1446 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1448 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1449 struct anv_subpass
*subpass
= pipeline
->subpass
;
1451 pipeline
->dynamic_state
= default_dynamic_state
;
1453 if (pCreateInfo
->pDynamicState
) {
1454 /* Remove all of the states that are marked as dynamic */
1455 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1456 for (uint32_t s
= 0; s
< count
; s
++)
1457 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1460 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1462 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1464 * pViewportState is [...] NULL if the pipeline
1465 * has rasterization disabled.
1467 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1468 assert(pCreateInfo
->pViewportState
);
1470 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1471 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1472 typed_memcpy(dynamic
->viewport
.viewports
,
1473 pCreateInfo
->pViewportState
->pViewports
,
1474 pCreateInfo
->pViewportState
->viewportCount
);
1477 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1478 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1479 typed_memcpy(dynamic
->scissor
.scissors
,
1480 pCreateInfo
->pViewportState
->pScissors
,
1481 pCreateInfo
->pViewportState
->scissorCount
);
1485 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1486 assert(pCreateInfo
->pRasterizationState
);
1487 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1490 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1491 assert(pCreateInfo
->pRasterizationState
);
1492 dynamic
->depth_bias
.bias
=
1493 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1494 dynamic
->depth_bias
.clamp
=
1495 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1496 dynamic
->depth_bias
.slope
=
1497 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1500 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1502 * pColorBlendState is [...] NULL if the pipeline has rasterization
1503 * disabled or if the subpass of the render pass the pipeline is
1504 * created against does not use any color attachments.
1506 bool uses_color_att
= false;
1507 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1508 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1509 uses_color_att
= true;
1514 if (uses_color_att
&&
1515 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1516 assert(pCreateInfo
->pColorBlendState
);
1518 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1519 typed_memcpy(dynamic
->blend_constants
,
1520 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1523 /* If there is no depthstencil attachment, then don't read
1524 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1525 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1526 * no need to override the depthstencil defaults in
1527 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1529 * Section 9.2 of the Vulkan 1.0.15 spec says:
1531 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1532 * disabled or if the subpass of the render pass the pipeline is created
1533 * against does not use a depth/stencil attachment.
1535 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1536 subpass
->depth_stencil_attachment
) {
1537 assert(pCreateInfo
->pDepthStencilState
);
1539 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1540 dynamic
->depth_bounds
.min
=
1541 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1542 dynamic
->depth_bounds
.max
=
1543 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1546 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1547 dynamic
->stencil_compare_mask
.front
=
1548 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1549 dynamic
->stencil_compare_mask
.back
=
1550 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1553 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1554 dynamic
->stencil_write_mask
.front
=
1555 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1556 dynamic
->stencil_write_mask
.back
=
1557 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1560 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1561 dynamic
->stencil_reference
.front
=
1562 pCreateInfo
->pDepthStencilState
->front
.reference
;
1563 dynamic
->stencil_reference
.back
=
1564 pCreateInfo
->pDepthStencilState
->back
.reference
;
1568 pipeline
->dynamic_state_mask
= states
;
1572 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1575 struct anv_render_pass
*renderpass
= NULL
;
1576 struct anv_subpass
*subpass
= NULL
;
1578 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1579 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1581 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1583 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1586 assert(info
->subpass
< renderpass
->subpass_count
);
1587 subpass
= &renderpass
->subpasses
[info
->subpass
];
1589 assert(info
->stageCount
>= 1);
1590 assert(info
->pVertexInputState
);
1591 assert(info
->pInputAssemblyState
);
1592 assert(info
->pRasterizationState
);
1593 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1594 assert(info
->pViewportState
);
1595 assert(info
->pMultisampleState
);
1597 if (subpass
&& subpass
->depth_stencil_attachment
)
1598 assert(info
->pDepthStencilState
);
1600 if (subpass
&& subpass
->color_count
> 0) {
1601 bool all_color_unused
= true;
1602 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1603 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1604 all_color_unused
= false;
1606 /* pColorBlendState is ignored if the pipeline has rasterization
1607 * disabled or if the subpass of the render pass the pipeline is
1608 * created against does not use any color attachments.
1610 assert(info
->pColorBlendState
|| all_color_unused
);
1614 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1615 switch (info
->pStages
[i
].stage
) {
1616 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1617 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1618 assert(info
->pTessellationState
);
1628 * Calculate the desired L3 partitioning based on the current state of the
1629 * pipeline. For now this simply returns the conservative defaults calculated
1630 * by get_default_l3_weights(), but we could probably do better by gathering
1631 * more statistics from the pipeline state (e.g. guess of expected URB usage
1632 * and bound surfaces), or by using feed-back from performance counters.
1635 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1637 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1639 const struct gen_l3_weights w
=
1640 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1642 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1643 pipeline
->urb
.total_size
=
1644 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1648 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1649 struct anv_device
*device
,
1650 struct anv_pipeline_cache
*cache
,
1651 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1652 const VkAllocationCallbacks
*alloc
)
1656 anv_pipeline_validate_create_info(pCreateInfo
);
1659 alloc
= &device
->alloc
;
1661 pipeline
->device
= device
;
1663 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1664 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1665 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1667 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1668 if (result
!= VK_SUCCESS
)
1671 pipeline
->batch
.alloc
= alloc
;
1672 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1673 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1674 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1675 pipeline
->batch
.status
= VK_SUCCESS
;
1677 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1678 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1679 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1681 /* Previously we enabled depth clipping when !depthClampEnable.
1682 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1683 * clipping info is available, use its enable value to determine clipping,
1684 * otherwise fallback to the previous !depthClampEnable logic.
1686 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1687 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1688 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1689 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1691 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1692 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1694 pipeline
->needs_data_cache
= false;
1696 /* When we free the pipeline, we detect stages based on the NULL status
1697 * of various prog_data pointers. Make them NULL by default.
1699 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1701 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1702 if (result
!= VK_SUCCESS
) {
1703 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1707 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1709 anv_pipeline_setup_l3_config(pipeline
, false);
1711 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1712 pCreateInfo
->pVertexInputState
;
1714 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1716 pipeline
->vb_used
= 0;
1717 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1718 const VkVertexInputAttributeDescription
*desc
=
1719 &vi_info
->pVertexAttributeDescriptions
[i
];
1721 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1722 pipeline
->vb_used
|= 1 << desc
->binding
;
1725 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1726 const VkVertexInputBindingDescription
*desc
=
1727 &vi_info
->pVertexBindingDescriptions
[i
];
1729 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1731 /* Step rate is programmed per vertex element (attribute), not
1732 * binding. Set up a map of which bindings step per instance, for
1733 * reference by vertex element setup. */
1734 switch (desc
->inputRate
) {
1736 case VK_VERTEX_INPUT_RATE_VERTEX
:
1737 pipeline
->vb
[desc
->binding
].instanced
= false;
1739 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1740 pipeline
->vb
[desc
->binding
].instanced
= true;
1744 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1747 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1748 vk_find_struct_const(vi_info
->pNext
,
1749 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1751 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1752 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1753 &vi_div_state
->pVertexBindingDivisors
[i
];
1755 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1759 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1760 * different views. If the client asks for instancing, we need to multiply
1761 * the instance divisor by the number of views ensure that we repeat the
1762 * client's per-instance data once for each view.
1764 if (pipeline
->subpass
->view_mask
) {
1765 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1766 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1767 if (pipeline
->vb
[vb
].instanced
)
1768 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1772 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1773 pCreateInfo
->pInputAssemblyState
;
1774 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1775 pCreateInfo
->pTessellationState
;
1776 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1778 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1779 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1781 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];