2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 struct anv_spirv_debug_data
{
99 struct anv_device
*device
;
100 const struct anv_shader_module
*module
;
103 static void anv_spirv_nir_debug(void *private_data
,
104 enum nir_spirv_debug_level level
,
108 struct anv_spirv_debug_data
*debug_data
= private_data
;
109 static const VkDebugReportFlagsEXT vk_flags
[] = {
110 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
111 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
116 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
118 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
120 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
121 (uint64_t) (uintptr_t) debug_data
->module
,
122 0, 0, "anv", buffer
);
125 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
126 * we can't do that yet because we don't have the ability to copy nir.
129 anv_shader_compile_to_nir(struct anv_device
*device
,
131 const struct anv_shader_module
*module
,
132 const char *entrypoint_name
,
133 gl_shader_stage stage
,
134 const VkSpecializationInfo
*spec_info
)
136 const struct anv_physical_device
*pdevice
=
137 &device
->instance
->physicalDevice
;
138 const struct brw_compiler
*compiler
= pdevice
->compiler
;
139 const nir_shader_compiler_options
*nir_options
=
140 compiler
->glsl_compiler_options
[stage
].NirOptions
;
142 uint32_t *spirv
= (uint32_t *) module
->data
;
143 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
144 assert(module
->size
% 4 == 0);
146 uint32_t num_spec_entries
= 0;
147 struct nir_spirv_specialization
*spec_entries
= NULL
;
148 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
149 num_spec_entries
= spec_info
->mapEntryCount
;
150 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
151 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
152 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
153 const void *data
= spec_info
->pData
+ entry
.offset
;
154 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
156 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
157 if (spec_info
->dataSize
== 8)
158 spec_entries
[i
].data64
= *(const uint64_t *)data
;
160 spec_entries
[i
].data32
= *(const uint32_t *)data
;
164 struct anv_spirv_debug_data spirv_debug_data
= {
168 struct spirv_to_nir_options spirv_options
= {
169 .frag_coord_is_sysval
= true,
171 .demote_to_helper_invocation
= true,
172 .derivative_group
= true,
173 .descriptor_array_dynamic_indexing
= true,
174 .descriptor_array_non_uniform_indexing
= true,
175 .descriptor_indexing
= true,
176 .device_group
= true,
177 .draw_parameters
= true,
178 .float16
= pdevice
->info
.gen
>= 8,
179 .float64
= pdevice
->info
.gen
>= 8,
180 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
181 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
182 .geometry_streams
= true,
183 .image_write_without_format
= true,
184 .int8
= pdevice
->info
.gen
>= 8,
185 .int16
= pdevice
->info
.gen
>= 8,
186 .int64
= pdevice
->info
.gen
>= 8,
187 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
190 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
191 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
192 .runtime_descriptor_array
= true,
193 .shader_viewport_index_layer
= true,
194 .stencil_export
= pdevice
->info
.gen
>= 9,
195 .storage_8bit
= pdevice
->info
.gen
>= 8,
196 .storage_16bit
= pdevice
->info
.gen
>= 8,
197 .subgroup_arithmetic
= true,
198 .subgroup_basic
= true,
199 .subgroup_ballot
= true,
200 .subgroup_quad
= true,
201 .subgroup_shuffle
= true,
202 .subgroup_vote
= true,
203 .tessellation
= true,
204 .transform_feedback
= pdevice
->info
.gen
>= 8,
205 .variable_pointers
= true,
207 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
209 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
210 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
211 .push_const_addr_format
= nir_address_format_logical
,
213 /* TODO: Consider changing this to an address format that has the NULL
214 * pointer equals to 0. That might be a better format to play nice
215 * with certain code / code generators.
217 .shared_addr_format
= nir_address_format_32bit_offset
,
219 .func
= anv_spirv_nir_debug
,
220 .private_data
= &spirv_debug_data
,
226 spirv_to_nir(spirv
, module
->size
/ 4,
227 spec_entries
, num_spec_entries
,
228 stage
, entrypoint_name
, &spirv_options
, nir_options
);
229 assert(nir
->info
.stage
== stage
);
230 nir_validate_shader(nir
, "after spirv_to_nir");
231 ralloc_steal(mem_ctx
, nir
);
235 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
236 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
237 gl_shader_stage_name(stage
));
238 nir_print_shader(nir
, stderr
);
241 /* We have to lower away local constant initializers right before we
242 * inline functions. That way they get properly initialized at the top
243 * of the function and not at the top of its caller.
245 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
246 NIR_PASS_V(nir
, nir_lower_returns
);
247 NIR_PASS_V(nir
, nir_inline_functions
);
248 NIR_PASS_V(nir
, nir_opt_deref
);
250 /* Pick off the single entrypoint that we want */
251 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
252 if (!func
->is_entrypoint
)
253 exec_node_remove(&func
->node
);
255 assert(exec_list_length(&nir
->functions
) == 1);
257 /* Now that we've deleted all but the main function, we can go ahead and
258 * lower the rest of the constant initializers. We do this here so that
259 * nir_remove_dead_variables and split_per_member_structs below see the
260 * corresponding stores.
262 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
264 /* Split member structs. We do this before lower_io_to_temporaries so that
265 * it doesn't lower system values to temporaries by accident.
267 NIR_PASS_V(nir
, nir_split_var_copies
);
268 NIR_PASS_V(nir
, nir_split_per_member_structs
);
270 NIR_PASS_V(nir
, nir_remove_dead_variables
,
271 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
273 NIR_PASS_V(nir
, nir_propagate_invariant
);
274 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
275 nir_shader_get_entrypoint(nir
), true, false);
277 NIR_PASS_V(nir
, nir_lower_frexp
);
279 /* Vulkan uses the separate-shader linking model */
280 nir
->info
.separate_shader
= true;
282 brw_preprocess_nir(compiler
, nir
, NULL
);
287 void anv_DestroyPipeline(
289 VkPipeline _pipeline
,
290 const VkAllocationCallbacks
* pAllocator
)
292 ANV_FROM_HANDLE(anv_device
, device
, _device
);
293 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
298 anv_reloc_list_finish(&pipeline
->batch_relocs
,
299 pAllocator
? pAllocator
: &device
->alloc
);
300 if (pipeline
->blend_state
.map
)
301 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
303 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
304 if (pipeline
->shaders
[s
])
305 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
308 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
311 static const uint32_t vk_to_gen_primitive_type
[] = {
312 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
313 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
314 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
315 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
316 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
317 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
318 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
319 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
320 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
321 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
325 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
326 struct brw_sampler_prog_key_data
*key
)
328 /* Almost all multisampled textures are compressed. The only time when we
329 * don't compress a multisampled texture is for 16x MSAA with a surface
330 * width greater than 8k which is a bit of an edge case. Since the sampler
331 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
332 * to tell the compiler to always assume compression.
334 key
->compressed_multisample_layout_mask
= ~0;
336 /* SkyLake added support for 16x MSAA. With this came a new message for
337 * reading from a 16x MSAA surface with compression. The new message was
338 * needed because now the MCS data is 64 bits instead of 32 or lower as is
339 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
340 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
341 * so we can just use it unconditionally. This may not be quite as
342 * efficient but it saves us from recompiling.
344 if (devinfo
->gen
>= 9)
347 /* XXX: Handle texture swizzle on HSW- */
348 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
349 /* Assume color sampler, no swizzling. (Works for BDW+) */
350 key
->swizzles
[i
] = SWIZZLE_XYZW
;
355 populate_base_prog_key(const struct gen_device_info
*devinfo
,
356 VkPipelineShaderStageCreateFlags flags
,
357 struct brw_base_prog_key
*key
)
359 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
360 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
362 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
364 populate_sampler_prog_key(devinfo
, &key
->tex
);
368 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
369 VkPipelineShaderStageCreateFlags flags
,
370 struct brw_vs_prog_key
*key
)
372 memset(key
, 0, sizeof(*key
));
374 populate_base_prog_key(devinfo
, flags
, &key
->base
);
376 /* XXX: Handle vertex input work-arounds */
378 /* XXX: Handle sampler_prog_key */
382 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
383 VkPipelineShaderStageCreateFlags flags
,
384 unsigned input_vertices
,
385 struct brw_tcs_prog_key
*key
)
387 memset(key
, 0, sizeof(*key
));
389 populate_base_prog_key(devinfo
, flags
, &key
->base
);
391 key
->input_vertices
= input_vertices
;
395 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
396 VkPipelineShaderStageCreateFlags flags
,
397 struct brw_tes_prog_key
*key
)
399 memset(key
, 0, sizeof(*key
));
401 populate_base_prog_key(devinfo
, flags
, &key
->base
);
405 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
406 VkPipelineShaderStageCreateFlags flags
,
407 struct brw_gs_prog_key
*key
)
409 memset(key
, 0, sizeof(*key
));
411 populate_base_prog_key(devinfo
, flags
, &key
->base
);
415 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
416 VkPipelineShaderStageCreateFlags flags
,
417 const struct anv_subpass
*subpass
,
418 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
419 struct brw_wm_prog_key
*key
)
421 memset(key
, 0, sizeof(*key
));
423 populate_base_prog_key(devinfo
, flags
, &key
->base
);
425 /* We set this to 0 here and set to the actual value before we call
428 key
->input_slots_valid
= 0;
430 /* Vulkan doesn't specify a default */
431 key
->high_quality_derivatives
= false;
433 /* XXX Vulkan doesn't appear to specify */
434 key
->clamp_fragment_color
= false;
436 assert(subpass
->color_count
<= MAX_RTS
);
437 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
438 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
439 key
->color_outputs_valid
|= (1 << i
);
442 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
444 /* To reduce possible shader recompilations we would need to know if
445 * there is a SampleMask output variable to compute if we should emit
446 * code to workaround the issue that hardware disables alpha to coverage
447 * when there is SampleMask output.
449 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
451 /* Vulkan doesn't support fixed-function alpha test */
452 key
->alpha_test_replicate_alpha
= false;
455 /* We should probably pull this out of the shader, but it's fairly
456 * harmless to compute it and then let dead-code take care of it.
458 if (ms_info
->rasterizationSamples
> 1) {
459 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
460 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
461 key
->multisample_fbo
= true;
464 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
469 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
470 VkPipelineShaderStageCreateFlags flags
,
471 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
472 struct brw_cs_prog_key
*key
)
474 memset(key
, 0, sizeof(*key
));
476 populate_base_prog_key(devinfo
, flags
, &key
->base
);
479 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
481 /* These enum values are expressly chosen to be equal to the subgroup
482 * size that they require.
484 assert(rss_info
->requiredSubgroupSize
== 8 ||
485 rss_info
->requiredSubgroupSize
== 16 ||
486 rss_info
->requiredSubgroupSize
== 32);
487 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
488 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
489 /* If the client expressly requests full subgroups and they don't
490 * specify a subgroup size, we need to pick one. If they're requested
491 * varying subgroup sizes, we set it to UNIFORM and let the back-end
492 * compiler pick. Otherwise, we specify the API value of 32.
493 * Performance will likely be terrible in this case but there's nothing
494 * we can do about that. The client should have chosen a size.
496 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
497 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
499 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
503 struct anv_pipeline_stage
{
504 gl_shader_stage stage
;
506 const struct anv_shader_module
*module
;
507 const char *entrypoint
;
508 const VkSpecializationInfo
*spec_info
;
510 unsigned char shader_sha1
[20];
512 union brw_any_prog_key key
;
515 gl_shader_stage stage
;
516 unsigned char sha1
[20];
521 struct anv_pipeline_binding surface_to_descriptor
[256];
522 struct anv_pipeline_binding sampler_to_descriptor
[256];
523 struct anv_pipeline_bind_map bind_map
;
525 union brw_any_prog_data prog_data
;
528 struct brw_compile_stats stats
[3];
530 VkPipelineCreationFeedbackEXT feedback
;
532 const unsigned *code
;
536 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
537 const char *entrypoint
,
538 gl_shader_stage stage
,
539 const VkSpecializationInfo
*spec_info
,
540 unsigned char *sha1_out
)
542 struct mesa_sha1 ctx
;
543 _mesa_sha1_init(&ctx
);
545 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
546 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
547 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
549 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
550 spec_info
->mapEntryCount
*
551 sizeof(*spec_info
->pMapEntries
));
552 _mesa_sha1_update(&ctx
, spec_info
->pData
,
553 spec_info
->dataSize
);
556 _mesa_sha1_final(&ctx
, sha1_out
);
560 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
561 struct anv_pipeline_layout
*layout
,
562 struct anv_pipeline_stage
*stages
,
563 unsigned char *sha1_out
)
565 struct mesa_sha1 ctx
;
566 _mesa_sha1_init(&ctx
);
568 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
569 sizeof(pipeline
->subpass
->view_mask
));
572 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
574 const bool rba
= pipeline
->device
->robust_buffer_access
;
575 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
577 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
578 if (stages
[s
].entrypoint
) {
579 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
580 sizeof(stages
[s
].shader_sha1
));
581 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
585 _mesa_sha1_final(&ctx
, sha1_out
);
589 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
590 struct anv_pipeline_layout
*layout
,
591 struct anv_pipeline_stage
*stage
,
592 unsigned char *sha1_out
)
594 struct mesa_sha1 ctx
;
595 _mesa_sha1_init(&ctx
);
598 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
600 const bool rba
= pipeline
->device
->robust_buffer_access
;
601 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
603 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
604 sizeof(stage
->shader_sha1
));
605 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
607 _mesa_sha1_final(&ctx
, sha1_out
);
611 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
612 struct anv_pipeline_cache
*cache
,
614 struct anv_pipeline_stage
*stage
)
616 const struct brw_compiler
*compiler
=
617 pipeline
->device
->instance
->physicalDevice
.compiler
;
618 const nir_shader_compiler_options
*nir_options
=
619 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
622 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
627 assert(nir
->info
.stage
== stage
->stage
);
631 nir
= anv_shader_compile_to_nir(pipeline
->device
,
638 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
646 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
648 struct anv_pipeline_stage
*stage
,
649 struct anv_pipeline_layout
*layout
)
651 const struct anv_physical_device
*pdevice
=
652 &pipeline
->device
->instance
->physicalDevice
;
653 const struct brw_compiler
*compiler
= pdevice
->compiler
;
655 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
656 nir_shader
*nir
= stage
->nir
;
658 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
659 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
660 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
663 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
665 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
667 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
668 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
670 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
672 if (nir
->num_uniforms
> 0) {
673 assert(prog_data
->nr_params
== 0);
675 /* If the shader uses any push constants at all, we'll just give
676 * them the maximum possible number
678 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
679 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
680 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
681 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
683 /* We now set the param values to be offsets into a
684 * anv_push_constant_data structure. Since the compiler doesn't
685 * actually dereference any of the gl_constant_value pointers in the
686 * params array, it doesn't really matter what we put here.
688 struct anv_push_constants
*null_data
= NULL
;
689 /* Fill out the push constants section of the param array */
690 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
691 prog_data
->param
[i
] = ANV_PARAM_PUSH(
692 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
696 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
697 pipeline
->needs_data_cache
= true;
699 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
701 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
702 nir_address_format_64bit_global
);
704 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
706 anv_nir_apply_pipeline_layout(pdevice
,
707 pipeline
->device
->robust_buffer_access
,
708 layout
, nir
, prog_data
,
711 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
712 nir_address_format_32bit_index_offset
);
713 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
714 anv_nir_ssbo_addr_format(pdevice
,
715 pipeline
->device
->robust_buffer_access
));
717 NIR_PASS_V(nir
, nir_opt_constant_folding
);
719 /* We don't support non-uniform UBOs and non-uniform SSBO access is
720 * handled naturally by falling back to A64 messages.
722 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
723 nir_lower_non_uniform_texture_access
|
724 nir_lower_non_uniform_image_access
);
727 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
728 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
730 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
736 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
737 struct anv_pipeline_stage
*vs_stage
,
738 struct anv_pipeline_stage
*next_stage
)
741 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
745 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
747 struct anv_device
*device
,
748 struct anv_pipeline_stage
*vs_stage
)
750 brw_compute_vue_map(compiler
->devinfo
,
751 &vs_stage
->prog_data
.vs
.base
.vue_map
,
752 vs_stage
->nir
->info
.outputs_written
,
753 vs_stage
->nir
->info
.separate_shader
);
755 vs_stage
->num_stats
= 1;
756 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
758 &vs_stage
->prog_data
.vs
,
760 vs_stage
->stats
, NULL
);
764 merge_tess_info(struct shader_info
*tes_info
,
765 const struct shader_info
*tcs_info
)
767 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
769 * "PointMode. Controls generation of points rather than triangles
770 * or lines. This functionality defaults to disabled, and is
771 * enabled if either shader stage includes the execution mode.
773 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
774 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
775 * and OutputVertices, it says:
777 * "One mode must be set in at least one of the tessellation
780 * So, the fields can be set in either the TCS or TES, but they must
781 * agree if set in both. Our backend looks at TES, so bitwise-or in
782 * the values from the TCS.
784 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
785 tes_info
->tess
.tcs_vertices_out
== 0 ||
786 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
787 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
789 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
790 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
791 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
792 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
794 assert(tcs_info
->tess
.primitive_mode
== 0 ||
795 tes_info
->tess
.primitive_mode
== 0 ||
796 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
797 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
798 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
799 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
803 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
804 struct anv_pipeline_stage
*tcs_stage
,
805 struct anv_pipeline_stage
*tes_stage
)
807 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
809 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
811 nir_lower_patch_vertices(tes_stage
->nir
,
812 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
815 /* Copy TCS info into the TES info */
816 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
818 /* Whacking the key after cache lookup is a bit sketchy, but all of
819 * this comes from the SPIR-V, which is part of the hash used for the
820 * pipeline cache. So it should be safe.
822 tcs_stage
->key
.tcs
.tes_primitive_mode
=
823 tes_stage
->nir
->info
.tess
.primitive_mode
;
824 tcs_stage
->key
.tcs
.quads_workaround
=
825 compiler
->devinfo
->gen
< 9 &&
826 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
827 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
831 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
833 struct anv_device
*device
,
834 struct anv_pipeline_stage
*tcs_stage
,
835 struct anv_pipeline_stage
*prev_stage
)
837 tcs_stage
->key
.tcs
.outputs_written
=
838 tcs_stage
->nir
->info
.outputs_written
;
839 tcs_stage
->key
.tcs
.patch_outputs_written
=
840 tcs_stage
->nir
->info
.patch_outputs_written
;
842 tcs_stage
->num_stats
= 1;
843 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
845 &tcs_stage
->prog_data
.tcs
,
847 tcs_stage
->stats
, NULL
);
851 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
852 struct anv_pipeline_stage
*tes_stage
,
853 struct anv_pipeline_stage
*next_stage
)
856 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
860 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
862 struct anv_device
*device
,
863 struct anv_pipeline_stage
*tes_stage
,
864 struct anv_pipeline_stage
*tcs_stage
)
866 tes_stage
->key
.tes
.inputs_read
=
867 tcs_stage
->nir
->info
.outputs_written
;
868 tes_stage
->key
.tes
.patch_inputs_read
=
869 tcs_stage
->nir
->info
.patch_outputs_written
;
871 tes_stage
->num_stats
= 1;
872 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
874 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
875 &tes_stage
->prog_data
.tes
,
876 tes_stage
->nir
, NULL
, -1,
877 tes_stage
->stats
, NULL
);
881 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
882 struct anv_pipeline_stage
*gs_stage
,
883 struct anv_pipeline_stage
*next_stage
)
886 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
890 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
892 struct anv_device
*device
,
893 struct anv_pipeline_stage
*gs_stage
,
894 struct anv_pipeline_stage
*prev_stage
)
896 brw_compute_vue_map(compiler
->devinfo
,
897 &gs_stage
->prog_data
.gs
.base
.vue_map
,
898 gs_stage
->nir
->info
.outputs_written
,
899 gs_stage
->nir
->info
.separate_shader
);
901 gs_stage
->num_stats
= 1;
902 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
904 &gs_stage
->prog_data
.gs
,
905 gs_stage
->nir
, NULL
, -1,
906 gs_stage
->stats
, NULL
);
910 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
911 struct anv_pipeline_stage
*stage
)
913 unsigned num_rts
= 0;
914 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
915 struct anv_pipeline_binding rt_bindings
[max_rt
];
916 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
917 int rt_to_bindings
[max_rt
];
918 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
919 bool rt_used
[max_rt
];
920 memset(rt_used
, 0, sizeof(rt_used
));
922 /* Flag used render targets */
923 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
924 if (var
->data
.location
< FRAG_RESULT_DATA0
)
927 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
932 const unsigned array_len
=
933 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
934 assert(rt
+ array_len
<= max_rt
);
937 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
938 /* If this is the RT at location 0 and we have alpha to coverage
939 * enabled we will have to create a null RT for it, so mark it as
942 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
946 for (unsigned i
= 0; i
< array_len
; i
++)
947 rt_used
[rt
+ i
] = true;
950 /* Set new, compacted, location */
951 for (unsigned i
= 0; i
< max_rt
; i
++) {
955 rt_to_bindings
[i
] = num_rts
;
957 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
958 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
959 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
964 /* Setup a null render target */
965 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
966 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
975 bool deleted_output
= false;
976 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
977 if (var
->data
.location
< FRAG_RESULT_DATA0
)
980 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
982 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
983 /* Unused or out-of-bounds, throw it away, unless it is the first
984 * RT and we have alpha to coverage enabled.
986 deleted_output
= true;
987 var
->data
.mode
= nir_var_function_temp
;
988 exec_node_remove(&var
->node
);
989 exec_list_push_tail(&impl
->locals
, &var
->node
);
993 /* Give it the new location */
994 assert(rt_to_bindings
[rt
] != -1);
995 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
999 nir_fixup_deref_modes(stage
->nir
);
1002 /* If we have no render targets, we need a null render target */
1003 rt_bindings
[0] = (struct anv_pipeline_binding
) {
1004 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
1006 .index
= UINT32_MAX
,
1011 /* Now that we've determined the actual number of render targets, adjust
1012 * the key accordingly.
1014 stage
->key
.wm
.nr_color_regions
= num_rts
;
1015 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
1017 assert(num_rts
<= max_rt
);
1018 assert(stage
->bind_map
.surface_count
== 0);
1019 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
1020 rt_bindings
, num_rts
);
1021 stage
->bind_map
.surface_count
+= num_rts
;
1025 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
1027 struct anv_device
*device
,
1028 struct anv_pipeline_stage
*fs_stage
,
1029 struct anv_pipeline_stage
*prev_stage
)
1031 /* TODO: we could set this to 0 based on the information in nir_shader, but
1032 * we need this before we call spirv_to_nir.
1035 fs_stage
->key
.wm
.input_slots_valid
=
1036 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
1038 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
1040 &fs_stage
->prog_data
.wm
,
1041 fs_stage
->nir
, NULL
, -1, -1, -1,
1043 fs_stage
->stats
, NULL
);
1045 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
1046 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
1047 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
1049 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
1050 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1051 !fs_stage
->prog_data
.wm
.uses_kill
&&
1052 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1053 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1054 /* This fragment shader has no outputs and no side effects. Go ahead
1055 * and return the code pointer so we don't accidentally think the
1056 * compile failed but zero out prog_data which will set program_size to
1057 * zero and disable the stage.
1059 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1064 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1065 struct anv_pipeline_cache
*cache
,
1066 const VkGraphicsPipelineCreateInfo
*info
)
1068 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1069 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1071 int64_t pipeline_start
= os_time_get_nano();
1073 const struct brw_compiler
*compiler
=
1074 pipeline
->device
->instance
->physicalDevice
.compiler
;
1075 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1077 pipeline
->active_stages
= 0;
1080 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1081 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1082 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1084 pipeline
->active_stages
|= sinfo
->stage
;
1086 int64_t stage_start
= os_time_get_nano();
1088 stages
[stage
].stage
= stage
;
1089 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1090 stages
[stage
].entrypoint
= sinfo
->pName
;
1091 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1092 anv_pipeline_hash_shader(stages
[stage
].module
,
1093 stages
[stage
].entrypoint
,
1095 stages
[stage
].spec_info
,
1096 stages
[stage
].shader_sha1
);
1098 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1100 case MESA_SHADER_VERTEX
:
1101 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1103 case MESA_SHADER_TESS_CTRL
:
1104 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1105 info
->pTessellationState
->patchControlPoints
,
1106 &stages
[stage
].key
.tcs
);
1108 case MESA_SHADER_TESS_EVAL
:
1109 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1111 case MESA_SHADER_GEOMETRY
:
1112 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1114 case MESA_SHADER_FRAGMENT
:
1115 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1117 info
->pMultisampleState
,
1118 &stages
[stage
].key
.wm
);
1121 unreachable("Invalid graphics shader stage");
1124 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1125 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1128 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1129 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1131 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1133 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1135 unsigned char sha1
[20];
1136 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1138 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1139 if (!stages
[s
].entrypoint
)
1142 stages
[s
].cache_key
.stage
= s
;
1143 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1147 unsigned cache_hits
= 0;
1148 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1149 if (!stages
[s
].entrypoint
)
1152 int64_t stage_start
= os_time_get_nano();
1155 struct anv_shader_bin
*bin
=
1156 anv_device_search_for_kernel(pipeline
->device
, cache
,
1157 &stages
[s
].cache_key
,
1158 sizeof(stages
[s
].cache_key
), &cache_hit
);
1161 pipeline
->shaders
[s
] = bin
;
1166 stages
[s
].feedback
.flags
|=
1167 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1169 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1172 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1173 if (cache_hits
== found
) {
1174 pipeline_feedback
.flags
|=
1175 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1177 /* We found all our shaders in the cache. We're done. */
1179 } else if (found
> 0) {
1180 /* We found some but not all of our shaders. This shouldn't happen
1181 * most of the time but it can if we have a partially populated
1184 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1186 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1187 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1188 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1189 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1190 (uint64_t)(uintptr_t)cache
,
1192 "Found a partial pipeline in the cache. This is "
1193 "most likely caused by an incomplete pipeline cache "
1194 "import or export");
1196 /* We're going to have to recompile anyway, so just throw away our
1197 * references to the shaders in the cache. We'll get them out of the
1198 * cache again as part of the compilation process.
1200 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1201 stages
[s
].feedback
.flags
= 0;
1202 if (pipeline
->shaders
[s
]) {
1203 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1204 pipeline
->shaders
[s
] = NULL
;
1209 void *pipeline_ctx
= ralloc_context(NULL
);
1211 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1212 if (!stages
[s
].entrypoint
)
1215 int64_t stage_start
= os_time_get_nano();
1217 assert(stages
[s
].stage
== s
);
1218 assert(pipeline
->shaders
[s
] == NULL
);
1220 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1221 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1222 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1225 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1228 if (stages
[s
].nir
== NULL
) {
1229 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1233 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1236 /* Walk backwards to link */
1237 struct anv_pipeline_stage
*next_stage
= NULL
;
1238 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1239 if (!stages
[s
].entrypoint
)
1243 case MESA_SHADER_VERTEX
:
1244 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1246 case MESA_SHADER_TESS_CTRL
:
1247 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1249 case MESA_SHADER_TESS_EVAL
:
1250 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1252 case MESA_SHADER_GEOMETRY
:
1253 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1255 case MESA_SHADER_FRAGMENT
:
1256 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1259 unreachable("Invalid graphics shader stage");
1262 next_stage
= &stages
[s
];
1265 struct anv_pipeline_stage
*prev_stage
= NULL
;
1266 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1267 if (!stages
[s
].entrypoint
)
1270 int64_t stage_start
= os_time_get_nano();
1272 void *stage_ctx
= ralloc_context(NULL
);
1274 nir_xfb_info
*xfb_info
= NULL
;
1275 if (s
== MESA_SHADER_VERTEX
||
1276 s
== MESA_SHADER_TESS_EVAL
||
1277 s
== MESA_SHADER_GEOMETRY
)
1278 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1280 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1283 case MESA_SHADER_VERTEX
:
1284 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1287 case MESA_SHADER_TESS_CTRL
:
1288 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1289 &stages
[s
], prev_stage
);
1291 case MESA_SHADER_TESS_EVAL
:
1292 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1293 &stages
[s
], prev_stage
);
1295 case MESA_SHADER_GEOMETRY
:
1296 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1297 &stages
[s
], prev_stage
);
1299 case MESA_SHADER_FRAGMENT
:
1300 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1301 &stages
[s
], prev_stage
);
1304 unreachable("Invalid graphics shader stage");
1306 if (stages
[s
].code
== NULL
) {
1307 ralloc_free(stage_ctx
);
1308 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1312 struct anv_shader_bin
*bin
=
1313 anv_device_upload_kernel(pipeline
->device
, cache
,
1314 &stages
[s
].cache_key
,
1315 sizeof(stages
[s
].cache_key
),
1317 stages
[s
].prog_data
.base
.program_size
,
1318 stages
[s
].nir
->constant_data
,
1319 stages
[s
].nir
->constant_data_size
,
1320 &stages
[s
].prog_data
.base
,
1321 brw_prog_data_size(s
),
1322 stages
[s
].stats
, stages
[s
].num_stats
,
1323 xfb_info
, &stages
[s
].bind_map
);
1325 ralloc_free(stage_ctx
);
1326 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1330 pipeline
->shaders
[s
] = bin
;
1331 ralloc_free(stage_ctx
);
1333 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1335 prev_stage
= &stages
[s
];
1338 ralloc_free(pipeline_ctx
);
1342 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1343 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1344 /* This can happen if we decided to implicitly disable the fragment
1345 * shader. See anv_pipeline_compile_fs().
1347 anv_shader_bin_unref(pipeline
->device
,
1348 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1349 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1350 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1353 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1355 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1356 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1357 if (create_feedback
) {
1358 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1360 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1361 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1362 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1363 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1370 ralloc_free(pipeline_ctx
);
1372 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1373 if (pipeline
->shaders
[s
])
1374 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1381 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1383 assert(glsl_type_is_vector_or_scalar(type
));
1385 uint32_t comp_size
= glsl_type_is_boolean(type
)
1386 ? 4 : glsl_get_bit_size(type
) / 8;
1387 unsigned length
= glsl_get_vector_elements(type
);
1388 *size
= comp_size
* length
,
1389 *align
= comp_size
* (length
== 3 ? 4 : length
);
1393 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1394 struct anv_pipeline_cache
*cache
,
1395 const VkComputePipelineCreateInfo
*info
,
1396 const struct anv_shader_module
*module
,
1397 const char *entrypoint
,
1398 const VkSpecializationInfo
*spec_info
)
1400 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1401 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1403 int64_t pipeline_start
= os_time_get_nano();
1405 const struct brw_compiler
*compiler
=
1406 pipeline
->device
->instance
->physicalDevice
.compiler
;
1408 struct anv_pipeline_stage stage
= {
1409 .stage
= MESA_SHADER_COMPUTE
,
1411 .entrypoint
= entrypoint
,
1412 .spec_info
= spec_info
,
1414 .stage
= MESA_SHADER_COMPUTE
,
1417 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1420 anv_pipeline_hash_shader(stage
.module
,
1422 MESA_SHADER_COMPUTE
,
1426 struct anv_shader_bin
*bin
= NULL
;
1428 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1429 vk_find_struct_const(info
->stage
.pNext
,
1430 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1432 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1433 rss_info
, &stage
.key
.cs
);
1435 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1437 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1439 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1440 sizeof(stage
.cache_key
), &cache_hit
);
1443 int64_t stage_start
= os_time_get_nano();
1445 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1446 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1447 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1450 /* Set up a binding for the gl_NumWorkGroups */
1451 stage
.bind_map
.surface_count
= 1;
1452 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1453 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1456 void *mem_ctx
= ralloc_context(NULL
);
1458 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1459 if (stage
.nir
== NULL
) {
1460 ralloc_free(mem_ctx
);
1461 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1464 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1466 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1467 &stage
.prog_data
.cs
);
1469 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1470 nir_var_mem_shared
, shared_type_info
);
1471 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1472 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1474 stage
.num_stats
= 1;
1475 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1476 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1477 stage
.nir
, -1, stage
.stats
, NULL
);
1478 if (stage
.code
== NULL
) {
1479 ralloc_free(mem_ctx
);
1480 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1483 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1484 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1485 &stage
.cache_key
, sizeof(stage
.cache_key
),
1486 stage
.code
, code_size
,
1487 stage
.nir
->constant_data
,
1488 stage
.nir
->constant_data_size
,
1489 &stage
.prog_data
.base
,
1490 sizeof(stage
.prog_data
.cs
),
1491 stage
.stats
, stage
.num_stats
,
1492 NULL
, &stage
.bind_map
);
1494 ralloc_free(mem_ctx
);
1495 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1498 ralloc_free(mem_ctx
);
1500 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1504 stage
.feedback
.flags
|=
1505 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1506 pipeline_feedback
.flags
|=
1507 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1509 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1511 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1512 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1513 if (create_feedback
) {
1514 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1516 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1517 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1520 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1521 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1527 * Copy pipeline state not marked as dynamic.
1528 * Dynamic state is pipeline state which hasn't been provided at pipeline
1529 * creation time, but is dynamically provided afterwards using various
1530 * vkCmdSet* functions.
1532 * The set of state considered "non_dynamic" is determined by the pieces of
1533 * state that have their corresponding VkDynamicState enums omitted from
1534 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1536 * @param[out] pipeline Destination non_dynamic state.
1537 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1540 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1541 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1543 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1544 struct anv_subpass
*subpass
= pipeline
->subpass
;
1546 pipeline
->dynamic_state
= default_dynamic_state
;
1548 if (pCreateInfo
->pDynamicState
) {
1549 /* Remove all of the states that are marked as dynamic */
1550 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1551 for (uint32_t s
= 0; s
< count
; s
++) {
1552 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1553 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1557 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1559 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1561 * pViewportState is [...] NULL if the pipeline
1562 * has rasterization disabled.
1564 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1565 assert(pCreateInfo
->pViewportState
);
1567 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1568 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1569 typed_memcpy(dynamic
->viewport
.viewports
,
1570 pCreateInfo
->pViewportState
->pViewports
,
1571 pCreateInfo
->pViewportState
->viewportCount
);
1574 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1575 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1576 typed_memcpy(dynamic
->scissor
.scissors
,
1577 pCreateInfo
->pViewportState
->pScissors
,
1578 pCreateInfo
->pViewportState
->scissorCount
);
1582 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1583 assert(pCreateInfo
->pRasterizationState
);
1584 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1587 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1588 assert(pCreateInfo
->pRasterizationState
);
1589 dynamic
->depth_bias
.bias
=
1590 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1591 dynamic
->depth_bias
.clamp
=
1592 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1593 dynamic
->depth_bias
.slope
=
1594 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1597 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1599 * pColorBlendState is [...] NULL if the pipeline has rasterization
1600 * disabled or if the subpass of the render pass the pipeline is
1601 * created against does not use any color attachments.
1603 bool uses_color_att
= false;
1604 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1605 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1606 uses_color_att
= true;
1611 if (uses_color_att
&&
1612 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1613 assert(pCreateInfo
->pColorBlendState
);
1615 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1616 typed_memcpy(dynamic
->blend_constants
,
1617 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1620 /* If there is no depthstencil attachment, then don't read
1621 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1622 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1623 * no need to override the depthstencil defaults in
1624 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1626 * Section 9.2 of the Vulkan 1.0.15 spec says:
1628 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1629 * disabled or if the subpass of the render pass the pipeline is created
1630 * against does not use a depth/stencil attachment.
1632 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1633 subpass
->depth_stencil_attachment
) {
1634 assert(pCreateInfo
->pDepthStencilState
);
1636 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1637 dynamic
->depth_bounds
.min
=
1638 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1639 dynamic
->depth_bounds
.max
=
1640 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1643 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1644 dynamic
->stencil_compare_mask
.front
=
1645 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1646 dynamic
->stencil_compare_mask
.back
=
1647 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1650 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1651 dynamic
->stencil_write_mask
.front
=
1652 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1653 dynamic
->stencil_write_mask
.back
=
1654 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1657 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1658 dynamic
->stencil_reference
.front
=
1659 pCreateInfo
->pDepthStencilState
->front
.reference
;
1660 dynamic
->stencil_reference
.back
=
1661 pCreateInfo
->pDepthStencilState
->back
.reference
;
1665 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1666 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1667 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1669 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1670 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1671 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1675 pipeline
->dynamic_state_mask
= states
;
1679 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1682 struct anv_render_pass
*renderpass
= NULL
;
1683 struct anv_subpass
*subpass
= NULL
;
1685 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1686 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1688 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1690 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1693 assert(info
->subpass
< renderpass
->subpass_count
);
1694 subpass
= &renderpass
->subpasses
[info
->subpass
];
1696 assert(info
->stageCount
>= 1);
1697 assert(info
->pVertexInputState
);
1698 assert(info
->pInputAssemblyState
);
1699 assert(info
->pRasterizationState
);
1700 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1701 assert(info
->pViewportState
);
1702 assert(info
->pMultisampleState
);
1704 if (subpass
&& subpass
->depth_stencil_attachment
)
1705 assert(info
->pDepthStencilState
);
1707 if (subpass
&& subpass
->color_count
> 0) {
1708 bool all_color_unused
= true;
1709 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1710 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1711 all_color_unused
= false;
1713 /* pColorBlendState is ignored if the pipeline has rasterization
1714 * disabled or if the subpass of the render pass the pipeline is
1715 * created against does not use any color attachments.
1717 assert(info
->pColorBlendState
|| all_color_unused
);
1721 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1722 switch (info
->pStages
[i
].stage
) {
1723 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1724 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1725 assert(info
->pTessellationState
);
1735 * Calculate the desired L3 partitioning based on the current state of the
1736 * pipeline. For now this simply returns the conservative defaults calculated
1737 * by get_default_l3_weights(), but we could probably do better by gathering
1738 * more statistics from the pipeline state (e.g. guess of expected URB usage
1739 * and bound surfaces), or by using feed-back from performance counters.
1742 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1744 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1746 const struct gen_l3_weights w
=
1747 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1749 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1750 pipeline
->urb
.total_size
=
1751 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1755 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1756 struct anv_device
*device
,
1757 struct anv_pipeline_cache
*cache
,
1758 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1759 const VkAllocationCallbacks
*alloc
)
1763 anv_pipeline_validate_create_info(pCreateInfo
);
1766 alloc
= &device
->alloc
;
1768 pipeline
->device
= device
;
1770 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1771 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1772 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1774 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1775 if (result
!= VK_SUCCESS
)
1778 pipeline
->batch
.alloc
= alloc
;
1779 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1780 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1781 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1782 pipeline
->batch
.status
= VK_SUCCESS
;
1784 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1785 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1786 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1788 /* Previously we enabled depth clipping when !depthClampEnable.
1789 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1790 * clipping info is available, use its enable value to determine clipping,
1791 * otherwise fallback to the previous !depthClampEnable logic.
1793 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1794 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1795 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1796 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1798 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1799 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1801 pipeline
->needs_data_cache
= false;
1803 /* When we free the pipeline, we detect stages based on the NULL status
1804 * of various prog_data pointers. Make them NULL by default.
1806 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1808 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1809 if (result
!= VK_SUCCESS
) {
1810 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1814 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1816 anv_pipeline_setup_l3_config(pipeline
, false);
1818 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1819 pCreateInfo
->pVertexInputState
;
1821 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1823 pipeline
->vb_used
= 0;
1824 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1825 const VkVertexInputAttributeDescription
*desc
=
1826 &vi_info
->pVertexAttributeDescriptions
[i
];
1828 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1829 pipeline
->vb_used
|= 1 << desc
->binding
;
1832 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1833 const VkVertexInputBindingDescription
*desc
=
1834 &vi_info
->pVertexBindingDescriptions
[i
];
1836 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1838 /* Step rate is programmed per vertex element (attribute), not
1839 * binding. Set up a map of which bindings step per instance, for
1840 * reference by vertex element setup. */
1841 switch (desc
->inputRate
) {
1843 case VK_VERTEX_INPUT_RATE_VERTEX
:
1844 pipeline
->vb
[desc
->binding
].instanced
= false;
1846 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1847 pipeline
->vb
[desc
->binding
].instanced
= true;
1851 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1854 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1855 vk_find_struct_const(vi_info
->pNext
,
1856 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1858 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1859 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1860 &vi_div_state
->pVertexBindingDivisors
[i
];
1862 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1866 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1867 * different views. If the client asks for instancing, we need to multiply
1868 * the instance divisor by the number of views ensure that we repeat the
1869 * client's per-instance data once for each view.
1871 if (pipeline
->subpass
->view_mask
) {
1872 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1873 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1874 if (pipeline
->vb
[vb
].instanced
)
1875 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1879 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1880 pCreateInfo
->pInputAssemblyState
;
1881 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1882 pCreateInfo
->pTessellationState
;
1883 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1885 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1886 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1888 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];