2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
46 VkResult
anv_CreateShaderModule(
48 const VkShaderModuleCreateInfo
* pCreateInfo
,
49 const VkAllocationCallbacks
* pAllocator
,
50 VkShaderModule
* pShaderModule
)
52 ANV_FROM_HANDLE(anv_device
, device
, _device
);
53 struct anv_shader_module
*module
;
55 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
56 assert(pCreateInfo
->flags
== 0);
58 module
= vk_alloc2(&device
->alloc
, pAllocator
,
59 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
64 module
->size
= pCreateInfo
->codeSize
;
65 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
67 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
69 *pShaderModule
= anv_shader_module_to_handle(module
);
74 void anv_DestroyShaderModule(
76 VkShaderModule _module
,
77 const VkAllocationCallbacks
* pAllocator
)
79 ANV_FROM_HANDLE(anv_device
, device
, _device
);
80 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
85 vk_free2(&device
->alloc
, pAllocator
, module
);
88 #define SPIR_V_MAGIC_NUMBER 0x07230203
90 struct anv_spirv_debug_data
{
91 struct anv_device
*device
;
92 const struct anv_shader_module
*module
;
95 static void anv_spirv_nir_debug(void *private_data
,
96 enum nir_spirv_debug_level level
,
100 struct anv_spirv_debug_data
*debug_data
= private_data
;
101 struct anv_instance
*instance
= debug_data
->device
->physical
->instance
;
103 static const VkDebugReportFlagsEXT vk_flags
[] = {
104 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
105 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
106 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
110 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
112 vk_debug_report(&instance
->debug_report_callbacks
,
114 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
115 (uint64_t) (uintptr_t) debug_data
->module
,
116 0, 0, "anv", buffer
);
119 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
120 * we can't do that yet because we don't have the ability to copy nir.
123 anv_shader_compile_to_nir(struct anv_device
*device
,
125 const struct anv_shader_module
*module
,
126 const char *entrypoint_name
,
127 gl_shader_stage stage
,
128 const VkSpecializationInfo
*spec_info
)
130 const struct anv_physical_device
*pdevice
= device
->physical
;
131 const struct brw_compiler
*compiler
= pdevice
->compiler
;
132 const nir_shader_compiler_options
*nir_options
=
133 compiler
->glsl_compiler_options
[stage
].NirOptions
;
135 uint32_t *spirv
= (uint32_t *) module
->data
;
136 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
137 assert(module
->size
% 4 == 0);
139 uint32_t num_spec_entries
= 0;
140 struct nir_spirv_specialization
*spec_entries
= NULL
;
141 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
142 num_spec_entries
= spec_info
->mapEntryCount
;
143 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
144 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
145 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
146 const void *data
= spec_info
->pData
+ entry
.offset
;
147 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
149 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
150 if (spec_info
->dataSize
== 8)
151 spec_entries
[i
].data64
= *(const uint64_t *)data
;
153 spec_entries
[i
].data32
= *(const uint32_t *)data
;
157 struct anv_spirv_debug_data spirv_debug_data
= {
161 struct spirv_to_nir_options spirv_options
= {
162 .frag_coord_is_sysval
= true,
163 .use_scoped_memory_barrier
= true,
165 .demote_to_helper_invocation
= true,
166 .derivative_group
= true,
167 .descriptor_array_dynamic_indexing
= true,
168 .descriptor_array_non_uniform_indexing
= true,
169 .descriptor_indexing
= true,
170 .device_group
= true,
171 .draw_parameters
= true,
172 .float16
= pdevice
->info
.gen
>= 8,
173 .float64
= pdevice
->info
.gen
>= 8,
174 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
175 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
176 .geometry_streams
= true,
177 .image_write_without_format
= true,
178 .int8
= pdevice
->info
.gen
>= 8,
179 .int16
= pdevice
->info
.gen
>= 8,
180 .int64
= pdevice
->info
.gen
>= 8,
181 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
182 .integer_functions2
= pdevice
->info
.gen
>= 8,
185 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
186 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
187 .runtime_descriptor_array
= true,
188 .float_controls
= pdevice
->info
.gen
>= 8,
189 .shader_clock
= true,
190 .shader_viewport_index_layer
= true,
191 .stencil_export
= pdevice
->info
.gen
>= 9,
192 .storage_8bit
= pdevice
->info
.gen
>= 8,
193 .storage_16bit
= pdevice
->info
.gen
>= 8,
194 .subgroup_arithmetic
= true,
195 .subgroup_basic
= true,
196 .subgroup_ballot
= true,
197 .subgroup_quad
= true,
198 .subgroup_shuffle
= true,
199 .subgroup_vote
= true,
200 .tessellation
= true,
201 .transform_feedback
= pdevice
->info
.gen
>= 8,
202 .variable_pointers
= true,
203 .vk_memory_model
= true,
204 .vk_memory_model_device_scope
= true,
206 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
208 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
209 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
210 .push_const_addr_format
= nir_address_format_logical
,
212 /* TODO: Consider changing this to an address format that has the NULL
213 * pointer equals to 0. That might be a better format to play nice
214 * with certain code / code generators.
216 .shared_addr_format
= nir_address_format_32bit_offset
,
218 .func
= anv_spirv_nir_debug
,
219 .private_data
= &spirv_debug_data
,
225 spirv_to_nir(spirv
, module
->size
/ 4,
226 spec_entries
, num_spec_entries
,
227 stage
, entrypoint_name
, &spirv_options
, nir_options
);
228 assert(nir
->info
.stage
== stage
);
229 nir_validate_shader(nir
, "after spirv_to_nir");
230 ralloc_steal(mem_ctx
, nir
);
234 if (unlikely(INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
))) {
235 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
236 gl_shader_stage_name(stage
));
237 nir_print_shader(nir
, stderr
);
240 /* We have to lower away local constant initializers right before we
241 * inline functions. That way they get properly initialized at the top
242 * of the function and not at the top of its caller.
244 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
245 NIR_PASS_V(nir
, nir_lower_returns
);
246 NIR_PASS_V(nir
, nir_inline_functions
);
247 NIR_PASS_V(nir
, nir_opt_deref
);
249 /* Pick off the single entrypoint that we want */
250 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
251 if (!func
->is_entrypoint
)
252 exec_node_remove(&func
->node
);
254 assert(exec_list_length(&nir
->functions
) == 1);
256 /* Now that we've deleted all but the main function, we can go ahead and
257 * lower the rest of the constant initializers. We do this here so that
258 * nir_remove_dead_variables and split_per_member_structs below see the
259 * corresponding stores.
261 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
263 /* Split member structs. We do this before lower_io_to_temporaries so that
264 * it doesn't lower system values to temporaries by accident.
266 NIR_PASS_V(nir
, nir_split_var_copies
);
267 NIR_PASS_V(nir
, nir_split_per_member_structs
);
269 NIR_PASS_V(nir
, nir_remove_dead_variables
,
270 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
272 NIR_PASS_V(nir
, nir_propagate_invariant
);
273 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
274 nir_shader_get_entrypoint(nir
), true, false);
276 NIR_PASS_V(nir
, nir_lower_frexp
);
278 /* Vulkan uses the separate-shader linking model */
279 nir
->info
.separate_shader
= true;
281 brw_preprocess_nir(compiler
, nir
, NULL
);
286 void anv_DestroyPipeline(
288 VkPipeline _pipeline
,
289 const VkAllocationCallbacks
* pAllocator
)
291 ANV_FROM_HANDLE(anv_device
, device
, _device
);
292 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
297 anv_reloc_list_finish(&pipeline
->batch_relocs
,
298 pAllocator
? pAllocator
: &device
->alloc
);
300 ralloc_free(pipeline
->mem_ctx
);
302 if (pipeline
->blend_state
.map
)
303 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
305 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
306 if (pipeline
->shaders
[s
])
307 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
310 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
313 static const uint32_t vk_to_gen_primitive_type
[] = {
314 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
315 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
316 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
317 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
318 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
319 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
320 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
321 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
322 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
323 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
327 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
328 struct brw_sampler_prog_key_data
*key
)
330 /* Almost all multisampled textures are compressed. The only time when we
331 * don't compress a multisampled texture is for 16x MSAA with a surface
332 * width greater than 8k which is a bit of an edge case. Since the sampler
333 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
334 * to tell the compiler to always assume compression.
336 key
->compressed_multisample_layout_mask
= ~0;
338 /* SkyLake added support for 16x MSAA. With this came a new message for
339 * reading from a 16x MSAA surface with compression. The new message was
340 * needed because now the MCS data is 64 bits instead of 32 or lower as is
341 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
342 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
343 * so we can just use it unconditionally. This may not be quite as
344 * efficient but it saves us from recompiling.
346 if (devinfo
->gen
>= 9)
349 /* XXX: Handle texture swizzle on HSW- */
350 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
351 /* Assume color sampler, no swizzling. (Works for BDW+) */
352 key
->swizzles
[i
] = SWIZZLE_XYZW
;
357 populate_base_prog_key(const struct gen_device_info
*devinfo
,
358 VkPipelineShaderStageCreateFlags flags
,
359 struct brw_base_prog_key
*key
)
361 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
362 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
364 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
366 populate_sampler_prog_key(devinfo
, &key
->tex
);
370 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
371 VkPipelineShaderStageCreateFlags flags
,
372 struct brw_vs_prog_key
*key
)
374 memset(key
, 0, sizeof(*key
));
376 populate_base_prog_key(devinfo
, flags
, &key
->base
);
378 /* XXX: Handle vertex input work-arounds */
380 /* XXX: Handle sampler_prog_key */
384 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
385 VkPipelineShaderStageCreateFlags flags
,
386 unsigned input_vertices
,
387 struct brw_tcs_prog_key
*key
)
389 memset(key
, 0, sizeof(*key
));
391 populate_base_prog_key(devinfo
, flags
, &key
->base
);
393 key
->input_vertices
= input_vertices
;
397 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
398 VkPipelineShaderStageCreateFlags flags
,
399 struct brw_tes_prog_key
*key
)
401 memset(key
, 0, sizeof(*key
));
403 populate_base_prog_key(devinfo
, flags
, &key
->base
);
407 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
408 VkPipelineShaderStageCreateFlags flags
,
409 struct brw_gs_prog_key
*key
)
411 memset(key
, 0, sizeof(*key
));
413 populate_base_prog_key(devinfo
, flags
, &key
->base
);
417 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
418 VkPipelineShaderStageCreateFlags flags
,
419 const struct anv_subpass
*subpass
,
420 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
421 struct brw_wm_prog_key
*key
)
423 memset(key
, 0, sizeof(*key
));
425 populate_base_prog_key(devinfo
, flags
, &key
->base
);
427 /* We set this to 0 here and set to the actual value before we call
430 key
->input_slots_valid
= 0;
432 /* Vulkan doesn't specify a default */
433 key
->high_quality_derivatives
= false;
435 /* XXX Vulkan doesn't appear to specify */
436 key
->clamp_fragment_color
= false;
438 assert(subpass
->color_count
<= MAX_RTS
);
439 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
440 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
441 key
->color_outputs_valid
|= (1 << i
);
444 key
->nr_color_regions
= subpass
->color_count
;
446 /* To reduce possible shader recompilations we would need to know if
447 * there is a SampleMask output variable to compute if we should emit
448 * code to workaround the issue that hardware disables alpha to coverage
449 * when there is SampleMask output.
451 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
453 /* Vulkan doesn't support fixed-function alpha test */
454 key
->alpha_test_replicate_alpha
= false;
457 /* We should probably pull this out of the shader, but it's fairly
458 * harmless to compute it and then let dead-code take care of it.
460 if (ms_info
->rasterizationSamples
> 1) {
461 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
462 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
463 key
->multisample_fbo
= true;
466 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
471 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
472 VkPipelineShaderStageCreateFlags flags
,
473 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
474 struct brw_cs_prog_key
*key
)
476 memset(key
, 0, sizeof(*key
));
478 populate_base_prog_key(devinfo
, flags
, &key
->base
);
481 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
483 /* These enum values are expressly chosen to be equal to the subgroup
484 * size that they require.
486 assert(rss_info
->requiredSubgroupSize
== 8 ||
487 rss_info
->requiredSubgroupSize
== 16 ||
488 rss_info
->requiredSubgroupSize
== 32);
489 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
490 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
491 /* If the client expressly requests full subgroups and they don't
492 * specify a subgroup size, we need to pick one. If they're requested
493 * varying subgroup sizes, we set it to UNIFORM and let the back-end
494 * compiler pick. Otherwise, we specify the API value of 32.
495 * Performance will likely be terrible in this case but there's nothing
496 * we can do about that. The client should have chosen a size.
498 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
499 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
501 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
505 struct anv_pipeline_stage
{
506 gl_shader_stage stage
;
508 const struct anv_shader_module
*module
;
509 const char *entrypoint
;
510 const VkSpecializationInfo
*spec_info
;
512 unsigned char shader_sha1
[20];
514 union brw_any_prog_key key
;
517 gl_shader_stage stage
;
518 unsigned char sha1
[20];
523 struct anv_pipeline_binding surface_to_descriptor
[256];
524 struct anv_pipeline_binding sampler_to_descriptor
[256];
525 struct anv_pipeline_bind_map bind_map
;
527 union brw_any_prog_data prog_data
;
530 struct brw_compile_stats stats
[3];
533 VkPipelineCreationFeedbackEXT feedback
;
535 const unsigned *code
;
539 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
540 const char *entrypoint
,
541 gl_shader_stage stage
,
542 const VkSpecializationInfo
*spec_info
,
543 unsigned char *sha1_out
)
545 struct mesa_sha1 ctx
;
546 _mesa_sha1_init(&ctx
);
548 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
549 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
550 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
552 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
553 spec_info
->mapEntryCount
*
554 sizeof(*spec_info
->pMapEntries
));
555 _mesa_sha1_update(&ctx
, spec_info
->pData
,
556 spec_info
->dataSize
);
559 _mesa_sha1_final(&ctx
, sha1_out
);
563 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
564 struct anv_pipeline_layout
*layout
,
565 struct anv_pipeline_stage
*stages
,
566 unsigned char *sha1_out
)
568 struct mesa_sha1 ctx
;
569 _mesa_sha1_init(&ctx
);
571 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
572 sizeof(pipeline
->subpass
->view_mask
));
575 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
577 const bool rba
= pipeline
->device
->robust_buffer_access
;
578 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
580 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
581 if (stages
[s
].entrypoint
) {
582 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
583 sizeof(stages
[s
].shader_sha1
));
584 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
588 _mesa_sha1_final(&ctx
, sha1_out
);
592 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
593 struct anv_pipeline_layout
*layout
,
594 struct anv_pipeline_stage
*stage
,
595 unsigned char *sha1_out
)
597 struct mesa_sha1 ctx
;
598 _mesa_sha1_init(&ctx
);
601 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
603 const bool rba
= pipeline
->device
->robust_buffer_access
;
604 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
606 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
607 sizeof(stage
->shader_sha1
));
608 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
610 _mesa_sha1_final(&ctx
, sha1_out
);
614 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
615 struct anv_pipeline_cache
*cache
,
617 struct anv_pipeline_stage
*stage
)
619 const struct brw_compiler
*compiler
=
620 pipeline
->device
->physical
->compiler
;
621 const nir_shader_compiler_options
*nir_options
=
622 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
625 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
630 assert(nir
->info
.stage
== stage
->stage
);
634 nir
= anv_shader_compile_to_nir(pipeline
->device
,
641 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
649 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
651 struct anv_pipeline_stage
*stage
,
652 struct anv_pipeline_layout
*layout
)
654 const struct anv_physical_device
*pdevice
= pipeline
->device
->physical
;
655 const struct brw_compiler
*compiler
= pdevice
->compiler
;
657 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
658 nir_shader
*nir
= stage
->nir
;
660 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
661 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
662 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
665 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
667 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
668 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
670 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
672 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
673 pipeline
->needs_data_cache
= true;
675 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
677 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
678 nir_address_format_64bit_global
);
680 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
681 anv_nir_apply_pipeline_layout(pdevice
,
682 pipeline
->device
->robust_buffer_access
,
683 layout
, nir
, &stage
->bind_map
);
685 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
686 nir_address_format_32bit_index_offset
);
687 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
688 anv_nir_ssbo_addr_format(pdevice
,
689 pipeline
->device
->robust_buffer_access
));
691 NIR_PASS_V(nir
, nir_opt_constant_folding
);
693 /* We don't support non-uniform UBOs and non-uniform SSBO access is
694 * handled naturally by falling back to A64 messages.
696 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
697 nir_lower_non_uniform_texture_access
|
698 nir_lower_non_uniform_image_access
);
700 anv_nir_compute_push_layout(pdevice
, nir
, prog_data
,
701 &stage
->bind_map
, mem_ctx
);
707 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
708 struct anv_pipeline_stage
*vs_stage
,
709 struct anv_pipeline_stage
*next_stage
)
712 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
716 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
718 struct anv_device
*device
,
719 struct anv_pipeline_stage
*vs_stage
)
721 brw_compute_vue_map(compiler
->devinfo
,
722 &vs_stage
->prog_data
.vs
.base
.vue_map
,
723 vs_stage
->nir
->info
.outputs_written
,
724 vs_stage
->nir
->info
.separate_shader
);
726 vs_stage
->num_stats
= 1;
727 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
729 &vs_stage
->prog_data
.vs
,
731 vs_stage
->stats
, NULL
);
735 merge_tess_info(struct shader_info
*tes_info
,
736 const struct shader_info
*tcs_info
)
738 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
740 * "PointMode. Controls generation of points rather than triangles
741 * or lines. This functionality defaults to disabled, and is
742 * enabled if either shader stage includes the execution mode.
744 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
745 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
746 * and OutputVertices, it says:
748 * "One mode must be set in at least one of the tessellation
751 * So, the fields can be set in either the TCS or TES, but they must
752 * agree if set in both. Our backend looks at TES, so bitwise-or in
753 * the values from the TCS.
755 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
756 tes_info
->tess
.tcs_vertices_out
== 0 ||
757 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
758 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
760 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
761 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
762 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
763 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
765 assert(tcs_info
->tess
.primitive_mode
== 0 ||
766 tes_info
->tess
.primitive_mode
== 0 ||
767 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
768 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
769 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
770 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
774 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
775 struct anv_pipeline_stage
*tcs_stage
,
776 struct anv_pipeline_stage
*tes_stage
)
778 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
780 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
782 nir_lower_patch_vertices(tes_stage
->nir
,
783 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
786 /* Copy TCS info into the TES info */
787 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
789 /* Whacking the key after cache lookup is a bit sketchy, but all of
790 * this comes from the SPIR-V, which is part of the hash used for the
791 * pipeline cache. So it should be safe.
793 tcs_stage
->key
.tcs
.tes_primitive_mode
=
794 tes_stage
->nir
->info
.tess
.primitive_mode
;
795 tcs_stage
->key
.tcs
.quads_workaround
=
796 compiler
->devinfo
->gen
< 9 &&
797 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
798 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
802 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
804 struct anv_device
*device
,
805 struct anv_pipeline_stage
*tcs_stage
,
806 struct anv_pipeline_stage
*prev_stage
)
808 tcs_stage
->key
.tcs
.outputs_written
=
809 tcs_stage
->nir
->info
.outputs_written
;
810 tcs_stage
->key
.tcs
.patch_outputs_written
=
811 tcs_stage
->nir
->info
.patch_outputs_written
;
813 tcs_stage
->num_stats
= 1;
814 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
816 &tcs_stage
->prog_data
.tcs
,
818 tcs_stage
->stats
, NULL
);
822 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
823 struct anv_pipeline_stage
*tes_stage
,
824 struct anv_pipeline_stage
*next_stage
)
827 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
831 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
833 struct anv_device
*device
,
834 struct anv_pipeline_stage
*tes_stage
,
835 struct anv_pipeline_stage
*tcs_stage
)
837 tes_stage
->key
.tes
.inputs_read
=
838 tcs_stage
->nir
->info
.outputs_written
;
839 tes_stage
->key
.tes
.patch_inputs_read
=
840 tcs_stage
->nir
->info
.patch_outputs_written
;
842 tes_stage
->num_stats
= 1;
843 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
845 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
846 &tes_stage
->prog_data
.tes
,
848 tes_stage
->stats
, NULL
);
852 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
853 struct anv_pipeline_stage
*gs_stage
,
854 struct anv_pipeline_stage
*next_stage
)
857 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
861 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
863 struct anv_device
*device
,
864 struct anv_pipeline_stage
*gs_stage
,
865 struct anv_pipeline_stage
*prev_stage
)
867 brw_compute_vue_map(compiler
->devinfo
,
868 &gs_stage
->prog_data
.gs
.base
.vue_map
,
869 gs_stage
->nir
->info
.outputs_written
,
870 gs_stage
->nir
->info
.separate_shader
);
872 gs_stage
->num_stats
= 1;
873 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
875 &gs_stage
->prog_data
.gs
,
876 gs_stage
->nir
, NULL
, -1,
877 gs_stage
->stats
, NULL
);
881 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
882 struct anv_pipeline_stage
*stage
)
884 unsigned num_rt_bindings
;
885 struct anv_pipeline_binding rt_bindings
[MAX_RTS
];
886 if (stage
->key
.wm
.nr_color_regions
> 0) {
887 assert(stage
->key
.wm
.nr_color_regions
<= MAX_RTS
);
888 for (unsigned rt
= 0; rt
< stage
->key
.wm
.nr_color_regions
; rt
++) {
889 if (stage
->key
.wm
.color_outputs_valid
& BITFIELD_BIT(rt
)) {
890 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
891 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
895 /* Setup a null render target */
896 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
897 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
902 num_rt_bindings
= stage
->key
.wm
.nr_color_regions
;
904 /* Setup a null render target */
905 rt_bindings
[0] = (struct anv_pipeline_binding
) {
906 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
912 assert(num_rt_bindings
<= MAX_RTS
);
913 assert(stage
->bind_map
.surface_count
== 0);
914 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
915 rt_bindings
, num_rt_bindings
);
916 stage
->bind_map
.surface_count
+= num_rt_bindings
;
918 /* Now that we've set up the color attachments, we can go through and
919 * eliminate any shader outputs that map to VK_ATTACHMENT_UNUSED in the
920 * hopes that dead code can clean them up in this and any earlier shader
923 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
924 bool deleted_output
= false;
925 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
926 /* TODO: We don't delete depth/stencil writes. We probably could if the
927 * subpass doesn't have a depth/stencil attachment.
929 if (var
->data
.location
< FRAG_RESULT_DATA0
)
932 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
934 /* If this is the RT at location 0 and we have alpha to coverage
935 * enabled we still need that write because it will affect the coverage
936 * mask even if it's never written to a color target.
938 if (rt
== 0 && stage
->key
.wm
.alpha_to_coverage
)
941 const unsigned array_len
=
942 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
943 assert(rt
+ array_len
<= MAX_RTS
);
945 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
&
946 BITFIELD_RANGE(rt
, array_len
))) {
947 deleted_output
= true;
948 var
->data
.mode
= nir_var_function_temp
;
949 exec_node_remove(&var
->node
);
950 exec_list_push_tail(&impl
->locals
, &var
->node
);
955 nir_fixup_deref_modes(stage
->nir
);
957 /* We stored the number of subpass color attachments in nr_color_regions
958 * when calculating the key for caching. Now that we've computed the bind
959 * map, we can reduce this to the actual max before we go into the back-end
962 stage
->key
.wm
.nr_color_regions
=
963 util_last_bit(stage
->key
.wm
.color_outputs_valid
);
967 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
969 struct anv_device
*device
,
970 struct anv_pipeline_stage
*fs_stage
,
971 struct anv_pipeline_stage
*prev_stage
)
973 /* TODO: we could set this to 0 based on the information in nir_shader, but
974 * we need this before we call spirv_to_nir.
977 fs_stage
->key
.wm
.input_slots_valid
=
978 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
980 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
982 &fs_stage
->prog_data
.wm
,
983 fs_stage
->nir
, -1, -1, -1,
985 fs_stage
->stats
, NULL
);
987 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
988 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
989 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
991 if (fs_stage
->key
.wm
.color_outputs_valid
== 0 &&
992 !fs_stage
->prog_data
.wm
.has_side_effects
&&
993 !fs_stage
->prog_data
.wm
.uses_omask
&&
994 !fs_stage
->key
.wm
.alpha_to_coverage
&&
995 !fs_stage
->prog_data
.wm
.uses_kill
&&
996 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
997 !fs_stage
->prog_data
.wm
.computed_stencil
) {
998 /* This fragment shader has no outputs and no side effects. Go ahead
999 * and return the code pointer so we don't accidentally think the
1000 * compile failed but zero out prog_data which will set program_size to
1001 * zero and disable the stage.
1003 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1008 anv_pipeline_add_executable(struct anv_pipeline
*pipeline
,
1009 struct anv_pipeline_stage
*stage
,
1010 struct brw_compile_stats
*stats
,
1011 uint32_t code_offset
)
1016 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1017 char *stream_data
= NULL
;
1018 size_t stream_size
= 0;
1019 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1021 nir_print_shader(stage
->nir
, stream
);
1025 /* Copy it to a ralloc'd thing */
1026 nir
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1027 memcpy(nir
, stream_data
, stream_size
);
1028 nir
[stream_size
] = 0;
1033 char *disasm
= NULL
;
1036 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1037 char *stream_data
= NULL
;
1038 size_t stream_size
= 0;
1039 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1041 /* Creating this is far cheaper than it looks. It's perfectly fine to
1042 * do it for every binary.
1044 struct gen_disasm
*d
= gen_disasm_create(&pipeline
->device
->info
);
1045 gen_disasm_disassemble(d
, stage
->code
, code_offset
, stream
);
1046 gen_disasm_destroy(d
);
1050 /* Copy it to a ralloc'd thing */
1051 disasm
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1052 memcpy(disasm
, stream_data
, stream_size
);
1053 disasm
[stream_size
] = 0;
1058 pipeline
->executables
[pipeline
->num_executables
++] =
1059 (struct anv_pipeline_executable
) {
1060 .stage
= stage
->stage
,
1068 anv_pipeline_add_executables(struct anv_pipeline
*pipeline
,
1069 struct anv_pipeline_stage
*stage
,
1070 struct anv_shader_bin
*bin
)
1072 if (stage
->stage
== MESA_SHADER_FRAGMENT
) {
1073 /* We pull the prog data and stats out of the anv_shader_bin because
1074 * the anv_pipeline_stage may not be fully populated if we successfully
1075 * looked up the shader in a cache.
1077 const struct brw_wm_prog_data
*wm_prog_data
=
1078 (const struct brw_wm_prog_data
*)bin
->prog_data
;
1079 struct brw_compile_stats
*stats
= bin
->stats
;
1081 if (wm_prog_data
->dispatch_8
) {
1082 anv_pipeline_add_executable(pipeline
, stage
, stats
++, 0);
1085 if (wm_prog_data
->dispatch_16
) {
1086 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1087 wm_prog_data
->prog_offset_16
);
1090 if (wm_prog_data
->dispatch_32
) {
1091 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1092 wm_prog_data
->prog_offset_32
);
1095 anv_pipeline_add_executable(pipeline
, stage
, bin
->stats
, 0);
1100 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1101 struct anv_pipeline_cache
*cache
,
1102 const VkGraphicsPipelineCreateInfo
*info
)
1104 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1105 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1107 int64_t pipeline_start
= os_time_get_nano();
1109 const struct brw_compiler
*compiler
= pipeline
->device
->physical
->compiler
;
1110 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1112 pipeline
->active_stages
= 0;
1115 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1116 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1117 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1119 pipeline
->active_stages
|= sinfo
->stage
;
1121 int64_t stage_start
= os_time_get_nano();
1123 stages
[stage
].stage
= stage
;
1124 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1125 stages
[stage
].entrypoint
= sinfo
->pName
;
1126 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1127 anv_pipeline_hash_shader(stages
[stage
].module
,
1128 stages
[stage
].entrypoint
,
1130 stages
[stage
].spec_info
,
1131 stages
[stage
].shader_sha1
);
1133 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1135 case MESA_SHADER_VERTEX
:
1136 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1138 case MESA_SHADER_TESS_CTRL
:
1139 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1140 info
->pTessellationState
->patchControlPoints
,
1141 &stages
[stage
].key
.tcs
);
1143 case MESA_SHADER_TESS_EVAL
:
1144 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1146 case MESA_SHADER_GEOMETRY
:
1147 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1149 case MESA_SHADER_FRAGMENT
: {
1150 const bool raster_enabled
=
1151 !info
->pRasterizationState
->rasterizerDiscardEnable
;
1152 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1154 raster_enabled
? info
->pMultisampleState
: NULL
,
1155 &stages
[stage
].key
.wm
);
1159 unreachable("Invalid graphics shader stage");
1162 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1163 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1166 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1167 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1169 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1171 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1173 unsigned char sha1
[20];
1174 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1176 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1177 if (!stages
[s
].entrypoint
)
1180 stages
[s
].cache_key
.stage
= s
;
1181 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1184 const bool skip_cache_lookup
=
1185 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1187 if (!skip_cache_lookup
) {
1189 unsigned cache_hits
= 0;
1190 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1191 if (!stages
[s
].entrypoint
)
1194 int64_t stage_start
= os_time_get_nano();
1197 struct anv_shader_bin
*bin
=
1198 anv_device_search_for_kernel(pipeline
->device
, cache
,
1199 &stages
[s
].cache_key
,
1200 sizeof(stages
[s
].cache_key
), &cache_hit
);
1203 pipeline
->shaders
[s
] = bin
;
1208 stages
[s
].feedback
.flags
|=
1209 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1211 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1214 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1215 if (cache_hits
== found
) {
1216 pipeline_feedback
.flags
|=
1217 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1219 /* We found all our shaders in the cache. We're done. */
1220 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1221 if (!stages
[s
].entrypoint
)
1224 anv_pipeline_add_executables(pipeline
, &stages
[s
],
1225 pipeline
->shaders
[s
]);
1228 } else if (found
> 0) {
1229 /* We found some but not all of our shaders. This shouldn't happen
1230 * most of the time but it can if we have a partially populated
1233 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1235 vk_debug_report(&pipeline
->device
->physical
->instance
->debug_report_callbacks
,
1236 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1237 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1238 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1239 (uint64_t)(uintptr_t)cache
,
1241 "Found a partial pipeline in the cache. This is "
1242 "most likely caused by an incomplete pipeline cache "
1243 "import or export");
1245 /* We're going to have to recompile anyway, so just throw away our
1246 * references to the shaders in the cache. We'll get them out of the
1247 * cache again as part of the compilation process.
1249 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1250 stages
[s
].feedback
.flags
= 0;
1251 if (pipeline
->shaders
[s
]) {
1252 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1253 pipeline
->shaders
[s
] = NULL
;
1259 void *pipeline_ctx
= ralloc_context(NULL
);
1261 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1262 if (!stages
[s
].entrypoint
)
1265 int64_t stage_start
= os_time_get_nano();
1267 assert(stages
[s
].stage
== s
);
1268 assert(pipeline
->shaders
[s
] == NULL
);
1270 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1271 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1272 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1275 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1278 if (stages
[s
].nir
== NULL
) {
1279 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1283 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1286 /* Walk backwards to link */
1287 struct anv_pipeline_stage
*next_stage
= NULL
;
1288 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1289 if (!stages
[s
].entrypoint
)
1293 case MESA_SHADER_VERTEX
:
1294 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1296 case MESA_SHADER_TESS_CTRL
:
1297 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1299 case MESA_SHADER_TESS_EVAL
:
1300 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1302 case MESA_SHADER_GEOMETRY
:
1303 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1305 case MESA_SHADER_FRAGMENT
:
1306 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1309 unreachable("Invalid graphics shader stage");
1312 next_stage
= &stages
[s
];
1315 struct anv_pipeline_stage
*prev_stage
= NULL
;
1316 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1317 if (!stages
[s
].entrypoint
)
1320 int64_t stage_start
= os_time_get_nano();
1322 void *stage_ctx
= ralloc_context(NULL
);
1324 nir_xfb_info
*xfb_info
= NULL
;
1325 if (s
== MESA_SHADER_VERTEX
||
1326 s
== MESA_SHADER_TESS_EVAL
||
1327 s
== MESA_SHADER_GEOMETRY
)
1328 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1330 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1333 case MESA_SHADER_VERTEX
:
1334 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1337 case MESA_SHADER_TESS_CTRL
:
1338 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1339 &stages
[s
], prev_stage
);
1341 case MESA_SHADER_TESS_EVAL
:
1342 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1343 &stages
[s
], prev_stage
);
1345 case MESA_SHADER_GEOMETRY
:
1346 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1347 &stages
[s
], prev_stage
);
1349 case MESA_SHADER_FRAGMENT
:
1350 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1351 &stages
[s
], prev_stage
);
1354 unreachable("Invalid graphics shader stage");
1356 if (stages
[s
].code
== NULL
) {
1357 ralloc_free(stage_ctx
);
1358 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1362 anv_nir_validate_push_layout(&stages
[s
].prog_data
.base
,
1363 &stages
[s
].bind_map
);
1365 struct anv_shader_bin
*bin
=
1366 anv_device_upload_kernel(pipeline
->device
, cache
,
1367 &stages
[s
].cache_key
,
1368 sizeof(stages
[s
].cache_key
),
1370 stages
[s
].prog_data
.base
.program_size
,
1371 stages
[s
].nir
->constant_data
,
1372 stages
[s
].nir
->constant_data_size
,
1373 &stages
[s
].prog_data
.base
,
1374 brw_prog_data_size(s
),
1375 stages
[s
].stats
, stages
[s
].num_stats
,
1376 xfb_info
, &stages
[s
].bind_map
);
1378 ralloc_free(stage_ctx
);
1379 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1383 anv_pipeline_add_executables(pipeline
, &stages
[s
], bin
);
1385 pipeline
->shaders
[s
] = bin
;
1386 ralloc_free(stage_ctx
);
1388 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1390 prev_stage
= &stages
[s
];
1393 ralloc_free(pipeline_ctx
);
1397 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1398 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1399 /* This can happen if we decided to implicitly disable the fragment
1400 * shader. See anv_pipeline_compile_fs().
1402 anv_shader_bin_unref(pipeline
->device
,
1403 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1404 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1405 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1408 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1410 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1411 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1412 if (create_feedback
) {
1413 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1415 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1416 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1417 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1418 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1425 ralloc_free(pipeline_ctx
);
1427 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1428 if (pipeline
->shaders
[s
])
1429 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1436 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1438 assert(glsl_type_is_vector_or_scalar(type
));
1440 uint32_t comp_size
= glsl_type_is_boolean(type
)
1441 ? 4 : glsl_get_bit_size(type
) / 8;
1442 unsigned length
= glsl_get_vector_elements(type
);
1443 *size
= comp_size
* length
,
1444 *align
= comp_size
* (length
== 3 ? 4 : length
);
1448 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1449 struct anv_pipeline_cache
*cache
,
1450 const VkComputePipelineCreateInfo
*info
,
1451 const struct anv_shader_module
*module
,
1452 const char *entrypoint
,
1453 const VkSpecializationInfo
*spec_info
)
1455 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1456 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1458 int64_t pipeline_start
= os_time_get_nano();
1460 const struct brw_compiler
*compiler
= pipeline
->device
->physical
->compiler
;
1462 struct anv_pipeline_stage stage
= {
1463 .stage
= MESA_SHADER_COMPUTE
,
1465 .entrypoint
= entrypoint
,
1466 .spec_info
= spec_info
,
1468 .stage
= MESA_SHADER_COMPUTE
,
1471 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1474 anv_pipeline_hash_shader(stage
.module
,
1476 MESA_SHADER_COMPUTE
,
1480 struct anv_shader_bin
*bin
= NULL
;
1482 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1483 vk_find_struct_const(info
->stage
.pNext
,
1484 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1486 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1487 rss_info
, &stage
.key
.cs
);
1489 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1491 const bool skip_cache_lookup
=
1492 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1494 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1496 bool cache_hit
= false;
1497 if (!skip_cache_lookup
) {
1498 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
1500 sizeof(stage
.cache_key
),
1504 void *mem_ctx
= ralloc_context(NULL
);
1506 int64_t stage_start
= os_time_get_nano();
1508 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1509 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1510 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1513 /* Set up a binding for the gl_NumWorkGroups */
1514 stage
.bind_map
.surface_count
= 1;
1515 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1516 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1519 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1520 if (stage
.nir
== NULL
) {
1521 ralloc_free(mem_ctx
);
1522 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1525 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
);
1527 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1529 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1530 nir_var_mem_shared
, shared_type_info
);
1531 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1532 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1534 stage
.num_stats
= 1;
1535 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1536 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1537 stage
.nir
, -1, stage
.stats
, NULL
);
1538 if (stage
.code
== NULL
) {
1539 ralloc_free(mem_ctx
);
1540 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1543 anv_nir_validate_push_layout(&stage
.prog_data
.base
, &stage
.bind_map
);
1545 if (!stage
.prog_data
.cs
.uses_num_work_groups
) {
1546 assert(stage
.bind_map
.surface_to_descriptor
[0].set
==
1547 ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
);
1548 stage
.bind_map
.surface_to_descriptor
[0].set
= ANV_DESCRIPTOR_SET_NULL
;
1551 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1552 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1553 &stage
.cache_key
, sizeof(stage
.cache_key
),
1554 stage
.code
, code_size
,
1555 stage
.nir
->constant_data
,
1556 stage
.nir
->constant_data_size
,
1557 &stage
.prog_data
.base
,
1558 sizeof(stage
.prog_data
.cs
),
1559 stage
.stats
, stage
.num_stats
,
1560 NULL
, &stage
.bind_map
);
1562 ralloc_free(mem_ctx
);
1563 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1566 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1569 anv_pipeline_add_executables(pipeline
, &stage
, bin
);
1571 ralloc_free(mem_ctx
);
1574 stage
.feedback
.flags
|=
1575 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1576 pipeline_feedback
.flags
|=
1577 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1579 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1581 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1582 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1583 if (create_feedback
) {
1584 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1586 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1587 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1590 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1591 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1597 * Copy pipeline state not marked as dynamic.
1598 * Dynamic state is pipeline state which hasn't been provided at pipeline
1599 * creation time, but is dynamically provided afterwards using various
1600 * vkCmdSet* functions.
1602 * The set of state considered "non_dynamic" is determined by the pieces of
1603 * state that have their corresponding VkDynamicState enums omitted from
1604 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1606 * @param[out] pipeline Destination non_dynamic state.
1607 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1610 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1611 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1613 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1614 struct anv_subpass
*subpass
= pipeline
->subpass
;
1616 pipeline
->dynamic_state
= default_dynamic_state
;
1618 if (pCreateInfo
->pDynamicState
) {
1619 /* Remove all of the states that are marked as dynamic */
1620 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1621 for (uint32_t s
= 0; s
< count
; s
++) {
1622 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1623 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1627 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1629 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1631 * pViewportState is [...] NULL if the pipeline
1632 * has rasterization disabled.
1634 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1635 assert(pCreateInfo
->pViewportState
);
1637 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1638 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1639 typed_memcpy(dynamic
->viewport
.viewports
,
1640 pCreateInfo
->pViewportState
->pViewports
,
1641 pCreateInfo
->pViewportState
->viewportCount
);
1644 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1645 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1646 typed_memcpy(dynamic
->scissor
.scissors
,
1647 pCreateInfo
->pViewportState
->pScissors
,
1648 pCreateInfo
->pViewportState
->scissorCount
);
1652 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1653 assert(pCreateInfo
->pRasterizationState
);
1654 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1657 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1658 assert(pCreateInfo
->pRasterizationState
);
1659 dynamic
->depth_bias
.bias
=
1660 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1661 dynamic
->depth_bias
.clamp
=
1662 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1663 dynamic
->depth_bias
.slope
=
1664 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1667 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1669 * pColorBlendState is [...] NULL if the pipeline has rasterization
1670 * disabled or if the subpass of the render pass the pipeline is
1671 * created against does not use any color attachments.
1673 bool uses_color_att
= false;
1674 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1675 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1676 uses_color_att
= true;
1681 if (uses_color_att
&&
1682 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1683 assert(pCreateInfo
->pColorBlendState
);
1685 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1686 typed_memcpy(dynamic
->blend_constants
,
1687 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1690 /* If there is no depthstencil attachment, then don't read
1691 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1692 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1693 * no need to override the depthstencil defaults in
1694 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1696 * Section 9.2 of the Vulkan 1.0.15 spec says:
1698 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1699 * disabled or if the subpass of the render pass the pipeline is created
1700 * against does not use a depth/stencil attachment.
1702 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1703 subpass
->depth_stencil_attachment
) {
1704 assert(pCreateInfo
->pDepthStencilState
);
1706 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1707 dynamic
->depth_bounds
.min
=
1708 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1709 dynamic
->depth_bounds
.max
=
1710 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1713 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1714 dynamic
->stencil_compare_mask
.front
=
1715 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1716 dynamic
->stencil_compare_mask
.back
=
1717 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1720 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1721 dynamic
->stencil_write_mask
.front
=
1722 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1723 dynamic
->stencil_write_mask
.back
=
1724 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1727 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1728 dynamic
->stencil_reference
.front
=
1729 pCreateInfo
->pDepthStencilState
->front
.reference
;
1730 dynamic
->stencil_reference
.back
=
1731 pCreateInfo
->pDepthStencilState
->back
.reference
;
1735 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1736 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1737 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1739 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1740 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1741 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1745 pipeline
->dynamic_state_mask
= states
;
1749 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1752 struct anv_render_pass
*renderpass
= NULL
;
1753 struct anv_subpass
*subpass
= NULL
;
1755 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1756 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1758 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1760 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1763 assert(info
->subpass
< renderpass
->subpass_count
);
1764 subpass
= &renderpass
->subpasses
[info
->subpass
];
1766 assert(info
->stageCount
>= 1);
1767 assert(info
->pVertexInputState
);
1768 assert(info
->pInputAssemblyState
);
1769 assert(info
->pRasterizationState
);
1770 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1771 assert(info
->pViewportState
);
1772 assert(info
->pMultisampleState
);
1774 if (subpass
&& subpass
->depth_stencil_attachment
)
1775 assert(info
->pDepthStencilState
);
1777 if (subpass
&& subpass
->color_count
> 0) {
1778 bool all_color_unused
= true;
1779 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1780 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1781 all_color_unused
= false;
1783 /* pColorBlendState is ignored if the pipeline has rasterization
1784 * disabled or if the subpass of the render pass the pipeline is
1785 * created against does not use any color attachments.
1787 assert(info
->pColorBlendState
|| all_color_unused
);
1791 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1792 switch (info
->pStages
[i
].stage
) {
1793 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1794 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1795 assert(info
->pTessellationState
);
1805 * Calculate the desired L3 partitioning based on the current state of the
1806 * pipeline. For now this simply returns the conservative defaults calculated
1807 * by get_default_l3_weights(), but we could probably do better by gathering
1808 * more statistics from the pipeline state (e.g. guess of expected URB usage
1809 * and bound surfaces), or by using feed-back from performance counters.
1812 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1814 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1816 const struct gen_l3_weights w
=
1817 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1819 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1820 pipeline
->urb
.total_size
=
1821 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1825 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1826 struct anv_device
*device
,
1827 struct anv_pipeline_cache
*cache
,
1828 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1829 const VkAllocationCallbacks
*alloc
)
1833 anv_pipeline_validate_create_info(pCreateInfo
);
1836 alloc
= &device
->alloc
;
1838 pipeline
->device
= device
;
1840 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1841 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1842 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1844 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1845 if (result
!= VK_SUCCESS
)
1848 pipeline
->batch
.alloc
= alloc
;
1849 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1850 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1851 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1852 pipeline
->batch
.status
= VK_SUCCESS
;
1854 pipeline
->mem_ctx
= ralloc_context(NULL
);
1855 pipeline
->flags
= pCreateInfo
->flags
;
1857 assert(pCreateInfo
->pRasterizationState
);
1859 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1860 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
->depthClampEnable
;
1862 /* Previously we enabled depth clipping when !depthClampEnable.
1863 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1864 * clipping info is available, use its enable value to determine clipping,
1865 * otherwise fallback to the previous !depthClampEnable logic.
1867 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1868 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1869 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1870 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1872 pipeline
->sample_shading_enable
=
1873 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1874 pCreateInfo
->pMultisampleState
&&
1875 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1877 pipeline
->needs_data_cache
= false;
1879 /* When we free the pipeline, we detect stages based on the NULL status
1880 * of various prog_data pointers. Make them NULL by default.
1882 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1883 pipeline
->num_executables
= 0;
1885 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1886 if (result
!= VK_SUCCESS
) {
1887 ralloc_free(pipeline
->mem_ctx
);
1888 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1892 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1894 anv_pipeline_setup_l3_config(pipeline
, false);
1896 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1897 pCreateInfo
->pVertexInputState
;
1899 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1901 pipeline
->vb_used
= 0;
1902 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1903 const VkVertexInputAttributeDescription
*desc
=
1904 &vi_info
->pVertexAttributeDescriptions
[i
];
1906 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1907 pipeline
->vb_used
|= 1 << desc
->binding
;
1910 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1911 const VkVertexInputBindingDescription
*desc
=
1912 &vi_info
->pVertexBindingDescriptions
[i
];
1914 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1916 /* Step rate is programmed per vertex element (attribute), not
1917 * binding. Set up a map of which bindings step per instance, for
1918 * reference by vertex element setup. */
1919 switch (desc
->inputRate
) {
1921 case VK_VERTEX_INPUT_RATE_VERTEX
:
1922 pipeline
->vb
[desc
->binding
].instanced
= false;
1924 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1925 pipeline
->vb
[desc
->binding
].instanced
= true;
1929 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1932 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1933 vk_find_struct_const(vi_info
->pNext
,
1934 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1936 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1937 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1938 &vi_div_state
->pVertexBindingDivisors
[i
];
1940 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1944 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1945 * different views. If the client asks for instancing, we need to multiply
1946 * the instance divisor by the number of views ensure that we repeat the
1947 * client's per-instance data once for each view.
1949 if (pipeline
->subpass
->view_mask
) {
1950 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1951 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1952 if (pipeline
->vb
[vb
].instanced
)
1953 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1957 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1958 pCreateInfo
->pInputAssemblyState
;
1959 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1960 pCreateInfo
->pTessellationState
;
1961 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1963 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1964 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1966 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1971 #define WRITE_STR(field, ...) ({ \
1972 memset(field, 0, sizeof(field)); \
1973 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
1974 assert(i > 0 && i < sizeof(field)); \
1977 VkResult
anv_GetPipelineExecutablePropertiesKHR(
1979 const VkPipelineInfoKHR
* pPipelineInfo
,
1980 uint32_t* pExecutableCount
,
1981 VkPipelineExecutablePropertiesKHR
* pProperties
)
1983 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
1984 VK_OUTARRAY_MAKE(out
, pProperties
, pExecutableCount
);
1986 for (uint32_t i
= 0; i
< pipeline
->num_executables
; i
++) {
1987 vk_outarray_append(&out
, props
) {
1988 gl_shader_stage stage
= pipeline
->executables
[i
].stage
;
1989 props
->stages
= mesa_to_vk_shader_stage(stage
);
1991 unsigned simd_width
= pipeline
->executables
[i
].stats
.dispatch_width
;
1992 if (stage
== MESA_SHADER_FRAGMENT
) {
1993 WRITE_STR(props
->name
, "%s%d %s",
1994 simd_width
? "SIMD" : "vec",
1995 simd_width
? simd_width
: 4,
1996 _mesa_shader_stage_to_string(stage
));
1998 WRITE_STR(props
->name
, "%s", _mesa_shader_stage_to_string(stage
));
2000 WRITE_STR(props
->description
, "%s%d %s shader",
2001 simd_width
? "SIMD" : "vec",
2002 simd_width
? simd_width
: 4,
2003 _mesa_shader_stage_to_string(stage
));
2005 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2006 * wants a subgroup size of 1.
2008 props
->subgroupSize
= MAX2(simd_width
, 1);
2012 return vk_outarray_status(&out
);
2015 VkResult
anv_GetPipelineExecutableStatisticsKHR(
2017 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2018 uint32_t* pStatisticCount
,
2019 VkPipelineExecutableStatisticKHR
* pStatistics
)
2021 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2022 VK_OUTARRAY_MAKE(out
, pStatistics
, pStatisticCount
);
2024 assert(pExecutableInfo
->executableIndex
< pipeline
->num_executables
);
2025 const struct anv_pipeline_executable
*exe
=
2026 &pipeline
->executables
[pExecutableInfo
->executableIndex
];
2027 const struct brw_stage_prog_data
*prog_data
=
2028 pipeline
->shaders
[exe
->stage
]->prog_data
;
2030 vk_outarray_append(&out
, stat
) {
2031 WRITE_STR(stat
->name
, "Instruction Count");
2032 WRITE_STR(stat
->description
,
2033 "Number of GEN instructions in the final generated "
2034 "shader executable.");
2035 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2036 stat
->value
.u64
= exe
->stats
.instructions
;
2039 vk_outarray_append(&out
, stat
) {
2040 WRITE_STR(stat
->name
, "Loop Count");
2041 WRITE_STR(stat
->description
,
2042 "Number of loops (not unrolled) in the final generated "
2043 "shader executable.");
2044 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2045 stat
->value
.u64
= exe
->stats
.loops
;
2048 vk_outarray_append(&out
, stat
) {
2049 WRITE_STR(stat
->name
, "Cycle Count");
2050 WRITE_STR(stat
->description
,
2051 "Estimate of the number of EU cycles required to execute "
2052 "the final generated executable. This is an estimate only "
2053 "and may vary greatly from actual run-time performance.");
2054 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2055 stat
->value
.u64
= exe
->stats
.cycles
;
2058 vk_outarray_append(&out
, stat
) {
2059 WRITE_STR(stat
->name
, "Spill Count");
2060 WRITE_STR(stat
->description
,
2061 "Number of scratch spill operations. This gives a rough "
2062 "estimate of the cost incurred due to spilling temporary "
2063 "values to memory. If this is non-zero, you may want to "
2064 "adjust your shader to reduce register pressure.");
2065 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2066 stat
->value
.u64
= exe
->stats
.spills
;
2069 vk_outarray_append(&out
, stat
) {
2070 WRITE_STR(stat
->name
, "Fill Count");
2071 WRITE_STR(stat
->description
,
2072 "Number of scratch fill operations. This gives a rough "
2073 "estimate of the cost incurred due to spilling temporary "
2074 "values to memory. If this is non-zero, you may want to "
2075 "adjust your shader to reduce register pressure.");
2076 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2077 stat
->value
.u64
= exe
->stats
.fills
;
2080 vk_outarray_append(&out
, stat
) {
2081 WRITE_STR(stat
->name
, "Scratch Memory Size");
2082 WRITE_STR(stat
->description
,
2083 "Number of bytes of scratch memory required by the "
2084 "generated shader executable. If this is non-zero, you "
2085 "may want to adjust your shader to reduce register "
2087 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2088 stat
->value
.u64
= prog_data
->total_scratch
;
2091 if (exe
->stage
== MESA_SHADER_COMPUTE
) {
2092 vk_outarray_append(&out
, stat
) {
2093 WRITE_STR(stat
->name
, "Workgroup Memory Size");
2094 WRITE_STR(stat
->description
,
2095 "Number of bytes of workgroup shared memory used by this "
2096 "compute shader including any padding.");
2097 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2098 stat
->value
.u64
= prog_data
->total_scratch
;
2102 return vk_outarray_status(&out
);
2106 write_ir_text(VkPipelineExecutableInternalRepresentationKHR
* ir
,
2109 ir
->isText
= VK_TRUE
;
2111 size_t data_len
= strlen(data
) + 1;
2113 if (ir
->pData
== NULL
) {
2114 ir
->dataSize
= data_len
;
2118 strncpy(ir
->pData
, data
, ir
->dataSize
);
2119 if (ir
->dataSize
< data_len
)
2122 ir
->dataSize
= data_len
;
2126 VkResult
anv_GetPipelineExecutableInternalRepresentationsKHR(
2128 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2129 uint32_t* pInternalRepresentationCount
,
2130 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
2132 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2133 VK_OUTARRAY_MAKE(out
, pInternalRepresentations
,
2134 pInternalRepresentationCount
);
2135 bool incomplete_text
= false;
2137 assert(pExecutableInfo
->executableIndex
< pipeline
->num_executables
);
2138 const struct anv_pipeline_executable
*exe
=
2139 &pipeline
->executables
[pExecutableInfo
->executableIndex
];
2142 vk_outarray_append(&out
, ir
) {
2143 WRITE_STR(ir
->name
, "Final NIR");
2144 WRITE_STR(ir
->description
,
2145 "Final NIR before going into the back-end compiler");
2147 if (!write_ir_text(ir
, exe
->nir
))
2148 incomplete_text
= true;
2153 vk_outarray_append(&out
, ir
) {
2154 WRITE_STR(ir
->name
, "GEN Assembly");
2155 WRITE_STR(ir
->description
,
2156 "Final GEN assembly for the generated shader binary");
2158 if (!write_ir_text(ir
, exe
->disasm
))
2159 incomplete_text
= true;
2163 return incomplete_text
? VK_INCOMPLETE
: vk_outarray_status(&out
);