2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "anv_private.h"
34 #include "compiler/brw_nir.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
40 /* Needed for SWIZZLE macros */
41 #include "program/prog_instruction.h"
45 VkResult
anv_CreateShaderModule(
47 const VkShaderModuleCreateInfo
* pCreateInfo
,
48 const VkAllocationCallbacks
* pAllocator
,
49 VkShaderModule
* pShaderModule
)
51 ANV_FROM_HANDLE(anv_device
, device
, _device
);
52 struct anv_shader_module
*module
;
54 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
55 assert(pCreateInfo
->flags
== 0);
57 module
= vk_alloc2(&device
->alloc
, pAllocator
,
58 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
59 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
61 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
63 module
->size
= pCreateInfo
->codeSize
;
64 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
66 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
68 *pShaderModule
= anv_shader_module_to_handle(module
);
73 void anv_DestroyShaderModule(
75 VkShaderModule _module
,
76 const VkAllocationCallbacks
* pAllocator
)
78 ANV_FROM_HANDLE(anv_device
, device
, _device
);
79 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
84 vk_free2(&device
->alloc
, pAllocator
, module
);
87 #define SPIR_V_MAGIC_NUMBER 0x07230203
89 static const uint64_t stage_to_debug
[] = {
90 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
91 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
92 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
93 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
94 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
95 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
98 struct anv_spirv_debug_data
{
99 struct anv_device
*device
;
100 const struct anv_shader_module
*module
;
103 static void anv_spirv_nir_debug(void *private_data
,
104 enum nir_spirv_debug_level level
,
108 struct anv_spirv_debug_data
*debug_data
= private_data
;
109 static const VkDebugReportFlagsEXT vk_flags
[] = {
110 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
111 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
116 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
118 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
120 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
121 (uint64_t) (uintptr_t) debug_data
->module
,
122 0, 0, "anv", buffer
);
125 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
126 * we can't do that yet because we don't have the ability to copy nir.
129 anv_shader_compile_to_nir(struct anv_device
*device
,
131 const struct anv_shader_module
*module
,
132 const char *entrypoint_name
,
133 gl_shader_stage stage
,
134 const VkSpecializationInfo
*spec_info
)
136 const struct anv_physical_device
*pdevice
=
137 &device
->instance
->physicalDevice
;
138 const struct brw_compiler
*compiler
= pdevice
->compiler
;
139 const nir_shader_compiler_options
*nir_options
=
140 compiler
->glsl_compiler_options
[stage
].NirOptions
;
142 uint32_t *spirv
= (uint32_t *) module
->data
;
143 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
144 assert(module
->size
% 4 == 0);
146 uint32_t num_spec_entries
= 0;
147 struct nir_spirv_specialization
*spec_entries
= NULL
;
148 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
149 num_spec_entries
= spec_info
->mapEntryCount
;
150 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
151 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
152 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
153 const void *data
= spec_info
->pData
+ entry
.offset
;
154 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
156 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
157 if (spec_info
->dataSize
== 8)
158 spec_entries
[i
].data64
= *(const uint64_t *)data
;
160 spec_entries
[i
].data32
= *(const uint32_t *)data
;
164 struct anv_spirv_debug_data spirv_debug_data
= {
168 struct spirv_to_nir_options spirv_options
= {
169 .lower_workgroup_access_to_offsets
= true,
171 .demote_to_helper_invocation
= true,
172 .derivative_group
= true,
173 .descriptor_array_dynamic_indexing
= true,
174 .descriptor_array_non_uniform_indexing
= true,
175 .descriptor_indexing
= true,
176 .device_group
= true,
177 .draw_parameters
= true,
178 .float16
= pdevice
->info
.gen
>= 8,
179 .float64
= pdevice
->info
.gen
>= 8,
180 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
181 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
182 .geometry_streams
= true,
183 .image_write_without_format
= true,
184 .int8
= pdevice
->info
.gen
>= 8,
185 .int16
= pdevice
->info
.gen
>= 8,
186 .int64
= pdevice
->info
.gen
>= 8,
187 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
190 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
191 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
192 .runtime_descriptor_array
= true,
193 .shader_viewport_index_layer
= true,
194 .stencil_export
= pdevice
->info
.gen
>= 9,
195 .storage_8bit
= pdevice
->info
.gen
>= 8,
196 .storage_16bit
= pdevice
->info
.gen
>= 8,
197 .subgroup_arithmetic
= true,
198 .subgroup_basic
= true,
199 .subgroup_ballot
= true,
200 .subgroup_quad
= true,
201 .subgroup_shuffle
= true,
202 .subgroup_vote
= true,
203 .tessellation
= true,
204 .transform_feedback
= pdevice
->info
.gen
>= 8,
205 .variable_pointers
= true,
207 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
209 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
210 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
211 .push_const_addr_format
= nir_address_format_logical
,
213 /* TODO: Consider changing this to an address format that has the NULL
214 * pointer equals to 0. That might be a better format to play nice
215 * with certain code / code generators.
217 .shared_addr_format
= nir_address_format_32bit_offset
,
219 .func
= anv_spirv_nir_debug
,
220 .private_data
= &spirv_debug_data
,
226 spirv_to_nir(spirv
, module
->size
/ 4,
227 spec_entries
, num_spec_entries
,
228 stage
, entrypoint_name
, &spirv_options
, nir_options
);
229 assert(nir
->info
.stage
== stage
);
230 nir_validate_shader(nir
, "after spirv_to_nir");
231 ralloc_steal(mem_ctx
, nir
);
235 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
236 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
237 gl_shader_stage_name(stage
));
238 nir_print_shader(nir
, stderr
);
241 /* We have to lower away local constant initializers right before we
242 * inline functions. That way they get properly initialized at the top
243 * of the function and not at the top of its caller.
245 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
246 NIR_PASS_V(nir
, nir_lower_returns
);
247 NIR_PASS_V(nir
, nir_inline_functions
);
248 NIR_PASS_V(nir
, nir_opt_deref
);
250 /* Pick off the single entrypoint that we want */
251 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
252 if (!func
->is_entrypoint
)
253 exec_node_remove(&func
->node
);
255 assert(exec_list_length(&nir
->functions
) == 1);
257 /* Now that we've deleted all but the main function, we can go ahead and
258 * lower the rest of the constant initializers. We do this here so that
259 * nir_remove_dead_variables and split_per_member_structs below see the
260 * corresponding stores.
262 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
264 /* Split member structs. We do this before lower_io_to_temporaries so that
265 * it doesn't lower system values to temporaries by accident.
267 NIR_PASS_V(nir
, nir_split_var_copies
);
268 NIR_PASS_V(nir
, nir_split_per_member_structs
);
270 NIR_PASS_V(nir
, nir_remove_dead_variables
,
271 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
273 NIR_PASS_V(nir
, nir_propagate_invariant
);
274 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
275 nir_shader_get_entrypoint(nir
), true, false);
277 NIR_PASS_V(nir
, nir_lower_frexp
);
279 /* Vulkan uses the separate-shader linking model */
280 nir
->info
.separate_shader
= true;
282 brw_preprocess_nir(compiler
, nir
, NULL
);
287 void anv_DestroyPipeline(
289 VkPipeline _pipeline
,
290 const VkAllocationCallbacks
* pAllocator
)
292 ANV_FROM_HANDLE(anv_device
, device
, _device
);
293 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
298 anv_reloc_list_finish(&pipeline
->batch_relocs
,
299 pAllocator
? pAllocator
: &device
->alloc
);
300 if (pipeline
->blend_state
.map
)
301 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
303 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
304 if (pipeline
->shaders
[s
])
305 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
308 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
311 static const uint32_t vk_to_gen_primitive_type
[] = {
312 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
313 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
314 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
315 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
316 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
317 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
318 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
319 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
320 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
321 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
325 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
326 struct brw_sampler_prog_key_data
*key
)
328 /* Almost all multisampled textures are compressed. The only time when we
329 * don't compress a multisampled texture is for 16x MSAA with a surface
330 * width greater than 8k which is a bit of an edge case. Since the sampler
331 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
332 * to tell the compiler to always assume compression.
334 key
->compressed_multisample_layout_mask
= ~0;
336 /* SkyLake added support for 16x MSAA. With this came a new message for
337 * reading from a 16x MSAA surface with compression. The new message was
338 * needed because now the MCS data is 64 bits instead of 32 or lower as is
339 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
340 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
341 * so we can just use it unconditionally. This may not be quite as
342 * efficient but it saves us from recompiling.
344 if (devinfo
->gen
>= 9)
347 /* XXX: Handle texture swizzle on HSW- */
348 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
349 /* Assume color sampler, no swizzling. (Works for BDW+) */
350 key
->swizzles
[i
] = SWIZZLE_XYZW
;
355 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
356 struct brw_vs_prog_key
*key
)
358 memset(key
, 0, sizeof(*key
));
360 populate_sampler_prog_key(devinfo
, &key
->tex
);
362 /* XXX: Handle vertex input work-arounds */
364 /* XXX: Handle sampler_prog_key */
368 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
369 unsigned input_vertices
,
370 struct brw_tcs_prog_key
*key
)
372 memset(key
, 0, sizeof(*key
));
374 populate_sampler_prog_key(devinfo
, &key
->tex
);
376 key
->input_vertices
= input_vertices
;
380 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
381 struct brw_tes_prog_key
*key
)
383 memset(key
, 0, sizeof(*key
));
385 populate_sampler_prog_key(devinfo
, &key
->tex
);
389 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
390 struct brw_gs_prog_key
*key
)
392 memset(key
, 0, sizeof(*key
));
394 populate_sampler_prog_key(devinfo
, &key
->tex
);
398 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
399 const struct anv_subpass
*subpass
,
400 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
401 struct brw_wm_prog_key
*key
)
403 memset(key
, 0, sizeof(*key
));
405 populate_sampler_prog_key(devinfo
, &key
->tex
);
407 /* We set this to 0 here and set to the actual value before we call
410 key
->input_slots_valid
= 0;
412 /* Vulkan doesn't specify a default */
413 key
->high_quality_derivatives
= false;
415 /* XXX Vulkan doesn't appear to specify */
416 key
->clamp_fragment_color
= false;
418 assert(subpass
->color_count
<= MAX_RTS
);
419 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
420 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
421 key
->color_outputs_valid
|= (1 << i
);
424 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
426 /* To reduce possible shader recompilations we would need to know if
427 * there is a SampleMask output variable to compute if we should emit
428 * code to workaround the issue that hardware disables alpha to coverage
429 * when there is SampleMask output.
431 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
433 /* Vulkan doesn't support fixed-function alpha test */
434 key
->alpha_test_replicate_alpha
= false;
437 /* We should probably pull this out of the shader, but it's fairly
438 * harmless to compute it and then let dead-code take care of it.
440 if (ms_info
->rasterizationSamples
> 1) {
441 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
442 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
443 key
->multisample_fbo
= true;
446 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
451 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
452 struct brw_cs_prog_key
*key
)
454 memset(key
, 0, sizeof(*key
));
456 populate_sampler_prog_key(devinfo
, &key
->tex
);
459 struct anv_pipeline_stage
{
460 gl_shader_stage stage
;
462 const struct anv_shader_module
*module
;
463 const char *entrypoint
;
464 const VkSpecializationInfo
*spec_info
;
466 unsigned char shader_sha1
[20];
468 union brw_any_prog_key key
;
471 gl_shader_stage stage
;
472 unsigned char sha1
[20];
477 struct anv_pipeline_binding surface_to_descriptor
[256];
478 struct anv_pipeline_binding sampler_to_descriptor
[256];
479 struct anv_pipeline_bind_map bind_map
;
481 union brw_any_prog_data prog_data
;
483 VkPipelineCreationFeedbackEXT feedback
;
487 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
488 const char *entrypoint
,
489 gl_shader_stage stage
,
490 const VkSpecializationInfo
*spec_info
,
491 unsigned char *sha1_out
)
493 struct mesa_sha1 ctx
;
494 _mesa_sha1_init(&ctx
);
496 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
497 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
498 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
500 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
501 spec_info
->mapEntryCount
*
502 sizeof(*spec_info
->pMapEntries
));
503 _mesa_sha1_update(&ctx
, spec_info
->pData
,
504 spec_info
->dataSize
);
507 _mesa_sha1_final(&ctx
, sha1_out
);
511 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
512 struct anv_pipeline_layout
*layout
,
513 struct anv_pipeline_stage
*stages
,
514 unsigned char *sha1_out
)
516 struct mesa_sha1 ctx
;
517 _mesa_sha1_init(&ctx
);
519 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
520 sizeof(pipeline
->subpass
->view_mask
));
523 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
525 const bool rba
= pipeline
->device
->robust_buffer_access
;
526 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
528 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
529 if (stages
[s
].entrypoint
) {
530 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
531 sizeof(stages
[s
].shader_sha1
));
532 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
536 _mesa_sha1_final(&ctx
, sha1_out
);
540 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
541 struct anv_pipeline_layout
*layout
,
542 struct anv_pipeline_stage
*stage
,
543 unsigned char *sha1_out
)
545 struct mesa_sha1 ctx
;
546 _mesa_sha1_init(&ctx
);
549 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
551 const bool rba
= pipeline
->device
->robust_buffer_access
;
552 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
554 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
555 sizeof(stage
->shader_sha1
));
556 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
558 _mesa_sha1_final(&ctx
, sha1_out
);
562 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
563 struct anv_pipeline_cache
*cache
,
565 struct anv_pipeline_stage
*stage
)
567 const struct brw_compiler
*compiler
=
568 pipeline
->device
->instance
->physicalDevice
.compiler
;
569 const nir_shader_compiler_options
*nir_options
=
570 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
573 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
578 assert(nir
->info
.stage
== stage
->stage
);
582 nir
= anv_shader_compile_to_nir(pipeline
->device
,
589 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
597 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
599 struct anv_pipeline_stage
*stage
,
600 struct anv_pipeline_layout
*layout
)
602 const struct anv_physical_device
*pdevice
=
603 &pipeline
->device
->instance
->physicalDevice
;
604 const struct brw_compiler
*compiler
= pdevice
->compiler
;
606 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
607 nir_shader
*nir
= stage
->nir
;
609 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
610 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
611 NIR_PASS_V(nir
, nir_lower_input_attachments
, false);
614 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
616 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
618 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
619 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
621 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
622 prog_data
->total_shared
= nir
->num_shared
;
624 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
626 if (nir
->num_uniforms
> 0) {
627 assert(prog_data
->nr_params
== 0);
629 /* If the shader uses any push constants at all, we'll just give
630 * them the maximum possible number
632 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
633 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
634 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
635 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
637 /* We now set the param values to be offsets into a
638 * anv_push_constant_data structure. Since the compiler doesn't
639 * actually dereference any of the gl_constant_value pointers in the
640 * params array, it doesn't really matter what we put here.
642 struct anv_push_constants
*null_data
= NULL
;
643 /* Fill out the push constants section of the param array */
644 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
645 prog_data
->param
[i
] = ANV_PARAM_PUSH(
646 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
650 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
651 pipeline
->needs_data_cache
= true;
653 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
655 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
656 nir_address_format_64bit_global
);
658 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
660 anv_nir_apply_pipeline_layout(pdevice
,
661 pipeline
->device
->robust_buffer_access
,
662 layout
, nir
, prog_data
,
665 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
666 nir_address_format_32bit_index_offset
);
667 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
668 anv_nir_ssbo_addr_format(pdevice
,
669 pipeline
->device
->robust_buffer_access
));
671 NIR_PASS_V(nir
, nir_opt_constant_folding
);
673 /* We don't support non-uniform UBOs and non-uniform SSBO access is
674 * handled naturally by falling back to A64 messages.
676 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
677 nir_lower_non_uniform_texture_access
|
678 nir_lower_non_uniform_image_access
);
681 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
682 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
684 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
690 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
691 struct anv_pipeline_stage
*vs_stage
,
692 struct anv_pipeline_stage
*next_stage
)
695 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
698 static const unsigned *
699 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
701 struct anv_device
*device
,
702 struct anv_pipeline_stage
*vs_stage
)
704 brw_compute_vue_map(compiler
->devinfo
,
705 &vs_stage
->prog_data
.vs
.base
.vue_map
,
706 vs_stage
->nir
->info
.outputs_written
,
707 vs_stage
->nir
->info
.separate_shader
);
709 return brw_compile_vs(compiler
, device
, mem_ctx
, &vs_stage
->key
.vs
,
710 &vs_stage
->prog_data
.vs
, vs_stage
->nir
, -1, NULL
);
714 merge_tess_info(struct shader_info
*tes_info
,
715 const struct shader_info
*tcs_info
)
717 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
719 * "PointMode. Controls generation of points rather than triangles
720 * or lines. This functionality defaults to disabled, and is
721 * enabled if either shader stage includes the execution mode.
723 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
724 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
725 * and OutputVertices, it says:
727 * "One mode must be set in at least one of the tessellation
730 * So, the fields can be set in either the TCS or TES, but they must
731 * agree if set in both. Our backend looks at TES, so bitwise-or in
732 * the values from the TCS.
734 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
735 tes_info
->tess
.tcs_vertices_out
== 0 ||
736 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
737 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
739 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
740 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
741 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
742 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
744 assert(tcs_info
->tess
.primitive_mode
== 0 ||
745 tes_info
->tess
.primitive_mode
== 0 ||
746 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
747 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
748 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
749 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
753 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
754 struct anv_pipeline_stage
*tcs_stage
,
755 struct anv_pipeline_stage
*tes_stage
)
757 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
759 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
761 nir_lower_patch_vertices(tes_stage
->nir
,
762 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
765 /* Copy TCS info into the TES info */
766 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
768 /* Whacking the key after cache lookup is a bit sketchy, but all of
769 * this comes from the SPIR-V, which is part of the hash used for the
770 * pipeline cache. So it should be safe.
772 tcs_stage
->key
.tcs
.tes_primitive_mode
=
773 tes_stage
->nir
->info
.tess
.primitive_mode
;
774 tcs_stage
->key
.tcs
.quads_workaround
=
775 compiler
->devinfo
->gen
< 9 &&
776 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
777 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
780 static const unsigned *
781 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
783 struct anv_device
*device
,
784 struct anv_pipeline_stage
*tcs_stage
,
785 struct anv_pipeline_stage
*prev_stage
)
787 tcs_stage
->key
.tcs
.outputs_written
=
788 tcs_stage
->nir
->info
.outputs_written
;
789 tcs_stage
->key
.tcs
.patch_outputs_written
=
790 tcs_stage
->nir
->info
.patch_outputs_written
;
792 return brw_compile_tcs(compiler
, device
, mem_ctx
, &tcs_stage
->key
.tcs
,
793 &tcs_stage
->prog_data
.tcs
, tcs_stage
->nir
,
798 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
799 struct anv_pipeline_stage
*tes_stage
,
800 struct anv_pipeline_stage
*next_stage
)
803 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
806 static const unsigned *
807 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
809 struct anv_device
*device
,
810 struct anv_pipeline_stage
*tes_stage
,
811 struct anv_pipeline_stage
*tcs_stage
)
813 tes_stage
->key
.tes
.inputs_read
=
814 tcs_stage
->nir
->info
.outputs_written
;
815 tes_stage
->key
.tes
.patch_inputs_read
=
816 tcs_stage
->nir
->info
.patch_outputs_written
;
818 return brw_compile_tes(compiler
, device
, mem_ctx
, &tes_stage
->key
.tes
,
819 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
820 &tes_stage
->prog_data
.tes
, tes_stage
->nir
,
825 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
826 struct anv_pipeline_stage
*gs_stage
,
827 struct anv_pipeline_stage
*next_stage
)
830 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
833 static const unsigned *
834 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
836 struct anv_device
*device
,
837 struct anv_pipeline_stage
*gs_stage
,
838 struct anv_pipeline_stage
*prev_stage
)
840 brw_compute_vue_map(compiler
->devinfo
,
841 &gs_stage
->prog_data
.gs
.base
.vue_map
,
842 gs_stage
->nir
->info
.outputs_written
,
843 gs_stage
->nir
->info
.separate_shader
);
845 return brw_compile_gs(compiler
, device
, mem_ctx
, &gs_stage
->key
.gs
,
846 &gs_stage
->prog_data
.gs
, gs_stage
->nir
,
851 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
852 struct anv_pipeline_stage
*stage
)
854 unsigned num_rts
= 0;
855 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
856 struct anv_pipeline_binding rt_bindings
[max_rt
];
857 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
858 int rt_to_bindings
[max_rt
];
859 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
860 bool rt_used
[max_rt
];
861 memset(rt_used
, 0, sizeof(rt_used
));
863 /* Flag used render targets */
864 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
865 if (var
->data
.location
< FRAG_RESULT_DATA0
)
868 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
873 const unsigned array_len
=
874 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
875 assert(rt
+ array_len
<= max_rt
);
878 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
879 /* If this is the RT at location 0 and we have alpha to coverage
880 * enabled we will have to create a null RT for it, so mark it as
883 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
887 for (unsigned i
= 0; i
< array_len
; i
++)
888 rt_used
[rt
+ i
] = true;
891 /* Set new, compacted, location */
892 for (unsigned i
= 0; i
< max_rt
; i
++) {
896 rt_to_bindings
[i
] = num_rts
;
898 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
899 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
900 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
905 /* Setup a null render target */
906 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
907 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
916 bool deleted_output
= false;
917 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
918 if (var
->data
.location
< FRAG_RESULT_DATA0
)
921 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
923 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
924 /* Unused or out-of-bounds, throw it away, unless it is the first
925 * RT and we have alpha to coverage enabled.
927 deleted_output
= true;
928 var
->data
.mode
= nir_var_function_temp
;
929 exec_node_remove(&var
->node
);
930 exec_list_push_tail(&impl
->locals
, &var
->node
);
934 /* Give it the new location */
935 assert(rt_to_bindings
[rt
] != -1);
936 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
940 nir_fixup_deref_modes(stage
->nir
);
943 /* If we have no render targets, we need a null render target */
944 rt_bindings
[0] = (struct anv_pipeline_binding
) {
945 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
952 /* Now that we've determined the actual number of render targets, adjust
953 * the key accordingly.
955 stage
->key
.wm
.nr_color_regions
= num_rts
;
956 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
958 assert(num_rts
<= max_rt
);
959 assert(stage
->bind_map
.surface_count
== 0);
960 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
961 rt_bindings
, num_rts
);
962 stage
->bind_map
.surface_count
+= num_rts
;
965 static const unsigned *
966 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
968 struct anv_device
*device
,
969 struct anv_pipeline_stage
*fs_stage
,
970 struct anv_pipeline_stage
*prev_stage
)
972 /* TODO: we could set this to 0 based on the information in nir_shader, but
973 * we need this before we call spirv_to_nir.
976 fs_stage
->key
.wm
.input_slots_valid
=
977 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
979 const unsigned *code
=
980 brw_compile_fs(compiler
, device
, mem_ctx
, &fs_stage
->key
.wm
,
981 &fs_stage
->prog_data
.wm
, fs_stage
->nir
,
982 NULL
, -1, -1, -1, true, false, NULL
, NULL
);
984 if (fs_stage
->key
.wm
.nr_color_regions
== 0 &&
985 !fs_stage
->prog_data
.wm
.has_side_effects
&&
986 !fs_stage
->prog_data
.wm
.uses_kill
&&
987 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
988 !fs_stage
->prog_data
.wm
.computed_stencil
) {
989 /* This fragment shader has no outputs and no side effects. Go ahead
990 * and return the code pointer so we don't accidentally think the
991 * compile failed but zero out prog_data which will set program_size to
992 * zero and disable the stage.
994 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1001 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1002 struct anv_pipeline_cache
*cache
,
1003 const VkGraphicsPipelineCreateInfo
*info
)
1005 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1006 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1008 int64_t pipeline_start
= os_time_get_nano();
1010 const struct brw_compiler
*compiler
=
1011 pipeline
->device
->instance
->physicalDevice
.compiler
;
1012 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1014 pipeline
->active_stages
= 0;
1017 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1018 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1019 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1021 pipeline
->active_stages
|= sinfo
->stage
;
1023 int64_t stage_start
= os_time_get_nano();
1025 stages
[stage
].stage
= stage
;
1026 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1027 stages
[stage
].entrypoint
= sinfo
->pName
;
1028 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1029 anv_pipeline_hash_shader(stages
[stage
].module
,
1030 stages
[stage
].entrypoint
,
1032 stages
[stage
].spec_info
,
1033 stages
[stage
].shader_sha1
);
1035 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1037 case MESA_SHADER_VERTEX
:
1038 populate_vs_prog_key(devinfo
, &stages
[stage
].key
.vs
);
1040 case MESA_SHADER_TESS_CTRL
:
1041 populate_tcs_prog_key(devinfo
,
1042 info
->pTessellationState
->patchControlPoints
,
1043 &stages
[stage
].key
.tcs
);
1045 case MESA_SHADER_TESS_EVAL
:
1046 populate_tes_prog_key(devinfo
, &stages
[stage
].key
.tes
);
1048 case MESA_SHADER_GEOMETRY
:
1049 populate_gs_prog_key(devinfo
, &stages
[stage
].key
.gs
);
1051 case MESA_SHADER_FRAGMENT
:
1052 populate_wm_prog_key(devinfo
, pipeline
->subpass
,
1053 info
->pMultisampleState
,
1054 &stages
[stage
].key
.wm
);
1057 unreachable("Invalid graphics shader stage");
1060 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1061 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1064 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1065 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1067 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1069 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1071 unsigned char sha1
[20];
1072 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1075 unsigned cache_hits
= 0;
1076 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1077 if (!stages
[s
].entrypoint
)
1080 int64_t stage_start
= os_time_get_nano();
1082 stages
[s
].cache_key
.stage
= s
;
1083 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1086 struct anv_shader_bin
*bin
=
1087 anv_device_search_for_kernel(pipeline
->device
, cache
,
1088 &stages
[s
].cache_key
,
1089 sizeof(stages
[s
].cache_key
), &cache_hit
);
1092 pipeline
->shaders
[s
] = bin
;
1097 stages
[s
].feedback
.flags
|=
1098 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1100 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1103 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1104 if (cache_hits
== found
) {
1105 pipeline_feedback
.flags
|=
1106 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1108 /* We found all our shaders in the cache. We're done. */
1110 } else if (found
> 0) {
1111 /* We found some but not all of our shaders. This shouldn't happen
1112 * most of the time but it can if we have a partially populated
1115 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1117 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1118 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1119 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1120 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1121 (uint64_t)(uintptr_t)cache
,
1123 "Found a partial pipeline in the cache. This is "
1124 "most likely caused by an incomplete pipeline cache "
1125 "import or export");
1127 /* We're going to have to recompile anyway, so just throw away our
1128 * references to the shaders in the cache. We'll get them out of the
1129 * cache again as part of the compilation process.
1131 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1132 stages
[s
].feedback
.flags
= 0;
1133 if (pipeline
->shaders
[s
]) {
1134 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1135 pipeline
->shaders
[s
] = NULL
;
1140 void *pipeline_ctx
= ralloc_context(NULL
);
1142 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1143 if (!stages
[s
].entrypoint
)
1146 int64_t stage_start
= os_time_get_nano();
1148 assert(stages
[s
].stage
== s
);
1149 assert(pipeline
->shaders
[s
] == NULL
);
1151 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1152 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1153 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1156 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1159 if (stages
[s
].nir
== NULL
) {
1160 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1164 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1167 /* Walk backwards to link */
1168 struct anv_pipeline_stage
*next_stage
= NULL
;
1169 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1170 if (!stages
[s
].entrypoint
)
1174 case MESA_SHADER_VERTEX
:
1175 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1177 case MESA_SHADER_TESS_CTRL
:
1178 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1180 case MESA_SHADER_TESS_EVAL
:
1181 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1183 case MESA_SHADER_GEOMETRY
:
1184 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1186 case MESA_SHADER_FRAGMENT
:
1187 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1190 unreachable("Invalid graphics shader stage");
1193 next_stage
= &stages
[s
];
1196 struct anv_pipeline_stage
*prev_stage
= NULL
;
1197 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1198 if (!stages
[s
].entrypoint
)
1201 int64_t stage_start
= os_time_get_nano();
1203 void *stage_ctx
= ralloc_context(NULL
);
1205 nir_xfb_info
*xfb_info
= NULL
;
1206 if (s
== MESA_SHADER_VERTEX
||
1207 s
== MESA_SHADER_TESS_EVAL
||
1208 s
== MESA_SHADER_GEOMETRY
)
1209 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1211 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1213 const unsigned *code
;
1215 case MESA_SHADER_VERTEX
:
1216 code
= anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1219 case MESA_SHADER_TESS_CTRL
:
1220 code
= anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1221 &stages
[s
], prev_stage
);
1223 case MESA_SHADER_TESS_EVAL
:
1224 code
= anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1225 &stages
[s
], prev_stage
);
1227 case MESA_SHADER_GEOMETRY
:
1228 code
= anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1229 &stages
[s
], prev_stage
);
1231 case MESA_SHADER_FRAGMENT
:
1232 code
= anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1233 &stages
[s
], prev_stage
);
1236 unreachable("Invalid graphics shader stage");
1239 ralloc_free(stage_ctx
);
1240 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1244 struct anv_shader_bin
*bin
=
1245 anv_device_upload_kernel(pipeline
->device
, cache
,
1246 &stages
[s
].cache_key
,
1247 sizeof(stages
[s
].cache_key
),
1248 code
, stages
[s
].prog_data
.base
.program_size
,
1249 stages
[s
].nir
->constant_data
,
1250 stages
[s
].nir
->constant_data_size
,
1251 &stages
[s
].prog_data
.base
,
1252 brw_prog_data_size(s
),
1253 xfb_info
, &stages
[s
].bind_map
);
1255 ralloc_free(stage_ctx
);
1256 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1260 pipeline
->shaders
[s
] = bin
;
1261 ralloc_free(stage_ctx
);
1263 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1265 prev_stage
= &stages
[s
];
1268 ralloc_free(pipeline_ctx
);
1272 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1273 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1274 /* This can happen if we decided to implicitly disable the fragment
1275 * shader. See anv_pipeline_compile_fs().
1277 anv_shader_bin_unref(pipeline
->device
,
1278 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1279 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1280 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1283 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1285 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1286 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1287 if (create_feedback
) {
1288 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1290 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1291 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1292 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1293 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1300 ralloc_free(pipeline_ctx
);
1302 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1303 if (pipeline
->shaders
[s
])
1304 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1311 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1312 struct anv_pipeline_cache
*cache
,
1313 const VkComputePipelineCreateInfo
*info
,
1314 const struct anv_shader_module
*module
,
1315 const char *entrypoint
,
1316 const VkSpecializationInfo
*spec_info
)
1318 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1319 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1321 int64_t pipeline_start
= os_time_get_nano();
1323 const struct brw_compiler
*compiler
=
1324 pipeline
->device
->instance
->physicalDevice
.compiler
;
1326 struct anv_pipeline_stage stage
= {
1327 .stage
= MESA_SHADER_COMPUTE
,
1329 .entrypoint
= entrypoint
,
1330 .spec_info
= spec_info
,
1332 .stage
= MESA_SHADER_COMPUTE
,
1335 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1338 anv_pipeline_hash_shader(stage
.module
,
1340 MESA_SHADER_COMPUTE
,
1344 struct anv_shader_bin
*bin
= NULL
;
1346 populate_cs_prog_key(&pipeline
->device
->info
, &stage
.key
.cs
);
1348 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1350 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1352 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
, &stage
.cache_key
,
1353 sizeof(stage
.cache_key
), &cache_hit
);
1356 int64_t stage_start
= os_time_get_nano();
1358 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1359 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1360 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1363 /* Set up a binding for the gl_NumWorkGroups */
1364 stage
.bind_map
.surface_count
= 1;
1365 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1366 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1369 void *mem_ctx
= ralloc_context(NULL
);
1371 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1372 if (stage
.nir
== NULL
) {
1373 ralloc_free(mem_ctx
);
1374 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1377 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1379 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1380 &stage
.prog_data
.cs
);
1382 const unsigned *shader_code
=
1383 brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
, &stage
.key
.cs
,
1384 &stage
.prog_data
.cs
, stage
.nir
, -1, NULL
);
1385 if (shader_code
== NULL
) {
1386 ralloc_free(mem_ctx
);
1387 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1390 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1391 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1392 &stage
.cache_key
, sizeof(stage
.cache_key
),
1393 shader_code
, code_size
,
1394 stage
.nir
->constant_data
,
1395 stage
.nir
->constant_data_size
,
1396 &stage
.prog_data
.base
,
1397 sizeof(stage
.prog_data
.cs
),
1398 NULL
, &stage
.bind_map
);
1400 ralloc_free(mem_ctx
);
1401 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1404 ralloc_free(mem_ctx
);
1406 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1410 stage
.feedback
.flags
|=
1411 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1412 pipeline_feedback
.flags
|=
1413 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1415 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1417 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1418 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1419 if (create_feedback
) {
1420 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1422 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1423 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1426 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1427 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1433 * Copy pipeline state not marked as dynamic.
1434 * Dynamic state is pipeline state which hasn't been provided at pipeline
1435 * creation time, but is dynamically provided afterwards using various
1436 * vkCmdSet* functions.
1438 * The set of state considered "non_dynamic" is determined by the pieces of
1439 * state that have their corresponding VkDynamicState enums omitted from
1440 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1442 * @param[out] pipeline Destination non_dynamic state.
1443 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1446 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1447 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1449 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1450 struct anv_subpass
*subpass
= pipeline
->subpass
;
1452 pipeline
->dynamic_state
= default_dynamic_state
;
1454 if (pCreateInfo
->pDynamicState
) {
1455 /* Remove all of the states that are marked as dynamic */
1456 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1457 for (uint32_t s
= 0; s
< count
; s
++)
1458 states
&= ~(1 << pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1461 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1463 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1465 * pViewportState is [...] NULL if the pipeline
1466 * has rasterization disabled.
1468 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1469 assert(pCreateInfo
->pViewportState
);
1471 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1472 if (states
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
1473 typed_memcpy(dynamic
->viewport
.viewports
,
1474 pCreateInfo
->pViewportState
->pViewports
,
1475 pCreateInfo
->pViewportState
->viewportCount
);
1478 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1479 if (states
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
1480 typed_memcpy(dynamic
->scissor
.scissors
,
1481 pCreateInfo
->pViewportState
->pScissors
,
1482 pCreateInfo
->pViewportState
->scissorCount
);
1486 if (states
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
)) {
1487 assert(pCreateInfo
->pRasterizationState
);
1488 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1491 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
)) {
1492 assert(pCreateInfo
->pRasterizationState
);
1493 dynamic
->depth_bias
.bias
=
1494 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1495 dynamic
->depth_bias
.clamp
=
1496 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1497 dynamic
->depth_bias
.slope
=
1498 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1501 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1503 * pColorBlendState is [...] NULL if the pipeline has rasterization
1504 * disabled or if the subpass of the render pass the pipeline is
1505 * created against does not use any color attachments.
1507 bool uses_color_att
= false;
1508 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1509 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1510 uses_color_att
= true;
1515 if (uses_color_att
&&
1516 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1517 assert(pCreateInfo
->pColorBlendState
);
1519 if (states
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
1520 typed_memcpy(dynamic
->blend_constants
,
1521 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1524 /* If there is no depthstencil attachment, then don't read
1525 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1526 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1527 * no need to override the depthstencil defaults in
1528 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1530 * Section 9.2 of the Vulkan 1.0.15 spec says:
1532 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1533 * disabled or if the subpass of the render pass the pipeline is created
1534 * against does not use a depth/stencil attachment.
1536 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1537 subpass
->depth_stencil_attachment
) {
1538 assert(pCreateInfo
->pDepthStencilState
);
1540 if (states
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
)) {
1541 dynamic
->depth_bounds
.min
=
1542 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1543 dynamic
->depth_bounds
.max
=
1544 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1547 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
)) {
1548 dynamic
->stencil_compare_mask
.front
=
1549 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1550 dynamic
->stencil_compare_mask
.back
=
1551 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1554 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
)) {
1555 dynamic
->stencil_write_mask
.front
=
1556 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1557 dynamic
->stencil_write_mask
.back
=
1558 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1561 if (states
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
)) {
1562 dynamic
->stencil_reference
.front
=
1563 pCreateInfo
->pDepthStencilState
->front
.reference
;
1564 dynamic
->stencil_reference
.back
=
1565 pCreateInfo
->pDepthStencilState
->back
.reference
;
1569 pipeline
->dynamic_state_mask
= states
;
1573 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1576 struct anv_render_pass
*renderpass
= NULL
;
1577 struct anv_subpass
*subpass
= NULL
;
1579 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1580 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1582 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1584 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1587 assert(info
->subpass
< renderpass
->subpass_count
);
1588 subpass
= &renderpass
->subpasses
[info
->subpass
];
1590 assert(info
->stageCount
>= 1);
1591 assert(info
->pVertexInputState
);
1592 assert(info
->pInputAssemblyState
);
1593 assert(info
->pRasterizationState
);
1594 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1595 assert(info
->pViewportState
);
1596 assert(info
->pMultisampleState
);
1598 if (subpass
&& subpass
->depth_stencil_attachment
)
1599 assert(info
->pDepthStencilState
);
1601 if (subpass
&& subpass
->color_count
> 0) {
1602 bool all_color_unused
= true;
1603 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1604 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1605 all_color_unused
= false;
1607 /* pColorBlendState is ignored if the pipeline has rasterization
1608 * disabled or if the subpass of the render pass the pipeline is
1609 * created against does not use any color attachments.
1611 assert(info
->pColorBlendState
|| all_color_unused
);
1615 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1616 switch (info
->pStages
[i
].stage
) {
1617 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1618 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1619 assert(info
->pTessellationState
);
1629 * Calculate the desired L3 partitioning based on the current state of the
1630 * pipeline. For now this simply returns the conservative defaults calculated
1631 * by get_default_l3_weights(), but we could probably do better by gathering
1632 * more statistics from the pipeline state (e.g. guess of expected URB usage
1633 * and bound surfaces), or by using feed-back from performance counters.
1636 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1638 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1640 const struct gen_l3_weights w
=
1641 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1643 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1644 pipeline
->urb
.total_size
=
1645 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1649 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1650 struct anv_device
*device
,
1651 struct anv_pipeline_cache
*cache
,
1652 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1653 const VkAllocationCallbacks
*alloc
)
1657 anv_pipeline_validate_create_info(pCreateInfo
);
1660 alloc
= &device
->alloc
;
1662 pipeline
->device
= device
;
1664 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1665 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1666 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1668 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1669 if (result
!= VK_SUCCESS
)
1672 pipeline
->batch
.alloc
= alloc
;
1673 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1674 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1675 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1676 pipeline
->batch
.status
= VK_SUCCESS
;
1678 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1679 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1680 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1682 /* Previously we enabled depth clipping when !depthClampEnable.
1683 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1684 * clipping info is available, use its enable value to determine clipping,
1685 * otherwise fallback to the previous !depthClampEnable logic.
1687 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1688 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1689 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1690 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1692 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1693 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1695 pipeline
->needs_data_cache
= false;
1697 /* When we free the pipeline, we detect stages based on the NULL status
1698 * of various prog_data pointers. Make them NULL by default.
1700 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1702 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1703 if (result
!= VK_SUCCESS
) {
1704 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1708 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1710 anv_pipeline_setup_l3_config(pipeline
, false);
1712 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1713 pCreateInfo
->pVertexInputState
;
1715 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1717 pipeline
->vb_used
= 0;
1718 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1719 const VkVertexInputAttributeDescription
*desc
=
1720 &vi_info
->pVertexAttributeDescriptions
[i
];
1722 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1723 pipeline
->vb_used
|= 1 << desc
->binding
;
1726 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1727 const VkVertexInputBindingDescription
*desc
=
1728 &vi_info
->pVertexBindingDescriptions
[i
];
1730 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1732 /* Step rate is programmed per vertex element (attribute), not
1733 * binding. Set up a map of which bindings step per instance, for
1734 * reference by vertex element setup. */
1735 switch (desc
->inputRate
) {
1737 case VK_VERTEX_INPUT_RATE_VERTEX
:
1738 pipeline
->vb
[desc
->binding
].instanced
= false;
1740 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1741 pipeline
->vb
[desc
->binding
].instanced
= true;
1745 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1748 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1749 vk_find_struct_const(vi_info
->pNext
,
1750 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1752 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1753 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1754 &vi_div_state
->pVertexBindingDivisors
[i
];
1756 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1760 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1761 * different views. If the client asks for instancing, we need to multiply
1762 * the instance divisor by the number of views ensure that we repeat the
1763 * client's per-instance data once for each view.
1765 if (pipeline
->subpass
->view_mask
) {
1766 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1767 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1768 if (pipeline
->vb
[vb
].instanced
)
1769 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1773 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1774 pCreateInfo
->pInputAssemblyState
;
1775 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1776 pCreateInfo
->pTessellationState
;
1777 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1779 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1780 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1782 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];