2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
46 VkResult
anv_CreateShaderModule(
48 const VkShaderModuleCreateInfo
* pCreateInfo
,
49 const VkAllocationCallbacks
* pAllocator
,
50 VkShaderModule
* pShaderModule
)
52 ANV_FROM_HANDLE(anv_device
, device
, _device
);
53 struct anv_shader_module
*module
;
55 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
56 assert(pCreateInfo
->flags
== 0);
58 module
= vk_alloc2(&device
->alloc
, pAllocator
,
59 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
64 module
->size
= pCreateInfo
->codeSize
;
65 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
67 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
69 *pShaderModule
= anv_shader_module_to_handle(module
);
74 void anv_DestroyShaderModule(
76 VkShaderModule _module
,
77 const VkAllocationCallbacks
* pAllocator
)
79 ANV_FROM_HANDLE(anv_device
, device
, _device
);
80 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
85 vk_free2(&device
->alloc
, pAllocator
, module
);
88 #define SPIR_V_MAGIC_NUMBER 0x07230203
90 static const uint64_t stage_to_debug
[] = {
91 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
92 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
93 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
94 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
95 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
96 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
99 struct anv_spirv_debug_data
{
100 struct anv_device
*device
;
101 const struct anv_shader_module
*module
;
104 static void anv_spirv_nir_debug(void *private_data
,
105 enum nir_spirv_debug_level level
,
109 struct anv_spirv_debug_data
*debug_data
= private_data
;
110 static const VkDebugReportFlagsEXT vk_flags
[] = {
111 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
113 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
117 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
119 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
121 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
122 (uint64_t) (uintptr_t) debug_data
->module
,
123 0, 0, "anv", buffer
);
126 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
127 * we can't do that yet because we don't have the ability to copy nir.
130 anv_shader_compile_to_nir(struct anv_device
*device
,
132 const struct anv_shader_module
*module
,
133 const char *entrypoint_name
,
134 gl_shader_stage stage
,
135 const VkSpecializationInfo
*spec_info
)
137 const struct anv_physical_device
*pdevice
=
138 &device
->instance
->physicalDevice
;
139 const struct brw_compiler
*compiler
= pdevice
->compiler
;
140 const nir_shader_compiler_options
*nir_options
=
141 compiler
->glsl_compiler_options
[stage
].NirOptions
;
143 uint32_t *spirv
= (uint32_t *) module
->data
;
144 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
145 assert(module
->size
% 4 == 0);
147 uint32_t num_spec_entries
= 0;
148 struct nir_spirv_specialization
*spec_entries
= NULL
;
149 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
150 num_spec_entries
= spec_info
->mapEntryCount
;
151 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
152 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
153 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
154 const void *data
= spec_info
->pData
+ entry
.offset
;
155 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
157 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
158 if (spec_info
->dataSize
== 8)
159 spec_entries
[i
].data64
= *(const uint64_t *)data
;
161 spec_entries
[i
].data32
= *(const uint32_t *)data
;
165 struct anv_spirv_debug_data spirv_debug_data
= {
169 struct spirv_to_nir_options spirv_options
= {
170 .frag_coord_is_sysval
= true,
171 .use_scoped_memory_barrier
= true,
173 .demote_to_helper_invocation
= true,
174 .derivative_group
= true,
175 .descriptor_array_dynamic_indexing
= true,
176 .descriptor_array_non_uniform_indexing
= true,
177 .descriptor_indexing
= true,
178 .device_group
= true,
179 .draw_parameters
= true,
180 .float16
= pdevice
->info
.gen
>= 8,
181 .float64
= pdevice
->info
.gen
>= 8,
182 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
183 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
184 .geometry_streams
= true,
185 .image_write_without_format
= true,
186 .int8
= pdevice
->info
.gen
>= 8,
187 .int16
= pdevice
->info
.gen
>= 8,
188 .int64
= pdevice
->info
.gen
>= 8,
189 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
192 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
193 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
194 .runtime_descriptor_array
= true,
195 .float_controls
= pdevice
->info
.gen
>= 8,
196 .shader_clock
= true,
197 .shader_viewport_index_layer
= true,
198 .stencil_export
= pdevice
->info
.gen
>= 9,
199 .storage_8bit
= pdevice
->info
.gen
>= 8,
200 .storage_16bit
= pdevice
->info
.gen
>= 8,
201 .subgroup_arithmetic
= true,
202 .subgroup_basic
= true,
203 .subgroup_ballot
= true,
204 .subgroup_quad
= true,
205 .subgroup_shuffle
= true,
206 .subgroup_vote
= true,
207 .tessellation
= true,
208 .transform_feedback
= pdevice
->info
.gen
>= 8,
209 .variable_pointers
= true,
210 .vk_memory_model
= true,
211 .vk_memory_model_device_scope
= true,
213 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
215 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
216 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
217 .push_const_addr_format
= nir_address_format_logical
,
219 /* TODO: Consider changing this to an address format that has the NULL
220 * pointer equals to 0. That might be a better format to play nice
221 * with certain code / code generators.
223 .shared_addr_format
= nir_address_format_32bit_offset
,
225 .func
= anv_spirv_nir_debug
,
226 .private_data
= &spirv_debug_data
,
232 spirv_to_nir(spirv
, module
->size
/ 4,
233 spec_entries
, num_spec_entries
,
234 stage
, entrypoint_name
, &spirv_options
, nir_options
);
235 assert(nir
->info
.stage
== stage
);
236 nir_validate_shader(nir
, "after spirv_to_nir");
237 ralloc_steal(mem_ctx
, nir
);
241 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
242 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
243 gl_shader_stage_name(stage
));
244 nir_print_shader(nir
, stderr
);
247 /* We have to lower away local constant initializers right before we
248 * inline functions. That way they get properly initialized at the top
249 * of the function and not at the top of its caller.
251 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
252 NIR_PASS_V(nir
, nir_lower_returns
);
253 NIR_PASS_V(nir
, nir_inline_functions
);
254 NIR_PASS_V(nir
, nir_opt_deref
);
256 /* Pick off the single entrypoint that we want */
257 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
258 if (!func
->is_entrypoint
)
259 exec_node_remove(&func
->node
);
261 assert(exec_list_length(&nir
->functions
) == 1);
263 /* Now that we've deleted all but the main function, we can go ahead and
264 * lower the rest of the constant initializers. We do this here so that
265 * nir_remove_dead_variables and split_per_member_structs below see the
266 * corresponding stores.
268 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
270 /* Split member structs. We do this before lower_io_to_temporaries so that
271 * it doesn't lower system values to temporaries by accident.
273 NIR_PASS_V(nir
, nir_split_var_copies
);
274 NIR_PASS_V(nir
, nir_split_per_member_structs
);
276 NIR_PASS_V(nir
, nir_remove_dead_variables
,
277 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
279 NIR_PASS_V(nir
, nir_propagate_invariant
);
280 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
281 nir_shader_get_entrypoint(nir
), true, false);
283 NIR_PASS_V(nir
, nir_lower_frexp
);
285 /* Vulkan uses the separate-shader linking model */
286 nir
->info
.separate_shader
= true;
288 brw_preprocess_nir(compiler
, nir
, NULL
);
293 void anv_DestroyPipeline(
295 VkPipeline _pipeline
,
296 const VkAllocationCallbacks
* pAllocator
)
298 ANV_FROM_HANDLE(anv_device
, device
, _device
);
299 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
304 anv_reloc_list_finish(&pipeline
->batch_relocs
,
305 pAllocator
? pAllocator
: &device
->alloc
);
307 ralloc_free(pipeline
->mem_ctx
);
309 if (pipeline
->blend_state
.map
)
310 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
312 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
313 if (pipeline
->shaders
[s
])
314 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
317 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
320 static const uint32_t vk_to_gen_primitive_type
[] = {
321 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
322 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
323 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
324 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
325 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
326 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
327 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
328 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
329 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
330 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
334 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
335 struct brw_sampler_prog_key_data
*key
)
337 /* Almost all multisampled textures are compressed. The only time when we
338 * don't compress a multisampled texture is for 16x MSAA with a surface
339 * width greater than 8k which is a bit of an edge case. Since the sampler
340 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
341 * to tell the compiler to always assume compression.
343 key
->compressed_multisample_layout_mask
= ~0;
345 /* SkyLake added support for 16x MSAA. With this came a new message for
346 * reading from a 16x MSAA surface with compression. The new message was
347 * needed because now the MCS data is 64 bits instead of 32 or lower as is
348 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
349 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
350 * so we can just use it unconditionally. This may not be quite as
351 * efficient but it saves us from recompiling.
353 if (devinfo
->gen
>= 9)
356 /* XXX: Handle texture swizzle on HSW- */
357 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
358 /* Assume color sampler, no swizzling. (Works for BDW+) */
359 key
->swizzles
[i
] = SWIZZLE_XYZW
;
364 populate_base_prog_key(const struct gen_device_info
*devinfo
,
365 VkPipelineShaderStageCreateFlags flags
,
366 struct brw_base_prog_key
*key
)
368 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
369 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
371 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
373 populate_sampler_prog_key(devinfo
, &key
->tex
);
377 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
378 VkPipelineShaderStageCreateFlags flags
,
379 struct brw_vs_prog_key
*key
)
381 memset(key
, 0, sizeof(*key
));
383 populate_base_prog_key(devinfo
, flags
, &key
->base
);
385 /* XXX: Handle vertex input work-arounds */
387 /* XXX: Handle sampler_prog_key */
391 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
392 VkPipelineShaderStageCreateFlags flags
,
393 unsigned input_vertices
,
394 struct brw_tcs_prog_key
*key
)
396 memset(key
, 0, sizeof(*key
));
398 populate_base_prog_key(devinfo
, flags
, &key
->base
);
400 key
->input_vertices
= input_vertices
;
404 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
405 VkPipelineShaderStageCreateFlags flags
,
406 struct brw_tes_prog_key
*key
)
408 memset(key
, 0, sizeof(*key
));
410 populate_base_prog_key(devinfo
, flags
, &key
->base
);
414 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
415 VkPipelineShaderStageCreateFlags flags
,
416 struct brw_gs_prog_key
*key
)
418 memset(key
, 0, sizeof(*key
));
420 populate_base_prog_key(devinfo
, flags
, &key
->base
);
424 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
425 VkPipelineShaderStageCreateFlags flags
,
426 const struct anv_subpass
*subpass
,
427 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
428 struct brw_wm_prog_key
*key
)
430 memset(key
, 0, sizeof(*key
));
432 populate_base_prog_key(devinfo
, flags
, &key
->base
);
434 /* We set this to 0 here and set to the actual value before we call
437 key
->input_slots_valid
= 0;
439 /* Vulkan doesn't specify a default */
440 key
->high_quality_derivatives
= false;
442 /* XXX Vulkan doesn't appear to specify */
443 key
->clamp_fragment_color
= false;
445 assert(subpass
->color_count
<= MAX_RTS
);
446 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
447 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
448 key
->color_outputs_valid
|= (1 << i
);
451 key
->nr_color_regions
= subpass
->color_count
;
453 /* To reduce possible shader recompilations we would need to know if
454 * there is a SampleMask output variable to compute if we should emit
455 * code to workaround the issue that hardware disables alpha to coverage
456 * when there is SampleMask output.
458 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
460 /* Vulkan doesn't support fixed-function alpha test */
461 key
->alpha_test_replicate_alpha
= false;
464 /* We should probably pull this out of the shader, but it's fairly
465 * harmless to compute it and then let dead-code take care of it.
467 if (ms_info
->rasterizationSamples
> 1) {
468 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
469 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
470 key
->multisample_fbo
= true;
473 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
478 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
479 VkPipelineShaderStageCreateFlags flags
,
480 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
481 struct brw_cs_prog_key
*key
)
483 memset(key
, 0, sizeof(*key
));
485 populate_base_prog_key(devinfo
, flags
, &key
->base
);
488 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
490 /* These enum values are expressly chosen to be equal to the subgroup
491 * size that they require.
493 assert(rss_info
->requiredSubgroupSize
== 8 ||
494 rss_info
->requiredSubgroupSize
== 16 ||
495 rss_info
->requiredSubgroupSize
== 32);
496 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
497 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
498 /* If the client expressly requests full subgroups and they don't
499 * specify a subgroup size, we need to pick one. If they're requested
500 * varying subgroup sizes, we set it to UNIFORM and let the back-end
501 * compiler pick. Otherwise, we specify the API value of 32.
502 * Performance will likely be terrible in this case but there's nothing
503 * we can do about that. The client should have chosen a size.
505 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
506 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
508 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
512 struct anv_pipeline_stage
{
513 gl_shader_stage stage
;
515 const struct anv_shader_module
*module
;
516 const char *entrypoint
;
517 const VkSpecializationInfo
*spec_info
;
519 unsigned char shader_sha1
[20];
521 union brw_any_prog_key key
;
524 gl_shader_stage stage
;
525 unsigned char sha1
[20];
530 struct anv_pipeline_binding surface_to_descriptor
[256];
531 struct anv_pipeline_binding sampler_to_descriptor
[256];
532 struct anv_pipeline_bind_map bind_map
;
534 union brw_any_prog_data prog_data
;
537 struct brw_compile_stats stats
[3];
540 VkPipelineCreationFeedbackEXT feedback
;
542 const unsigned *code
;
546 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
547 const char *entrypoint
,
548 gl_shader_stage stage
,
549 const VkSpecializationInfo
*spec_info
,
550 unsigned char *sha1_out
)
552 struct mesa_sha1 ctx
;
553 _mesa_sha1_init(&ctx
);
555 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
556 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
557 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
559 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
560 spec_info
->mapEntryCount
*
561 sizeof(*spec_info
->pMapEntries
));
562 _mesa_sha1_update(&ctx
, spec_info
->pData
,
563 spec_info
->dataSize
);
566 _mesa_sha1_final(&ctx
, sha1_out
);
570 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
571 struct anv_pipeline_layout
*layout
,
572 struct anv_pipeline_stage
*stages
,
573 unsigned char *sha1_out
)
575 struct mesa_sha1 ctx
;
576 _mesa_sha1_init(&ctx
);
578 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
579 sizeof(pipeline
->subpass
->view_mask
));
582 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
584 const bool rba
= pipeline
->device
->robust_buffer_access
;
585 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
587 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
588 if (stages
[s
].entrypoint
) {
589 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
590 sizeof(stages
[s
].shader_sha1
));
591 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
595 _mesa_sha1_final(&ctx
, sha1_out
);
599 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
600 struct anv_pipeline_layout
*layout
,
601 struct anv_pipeline_stage
*stage
,
602 unsigned char *sha1_out
)
604 struct mesa_sha1 ctx
;
605 _mesa_sha1_init(&ctx
);
608 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
610 const bool rba
= pipeline
->device
->robust_buffer_access
;
611 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
613 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
614 sizeof(stage
->shader_sha1
));
615 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
617 _mesa_sha1_final(&ctx
, sha1_out
);
621 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
622 struct anv_pipeline_cache
*cache
,
624 struct anv_pipeline_stage
*stage
)
626 const struct brw_compiler
*compiler
=
627 pipeline
->device
->instance
->physicalDevice
.compiler
;
628 const nir_shader_compiler_options
*nir_options
=
629 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
632 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
637 assert(nir
->info
.stage
== stage
->stage
);
641 nir
= anv_shader_compile_to_nir(pipeline
->device
,
648 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
656 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
658 struct anv_pipeline_stage
*stage
,
659 struct anv_pipeline_layout
*layout
)
661 const struct anv_physical_device
*pdevice
=
662 &pipeline
->device
->instance
->physicalDevice
;
663 const struct brw_compiler
*compiler
= pdevice
->compiler
;
665 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
666 nir_shader
*nir
= stage
->nir
;
668 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
669 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
670 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
673 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
675 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
676 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
678 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
680 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
681 pipeline
->needs_data_cache
= true;
683 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
685 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
686 nir_address_format_64bit_global
);
688 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
689 anv_nir_apply_pipeline_layout(pdevice
,
690 pipeline
->device
->robust_buffer_access
,
691 layout
, nir
, &stage
->bind_map
);
693 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
694 nir_address_format_32bit_index_offset
);
695 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
696 anv_nir_ssbo_addr_format(pdevice
,
697 pipeline
->device
->robust_buffer_access
));
699 NIR_PASS_V(nir
, nir_opt_constant_folding
);
701 /* We don't support non-uniform UBOs and non-uniform SSBO access is
702 * handled naturally by falling back to A64 messages.
704 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
705 nir_lower_non_uniform_texture_access
|
706 nir_lower_non_uniform_image_access
);
708 anv_nir_compute_push_layout(pdevice
, nir
, prog_data
,
709 &stage
->bind_map
, mem_ctx
);
715 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
716 struct anv_pipeline_stage
*vs_stage
,
717 struct anv_pipeline_stage
*next_stage
)
720 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
724 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
726 struct anv_device
*device
,
727 struct anv_pipeline_stage
*vs_stage
)
729 brw_compute_vue_map(compiler
->devinfo
,
730 &vs_stage
->prog_data
.vs
.base
.vue_map
,
731 vs_stage
->nir
->info
.outputs_written
,
732 vs_stage
->nir
->info
.separate_shader
);
734 vs_stage
->num_stats
= 1;
735 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
737 &vs_stage
->prog_data
.vs
,
739 vs_stage
->stats
, NULL
);
743 merge_tess_info(struct shader_info
*tes_info
,
744 const struct shader_info
*tcs_info
)
746 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
748 * "PointMode. Controls generation of points rather than triangles
749 * or lines. This functionality defaults to disabled, and is
750 * enabled if either shader stage includes the execution mode.
752 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
753 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
754 * and OutputVertices, it says:
756 * "One mode must be set in at least one of the tessellation
759 * So, the fields can be set in either the TCS or TES, but they must
760 * agree if set in both. Our backend looks at TES, so bitwise-or in
761 * the values from the TCS.
763 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
764 tes_info
->tess
.tcs_vertices_out
== 0 ||
765 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
766 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
768 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
769 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
770 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
771 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
773 assert(tcs_info
->tess
.primitive_mode
== 0 ||
774 tes_info
->tess
.primitive_mode
== 0 ||
775 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
776 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
777 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
778 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
782 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
783 struct anv_pipeline_stage
*tcs_stage
,
784 struct anv_pipeline_stage
*tes_stage
)
786 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
788 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
790 nir_lower_patch_vertices(tes_stage
->nir
,
791 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
794 /* Copy TCS info into the TES info */
795 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
797 /* Whacking the key after cache lookup is a bit sketchy, but all of
798 * this comes from the SPIR-V, which is part of the hash used for the
799 * pipeline cache. So it should be safe.
801 tcs_stage
->key
.tcs
.tes_primitive_mode
=
802 tes_stage
->nir
->info
.tess
.primitive_mode
;
803 tcs_stage
->key
.tcs
.quads_workaround
=
804 compiler
->devinfo
->gen
< 9 &&
805 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
806 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
810 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
812 struct anv_device
*device
,
813 struct anv_pipeline_stage
*tcs_stage
,
814 struct anv_pipeline_stage
*prev_stage
)
816 tcs_stage
->key
.tcs
.outputs_written
=
817 tcs_stage
->nir
->info
.outputs_written
;
818 tcs_stage
->key
.tcs
.patch_outputs_written
=
819 tcs_stage
->nir
->info
.patch_outputs_written
;
821 tcs_stage
->num_stats
= 1;
822 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
824 &tcs_stage
->prog_data
.tcs
,
826 tcs_stage
->stats
, NULL
);
830 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
831 struct anv_pipeline_stage
*tes_stage
,
832 struct anv_pipeline_stage
*next_stage
)
835 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
839 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
841 struct anv_device
*device
,
842 struct anv_pipeline_stage
*tes_stage
,
843 struct anv_pipeline_stage
*tcs_stage
)
845 tes_stage
->key
.tes
.inputs_read
=
846 tcs_stage
->nir
->info
.outputs_written
;
847 tes_stage
->key
.tes
.patch_inputs_read
=
848 tcs_stage
->nir
->info
.patch_outputs_written
;
850 tes_stage
->num_stats
= 1;
851 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
853 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
854 &tes_stage
->prog_data
.tes
,
856 tes_stage
->stats
, NULL
);
860 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
861 struct anv_pipeline_stage
*gs_stage
,
862 struct anv_pipeline_stage
*next_stage
)
865 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
869 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
871 struct anv_device
*device
,
872 struct anv_pipeline_stage
*gs_stage
,
873 struct anv_pipeline_stage
*prev_stage
)
875 brw_compute_vue_map(compiler
->devinfo
,
876 &gs_stage
->prog_data
.gs
.base
.vue_map
,
877 gs_stage
->nir
->info
.outputs_written
,
878 gs_stage
->nir
->info
.separate_shader
);
880 gs_stage
->num_stats
= 1;
881 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
883 &gs_stage
->prog_data
.gs
,
884 gs_stage
->nir
, NULL
, -1,
885 gs_stage
->stats
, NULL
);
889 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
890 struct anv_pipeline_stage
*stage
)
892 unsigned num_rt_bindings
;
893 struct anv_pipeline_binding rt_bindings
[MAX_RTS
];
894 if (stage
->key
.wm
.nr_color_regions
> 0) {
895 assert(stage
->key
.wm
.nr_color_regions
<= MAX_RTS
);
896 for (unsigned rt
= 0; rt
< stage
->key
.wm
.nr_color_regions
; rt
++) {
897 if (stage
->key
.wm
.color_outputs_valid
& BITFIELD_BIT(rt
)) {
898 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
899 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
903 /* Setup a null render target */
904 rt_bindings
[rt
] = (struct anv_pipeline_binding
) {
905 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
910 num_rt_bindings
= stage
->key
.wm
.nr_color_regions
;
912 /* Setup a null render target */
913 rt_bindings
[0] = (struct anv_pipeline_binding
) {
914 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
920 assert(num_rt_bindings
<= MAX_RTS
);
921 assert(stage
->bind_map
.surface_count
== 0);
922 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
923 rt_bindings
, num_rt_bindings
);
924 stage
->bind_map
.surface_count
+= num_rt_bindings
;
926 /* Now that we've set up the color attachments, we can go through and
927 * eliminate any shader outputs that map to VK_ATTACHMENT_UNUSED in the
928 * hopes that dead code can clean them up in this and any earlier shader
931 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
932 bool deleted_output
= false;
933 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
934 /* TODO: We don't delete depth/stencil writes. We probably could if the
935 * subpass doesn't have a depth/stencil attachment.
937 if (var
->data
.location
< FRAG_RESULT_DATA0
)
940 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
942 /* If this is the RT at location 0 and we have alpha to coverage
943 * enabled we still need that write because it will affect the coverage
944 * mask even if it's never written to a color target.
946 if (rt
== 0 && stage
->key
.wm
.alpha_to_coverage
)
949 const unsigned array_len
=
950 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
951 assert(rt
+ array_len
<= MAX_RTS
);
953 if (rt
>= MAX_RTS
|| !(stage
->key
.wm
.color_outputs_valid
&
954 BITFIELD_RANGE(rt
, array_len
))) {
955 deleted_output
= true;
956 var
->data
.mode
= nir_var_function_temp
;
957 exec_node_remove(&var
->node
);
958 exec_list_push_tail(&impl
->locals
, &var
->node
);
963 nir_fixup_deref_modes(stage
->nir
);
965 /* We stored the number of subpass color attachments in nr_color_regions
966 * when calculating the key for caching. Now that we've computed the bind
967 * map, we can reduce this to the actual max before we go into the back-end
970 stage
->key
.wm
.nr_color_regions
=
971 util_last_bit(stage
->key
.wm
.color_outputs_valid
);
975 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
977 struct anv_device
*device
,
978 struct anv_pipeline_stage
*fs_stage
,
979 struct anv_pipeline_stage
*prev_stage
)
981 /* TODO: we could set this to 0 based on the information in nir_shader, but
982 * we need this before we call spirv_to_nir.
985 fs_stage
->key
.wm
.input_slots_valid
=
986 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
988 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
990 &fs_stage
->prog_data
.wm
,
991 fs_stage
->nir
, -1, -1, -1,
993 fs_stage
->stats
, NULL
);
995 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
996 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
997 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
999 if (fs_stage
->key
.wm
.color_outputs_valid
== 0 &&
1000 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1001 !fs_stage
->prog_data
.wm
.uses_omask
&&
1002 !fs_stage
->key
.wm
.alpha_to_coverage
&&
1003 !fs_stage
->prog_data
.wm
.uses_kill
&&
1004 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1005 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1006 /* This fragment shader has no outputs and no side effects. Go ahead
1007 * and return the code pointer so we don't accidentally think the
1008 * compile failed but zero out prog_data which will set program_size to
1009 * zero and disable the stage.
1011 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1016 anv_pipeline_add_executable(struct anv_pipeline
*pipeline
,
1017 struct anv_pipeline_stage
*stage
,
1018 struct brw_compile_stats
*stats
,
1019 uint32_t code_offset
)
1024 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1025 char *stream_data
= NULL
;
1026 size_t stream_size
= 0;
1027 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1029 nir_print_shader(stage
->nir
, stream
);
1033 /* Copy it to a ralloc'd thing */
1034 nir
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1035 memcpy(nir
, stream_data
, stream_size
);
1036 nir
[stream_size
] = 0;
1041 char *disasm
= NULL
;
1044 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1045 char *stream_data
= NULL
;
1046 size_t stream_size
= 0;
1047 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1049 /* Creating this is far cheaper than it looks. It's perfectly fine to
1050 * do it for every binary.
1052 struct gen_disasm
*d
= gen_disasm_create(&pipeline
->device
->info
);
1053 gen_disasm_disassemble(d
, stage
->code
, code_offset
, stream
);
1054 gen_disasm_destroy(d
);
1058 /* Copy it to a ralloc'd thing */
1059 disasm
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1060 memcpy(disasm
, stream_data
, stream_size
);
1061 disasm
[stream_size
] = 0;
1066 pipeline
->executables
[pipeline
->num_executables
++] =
1067 (struct anv_pipeline_executable
) {
1068 .stage
= stage
->stage
,
1076 anv_pipeline_add_executables(struct anv_pipeline
*pipeline
,
1077 struct anv_pipeline_stage
*stage
,
1078 struct anv_shader_bin
*bin
)
1080 if (stage
->stage
== MESA_SHADER_FRAGMENT
) {
1081 /* We pull the prog data and stats out of the anv_shader_bin because
1082 * the anv_pipeline_stage may not be fully populated if we successfully
1083 * looked up the shader in a cache.
1085 const struct brw_wm_prog_data
*wm_prog_data
=
1086 (const struct brw_wm_prog_data
*)bin
->prog_data
;
1087 struct brw_compile_stats
*stats
= bin
->stats
;
1089 if (wm_prog_data
->dispatch_8
) {
1090 anv_pipeline_add_executable(pipeline
, stage
, stats
++, 0);
1093 if (wm_prog_data
->dispatch_16
) {
1094 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1095 wm_prog_data
->prog_offset_16
);
1098 if (wm_prog_data
->dispatch_32
) {
1099 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1100 wm_prog_data
->prog_offset_32
);
1103 anv_pipeline_add_executable(pipeline
, stage
, bin
->stats
, 0);
1108 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1109 struct anv_pipeline_cache
*cache
,
1110 const VkGraphicsPipelineCreateInfo
*info
)
1112 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1113 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1115 int64_t pipeline_start
= os_time_get_nano();
1117 const struct brw_compiler
*compiler
=
1118 pipeline
->device
->instance
->physicalDevice
.compiler
;
1119 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1121 pipeline
->active_stages
= 0;
1124 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1125 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1126 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1128 pipeline
->active_stages
|= sinfo
->stage
;
1130 int64_t stage_start
= os_time_get_nano();
1132 stages
[stage
].stage
= stage
;
1133 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1134 stages
[stage
].entrypoint
= sinfo
->pName
;
1135 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1136 anv_pipeline_hash_shader(stages
[stage
].module
,
1137 stages
[stage
].entrypoint
,
1139 stages
[stage
].spec_info
,
1140 stages
[stage
].shader_sha1
);
1142 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1144 case MESA_SHADER_VERTEX
:
1145 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1147 case MESA_SHADER_TESS_CTRL
:
1148 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1149 info
->pTessellationState
->patchControlPoints
,
1150 &stages
[stage
].key
.tcs
);
1152 case MESA_SHADER_TESS_EVAL
:
1153 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1155 case MESA_SHADER_GEOMETRY
:
1156 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1158 case MESA_SHADER_FRAGMENT
:
1159 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1161 info
->pMultisampleState
,
1162 &stages
[stage
].key
.wm
);
1165 unreachable("Invalid graphics shader stage");
1168 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1169 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1172 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1173 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1175 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1177 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1179 unsigned char sha1
[20];
1180 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1182 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1183 if (!stages
[s
].entrypoint
)
1186 stages
[s
].cache_key
.stage
= s
;
1187 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1190 const bool skip_cache_lookup
=
1191 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1193 if (!skip_cache_lookup
) {
1195 unsigned cache_hits
= 0;
1196 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1197 if (!stages
[s
].entrypoint
)
1200 int64_t stage_start
= os_time_get_nano();
1203 struct anv_shader_bin
*bin
=
1204 anv_device_search_for_kernel(pipeline
->device
, cache
,
1205 &stages
[s
].cache_key
,
1206 sizeof(stages
[s
].cache_key
), &cache_hit
);
1209 pipeline
->shaders
[s
] = bin
;
1214 stages
[s
].feedback
.flags
|=
1215 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1217 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1220 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1221 if (cache_hits
== found
) {
1222 pipeline_feedback
.flags
|=
1223 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1225 /* We found all our shaders in the cache. We're done. */
1226 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1227 if (!stages
[s
].entrypoint
)
1230 anv_pipeline_add_executables(pipeline
, &stages
[s
],
1231 pipeline
->shaders
[s
]);
1234 } else if (found
> 0) {
1235 /* We found some but not all of our shaders. This shouldn't happen
1236 * most of the time but it can if we have a partially populated
1239 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1241 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1242 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1243 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1244 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1245 (uint64_t)(uintptr_t)cache
,
1247 "Found a partial pipeline in the cache. This is "
1248 "most likely caused by an incomplete pipeline cache "
1249 "import or export");
1251 /* We're going to have to recompile anyway, so just throw away our
1252 * references to the shaders in the cache. We'll get them out of the
1253 * cache again as part of the compilation process.
1255 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1256 stages
[s
].feedback
.flags
= 0;
1257 if (pipeline
->shaders
[s
]) {
1258 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1259 pipeline
->shaders
[s
] = NULL
;
1265 void *pipeline_ctx
= ralloc_context(NULL
);
1267 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1268 if (!stages
[s
].entrypoint
)
1271 int64_t stage_start
= os_time_get_nano();
1273 assert(stages
[s
].stage
== s
);
1274 assert(pipeline
->shaders
[s
] == NULL
);
1276 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1277 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1278 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1281 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1284 if (stages
[s
].nir
== NULL
) {
1285 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1289 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1292 /* Walk backwards to link */
1293 struct anv_pipeline_stage
*next_stage
= NULL
;
1294 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1295 if (!stages
[s
].entrypoint
)
1299 case MESA_SHADER_VERTEX
:
1300 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1302 case MESA_SHADER_TESS_CTRL
:
1303 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1305 case MESA_SHADER_TESS_EVAL
:
1306 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1308 case MESA_SHADER_GEOMETRY
:
1309 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1311 case MESA_SHADER_FRAGMENT
:
1312 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1315 unreachable("Invalid graphics shader stage");
1318 next_stage
= &stages
[s
];
1321 struct anv_pipeline_stage
*prev_stage
= NULL
;
1322 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1323 if (!stages
[s
].entrypoint
)
1326 int64_t stage_start
= os_time_get_nano();
1328 void *stage_ctx
= ralloc_context(NULL
);
1330 nir_xfb_info
*xfb_info
= NULL
;
1331 if (s
== MESA_SHADER_VERTEX
||
1332 s
== MESA_SHADER_TESS_EVAL
||
1333 s
== MESA_SHADER_GEOMETRY
)
1334 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1336 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1339 case MESA_SHADER_VERTEX
:
1340 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1343 case MESA_SHADER_TESS_CTRL
:
1344 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1345 &stages
[s
], prev_stage
);
1347 case MESA_SHADER_TESS_EVAL
:
1348 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1349 &stages
[s
], prev_stage
);
1351 case MESA_SHADER_GEOMETRY
:
1352 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1353 &stages
[s
], prev_stage
);
1355 case MESA_SHADER_FRAGMENT
:
1356 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1357 &stages
[s
], prev_stage
);
1360 unreachable("Invalid graphics shader stage");
1362 if (stages
[s
].code
== NULL
) {
1363 ralloc_free(stage_ctx
);
1364 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1368 anv_nir_validate_push_layout(&stages
[s
].prog_data
.base
,
1369 &stages
[s
].bind_map
);
1371 struct anv_shader_bin
*bin
=
1372 anv_device_upload_kernel(pipeline
->device
, cache
,
1373 &stages
[s
].cache_key
,
1374 sizeof(stages
[s
].cache_key
),
1376 stages
[s
].prog_data
.base
.program_size
,
1377 stages
[s
].nir
->constant_data
,
1378 stages
[s
].nir
->constant_data_size
,
1379 &stages
[s
].prog_data
.base
,
1380 brw_prog_data_size(s
),
1381 stages
[s
].stats
, stages
[s
].num_stats
,
1382 xfb_info
, &stages
[s
].bind_map
);
1384 ralloc_free(stage_ctx
);
1385 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1389 anv_pipeline_add_executables(pipeline
, &stages
[s
], bin
);
1391 pipeline
->shaders
[s
] = bin
;
1392 ralloc_free(stage_ctx
);
1394 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1396 prev_stage
= &stages
[s
];
1399 ralloc_free(pipeline_ctx
);
1403 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1404 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1405 /* This can happen if we decided to implicitly disable the fragment
1406 * shader. See anv_pipeline_compile_fs().
1408 anv_shader_bin_unref(pipeline
->device
,
1409 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1410 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1411 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1414 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1416 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1417 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1418 if (create_feedback
) {
1419 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1421 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1422 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1423 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1424 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1431 ralloc_free(pipeline_ctx
);
1433 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1434 if (pipeline
->shaders
[s
])
1435 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1442 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1444 assert(glsl_type_is_vector_or_scalar(type
));
1446 uint32_t comp_size
= glsl_type_is_boolean(type
)
1447 ? 4 : glsl_get_bit_size(type
) / 8;
1448 unsigned length
= glsl_get_vector_elements(type
);
1449 *size
= comp_size
* length
,
1450 *align
= comp_size
* (length
== 3 ? 4 : length
);
1454 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1455 struct anv_pipeline_cache
*cache
,
1456 const VkComputePipelineCreateInfo
*info
,
1457 const struct anv_shader_module
*module
,
1458 const char *entrypoint
,
1459 const VkSpecializationInfo
*spec_info
)
1461 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1462 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1464 int64_t pipeline_start
= os_time_get_nano();
1466 const struct brw_compiler
*compiler
=
1467 pipeline
->device
->instance
->physicalDevice
.compiler
;
1469 struct anv_pipeline_stage stage
= {
1470 .stage
= MESA_SHADER_COMPUTE
,
1472 .entrypoint
= entrypoint
,
1473 .spec_info
= spec_info
,
1475 .stage
= MESA_SHADER_COMPUTE
,
1478 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1481 anv_pipeline_hash_shader(stage
.module
,
1483 MESA_SHADER_COMPUTE
,
1487 struct anv_shader_bin
*bin
= NULL
;
1489 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1490 vk_find_struct_const(info
->stage
.pNext
,
1491 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1493 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1494 rss_info
, &stage
.key
.cs
);
1496 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1498 const bool skip_cache_lookup
=
1499 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1501 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1503 bool cache_hit
= false;
1504 if (!skip_cache_lookup
) {
1505 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
1507 sizeof(stage
.cache_key
),
1511 void *mem_ctx
= ralloc_context(NULL
);
1513 int64_t stage_start
= os_time_get_nano();
1515 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1516 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1517 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1520 /* Set up a binding for the gl_NumWorkGroups */
1521 stage
.bind_map
.surface_count
= 1;
1522 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1523 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1526 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1527 if (stage
.nir
== NULL
) {
1528 ralloc_free(mem_ctx
);
1529 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1532 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
);
1534 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1536 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1537 nir_var_mem_shared
, shared_type_info
);
1538 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1539 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1541 stage
.num_stats
= 1;
1542 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1543 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1544 stage
.nir
, -1, stage
.stats
, NULL
);
1545 if (stage
.code
== NULL
) {
1546 ralloc_free(mem_ctx
);
1547 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1550 anv_nir_validate_push_layout(&stage
.prog_data
.base
, &stage
.bind_map
);
1552 if (!stage
.prog_data
.cs
.uses_num_work_groups
) {
1553 assert(stage
.bind_map
.surface_to_descriptor
[0].set
==
1554 ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
);
1555 stage
.bind_map
.surface_to_descriptor
[0].set
= ANV_DESCRIPTOR_SET_NULL
;
1558 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1559 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1560 &stage
.cache_key
, sizeof(stage
.cache_key
),
1561 stage
.code
, code_size
,
1562 stage
.nir
->constant_data
,
1563 stage
.nir
->constant_data_size
,
1564 &stage
.prog_data
.base
,
1565 sizeof(stage
.prog_data
.cs
),
1566 stage
.stats
, stage
.num_stats
,
1567 NULL
, &stage
.bind_map
);
1569 ralloc_free(mem_ctx
);
1570 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1573 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1576 anv_pipeline_add_executables(pipeline
, &stage
, bin
);
1578 ralloc_free(mem_ctx
);
1581 stage
.feedback
.flags
|=
1582 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1583 pipeline_feedback
.flags
|=
1584 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1586 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1588 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1589 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1590 if (create_feedback
) {
1591 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1593 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1594 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1597 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1598 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1604 * Copy pipeline state not marked as dynamic.
1605 * Dynamic state is pipeline state which hasn't been provided at pipeline
1606 * creation time, but is dynamically provided afterwards using various
1607 * vkCmdSet* functions.
1609 * The set of state considered "non_dynamic" is determined by the pieces of
1610 * state that have their corresponding VkDynamicState enums omitted from
1611 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1613 * @param[out] pipeline Destination non_dynamic state.
1614 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1617 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1618 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1620 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1621 struct anv_subpass
*subpass
= pipeline
->subpass
;
1623 pipeline
->dynamic_state
= default_dynamic_state
;
1625 if (pCreateInfo
->pDynamicState
) {
1626 /* Remove all of the states that are marked as dynamic */
1627 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1628 for (uint32_t s
= 0; s
< count
; s
++) {
1629 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1630 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1634 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1636 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1638 * pViewportState is [...] NULL if the pipeline
1639 * has rasterization disabled.
1641 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1642 assert(pCreateInfo
->pViewportState
);
1644 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1645 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1646 typed_memcpy(dynamic
->viewport
.viewports
,
1647 pCreateInfo
->pViewportState
->pViewports
,
1648 pCreateInfo
->pViewportState
->viewportCount
);
1651 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1652 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1653 typed_memcpy(dynamic
->scissor
.scissors
,
1654 pCreateInfo
->pViewportState
->pScissors
,
1655 pCreateInfo
->pViewportState
->scissorCount
);
1659 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1660 assert(pCreateInfo
->pRasterizationState
);
1661 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1664 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1665 assert(pCreateInfo
->pRasterizationState
);
1666 dynamic
->depth_bias
.bias
=
1667 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1668 dynamic
->depth_bias
.clamp
=
1669 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1670 dynamic
->depth_bias
.slope
=
1671 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1674 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1676 * pColorBlendState is [...] NULL if the pipeline has rasterization
1677 * disabled or if the subpass of the render pass the pipeline is
1678 * created against does not use any color attachments.
1680 bool uses_color_att
= false;
1681 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1682 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1683 uses_color_att
= true;
1688 if (uses_color_att
&&
1689 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1690 assert(pCreateInfo
->pColorBlendState
);
1692 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1693 typed_memcpy(dynamic
->blend_constants
,
1694 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1697 /* If there is no depthstencil attachment, then don't read
1698 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1699 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1700 * no need to override the depthstencil defaults in
1701 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1703 * Section 9.2 of the Vulkan 1.0.15 spec says:
1705 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1706 * disabled or if the subpass of the render pass the pipeline is created
1707 * against does not use a depth/stencil attachment.
1709 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1710 subpass
->depth_stencil_attachment
) {
1711 assert(pCreateInfo
->pDepthStencilState
);
1713 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1714 dynamic
->depth_bounds
.min
=
1715 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1716 dynamic
->depth_bounds
.max
=
1717 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1720 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1721 dynamic
->stencil_compare_mask
.front
=
1722 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1723 dynamic
->stencil_compare_mask
.back
=
1724 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1727 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1728 dynamic
->stencil_write_mask
.front
=
1729 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1730 dynamic
->stencil_write_mask
.back
=
1731 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1734 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1735 dynamic
->stencil_reference
.front
=
1736 pCreateInfo
->pDepthStencilState
->front
.reference
;
1737 dynamic
->stencil_reference
.back
=
1738 pCreateInfo
->pDepthStencilState
->back
.reference
;
1742 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1743 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1744 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1746 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1747 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1748 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1752 pipeline
->dynamic_state_mask
= states
;
1756 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1759 struct anv_render_pass
*renderpass
= NULL
;
1760 struct anv_subpass
*subpass
= NULL
;
1762 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1763 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1765 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1767 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1770 assert(info
->subpass
< renderpass
->subpass_count
);
1771 subpass
= &renderpass
->subpasses
[info
->subpass
];
1773 assert(info
->stageCount
>= 1);
1774 assert(info
->pVertexInputState
);
1775 assert(info
->pInputAssemblyState
);
1776 assert(info
->pRasterizationState
);
1777 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1778 assert(info
->pViewportState
);
1779 assert(info
->pMultisampleState
);
1781 if (subpass
&& subpass
->depth_stencil_attachment
)
1782 assert(info
->pDepthStencilState
);
1784 if (subpass
&& subpass
->color_count
> 0) {
1785 bool all_color_unused
= true;
1786 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1787 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1788 all_color_unused
= false;
1790 /* pColorBlendState is ignored if the pipeline has rasterization
1791 * disabled or if the subpass of the render pass the pipeline is
1792 * created against does not use any color attachments.
1794 assert(info
->pColorBlendState
|| all_color_unused
);
1798 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1799 switch (info
->pStages
[i
].stage
) {
1800 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1801 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1802 assert(info
->pTessellationState
);
1812 * Calculate the desired L3 partitioning based on the current state of the
1813 * pipeline. For now this simply returns the conservative defaults calculated
1814 * by get_default_l3_weights(), but we could probably do better by gathering
1815 * more statistics from the pipeline state (e.g. guess of expected URB usage
1816 * and bound surfaces), or by using feed-back from performance counters.
1819 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1821 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1823 const struct gen_l3_weights w
=
1824 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1826 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1827 pipeline
->urb
.total_size
=
1828 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1832 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1833 struct anv_device
*device
,
1834 struct anv_pipeline_cache
*cache
,
1835 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1836 const VkAllocationCallbacks
*alloc
)
1840 anv_pipeline_validate_create_info(pCreateInfo
);
1843 alloc
= &device
->alloc
;
1845 pipeline
->device
= device
;
1847 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1848 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1849 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1851 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1852 if (result
!= VK_SUCCESS
)
1855 pipeline
->batch
.alloc
= alloc
;
1856 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1857 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1858 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1859 pipeline
->batch
.status
= VK_SUCCESS
;
1861 pipeline
->mem_ctx
= ralloc_context(NULL
);
1862 pipeline
->flags
= pCreateInfo
->flags
;
1864 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1865 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1866 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1868 /* Previously we enabled depth clipping when !depthClampEnable.
1869 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1870 * clipping info is available, use its enable value to determine clipping,
1871 * otherwise fallback to the previous !depthClampEnable logic.
1873 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1874 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1875 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1876 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1878 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1879 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1881 pipeline
->needs_data_cache
= false;
1883 /* When we free the pipeline, we detect stages based on the NULL status
1884 * of various prog_data pointers. Make them NULL by default.
1886 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1887 pipeline
->num_executables
= 0;
1889 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1890 if (result
!= VK_SUCCESS
) {
1891 ralloc_free(pipeline
->mem_ctx
);
1892 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1896 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1898 anv_pipeline_setup_l3_config(pipeline
, false);
1900 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1901 pCreateInfo
->pVertexInputState
;
1903 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1905 pipeline
->vb_used
= 0;
1906 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1907 const VkVertexInputAttributeDescription
*desc
=
1908 &vi_info
->pVertexAttributeDescriptions
[i
];
1910 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1911 pipeline
->vb_used
|= 1 << desc
->binding
;
1914 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1915 const VkVertexInputBindingDescription
*desc
=
1916 &vi_info
->pVertexBindingDescriptions
[i
];
1918 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1920 /* Step rate is programmed per vertex element (attribute), not
1921 * binding. Set up a map of which bindings step per instance, for
1922 * reference by vertex element setup. */
1923 switch (desc
->inputRate
) {
1925 case VK_VERTEX_INPUT_RATE_VERTEX
:
1926 pipeline
->vb
[desc
->binding
].instanced
= false;
1928 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1929 pipeline
->vb
[desc
->binding
].instanced
= true;
1933 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1936 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1937 vk_find_struct_const(vi_info
->pNext
,
1938 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1940 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1941 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1942 &vi_div_state
->pVertexBindingDivisors
[i
];
1944 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1948 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1949 * different views. If the client asks for instancing, we need to multiply
1950 * the instance divisor by the number of views ensure that we repeat the
1951 * client's per-instance data once for each view.
1953 if (pipeline
->subpass
->view_mask
) {
1954 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
1955 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
1956 if (pipeline
->vb
[vb
].instanced
)
1957 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
1961 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
1962 pCreateInfo
->pInputAssemblyState
;
1963 const VkPipelineTessellationStateCreateInfo
*tess_info
=
1964 pCreateInfo
->pTessellationState
;
1965 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
1967 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
1968 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
1970 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
1975 #define WRITE_STR(field, ...) ({ \
1976 memset(field, 0, sizeof(field)); \
1977 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
1978 assert(i > 0 && i < sizeof(field)); \
1981 VkResult
anv_GetPipelineExecutablePropertiesKHR(
1983 const VkPipelineInfoKHR
* pPipelineInfo
,
1984 uint32_t* pExecutableCount
,
1985 VkPipelineExecutablePropertiesKHR
* pProperties
)
1987 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
1988 VK_OUTARRAY_MAKE(out
, pProperties
, pExecutableCount
);
1990 for (uint32_t i
= 0; i
< pipeline
->num_executables
; i
++) {
1991 vk_outarray_append(&out
, props
) {
1992 gl_shader_stage stage
= pipeline
->executables
[i
].stage
;
1993 props
->stages
= mesa_to_vk_shader_stage(stage
);
1995 unsigned simd_width
= pipeline
->executables
[i
].stats
.dispatch_width
;
1996 if (stage
== MESA_SHADER_FRAGMENT
) {
1997 WRITE_STR(props
->name
, "%s%d %s",
1998 simd_width
? "SIMD" : "vec",
1999 simd_width
? simd_width
: 4,
2000 _mesa_shader_stage_to_string(stage
));
2002 WRITE_STR(props
->name
, "%s", _mesa_shader_stage_to_string(stage
));
2004 WRITE_STR(props
->description
, "%s%d %s shader",
2005 simd_width
? "SIMD" : "vec",
2006 simd_width
? simd_width
: 4,
2007 _mesa_shader_stage_to_string(stage
));
2009 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2010 * wants a subgroup size of 1.
2012 props
->subgroupSize
= MAX2(simd_width
, 1);
2016 return vk_outarray_status(&out
);
2019 VkResult
anv_GetPipelineExecutableStatisticsKHR(
2021 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2022 uint32_t* pStatisticCount
,
2023 VkPipelineExecutableStatisticKHR
* pStatistics
)
2025 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2026 VK_OUTARRAY_MAKE(out
, pStatistics
, pStatisticCount
);
2028 assert(pExecutableInfo
->executableIndex
< pipeline
->num_executables
);
2029 const struct anv_pipeline_executable
*exe
=
2030 &pipeline
->executables
[pExecutableInfo
->executableIndex
];
2031 const struct brw_stage_prog_data
*prog_data
=
2032 pipeline
->shaders
[exe
->stage
]->prog_data
;
2034 vk_outarray_append(&out
, stat
) {
2035 WRITE_STR(stat
->name
, "Instruction Count");
2036 WRITE_STR(stat
->description
,
2037 "Number of GEN instructions in the final generated "
2038 "shader executable.");
2039 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2040 stat
->value
.u64
= exe
->stats
.instructions
;
2043 vk_outarray_append(&out
, stat
) {
2044 WRITE_STR(stat
->name
, "Loop Count");
2045 WRITE_STR(stat
->description
,
2046 "Number of loops (not unrolled) in the final generated "
2047 "shader executable.");
2048 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2049 stat
->value
.u64
= exe
->stats
.loops
;
2052 vk_outarray_append(&out
, stat
) {
2053 WRITE_STR(stat
->name
, "Cycle Count");
2054 WRITE_STR(stat
->description
,
2055 "Estimate of the number of EU cycles required to execute "
2056 "the final generated executable. This is an estimate only "
2057 "and may vary greatly from actual run-time performance.");
2058 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2059 stat
->value
.u64
= exe
->stats
.cycles
;
2062 vk_outarray_append(&out
, stat
) {
2063 WRITE_STR(stat
->name
, "Spill Count");
2064 WRITE_STR(stat
->description
,
2065 "Number of scratch spill operations. This gives a rough "
2066 "estimate of the cost incurred due to spilling temporary "
2067 "values to memory. If this is non-zero, you may want to "
2068 "adjust your shader to reduce register pressure.");
2069 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2070 stat
->value
.u64
= exe
->stats
.spills
;
2073 vk_outarray_append(&out
, stat
) {
2074 WRITE_STR(stat
->name
, "Fill Count");
2075 WRITE_STR(stat
->description
,
2076 "Number of scratch fill operations. This gives a rough "
2077 "estimate of the cost incurred due to spilling temporary "
2078 "values to memory. If this is non-zero, you may want to "
2079 "adjust your shader to reduce register pressure.");
2080 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2081 stat
->value
.u64
= exe
->stats
.fills
;
2084 vk_outarray_append(&out
, stat
) {
2085 WRITE_STR(stat
->name
, "Scratch Memory Size");
2086 WRITE_STR(stat
->description
,
2087 "Number of bytes of scratch memory required by the "
2088 "generated shader executable. If this is non-zero, you "
2089 "may want to adjust your shader to reduce register "
2091 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2092 stat
->value
.u64
= prog_data
->total_scratch
;
2095 if (exe
->stage
== MESA_SHADER_COMPUTE
) {
2096 vk_outarray_append(&out
, stat
) {
2097 WRITE_STR(stat
->name
, "Workgroup Memory Size");
2098 WRITE_STR(stat
->description
,
2099 "Number of bytes of workgroup shared memory used by this "
2100 "compute shader including any padding.");
2101 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2102 stat
->value
.u64
= prog_data
->total_scratch
;
2106 return vk_outarray_status(&out
);
2110 write_ir_text(VkPipelineExecutableInternalRepresentationKHR
* ir
,
2113 ir
->isText
= VK_TRUE
;
2115 size_t data_len
= strlen(data
) + 1;
2117 if (ir
->pData
== NULL
) {
2118 ir
->dataSize
= data_len
;
2122 strncpy(ir
->pData
, data
, ir
->dataSize
);
2123 if (ir
->dataSize
< data_len
)
2126 ir
->dataSize
= data_len
;
2130 VkResult
anv_GetPipelineExecutableInternalRepresentationsKHR(
2132 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2133 uint32_t* pInternalRepresentationCount
,
2134 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
2136 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2137 VK_OUTARRAY_MAKE(out
, pInternalRepresentations
,
2138 pInternalRepresentationCount
);
2139 bool incomplete_text
= false;
2141 assert(pExecutableInfo
->executableIndex
< pipeline
->num_executables
);
2142 const struct anv_pipeline_executable
*exe
=
2143 &pipeline
->executables
[pExecutableInfo
->executableIndex
];
2146 vk_outarray_append(&out
, ir
) {
2147 WRITE_STR(ir
->name
, "Final NIR");
2148 WRITE_STR(ir
->description
,
2149 "Final NIR before going into the back-end compiler");
2151 if (!write_ir_text(ir
, exe
->nir
))
2152 incomplete_text
= true;
2157 vk_outarray_append(&out
, ir
) {
2158 WRITE_STR(ir
->name
, "GEN Assembly");
2159 WRITE_STR(ir
->description
,
2160 "Final GEN assembly for the generated shader binary");
2162 if (!write_ir_text(ir
, exe
->disasm
))
2163 incomplete_text
= true;
2167 return incomplete_text
? VK_INCOMPLETE
: vk_outarray_status(&out
);