2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "util/mesa-sha1.h"
31 #include "util/os_time.h"
32 #include "common/gen_l3_config.h"
33 #include "common/gen_disasm.h"
34 #include "anv_private.h"
35 #include "compiler/brw_nir.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 /* Needed for SWIZZLE macros */
42 #include "program/prog_instruction.h"
46 VkResult
anv_CreateShaderModule(
48 const VkShaderModuleCreateInfo
* pCreateInfo
,
49 const VkAllocationCallbacks
* pAllocator
,
50 VkShaderModule
* pShaderModule
)
52 ANV_FROM_HANDLE(anv_device
, device
, _device
);
53 struct anv_shader_module
*module
;
55 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
56 assert(pCreateInfo
->flags
== 0);
58 module
= vk_alloc2(&device
->alloc
, pAllocator
,
59 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
60 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
62 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
64 module
->size
= pCreateInfo
->codeSize
;
65 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
67 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
69 *pShaderModule
= anv_shader_module_to_handle(module
);
74 void anv_DestroyShaderModule(
76 VkShaderModule _module
,
77 const VkAllocationCallbacks
* pAllocator
)
79 ANV_FROM_HANDLE(anv_device
, device
, _device
);
80 ANV_FROM_HANDLE(anv_shader_module
, module
, _module
);
85 vk_free2(&device
->alloc
, pAllocator
, module
);
88 #define SPIR_V_MAGIC_NUMBER 0x07230203
90 static const uint64_t stage_to_debug
[] = {
91 [MESA_SHADER_VERTEX
] = DEBUG_VS
,
92 [MESA_SHADER_TESS_CTRL
] = DEBUG_TCS
,
93 [MESA_SHADER_TESS_EVAL
] = DEBUG_TES
,
94 [MESA_SHADER_GEOMETRY
] = DEBUG_GS
,
95 [MESA_SHADER_FRAGMENT
] = DEBUG_WM
,
96 [MESA_SHADER_COMPUTE
] = DEBUG_CS
,
99 struct anv_spirv_debug_data
{
100 struct anv_device
*device
;
101 const struct anv_shader_module
*module
;
104 static void anv_spirv_nir_debug(void *private_data
,
105 enum nir_spirv_debug_level level
,
109 struct anv_spirv_debug_data
*debug_data
= private_data
;
110 static const VkDebugReportFlagsEXT vk_flags
[] = {
111 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
112 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
113 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
117 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset
, message
);
119 vk_debug_report(&debug_data
->device
->instance
->debug_report_callbacks
,
121 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
122 (uint64_t) (uintptr_t) debug_data
->module
,
123 0, 0, "anv", buffer
);
126 /* Eventually, this will become part of anv_CreateShader. Unfortunately,
127 * we can't do that yet because we don't have the ability to copy nir.
130 anv_shader_compile_to_nir(struct anv_device
*device
,
132 const struct anv_shader_module
*module
,
133 const char *entrypoint_name
,
134 gl_shader_stage stage
,
135 const VkSpecializationInfo
*spec_info
)
137 const struct anv_physical_device
*pdevice
=
138 &device
->instance
->physicalDevice
;
139 const struct brw_compiler
*compiler
= pdevice
->compiler
;
140 const nir_shader_compiler_options
*nir_options
=
141 compiler
->glsl_compiler_options
[stage
].NirOptions
;
143 uint32_t *spirv
= (uint32_t *) module
->data
;
144 assert(spirv
[0] == SPIR_V_MAGIC_NUMBER
);
145 assert(module
->size
% 4 == 0);
147 uint32_t num_spec_entries
= 0;
148 struct nir_spirv_specialization
*spec_entries
= NULL
;
149 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
150 num_spec_entries
= spec_info
->mapEntryCount
;
151 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
152 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
153 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
154 const void *data
= spec_info
->pData
+ entry
.offset
;
155 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
157 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
158 if (spec_info
->dataSize
== 8)
159 spec_entries
[i
].data64
= *(const uint64_t *)data
;
161 spec_entries
[i
].data32
= *(const uint32_t *)data
;
165 struct anv_spirv_debug_data spirv_debug_data
= {
169 struct spirv_to_nir_options spirv_options
= {
170 .frag_coord_is_sysval
= true,
171 .use_scoped_memory_barrier
= true,
173 .demote_to_helper_invocation
= true,
174 .derivative_group
= true,
175 .descriptor_array_dynamic_indexing
= true,
176 .descriptor_array_non_uniform_indexing
= true,
177 .descriptor_indexing
= true,
178 .device_group
= true,
179 .draw_parameters
= true,
180 .float16
= pdevice
->info
.gen
>= 8,
181 .float64
= pdevice
->info
.gen
>= 8,
182 .fragment_shader_sample_interlock
= pdevice
->info
.gen
>= 9,
183 .fragment_shader_pixel_interlock
= pdevice
->info
.gen
>= 9,
184 .geometry_streams
= true,
185 .image_write_without_format
= true,
186 .int8
= pdevice
->info
.gen
>= 8,
187 .int16
= pdevice
->info
.gen
>= 8,
188 .int64
= pdevice
->info
.gen
>= 8,
189 .int64_atomics
= pdevice
->info
.gen
>= 9 && pdevice
->use_softpin
,
192 .physical_storage_buffer_address
= pdevice
->has_a64_buffer_access
,
193 .post_depth_coverage
= pdevice
->info
.gen
>= 9,
194 .runtime_descriptor_array
= true,
195 .float_controls
= pdevice
->info
.gen
>= 8,
196 .shader_clock
= true,
197 .shader_viewport_index_layer
= true,
198 .stencil_export
= pdevice
->info
.gen
>= 9,
199 .storage_8bit
= pdevice
->info
.gen
>= 8,
200 .storage_16bit
= pdevice
->info
.gen
>= 8,
201 .subgroup_arithmetic
= true,
202 .subgroup_basic
= true,
203 .subgroup_ballot
= true,
204 .subgroup_quad
= true,
205 .subgroup_shuffle
= true,
206 .subgroup_vote
= true,
207 .tessellation
= true,
208 .transform_feedback
= pdevice
->info
.gen
>= 8,
209 .variable_pointers
= true,
210 .vk_memory_model
= true,
211 .vk_memory_model_device_scope
= true,
213 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
215 anv_nir_ssbo_addr_format(pdevice
, device
->robust_buffer_access
),
216 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
217 .push_const_addr_format
= nir_address_format_logical
,
219 /* TODO: Consider changing this to an address format that has the NULL
220 * pointer equals to 0. That might be a better format to play nice
221 * with certain code / code generators.
223 .shared_addr_format
= nir_address_format_32bit_offset
,
225 .func
= anv_spirv_nir_debug
,
226 .private_data
= &spirv_debug_data
,
232 spirv_to_nir(spirv
, module
->size
/ 4,
233 spec_entries
, num_spec_entries
,
234 stage
, entrypoint_name
, &spirv_options
, nir_options
);
235 assert(nir
->info
.stage
== stage
);
236 nir_validate_shader(nir
, "after spirv_to_nir");
237 ralloc_steal(mem_ctx
, nir
);
241 if (unlikely(INTEL_DEBUG
& stage_to_debug
[stage
])) {
242 fprintf(stderr
, "NIR (from SPIR-V) for %s shader:\n",
243 gl_shader_stage_name(stage
));
244 nir_print_shader(nir
, stderr
);
247 /* We have to lower away local constant initializers right before we
248 * inline functions. That way they get properly initialized at the top
249 * of the function and not at the top of its caller.
251 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
252 NIR_PASS_V(nir
, nir_lower_returns
);
253 NIR_PASS_V(nir
, nir_inline_functions
);
254 NIR_PASS_V(nir
, nir_opt_deref
);
256 /* Pick off the single entrypoint that we want */
257 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
258 if (!func
->is_entrypoint
)
259 exec_node_remove(&func
->node
);
261 assert(exec_list_length(&nir
->functions
) == 1);
263 /* Now that we've deleted all but the main function, we can go ahead and
264 * lower the rest of the constant initializers. We do this here so that
265 * nir_remove_dead_variables and split_per_member_structs below see the
266 * corresponding stores.
268 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
270 /* Split member structs. We do this before lower_io_to_temporaries so that
271 * it doesn't lower system values to temporaries by accident.
273 NIR_PASS_V(nir
, nir_split_var_copies
);
274 NIR_PASS_V(nir
, nir_split_per_member_structs
);
276 NIR_PASS_V(nir
, nir_remove_dead_variables
,
277 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
279 NIR_PASS_V(nir
, nir_propagate_invariant
);
280 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
281 nir_shader_get_entrypoint(nir
), true, false);
283 NIR_PASS_V(nir
, nir_lower_frexp
);
285 /* Vulkan uses the separate-shader linking model */
286 nir
->info
.separate_shader
= true;
288 brw_preprocess_nir(compiler
, nir
, NULL
);
293 void anv_DestroyPipeline(
295 VkPipeline _pipeline
,
296 const VkAllocationCallbacks
* pAllocator
)
298 ANV_FROM_HANDLE(anv_device
, device
, _device
);
299 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
304 anv_reloc_list_finish(&pipeline
->batch_relocs
,
305 pAllocator
? pAllocator
: &device
->alloc
);
307 ralloc_free(pipeline
->mem_ctx
);
309 if (pipeline
->blend_state
.map
)
310 anv_state_pool_free(&device
->dynamic_state_pool
, pipeline
->blend_state
);
312 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
313 if (pipeline
->shaders
[s
])
314 anv_shader_bin_unref(device
, pipeline
->shaders
[s
]);
317 vk_free2(&device
->alloc
, pAllocator
, pipeline
);
320 static const uint32_t vk_to_gen_primitive_type
[] = {
321 [VK_PRIMITIVE_TOPOLOGY_POINT_LIST
] = _3DPRIM_POINTLIST
,
322 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST
] = _3DPRIM_LINELIST
,
323 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
] = _3DPRIM_LINESTRIP
,
324 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
] = _3DPRIM_TRILIST
,
325 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
] = _3DPRIM_TRISTRIP
,
326 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
] = _3DPRIM_TRIFAN
,
327 [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
] = _3DPRIM_LINELIST_ADJ
,
328 [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
] = _3DPRIM_LINESTRIP_ADJ
,
329 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
] = _3DPRIM_TRILIST_ADJ
,
330 [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
] = _3DPRIM_TRISTRIP_ADJ
,
334 populate_sampler_prog_key(const struct gen_device_info
*devinfo
,
335 struct brw_sampler_prog_key_data
*key
)
337 /* Almost all multisampled textures are compressed. The only time when we
338 * don't compress a multisampled texture is for 16x MSAA with a surface
339 * width greater than 8k which is a bit of an edge case. Since the sampler
340 * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
341 * to tell the compiler to always assume compression.
343 key
->compressed_multisample_layout_mask
= ~0;
345 /* SkyLake added support for 16x MSAA. With this came a new message for
346 * reading from a 16x MSAA surface with compression. The new message was
347 * needed because now the MCS data is 64 bits instead of 32 or lower as is
348 * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
349 * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
350 * so we can just use it unconditionally. This may not be quite as
351 * efficient but it saves us from recompiling.
353 if (devinfo
->gen
>= 9)
356 /* XXX: Handle texture swizzle on HSW- */
357 for (int i
= 0; i
< MAX_SAMPLERS
; i
++) {
358 /* Assume color sampler, no swizzling. (Works for BDW+) */
359 key
->swizzles
[i
] = SWIZZLE_XYZW
;
364 populate_base_prog_key(const struct gen_device_info
*devinfo
,
365 VkPipelineShaderStageCreateFlags flags
,
366 struct brw_base_prog_key
*key
)
368 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
369 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_VARYING
;
371 key
->subgroup_size_type
= BRW_SUBGROUP_SIZE_API_CONSTANT
;
373 populate_sampler_prog_key(devinfo
, &key
->tex
);
377 populate_vs_prog_key(const struct gen_device_info
*devinfo
,
378 VkPipelineShaderStageCreateFlags flags
,
379 struct brw_vs_prog_key
*key
)
381 memset(key
, 0, sizeof(*key
));
383 populate_base_prog_key(devinfo
, flags
, &key
->base
);
385 /* XXX: Handle vertex input work-arounds */
387 /* XXX: Handle sampler_prog_key */
391 populate_tcs_prog_key(const struct gen_device_info
*devinfo
,
392 VkPipelineShaderStageCreateFlags flags
,
393 unsigned input_vertices
,
394 struct brw_tcs_prog_key
*key
)
396 memset(key
, 0, sizeof(*key
));
398 populate_base_prog_key(devinfo
, flags
, &key
->base
);
400 key
->input_vertices
= input_vertices
;
404 populate_tes_prog_key(const struct gen_device_info
*devinfo
,
405 VkPipelineShaderStageCreateFlags flags
,
406 struct brw_tes_prog_key
*key
)
408 memset(key
, 0, sizeof(*key
));
410 populate_base_prog_key(devinfo
, flags
, &key
->base
);
414 populate_gs_prog_key(const struct gen_device_info
*devinfo
,
415 VkPipelineShaderStageCreateFlags flags
,
416 struct brw_gs_prog_key
*key
)
418 memset(key
, 0, sizeof(*key
));
420 populate_base_prog_key(devinfo
, flags
, &key
->base
);
424 populate_wm_prog_key(const struct gen_device_info
*devinfo
,
425 VkPipelineShaderStageCreateFlags flags
,
426 const struct anv_subpass
*subpass
,
427 const VkPipelineMultisampleStateCreateInfo
*ms_info
,
428 struct brw_wm_prog_key
*key
)
430 memset(key
, 0, sizeof(*key
));
432 populate_base_prog_key(devinfo
, flags
, &key
->base
);
434 /* We set this to 0 here and set to the actual value before we call
437 key
->input_slots_valid
= 0;
439 /* Vulkan doesn't specify a default */
440 key
->high_quality_derivatives
= false;
442 /* XXX Vulkan doesn't appear to specify */
443 key
->clamp_fragment_color
= false;
445 assert(subpass
->color_count
<= MAX_RTS
);
446 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
447 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
448 key
->color_outputs_valid
|= (1 << i
);
451 key
->nr_color_regions
= util_bitcount(key
->color_outputs_valid
);
453 /* To reduce possible shader recompilations we would need to know if
454 * there is a SampleMask output variable to compute if we should emit
455 * code to workaround the issue that hardware disables alpha to coverage
456 * when there is SampleMask output.
458 key
->alpha_to_coverage
= ms_info
&& ms_info
->alphaToCoverageEnable
;
460 /* Vulkan doesn't support fixed-function alpha test */
461 key
->alpha_test_replicate_alpha
= false;
464 /* We should probably pull this out of the shader, but it's fairly
465 * harmless to compute it and then let dead-code take care of it.
467 if (ms_info
->rasterizationSamples
> 1) {
468 key
->persample_interp
= ms_info
->sampleShadingEnable
&&
469 (ms_info
->minSampleShading
* ms_info
->rasterizationSamples
) > 1;
470 key
->multisample_fbo
= true;
473 key
->frag_coord_adds_sample_pos
= key
->persample_interp
;
478 populate_cs_prog_key(const struct gen_device_info
*devinfo
,
479 VkPipelineShaderStageCreateFlags flags
,
480 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
,
481 struct brw_cs_prog_key
*key
)
483 memset(key
, 0, sizeof(*key
));
485 populate_base_prog_key(devinfo
, flags
, &key
->base
);
488 assert(key
->base
.subgroup_size_type
!= BRW_SUBGROUP_SIZE_VARYING
);
490 /* These enum values are expressly chosen to be equal to the subgroup
491 * size that they require.
493 assert(rss_info
->requiredSubgroupSize
== 8 ||
494 rss_info
->requiredSubgroupSize
== 16 ||
495 rss_info
->requiredSubgroupSize
== 32);
496 key
->base
.subgroup_size_type
= rss_info
->requiredSubgroupSize
;
497 } else if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT_EXT
) {
498 /* If the client expressly requests full subgroups and they don't
499 * specify a subgroup size, we need to pick one. If they're requested
500 * varying subgroup sizes, we set it to UNIFORM and let the back-end
501 * compiler pick. Otherwise, we specify the API value of 32.
502 * Performance will likely be terrible in this case but there's nothing
503 * we can do about that. The client should have chosen a size.
505 if (flags
& VK_PIPELINE_SHADER_STAGE_CREATE_ALLOW_VARYING_SUBGROUP_SIZE_BIT_EXT
)
506 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_UNIFORM
;
508 key
->base
.subgroup_size_type
= BRW_SUBGROUP_SIZE_REQUIRE_32
;
512 struct anv_pipeline_stage
{
513 gl_shader_stage stage
;
515 const struct anv_shader_module
*module
;
516 const char *entrypoint
;
517 const VkSpecializationInfo
*spec_info
;
519 unsigned char shader_sha1
[20];
521 union brw_any_prog_key key
;
524 gl_shader_stage stage
;
525 unsigned char sha1
[20];
530 struct anv_pipeline_binding surface_to_descriptor
[256];
531 struct anv_pipeline_binding sampler_to_descriptor
[256];
532 struct anv_pipeline_bind_map bind_map
;
534 union brw_any_prog_data prog_data
;
537 struct brw_compile_stats stats
[3];
540 VkPipelineCreationFeedbackEXT feedback
;
542 const unsigned *code
;
546 anv_pipeline_hash_shader(const struct anv_shader_module
*module
,
547 const char *entrypoint
,
548 gl_shader_stage stage
,
549 const VkSpecializationInfo
*spec_info
,
550 unsigned char *sha1_out
)
552 struct mesa_sha1 ctx
;
553 _mesa_sha1_init(&ctx
);
555 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
556 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
557 _mesa_sha1_update(&ctx
, &stage
, sizeof(stage
));
559 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
560 spec_info
->mapEntryCount
*
561 sizeof(*spec_info
->pMapEntries
));
562 _mesa_sha1_update(&ctx
, spec_info
->pData
,
563 spec_info
->dataSize
);
566 _mesa_sha1_final(&ctx
, sha1_out
);
570 anv_pipeline_hash_graphics(struct anv_pipeline
*pipeline
,
571 struct anv_pipeline_layout
*layout
,
572 struct anv_pipeline_stage
*stages
,
573 unsigned char *sha1_out
)
575 struct mesa_sha1 ctx
;
576 _mesa_sha1_init(&ctx
);
578 _mesa_sha1_update(&ctx
, &pipeline
->subpass
->view_mask
,
579 sizeof(pipeline
->subpass
->view_mask
));
582 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
584 const bool rba
= pipeline
->device
->robust_buffer_access
;
585 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
587 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
588 if (stages
[s
].entrypoint
) {
589 _mesa_sha1_update(&ctx
, stages
[s
].shader_sha1
,
590 sizeof(stages
[s
].shader_sha1
));
591 _mesa_sha1_update(&ctx
, &stages
[s
].key
, brw_prog_key_size(s
));
595 _mesa_sha1_final(&ctx
, sha1_out
);
599 anv_pipeline_hash_compute(struct anv_pipeline
*pipeline
,
600 struct anv_pipeline_layout
*layout
,
601 struct anv_pipeline_stage
*stage
,
602 unsigned char *sha1_out
)
604 struct mesa_sha1 ctx
;
605 _mesa_sha1_init(&ctx
);
608 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
610 const bool rba
= pipeline
->device
->robust_buffer_access
;
611 _mesa_sha1_update(&ctx
, &rba
, sizeof(rba
));
613 _mesa_sha1_update(&ctx
, stage
->shader_sha1
,
614 sizeof(stage
->shader_sha1
));
615 _mesa_sha1_update(&ctx
, &stage
->key
.cs
, sizeof(stage
->key
.cs
));
617 _mesa_sha1_final(&ctx
, sha1_out
);
621 anv_pipeline_stage_get_nir(struct anv_pipeline
*pipeline
,
622 struct anv_pipeline_cache
*cache
,
624 struct anv_pipeline_stage
*stage
)
626 const struct brw_compiler
*compiler
=
627 pipeline
->device
->instance
->physicalDevice
.compiler
;
628 const nir_shader_compiler_options
*nir_options
=
629 compiler
->glsl_compiler_options
[stage
->stage
].NirOptions
;
632 nir
= anv_device_search_for_nir(pipeline
->device
, cache
,
637 assert(nir
->info
.stage
== stage
->stage
);
641 nir
= anv_shader_compile_to_nir(pipeline
->device
,
648 anv_device_upload_nir(pipeline
->device
, cache
, nir
, stage
->shader_sha1
);
656 anv_pipeline_lower_nir(struct anv_pipeline
*pipeline
,
658 struct anv_pipeline_stage
*stage
,
659 struct anv_pipeline_layout
*layout
)
661 const struct anv_physical_device
*pdevice
=
662 &pipeline
->device
->instance
->physicalDevice
;
663 const struct brw_compiler
*compiler
= pdevice
->compiler
;
665 struct brw_stage_prog_data
*prog_data
= &stage
->prog_data
.base
;
666 nir_shader
*nir
= stage
->nir
;
668 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
669 NIR_PASS_V(nir
, nir_lower_wpos_center
, pipeline
->sample_shading_enable
);
670 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
673 NIR_PASS_V(nir
, anv_nir_lower_ycbcr_textures
, layout
);
675 NIR_PASS_V(nir
, anv_nir_lower_push_constants
);
677 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
678 NIR_PASS_V(nir
, anv_nir_lower_multiview
, pipeline
->subpass
->view_mask
);
680 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
682 if (nir
->num_uniforms
> 0) {
683 assert(prog_data
->nr_params
== 0);
685 /* If the shader uses any push constants at all, we'll just give
686 * them the maximum possible number
688 assert(nir
->num_uniforms
<= MAX_PUSH_CONSTANTS_SIZE
);
689 nir
->num_uniforms
= MAX_PUSH_CONSTANTS_SIZE
;
690 prog_data
->nr_params
+= MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float);
691 prog_data
->param
= ralloc_array(mem_ctx
, uint32_t, prog_data
->nr_params
);
693 /* We now set the param values to be offsets into a
694 * anv_push_constant_data structure. Since the compiler doesn't
695 * actually dereference any of the gl_constant_value pointers in the
696 * params array, it doesn't really matter what we put here.
698 struct anv_push_constants
*null_data
= NULL
;
699 /* Fill out the push constants section of the param array */
700 for (unsigned i
= 0; i
< MAX_PUSH_CONSTANTS_SIZE
/ sizeof(float); i
++) {
701 prog_data
->param
[i
] = ANV_PARAM_PUSH(
702 (uintptr_t)&null_data
->client_data
[i
* sizeof(float)]);
706 if (nir
->info
.num_ssbos
> 0 || nir
->info
.num_images
> 0)
707 pipeline
->needs_data_cache
= true;
709 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, compiler
->devinfo
);
711 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_global
,
712 nir_address_format_64bit_global
);
714 /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
716 anv_nir_apply_pipeline_layout(pdevice
,
717 pipeline
->device
->robust_buffer_access
,
718 layout
, nir
, prog_data
,
721 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ubo
,
722 nir_address_format_32bit_index_offset
);
723 NIR_PASS_V(nir
, nir_lower_explicit_io
, nir_var_mem_ssbo
,
724 anv_nir_ssbo_addr_format(pdevice
,
725 pipeline
->device
->robust_buffer_access
));
727 NIR_PASS_V(nir
, nir_opt_constant_folding
);
729 /* We don't support non-uniform UBOs and non-uniform SSBO access is
730 * handled naturally by falling back to A64 messages.
732 NIR_PASS_V(nir
, nir_lower_non_uniform_access
,
733 nir_lower_non_uniform_texture_access
|
734 nir_lower_non_uniform_image_access
);
737 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
738 brw_nir_analyze_ubo_ranges(compiler
, nir
, NULL
, prog_data
->ubo_ranges
);
740 assert(nir
->num_uniforms
== prog_data
->nr_params
* 4);
746 anv_pipeline_link_vs(const struct brw_compiler
*compiler
,
747 struct anv_pipeline_stage
*vs_stage
,
748 struct anv_pipeline_stage
*next_stage
)
751 brw_nir_link_shaders(compiler
, vs_stage
->nir
, next_stage
->nir
);
755 anv_pipeline_compile_vs(const struct brw_compiler
*compiler
,
757 struct anv_device
*device
,
758 struct anv_pipeline_stage
*vs_stage
)
760 brw_compute_vue_map(compiler
->devinfo
,
761 &vs_stage
->prog_data
.vs
.base
.vue_map
,
762 vs_stage
->nir
->info
.outputs_written
,
763 vs_stage
->nir
->info
.separate_shader
);
765 vs_stage
->num_stats
= 1;
766 vs_stage
->code
= brw_compile_vs(compiler
, device
, mem_ctx
,
768 &vs_stage
->prog_data
.vs
,
770 vs_stage
->stats
, NULL
);
774 merge_tess_info(struct shader_info
*tes_info
,
775 const struct shader_info
*tcs_info
)
777 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
779 * "PointMode. Controls generation of points rather than triangles
780 * or lines. This functionality defaults to disabled, and is
781 * enabled if either shader stage includes the execution mode.
783 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
784 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
785 * and OutputVertices, it says:
787 * "One mode must be set in at least one of the tessellation
790 * So, the fields can be set in either the TCS or TES, but they must
791 * agree if set in both. Our backend looks at TES, so bitwise-or in
792 * the values from the TCS.
794 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
795 tes_info
->tess
.tcs_vertices_out
== 0 ||
796 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
797 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
799 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
800 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
801 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
802 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
804 assert(tcs_info
->tess
.primitive_mode
== 0 ||
805 tes_info
->tess
.primitive_mode
== 0 ||
806 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
807 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
808 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
809 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
813 anv_pipeline_link_tcs(const struct brw_compiler
*compiler
,
814 struct anv_pipeline_stage
*tcs_stage
,
815 struct anv_pipeline_stage
*tes_stage
)
817 assert(tes_stage
&& tes_stage
->stage
== MESA_SHADER_TESS_EVAL
);
819 brw_nir_link_shaders(compiler
, tcs_stage
->nir
, tes_stage
->nir
);
821 nir_lower_patch_vertices(tes_stage
->nir
,
822 tcs_stage
->nir
->info
.tess
.tcs_vertices_out
,
825 /* Copy TCS info into the TES info */
826 merge_tess_info(&tes_stage
->nir
->info
, &tcs_stage
->nir
->info
);
828 /* Whacking the key after cache lookup is a bit sketchy, but all of
829 * this comes from the SPIR-V, which is part of the hash used for the
830 * pipeline cache. So it should be safe.
832 tcs_stage
->key
.tcs
.tes_primitive_mode
=
833 tes_stage
->nir
->info
.tess
.primitive_mode
;
834 tcs_stage
->key
.tcs
.quads_workaround
=
835 compiler
->devinfo
->gen
< 9 &&
836 tes_stage
->nir
->info
.tess
.primitive_mode
== 7 /* GL_QUADS */ &&
837 tes_stage
->nir
->info
.tess
.spacing
== TESS_SPACING_EQUAL
;
841 anv_pipeline_compile_tcs(const struct brw_compiler
*compiler
,
843 struct anv_device
*device
,
844 struct anv_pipeline_stage
*tcs_stage
,
845 struct anv_pipeline_stage
*prev_stage
)
847 tcs_stage
->key
.tcs
.outputs_written
=
848 tcs_stage
->nir
->info
.outputs_written
;
849 tcs_stage
->key
.tcs
.patch_outputs_written
=
850 tcs_stage
->nir
->info
.patch_outputs_written
;
852 tcs_stage
->num_stats
= 1;
853 tcs_stage
->code
= brw_compile_tcs(compiler
, device
, mem_ctx
,
855 &tcs_stage
->prog_data
.tcs
,
857 tcs_stage
->stats
, NULL
);
861 anv_pipeline_link_tes(const struct brw_compiler
*compiler
,
862 struct anv_pipeline_stage
*tes_stage
,
863 struct anv_pipeline_stage
*next_stage
)
866 brw_nir_link_shaders(compiler
, tes_stage
->nir
, next_stage
->nir
);
870 anv_pipeline_compile_tes(const struct brw_compiler
*compiler
,
872 struct anv_device
*device
,
873 struct anv_pipeline_stage
*tes_stage
,
874 struct anv_pipeline_stage
*tcs_stage
)
876 tes_stage
->key
.tes
.inputs_read
=
877 tcs_stage
->nir
->info
.outputs_written
;
878 tes_stage
->key
.tes
.patch_inputs_read
=
879 tcs_stage
->nir
->info
.patch_outputs_written
;
881 tes_stage
->num_stats
= 1;
882 tes_stage
->code
= brw_compile_tes(compiler
, device
, mem_ctx
,
884 &tcs_stage
->prog_data
.tcs
.base
.vue_map
,
885 &tes_stage
->prog_data
.tes
,
887 tes_stage
->stats
, NULL
);
891 anv_pipeline_link_gs(const struct brw_compiler
*compiler
,
892 struct anv_pipeline_stage
*gs_stage
,
893 struct anv_pipeline_stage
*next_stage
)
896 brw_nir_link_shaders(compiler
, gs_stage
->nir
, next_stage
->nir
);
900 anv_pipeline_compile_gs(const struct brw_compiler
*compiler
,
902 struct anv_device
*device
,
903 struct anv_pipeline_stage
*gs_stage
,
904 struct anv_pipeline_stage
*prev_stage
)
906 brw_compute_vue_map(compiler
->devinfo
,
907 &gs_stage
->prog_data
.gs
.base
.vue_map
,
908 gs_stage
->nir
->info
.outputs_written
,
909 gs_stage
->nir
->info
.separate_shader
);
911 gs_stage
->num_stats
= 1;
912 gs_stage
->code
= brw_compile_gs(compiler
, device
, mem_ctx
,
914 &gs_stage
->prog_data
.gs
,
915 gs_stage
->nir
, NULL
, -1,
916 gs_stage
->stats
, NULL
);
920 anv_pipeline_link_fs(const struct brw_compiler
*compiler
,
921 struct anv_pipeline_stage
*stage
)
923 unsigned num_rts
= 0;
924 const int max_rt
= FRAG_RESULT_DATA7
- FRAG_RESULT_DATA0
+ 1;
925 struct anv_pipeline_binding rt_bindings
[max_rt
];
926 nir_function_impl
*impl
= nir_shader_get_entrypoint(stage
->nir
);
927 int rt_to_bindings
[max_rt
];
928 memset(rt_to_bindings
, -1, sizeof(rt_to_bindings
));
929 bool rt_used
[max_rt
];
930 memset(rt_used
, 0, sizeof(rt_used
));
932 /* Flag used render targets */
933 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
934 if (var
->data
.location
< FRAG_RESULT_DATA0
)
937 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
942 const unsigned array_len
=
943 glsl_type_is_array(var
->type
) ? glsl_get_length(var
->type
) : 1;
944 assert(rt
+ array_len
<= max_rt
);
947 if (!(stage
->key
.wm
.color_outputs_valid
& BITFIELD_RANGE(rt
, array_len
))) {
948 /* If this is the RT at location 0 and we have alpha to coverage
949 * enabled we will have to create a null RT for it, so mark it as
952 if (rt
> 0 || !stage
->key
.wm
.alpha_to_coverage
)
956 for (unsigned i
= 0; i
< array_len
; i
++)
957 rt_used
[rt
+ i
] = true;
960 /* Set new, compacted, location */
961 for (unsigned i
= 0; i
< max_rt
; i
++) {
965 rt_to_bindings
[i
] = num_rts
;
967 if (stage
->key
.wm
.color_outputs_valid
& (1 << i
)) {
968 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
969 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
974 /* Setup a null render target */
975 rt_bindings
[rt_to_bindings
[i
]] = (struct anv_pipeline_binding
) {
976 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
985 bool deleted_output
= false;
986 nir_foreach_variable_safe(var
, &stage
->nir
->outputs
) {
987 if (var
->data
.location
< FRAG_RESULT_DATA0
)
990 const unsigned rt
= var
->data
.location
- FRAG_RESULT_DATA0
;
992 if (rt
>= MAX_RTS
|| !rt_used
[rt
]) {
993 /* Unused or out-of-bounds, throw it away, unless it is the first
994 * RT and we have alpha to coverage enabled.
996 deleted_output
= true;
997 var
->data
.mode
= nir_var_function_temp
;
998 exec_node_remove(&var
->node
);
999 exec_list_push_tail(&impl
->locals
, &var
->node
);
1003 /* Give it the new location */
1004 assert(rt_to_bindings
[rt
] != -1);
1005 var
->data
.location
= rt_to_bindings
[rt
] + FRAG_RESULT_DATA0
;
1009 nir_fixup_deref_modes(stage
->nir
);
1011 /* Now that we've determined the actual number of render targets, adjust
1012 * the key accordingly.
1014 stage
->key
.wm
.nr_color_regions
= num_rts
;
1015 stage
->key
.wm
.color_outputs_valid
= (1 << num_rts
) - 1;
1018 /* If we have no render targets, we need a null render target */
1019 rt_bindings
[0] = (struct anv_pipeline_binding
) {
1020 .set
= ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
,
1022 .index
= UINT32_MAX
,
1027 assert(num_rts
<= max_rt
);
1028 assert(stage
->bind_map
.surface_count
== 0);
1029 typed_memcpy(stage
->bind_map
.surface_to_descriptor
,
1030 rt_bindings
, num_rts
);
1031 stage
->bind_map
.surface_count
+= num_rts
;
1035 anv_pipeline_compile_fs(const struct brw_compiler
*compiler
,
1037 struct anv_device
*device
,
1038 struct anv_pipeline_stage
*fs_stage
,
1039 struct anv_pipeline_stage
*prev_stage
)
1041 /* TODO: we could set this to 0 based on the information in nir_shader, but
1042 * we need this before we call spirv_to_nir.
1045 fs_stage
->key
.wm
.input_slots_valid
=
1046 prev_stage
->prog_data
.vue
.vue_map
.slots_valid
;
1048 fs_stage
->code
= brw_compile_fs(compiler
, device
, mem_ctx
,
1050 &fs_stage
->prog_data
.wm
,
1051 fs_stage
->nir
, -1, -1, -1,
1053 fs_stage
->stats
, NULL
);
1055 fs_stage
->num_stats
= (uint32_t)fs_stage
->prog_data
.wm
.dispatch_8
+
1056 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_16
+
1057 (uint32_t)fs_stage
->prog_data
.wm
.dispatch_32
;
1059 if (fs_stage
->key
.wm
.color_outputs_valid
== 0 &&
1060 !fs_stage
->prog_data
.wm
.has_side_effects
&&
1061 !fs_stage
->prog_data
.wm
.uses_omask
&&
1062 !fs_stage
->key
.wm
.alpha_to_coverage
&&
1063 !fs_stage
->prog_data
.wm
.uses_kill
&&
1064 fs_stage
->prog_data
.wm
.computed_depth_mode
== BRW_PSCDEPTH_OFF
&&
1065 !fs_stage
->prog_data
.wm
.computed_stencil
) {
1066 /* This fragment shader has no outputs and no side effects. Go ahead
1067 * and return the code pointer so we don't accidentally think the
1068 * compile failed but zero out prog_data which will set program_size to
1069 * zero and disable the stage.
1071 memset(&fs_stage
->prog_data
, 0, sizeof(fs_stage
->prog_data
));
1076 anv_pipeline_add_executable(struct anv_pipeline
*pipeline
,
1077 struct anv_pipeline_stage
*stage
,
1078 struct brw_compile_stats
*stats
,
1079 uint32_t code_offset
)
1084 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1085 char *stream_data
= NULL
;
1086 size_t stream_size
= 0;
1087 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1089 nir_print_shader(stage
->nir
, stream
);
1093 /* Copy it to a ralloc'd thing */
1094 nir
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1095 memcpy(nir
, stream_data
, stream_size
);
1096 nir
[stream_size
] = 0;
1101 char *disasm
= NULL
;
1104 VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
)) {
1105 char *stream_data
= NULL
;
1106 size_t stream_size
= 0;
1107 FILE *stream
= open_memstream(&stream_data
, &stream_size
);
1109 /* Creating this is far cheaper than it looks. It's perfectly fine to
1110 * do it for every binary.
1112 struct gen_disasm
*d
= gen_disasm_create(&pipeline
->device
->info
);
1113 gen_disasm_disassemble(d
, stage
->code
, code_offset
, stream
);
1114 gen_disasm_destroy(d
);
1118 /* Copy it to a ralloc'd thing */
1119 disasm
= ralloc_size(pipeline
->mem_ctx
, stream_size
+ 1);
1120 memcpy(disasm
, stream_data
, stream_size
);
1121 disasm
[stream_size
] = 0;
1126 pipeline
->executables
[pipeline
->num_executables
++] =
1127 (struct anv_pipeline_executable
) {
1128 .stage
= stage
->stage
,
1136 anv_pipeline_add_executables(struct anv_pipeline
*pipeline
,
1137 struct anv_pipeline_stage
*stage
,
1138 struct anv_shader_bin
*bin
)
1140 if (stage
->stage
== MESA_SHADER_FRAGMENT
) {
1141 /* We pull the prog data and stats out of the anv_shader_bin because
1142 * the anv_pipeline_stage may not be fully populated if we successfully
1143 * looked up the shader in a cache.
1145 const struct brw_wm_prog_data
*wm_prog_data
=
1146 (const struct brw_wm_prog_data
*)bin
->prog_data
;
1147 struct brw_compile_stats
*stats
= bin
->stats
;
1149 if (wm_prog_data
->dispatch_8
) {
1150 anv_pipeline_add_executable(pipeline
, stage
, stats
++, 0);
1153 if (wm_prog_data
->dispatch_16
) {
1154 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1155 wm_prog_data
->prog_offset_16
);
1158 if (wm_prog_data
->dispatch_32
) {
1159 anv_pipeline_add_executable(pipeline
, stage
, stats
++,
1160 wm_prog_data
->prog_offset_32
);
1163 anv_pipeline_add_executable(pipeline
, stage
, bin
->stats
, 0);
1168 anv_pipeline_compile_graphics(struct anv_pipeline
*pipeline
,
1169 struct anv_pipeline_cache
*cache
,
1170 const VkGraphicsPipelineCreateInfo
*info
)
1172 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1173 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1175 int64_t pipeline_start
= os_time_get_nano();
1177 const struct brw_compiler
*compiler
=
1178 pipeline
->device
->instance
->physicalDevice
.compiler
;
1179 struct anv_pipeline_stage stages
[MESA_SHADER_STAGES
] = {};
1181 pipeline
->active_stages
= 0;
1184 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1185 const VkPipelineShaderStageCreateInfo
*sinfo
= &info
->pStages
[i
];
1186 gl_shader_stage stage
= vk_to_mesa_shader_stage(sinfo
->stage
);
1188 pipeline
->active_stages
|= sinfo
->stage
;
1190 int64_t stage_start
= os_time_get_nano();
1192 stages
[stage
].stage
= stage
;
1193 stages
[stage
].module
= anv_shader_module_from_handle(sinfo
->module
);
1194 stages
[stage
].entrypoint
= sinfo
->pName
;
1195 stages
[stage
].spec_info
= sinfo
->pSpecializationInfo
;
1196 anv_pipeline_hash_shader(stages
[stage
].module
,
1197 stages
[stage
].entrypoint
,
1199 stages
[stage
].spec_info
,
1200 stages
[stage
].shader_sha1
);
1202 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1204 case MESA_SHADER_VERTEX
:
1205 populate_vs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.vs
);
1207 case MESA_SHADER_TESS_CTRL
:
1208 populate_tcs_prog_key(devinfo
, sinfo
->flags
,
1209 info
->pTessellationState
->patchControlPoints
,
1210 &stages
[stage
].key
.tcs
);
1212 case MESA_SHADER_TESS_EVAL
:
1213 populate_tes_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.tes
);
1215 case MESA_SHADER_GEOMETRY
:
1216 populate_gs_prog_key(devinfo
, sinfo
->flags
, &stages
[stage
].key
.gs
);
1218 case MESA_SHADER_FRAGMENT
:
1219 populate_wm_prog_key(devinfo
, sinfo
->flags
,
1221 info
->pMultisampleState
,
1222 &stages
[stage
].key
.wm
);
1225 unreachable("Invalid graphics shader stage");
1228 stages
[stage
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1229 stages
[stage
].feedback
.flags
|= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
1232 if (pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
)
1233 pipeline
->active_stages
|= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
1235 assert(pipeline
->active_stages
& VK_SHADER_STAGE_VERTEX_BIT
);
1237 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1239 unsigned char sha1
[20];
1240 anv_pipeline_hash_graphics(pipeline
, layout
, stages
, sha1
);
1242 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1243 if (!stages
[s
].entrypoint
)
1246 stages
[s
].cache_key
.stage
= s
;
1247 memcpy(stages
[s
].cache_key
.sha1
, sha1
, sizeof(sha1
));
1250 const bool skip_cache_lookup
=
1251 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1253 if (!skip_cache_lookup
) {
1255 unsigned cache_hits
= 0;
1256 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1257 if (!stages
[s
].entrypoint
)
1260 int64_t stage_start
= os_time_get_nano();
1263 struct anv_shader_bin
*bin
=
1264 anv_device_search_for_kernel(pipeline
->device
, cache
,
1265 &stages
[s
].cache_key
,
1266 sizeof(stages
[s
].cache_key
), &cache_hit
);
1269 pipeline
->shaders
[s
] = bin
;
1274 stages
[s
].feedback
.flags
|=
1275 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1277 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1280 if (found
== __builtin_popcount(pipeline
->active_stages
)) {
1281 if (cache_hits
== found
) {
1282 pipeline_feedback
.flags
|=
1283 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1285 /* We found all our shaders in the cache. We're done. */
1286 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1287 if (!stages
[s
].entrypoint
)
1290 anv_pipeline_add_executables(pipeline
, &stages
[s
],
1291 pipeline
->shaders
[s
]);
1294 } else if (found
> 0) {
1295 /* We found some but not all of our shaders. This shouldn't happen
1296 * most of the time but it can if we have a partially populated
1299 assert(found
< __builtin_popcount(pipeline
->active_stages
));
1301 vk_debug_report(&pipeline
->device
->instance
->debug_report_callbacks
,
1302 VK_DEBUG_REPORT_WARNING_BIT_EXT
|
1303 VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT
,
1304 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT
,
1305 (uint64_t)(uintptr_t)cache
,
1307 "Found a partial pipeline in the cache. This is "
1308 "most likely caused by an incomplete pipeline cache "
1309 "import or export");
1311 /* We're going to have to recompile anyway, so just throw away our
1312 * references to the shaders in the cache. We'll get them out of the
1313 * cache again as part of the compilation process.
1315 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1316 stages
[s
].feedback
.flags
= 0;
1317 if (pipeline
->shaders
[s
]) {
1318 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1319 pipeline
->shaders
[s
] = NULL
;
1325 void *pipeline_ctx
= ralloc_context(NULL
);
1327 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1328 if (!stages
[s
].entrypoint
)
1331 int64_t stage_start
= os_time_get_nano();
1333 assert(stages
[s
].stage
== s
);
1334 assert(pipeline
->shaders
[s
] == NULL
);
1336 stages
[s
].bind_map
= (struct anv_pipeline_bind_map
) {
1337 .surface_to_descriptor
= stages
[s
].surface_to_descriptor
,
1338 .sampler_to_descriptor
= stages
[s
].sampler_to_descriptor
1341 stages
[s
].nir
= anv_pipeline_stage_get_nir(pipeline
, cache
,
1344 if (stages
[s
].nir
== NULL
) {
1345 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1349 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1352 /* Walk backwards to link */
1353 struct anv_pipeline_stage
*next_stage
= NULL
;
1354 for (int s
= MESA_SHADER_STAGES
- 1; s
>= 0; s
--) {
1355 if (!stages
[s
].entrypoint
)
1359 case MESA_SHADER_VERTEX
:
1360 anv_pipeline_link_vs(compiler
, &stages
[s
], next_stage
);
1362 case MESA_SHADER_TESS_CTRL
:
1363 anv_pipeline_link_tcs(compiler
, &stages
[s
], next_stage
);
1365 case MESA_SHADER_TESS_EVAL
:
1366 anv_pipeline_link_tes(compiler
, &stages
[s
], next_stage
);
1368 case MESA_SHADER_GEOMETRY
:
1369 anv_pipeline_link_gs(compiler
, &stages
[s
], next_stage
);
1371 case MESA_SHADER_FRAGMENT
:
1372 anv_pipeline_link_fs(compiler
, &stages
[s
]);
1375 unreachable("Invalid graphics shader stage");
1378 next_stage
= &stages
[s
];
1381 struct anv_pipeline_stage
*prev_stage
= NULL
;
1382 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1383 if (!stages
[s
].entrypoint
)
1386 int64_t stage_start
= os_time_get_nano();
1388 void *stage_ctx
= ralloc_context(NULL
);
1390 nir_xfb_info
*xfb_info
= NULL
;
1391 if (s
== MESA_SHADER_VERTEX
||
1392 s
== MESA_SHADER_TESS_EVAL
||
1393 s
== MESA_SHADER_GEOMETRY
)
1394 xfb_info
= nir_gather_xfb_info(stages
[s
].nir
, stage_ctx
);
1396 anv_pipeline_lower_nir(pipeline
, stage_ctx
, &stages
[s
], layout
);
1399 case MESA_SHADER_VERTEX
:
1400 anv_pipeline_compile_vs(compiler
, stage_ctx
, pipeline
->device
,
1403 case MESA_SHADER_TESS_CTRL
:
1404 anv_pipeline_compile_tcs(compiler
, stage_ctx
, pipeline
->device
,
1405 &stages
[s
], prev_stage
);
1407 case MESA_SHADER_TESS_EVAL
:
1408 anv_pipeline_compile_tes(compiler
, stage_ctx
, pipeline
->device
,
1409 &stages
[s
], prev_stage
);
1411 case MESA_SHADER_GEOMETRY
:
1412 anv_pipeline_compile_gs(compiler
, stage_ctx
, pipeline
->device
,
1413 &stages
[s
], prev_stage
);
1415 case MESA_SHADER_FRAGMENT
:
1416 anv_pipeline_compile_fs(compiler
, stage_ctx
, pipeline
->device
,
1417 &stages
[s
], prev_stage
);
1420 unreachable("Invalid graphics shader stage");
1422 if (stages
[s
].code
== NULL
) {
1423 ralloc_free(stage_ctx
);
1424 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1428 struct anv_shader_bin
*bin
=
1429 anv_device_upload_kernel(pipeline
->device
, cache
,
1430 &stages
[s
].cache_key
,
1431 sizeof(stages
[s
].cache_key
),
1433 stages
[s
].prog_data
.base
.program_size
,
1434 stages
[s
].nir
->constant_data
,
1435 stages
[s
].nir
->constant_data_size
,
1436 &stages
[s
].prog_data
.base
,
1437 brw_prog_data_size(s
),
1438 stages
[s
].stats
, stages
[s
].num_stats
,
1439 xfb_info
, &stages
[s
].bind_map
);
1441 ralloc_free(stage_ctx
);
1442 result
= vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1446 anv_pipeline_add_executables(pipeline
, &stages
[s
], bin
);
1448 pipeline
->shaders
[s
] = bin
;
1449 ralloc_free(stage_ctx
);
1451 stages
[s
].feedback
.duration
+= os_time_get_nano() - stage_start
;
1453 prev_stage
= &stages
[s
];
1456 ralloc_free(pipeline_ctx
);
1460 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
] &&
1461 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->prog_data
->program_size
== 0) {
1462 /* This can happen if we decided to implicitly disable the fragment
1463 * shader. See anv_pipeline_compile_fs().
1465 anv_shader_bin_unref(pipeline
->device
,
1466 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1467 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] = NULL
;
1468 pipeline
->active_stages
&= ~VK_SHADER_STAGE_FRAGMENT_BIT
;
1471 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1473 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1474 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1475 if (create_feedback
) {
1476 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1478 assert(info
->stageCount
== create_feedback
->pipelineStageCreationFeedbackCount
);
1479 for (uint32_t i
= 0; i
< info
->stageCount
; i
++) {
1480 gl_shader_stage s
= vk_to_mesa_shader_stage(info
->pStages
[i
].stage
);
1481 create_feedback
->pPipelineStageCreationFeedbacks
[i
] = stages
[s
].feedback
;
1488 ralloc_free(pipeline_ctx
);
1490 for (unsigned s
= 0; s
< MESA_SHADER_STAGES
; s
++) {
1491 if (pipeline
->shaders
[s
])
1492 anv_shader_bin_unref(pipeline
->device
, pipeline
->shaders
[s
]);
1499 shared_type_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
1501 assert(glsl_type_is_vector_or_scalar(type
));
1503 uint32_t comp_size
= glsl_type_is_boolean(type
)
1504 ? 4 : glsl_get_bit_size(type
) / 8;
1505 unsigned length
= glsl_get_vector_elements(type
);
1506 *size
= comp_size
* length
,
1507 *align
= comp_size
* (length
== 3 ? 4 : length
);
1511 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
1512 struct anv_pipeline_cache
*cache
,
1513 const VkComputePipelineCreateInfo
*info
,
1514 const struct anv_shader_module
*module
,
1515 const char *entrypoint
,
1516 const VkSpecializationInfo
*spec_info
)
1518 VkPipelineCreationFeedbackEXT pipeline_feedback
= {
1519 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1521 int64_t pipeline_start
= os_time_get_nano();
1523 const struct brw_compiler
*compiler
=
1524 pipeline
->device
->instance
->physicalDevice
.compiler
;
1526 struct anv_pipeline_stage stage
= {
1527 .stage
= MESA_SHADER_COMPUTE
,
1529 .entrypoint
= entrypoint
,
1530 .spec_info
= spec_info
,
1532 .stage
= MESA_SHADER_COMPUTE
,
1535 .flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
,
1538 anv_pipeline_hash_shader(stage
.module
,
1540 MESA_SHADER_COMPUTE
,
1544 struct anv_shader_bin
*bin
= NULL
;
1546 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*rss_info
=
1547 vk_find_struct_const(info
->stage
.pNext
,
1548 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
1550 populate_cs_prog_key(&pipeline
->device
->info
, info
->stage
.flags
,
1551 rss_info
, &stage
.key
.cs
);
1553 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, info
->layout
);
1555 const bool skip_cache_lookup
=
1556 (pipeline
->flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
);
1558 anv_pipeline_hash_compute(pipeline
, layout
, &stage
, stage
.cache_key
.sha1
);
1560 bool cache_hit
= false;
1561 if (!skip_cache_lookup
) {
1562 bin
= anv_device_search_for_kernel(pipeline
->device
, cache
,
1564 sizeof(stage
.cache_key
),
1568 void *mem_ctx
= ralloc_context(NULL
);
1570 int64_t stage_start
= os_time_get_nano();
1572 stage
.bind_map
= (struct anv_pipeline_bind_map
) {
1573 .surface_to_descriptor
= stage
.surface_to_descriptor
,
1574 .sampler_to_descriptor
= stage
.sampler_to_descriptor
1577 /* Set up a binding for the gl_NumWorkGroups */
1578 stage
.bind_map
.surface_count
= 1;
1579 stage
.bind_map
.surface_to_descriptor
[0] = (struct anv_pipeline_binding
) {
1580 .set
= ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
,
1583 stage
.nir
= anv_pipeline_stage_get_nir(pipeline
, cache
, mem_ctx
, &stage
);
1584 if (stage
.nir
== NULL
) {
1585 ralloc_free(mem_ctx
);
1586 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1589 anv_pipeline_lower_nir(pipeline
, mem_ctx
, &stage
, layout
);
1591 NIR_PASS_V(stage
.nir
, anv_nir_add_base_work_group_id
,
1592 &stage
.prog_data
.cs
);
1594 NIR_PASS_V(stage
.nir
, nir_lower_vars_to_explicit_types
,
1595 nir_var_mem_shared
, shared_type_info
);
1596 NIR_PASS_V(stage
.nir
, nir_lower_explicit_io
,
1597 nir_var_mem_shared
, nir_address_format_32bit_offset
);
1599 stage
.num_stats
= 1;
1600 stage
.code
= brw_compile_cs(compiler
, pipeline
->device
, mem_ctx
,
1601 &stage
.key
.cs
, &stage
.prog_data
.cs
,
1602 stage
.nir
, -1, stage
.stats
, NULL
);
1603 if (stage
.code
== NULL
) {
1604 ralloc_free(mem_ctx
);
1605 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1608 const unsigned code_size
= stage
.prog_data
.base
.program_size
;
1609 bin
= anv_device_upload_kernel(pipeline
->device
, cache
,
1610 &stage
.cache_key
, sizeof(stage
.cache_key
),
1611 stage
.code
, code_size
,
1612 stage
.nir
->constant_data
,
1613 stage
.nir
->constant_data_size
,
1614 &stage
.prog_data
.base
,
1615 sizeof(stage
.prog_data
.cs
),
1616 stage
.stats
, stage
.num_stats
,
1617 NULL
, &stage
.bind_map
);
1619 ralloc_free(mem_ctx
);
1620 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1623 stage
.feedback
.duration
= os_time_get_nano() - stage_start
;
1626 anv_pipeline_add_executables(pipeline
, &stage
, bin
);
1628 ralloc_free(mem_ctx
);
1631 stage
.feedback
.flags
|=
1632 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1633 pipeline_feedback
.flags
|=
1634 VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
;
1636 pipeline_feedback
.duration
= os_time_get_nano() - pipeline_start
;
1638 const VkPipelineCreationFeedbackCreateInfoEXT
*create_feedback
=
1639 vk_find_struct_const(info
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
1640 if (create_feedback
) {
1641 *create_feedback
->pPipelineCreationFeedback
= pipeline_feedback
;
1643 assert(create_feedback
->pipelineStageCreationFeedbackCount
== 1);
1644 create_feedback
->pPipelineStageCreationFeedbacks
[0] = stage
.feedback
;
1647 pipeline
->active_stages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1648 pipeline
->shaders
[MESA_SHADER_COMPUTE
] = bin
;
1654 * Copy pipeline state not marked as dynamic.
1655 * Dynamic state is pipeline state which hasn't been provided at pipeline
1656 * creation time, but is dynamically provided afterwards using various
1657 * vkCmdSet* functions.
1659 * The set of state considered "non_dynamic" is determined by the pieces of
1660 * state that have their corresponding VkDynamicState enums omitted from
1661 * VkPipelineDynamicStateCreateInfo::pDynamicStates.
1663 * @param[out] pipeline Destination non_dynamic state.
1664 * @param[in] pCreateInfo Source of non_dynamic state to be copied.
1667 copy_non_dynamic_state(struct anv_pipeline
*pipeline
,
1668 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1670 anv_cmd_dirty_mask_t states
= ANV_CMD_DIRTY_DYNAMIC_ALL
;
1671 struct anv_subpass
*subpass
= pipeline
->subpass
;
1673 pipeline
->dynamic_state
= default_dynamic_state
;
1675 if (pCreateInfo
->pDynamicState
) {
1676 /* Remove all of the states that are marked as dynamic */
1677 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1678 for (uint32_t s
= 0; s
< count
; s
++) {
1679 states
&= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
1680 pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1684 struct anv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1686 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1688 * pViewportState is [...] NULL if the pipeline
1689 * has rasterization disabled.
1691 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1692 assert(pCreateInfo
->pViewportState
);
1694 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1695 if (states
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
) {
1696 typed_memcpy(dynamic
->viewport
.viewports
,
1697 pCreateInfo
->pViewportState
->pViewports
,
1698 pCreateInfo
->pViewportState
->viewportCount
);
1701 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1702 if (states
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
) {
1703 typed_memcpy(dynamic
->scissor
.scissors
,
1704 pCreateInfo
->pViewportState
->pScissors
,
1705 pCreateInfo
->pViewportState
->scissorCount
);
1709 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) {
1710 assert(pCreateInfo
->pRasterizationState
);
1711 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1714 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
) {
1715 assert(pCreateInfo
->pRasterizationState
);
1716 dynamic
->depth_bias
.bias
=
1717 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1718 dynamic
->depth_bias
.clamp
=
1719 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1720 dynamic
->depth_bias
.slope
=
1721 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1724 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1726 * pColorBlendState is [...] NULL if the pipeline has rasterization
1727 * disabled or if the subpass of the render pass the pipeline is
1728 * created against does not use any color attachments.
1730 bool uses_color_att
= false;
1731 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1732 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
) {
1733 uses_color_att
= true;
1738 if (uses_color_att
&&
1739 !pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
) {
1740 assert(pCreateInfo
->pColorBlendState
);
1742 if (states
& ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
1743 typed_memcpy(dynamic
->blend_constants
,
1744 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1747 /* If there is no depthstencil attachment, then don't read
1748 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1749 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1750 * no need to override the depthstencil defaults in
1751 * anv_pipeline::dynamic_state when there is no depthstencil attachment.
1753 * Section 9.2 of the Vulkan 1.0.15 spec says:
1755 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1756 * disabled or if the subpass of the render pass the pipeline is created
1757 * against does not use a depth/stencil attachment.
1759 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
1760 subpass
->depth_stencil_attachment
) {
1761 assert(pCreateInfo
->pDepthStencilState
);
1763 if (states
& ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
) {
1764 dynamic
->depth_bounds
.min
=
1765 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1766 dynamic
->depth_bounds
.max
=
1767 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1770 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) {
1771 dynamic
->stencil_compare_mask
.front
=
1772 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1773 dynamic
->stencil_compare_mask
.back
=
1774 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1777 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) {
1778 dynamic
->stencil_write_mask
.front
=
1779 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1780 dynamic
->stencil_write_mask
.back
=
1781 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1784 if (states
& ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) {
1785 dynamic
->stencil_reference
.front
=
1786 pCreateInfo
->pDepthStencilState
->front
.reference
;
1787 dynamic
->stencil_reference
.back
=
1788 pCreateInfo
->pDepthStencilState
->back
.reference
;
1792 const VkPipelineRasterizationLineStateCreateInfoEXT
*line_state
=
1793 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1794 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1796 if (states
& ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
) {
1797 dynamic
->line_stipple
.factor
= line_state
->lineStippleFactor
;
1798 dynamic
->line_stipple
.pattern
= line_state
->lineStipplePattern
;
1802 pipeline
->dynamic_state_mask
= states
;
1806 anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo
*info
)
1809 struct anv_render_pass
*renderpass
= NULL
;
1810 struct anv_subpass
*subpass
= NULL
;
1812 /* Assert that all required members of VkGraphicsPipelineCreateInfo are
1813 * present. See the Vulkan 1.0.28 spec, Section 9.2 Graphics Pipelines.
1815 assert(info
->sType
== VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
);
1817 renderpass
= anv_render_pass_from_handle(info
->renderPass
);
1820 assert(info
->subpass
< renderpass
->subpass_count
);
1821 subpass
= &renderpass
->subpasses
[info
->subpass
];
1823 assert(info
->stageCount
>= 1);
1824 assert(info
->pVertexInputState
);
1825 assert(info
->pInputAssemblyState
);
1826 assert(info
->pRasterizationState
);
1827 if (!info
->pRasterizationState
->rasterizerDiscardEnable
) {
1828 assert(info
->pViewportState
);
1829 assert(info
->pMultisampleState
);
1831 if (subpass
&& subpass
->depth_stencil_attachment
)
1832 assert(info
->pDepthStencilState
);
1834 if (subpass
&& subpass
->color_count
> 0) {
1835 bool all_color_unused
= true;
1836 for (int i
= 0; i
< subpass
->color_count
; i
++) {
1837 if (subpass
->color_attachments
[i
].attachment
!= VK_ATTACHMENT_UNUSED
)
1838 all_color_unused
= false;
1840 /* pColorBlendState is ignored if the pipeline has rasterization
1841 * disabled or if the subpass of the render pass the pipeline is
1842 * created against does not use any color attachments.
1844 assert(info
->pColorBlendState
|| all_color_unused
);
1848 for (uint32_t i
= 0; i
< info
->stageCount
; ++i
) {
1849 switch (info
->pStages
[i
].stage
) {
1850 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
:
1851 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
:
1852 assert(info
->pTessellationState
);
1862 * Calculate the desired L3 partitioning based on the current state of the
1863 * pipeline. For now this simply returns the conservative defaults calculated
1864 * by get_default_l3_weights(), but we could probably do better by gathering
1865 * more statistics from the pipeline state (e.g. guess of expected URB usage
1866 * and bound surfaces), or by using feed-back from performance counters.
1869 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
)
1871 const struct gen_device_info
*devinfo
= &pipeline
->device
->info
;
1873 const struct gen_l3_weights w
=
1874 gen_get_default_l3_weights(devinfo
, pipeline
->needs_data_cache
, needs_slm
);
1876 pipeline
->urb
.l3_config
= gen_get_l3_config(devinfo
, w
);
1877 pipeline
->urb
.total_size
=
1878 gen_get_l3_config_urb_size(devinfo
, pipeline
->urb
.l3_config
);
1882 anv_pipeline_init(struct anv_pipeline
*pipeline
,
1883 struct anv_device
*device
,
1884 struct anv_pipeline_cache
*cache
,
1885 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1886 const VkAllocationCallbacks
*alloc
)
1890 anv_pipeline_validate_create_info(pCreateInfo
);
1893 alloc
= &device
->alloc
;
1895 pipeline
->device
= device
;
1897 ANV_FROM_HANDLE(anv_render_pass
, render_pass
, pCreateInfo
->renderPass
);
1898 assert(pCreateInfo
->subpass
< render_pass
->subpass_count
);
1899 pipeline
->subpass
= &render_pass
->subpasses
[pCreateInfo
->subpass
];
1901 result
= anv_reloc_list_init(&pipeline
->batch_relocs
, alloc
);
1902 if (result
!= VK_SUCCESS
)
1905 pipeline
->batch
.alloc
= alloc
;
1906 pipeline
->batch
.next
= pipeline
->batch
.start
= pipeline
->batch_data
;
1907 pipeline
->batch
.end
= pipeline
->batch
.start
+ sizeof(pipeline
->batch_data
);
1908 pipeline
->batch
.relocs
= &pipeline
->batch_relocs
;
1909 pipeline
->batch
.status
= VK_SUCCESS
;
1911 pipeline
->mem_ctx
= ralloc_context(NULL
);
1912 pipeline
->flags
= pCreateInfo
->flags
;
1914 copy_non_dynamic_state(pipeline
, pCreateInfo
);
1915 pipeline
->depth_clamp_enable
= pCreateInfo
->pRasterizationState
&&
1916 pCreateInfo
->pRasterizationState
->depthClampEnable
;
1918 /* Previously we enabled depth clipping when !depthClampEnable.
1919 * DepthClipStateCreateInfo now makes depth clipping explicit so if the
1920 * clipping info is available, use its enable value to determine clipping,
1921 * otherwise fallback to the previous !depthClampEnable logic.
1923 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*clip_info
=
1924 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1925 PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
1926 pipeline
->depth_clip_enable
= clip_info
? clip_info
->depthClipEnable
: !pipeline
->depth_clamp_enable
;
1928 pipeline
->sample_shading_enable
= pCreateInfo
->pMultisampleState
&&
1929 pCreateInfo
->pMultisampleState
->sampleShadingEnable
;
1931 pipeline
->needs_data_cache
= false;
1933 /* When we free the pipeline, we detect stages based on the NULL status
1934 * of various prog_data pointers. Make them NULL by default.
1936 memset(pipeline
->shaders
, 0, sizeof(pipeline
->shaders
));
1937 pipeline
->num_executables
= 0;
1939 result
= anv_pipeline_compile_graphics(pipeline
, cache
, pCreateInfo
);
1940 if (result
!= VK_SUCCESS
) {
1941 ralloc_free(pipeline
->mem_ctx
);
1942 anv_reloc_list_finish(&pipeline
->batch_relocs
, alloc
);
1946 assert(pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1948 anv_pipeline_setup_l3_config(pipeline
, false);
1950 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
1951 pCreateInfo
->pVertexInputState
;
1953 const uint64_t inputs_read
= get_vs_prog_data(pipeline
)->inputs_read
;
1955 pipeline
->vb_used
= 0;
1956 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
1957 const VkVertexInputAttributeDescription
*desc
=
1958 &vi_info
->pVertexAttributeDescriptions
[i
];
1960 if (inputs_read
& (1ull << (VERT_ATTRIB_GENERIC0
+ desc
->location
)))
1961 pipeline
->vb_used
|= 1 << desc
->binding
;
1964 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
1965 const VkVertexInputBindingDescription
*desc
=
1966 &vi_info
->pVertexBindingDescriptions
[i
];
1968 pipeline
->vb
[desc
->binding
].stride
= desc
->stride
;
1970 /* Step rate is programmed per vertex element (attribute), not
1971 * binding. Set up a map of which bindings step per instance, for
1972 * reference by vertex element setup. */
1973 switch (desc
->inputRate
) {
1975 case VK_VERTEX_INPUT_RATE_VERTEX
:
1976 pipeline
->vb
[desc
->binding
].instanced
= false;
1978 case VK_VERTEX_INPUT_RATE_INSTANCE
:
1979 pipeline
->vb
[desc
->binding
].instanced
= true;
1983 pipeline
->vb
[desc
->binding
].instance_divisor
= 1;
1986 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*vi_div_state
=
1987 vk_find_struct_const(vi_info
->pNext
,
1988 PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
1990 for (uint32_t i
= 0; i
< vi_div_state
->vertexBindingDivisorCount
; i
++) {
1991 const VkVertexInputBindingDivisorDescriptionEXT
*desc
=
1992 &vi_div_state
->pVertexBindingDivisors
[i
];
1994 pipeline
->vb
[desc
->binding
].instance_divisor
= desc
->divisor
;
1998 /* Our implementation of VK_KHR_multiview uses instancing to draw the
1999 * different views. If the client asks for instancing, we need to multiply
2000 * the instance divisor by the number of views ensure that we repeat the
2001 * client's per-instance data once for each view.
2003 if (pipeline
->subpass
->view_mask
) {
2004 const uint32_t view_count
= anv_subpass_view_count(pipeline
->subpass
);
2005 for (uint32_t vb
= 0; vb
< MAX_VBS
; vb
++) {
2006 if (pipeline
->vb
[vb
].instanced
)
2007 pipeline
->vb
[vb
].instance_divisor
*= view_count
;
2011 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2012 pCreateInfo
->pInputAssemblyState
;
2013 const VkPipelineTessellationStateCreateInfo
*tess_info
=
2014 pCreateInfo
->pTessellationState
;
2015 pipeline
->primitive_restart
= ia_info
->primitiveRestartEnable
;
2017 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
2018 pipeline
->topology
= _3DPRIM_PATCHLIST(tess_info
->patchControlPoints
);
2020 pipeline
->topology
= vk_to_gen_primitive_type
[ia_info
->topology
];
2025 #define WRITE_STR(field, ...) ({ \
2026 memset(field, 0, sizeof(field)); \
2027 UNUSED int i = snprintf(field, sizeof(field), __VA_ARGS__); \
2028 assert(i > 0 && i < sizeof(field)); \
2031 VkResult
anv_GetPipelineExecutablePropertiesKHR(
2033 const VkPipelineInfoKHR
* pPipelineInfo
,
2034 uint32_t* pExecutableCount
,
2035 VkPipelineExecutablePropertiesKHR
* pProperties
)
2037 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
2038 VK_OUTARRAY_MAKE(out
, pProperties
, pExecutableCount
);
2040 for (uint32_t i
= 0; i
< pipeline
->num_executables
; i
++) {
2041 vk_outarray_append(&out
, props
) {
2042 gl_shader_stage stage
= pipeline
->executables
[i
].stage
;
2043 props
->stages
= mesa_to_vk_shader_stage(stage
);
2045 unsigned simd_width
= pipeline
->executables
[i
].stats
.dispatch_width
;
2046 if (stage
== MESA_SHADER_FRAGMENT
) {
2047 WRITE_STR(props
->name
, "%s%d %s",
2048 simd_width
? "SIMD" : "vec",
2049 simd_width
? simd_width
: 4,
2050 _mesa_shader_stage_to_string(stage
));
2052 WRITE_STR(props
->name
, "%s", _mesa_shader_stage_to_string(stage
));
2054 WRITE_STR(props
->description
, "%s%d %s shader",
2055 simd_width
? "SIMD" : "vec",
2056 simd_width
? simd_width
: 4,
2057 _mesa_shader_stage_to_string(stage
));
2059 /* The compiler gives us a dispatch width of 0 for vec4 but Vulkan
2060 * wants a subgroup size of 1.
2062 props
->subgroupSize
= MAX2(simd_width
, 1);
2066 return vk_outarray_status(&out
);
2069 VkResult
anv_GetPipelineExecutableStatisticsKHR(
2071 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2072 uint32_t* pStatisticCount
,
2073 VkPipelineExecutableStatisticKHR
* pStatistics
)
2075 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2076 VK_OUTARRAY_MAKE(out
, pStatistics
, pStatisticCount
);
2078 assert(pExecutableInfo
->executableIndex
< pipeline
->num_executables
);
2079 const struct anv_pipeline_executable
*exe
=
2080 &pipeline
->executables
[pExecutableInfo
->executableIndex
];
2081 const struct brw_stage_prog_data
*prog_data
=
2082 pipeline
->shaders
[exe
->stage
]->prog_data
;
2084 vk_outarray_append(&out
, stat
) {
2085 WRITE_STR(stat
->name
, "Instruction Count");
2086 WRITE_STR(stat
->description
,
2087 "Number of GEN instructions in the final generated "
2088 "shader executable.");
2089 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2090 stat
->value
.u64
= exe
->stats
.instructions
;
2093 vk_outarray_append(&out
, stat
) {
2094 WRITE_STR(stat
->name
, "Loop Count");
2095 WRITE_STR(stat
->description
,
2096 "Number of loops (not unrolled) in the final generated "
2097 "shader executable.");
2098 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2099 stat
->value
.u64
= exe
->stats
.loops
;
2102 vk_outarray_append(&out
, stat
) {
2103 WRITE_STR(stat
->name
, "Cycle Count");
2104 WRITE_STR(stat
->description
,
2105 "Estimate of the number of EU cycles required to execute "
2106 "the final generated executable. This is an estimate only "
2107 "and may vary greatly from actual run-time performance.");
2108 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2109 stat
->value
.u64
= exe
->stats
.cycles
;
2112 vk_outarray_append(&out
, stat
) {
2113 WRITE_STR(stat
->name
, "Spill Count");
2114 WRITE_STR(stat
->description
,
2115 "Number of scratch spill operations. This gives a rough "
2116 "estimate of the cost incurred due to spilling temporary "
2117 "values to memory. If this is non-zero, you may want to "
2118 "adjust your shader to reduce register pressure.");
2119 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2120 stat
->value
.u64
= exe
->stats
.spills
;
2123 vk_outarray_append(&out
, stat
) {
2124 WRITE_STR(stat
->name
, "Fill Count");
2125 WRITE_STR(stat
->description
,
2126 "Number of scratch fill operations. This gives a rough "
2127 "estimate of the cost incurred due to spilling temporary "
2128 "values to memory. If this is non-zero, you may want to "
2129 "adjust your shader to reduce register pressure.");
2130 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2131 stat
->value
.u64
= exe
->stats
.fills
;
2134 vk_outarray_append(&out
, stat
) {
2135 WRITE_STR(stat
->name
, "Scratch Memory Size");
2136 WRITE_STR(stat
->description
,
2137 "Number of bytes of scratch memory required by the "
2138 "generated shader executable. If this is non-zero, you "
2139 "may want to adjust your shader to reduce register "
2141 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2142 stat
->value
.u64
= prog_data
->total_scratch
;
2145 if (exe
->stage
== MESA_SHADER_COMPUTE
) {
2146 vk_outarray_append(&out
, stat
) {
2147 WRITE_STR(stat
->name
, "Workgroup Memory Size");
2148 WRITE_STR(stat
->description
,
2149 "Number of bytes of workgroup shared memory used by this "
2150 "compute shader including any padding.");
2151 stat
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
2152 stat
->value
.u64
= prog_data
->total_scratch
;
2156 return vk_outarray_status(&out
);
2160 write_ir_text(VkPipelineExecutableInternalRepresentationKHR
* ir
,
2163 ir
->isText
= VK_TRUE
;
2165 size_t data_len
= strlen(data
) + 1;
2167 if (ir
->pData
== NULL
) {
2168 ir
->dataSize
= data_len
;
2172 strncpy(ir
->pData
, data
, ir
->dataSize
);
2173 if (ir
->dataSize
< data_len
)
2176 ir
->dataSize
= data_len
;
2180 VkResult
anv_GetPipelineExecutableInternalRepresentationsKHR(
2182 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
2183 uint32_t* pInternalRepresentationCount
,
2184 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
2186 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
2187 VK_OUTARRAY_MAKE(out
, pInternalRepresentations
,
2188 pInternalRepresentationCount
);
2189 bool incomplete_text
= false;
2191 assert(pExecutableInfo
->executableIndex
< pipeline
->num_executables
);
2192 const struct anv_pipeline_executable
*exe
=
2193 &pipeline
->executables
[pExecutableInfo
->executableIndex
];
2196 vk_outarray_append(&out
, ir
) {
2197 WRITE_STR(ir
->name
, "Final NIR");
2198 WRITE_STR(ir
->description
,
2199 "Final NIR before going into the back-end compiler");
2201 if (!write_ir_text(ir
, exe
->nir
))
2202 incomplete_text
= true;
2207 vk_outarray_append(&out
, ir
) {
2208 WRITE_STR(ir
->name
, "GEN Assembly");
2209 WRITE_STR(ir
->description
,
2210 "Final GEN assembly for the generated shader binary");
2212 if (!write_ir_text(ir
, exe
->disasm
))
2213 incomplete_text
= true;
2217 return incomplete_text
? VK_INCOMPLETE
: vk_outarray_status(&out
);