src/intel/vulkan/anv_pipeline_cache.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/blob.h"
  25 #include "util/hash_table.h"
  26 #include "util/debug.h"
  27 #include "util/disk_cache.h"
  28 #include "util/mesa-sha1.h"
  29 #include "nir/nir_serialize.h"
  30 #include "anv_private.h"
  31 #include "nir/nir_xfb_info.h"
  32 #include "vulkan/util/vk_util.h"
  33
  34 struct anv_shader_bin *
  35 anv_shader_bin_create(struct anv_device *device,
  36                       gl_shader_stage stage,
  37                       const void *key_data, uint32_t key_size,
  38                       const void *kernel_data, uint32_t kernel_size,
  39                       const struct brw_stage_prog_data *prog_data_in,
  40                       uint32_t prog_data_size,
  41                       const struct brw_compile_stats *stats, uint32_t num_stats,
  42                       const nir_xfb_info *xfb_info_in,
  43                       const struct anv_pipeline_bind_map *bind_map)
  44 {
  45    struct anv_shader_bin *shader;
  46    struct anv_shader_bin_key *key;
  47    struct brw_stage_prog_data *prog_data;
  48    uint32_t *prog_data_param;
  49    nir_xfb_info *xfb_info;
  50    struct anv_pipeline_binding *surface_to_descriptor, *sampler_to_descriptor;
  51
  52    ANV_MULTIALLOC(ma);
  53    anv_multialloc_add(&ma, &shader, 1);
  54    anv_multialloc_add_size(&ma, &key, sizeof(*key) + key_size);
  55    anv_multialloc_add_size(&ma, &prog_data, prog_data_size);
  56    anv_multialloc_add(&ma, &prog_data_param, prog_data_in->nr_params);
  57    if (xfb_info_in) {
  58       uint32_t xfb_info_size = nir_xfb_info_size(xfb_info_in->output_count);
  59       anv_multialloc_add_size(&ma, &xfb_info, xfb_info_size);
  60    }
  61    anv_multialloc_add(&ma, &surface_to_descriptor,
  62                            bind_map->surface_count);
  63    anv_multialloc_add(&ma, &sampler_to_descriptor,
  64                            bind_map->sampler_count);
  65
  66    if (!anv_multialloc_alloc(&ma, &device->vk.alloc,
  67                              VK_SYSTEM_ALLOCATION_SCOPE_DEVICE))
  68       return NULL;
  69
  70    shader->ref_cnt = 1;
  71
  72    shader->stage = stage;
  73
  74    key->size = key_size;
  75    memcpy(key->data, key_data, key_size);
  76    shader->key = key;
  77
  78    shader->kernel =
  79       anv_state_pool_alloc(&device->instruction_state_pool, kernel_size, 64);
  80    memcpy(shader->kernel.map, kernel_data, kernel_size);
  81    shader->kernel_size = kernel_size;
  82
  83    memcpy(prog_data, prog_data_in, prog_data_size);
  84    memset(prog_data_param, 0,
  85           prog_data->nr_params * sizeof(*prog_data_param));
  86    prog_data->param = prog_data_param;
  87    shader->prog_data = prog_data;
  88    shader->prog_data_size = prog_data_size;
  89
  90    assert(num_stats <= ARRAY_SIZE(shader->stats));
  91    typed_memcpy(shader->stats, stats, num_stats);
  92    shader->num_stats = num_stats;
  93
  94    if (xfb_info_in) {
  95       *xfb_info = *xfb_info_in;
  96       typed_memcpy(xfb_info->outputs, xfb_info_in->outputs,
  97                    xfb_info_in->output_count);
  98       shader->xfb_info = xfb_info;
  99    } else {
 100       shader->xfb_info = NULL;
 101    }
 102
 103    shader->bind_map = *bind_map;
 104    typed_memcpy(surface_to_descriptor, bind_map->surface_to_descriptor,
 105                 bind_map->surface_count);
 106    shader->bind_map.surface_to_descriptor = surface_to_descriptor;
 107    typed_memcpy(sampler_to_descriptor, bind_map->sampler_to_descriptor,
 108                 bind_map->sampler_count);
 109    shader->bind_map.sampler_to_descriptor = sampler_to_descriptor;
 110
 111    return shader;
 112 }
 113
 114 void
 115 anv_shader_bin_destroy(struct anv_device *device,
 116                        struct anv_shader_bin *shader)
 117 {
 118    assert(shader->ref_cnt == 0);
 119    anv_state_pool_free(&device->instruction_state_pool, shader->kernel);
 120    vk_free(&device->vk.alloc, shader);
 121 }
 122
 123 static bool
 124 anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
 125                              struct blob *blob)
 126 {
 127    blob_write_uint32(blob, shader->stage);
 128
 129    blob_write_uint32(blob, shader->key->size);
 130    blob_write_bytes(blob, shader->key->data, shader->key->size);
 131
 132    blob_write_uint32(blob, shader->kernel_size);
 133    blob_write_bytes(blob, shader->kernel.map, shader->kernel_size);
 134
 135    blob_write_uint32(blob, shader->prog_data_size);
 136    blob_write_bytes(blob, shader->prog_data, shader->prog_data_size);
 137
 138    blob_write_uint32(blob, shader->num_stats);
 139    blob_write_bytes(blob, shader->stats,
 140                     shader->num_stats * sizeof(shader->stats[0]));
 141
 142    if (shader->xfb_info) {
 143       uint32_t xfb_info_size =
 144          nir_xfb_info_size(shader->xfb_info->output_count);
 145       blob_write_uint32(blob, xfb_info_size);
 146       blob_write_bytes(blob, shader->xfb_info, xfb_info_size);
 147    } else {
 148       blob_write_uint32(blob, 0);
 149    }
 150
 151    blob_write_bytes(blob, shader->bind_map.surface_sha1,
 152                     sizeof(shader->bind_map.surface_sha1));
 153    blob_write_bytes(blob, shader->bind_map.sampler_sha1,
 154                     sizeof(shader->bind_map.sampler_sha1));
 155    blob_write_bytes(blob, shader->bind_map.push_sha1,
 156                     sizeof(shader->bind_map.push_sha1));
 157    blob_write_uint32(blob, shader->bind_map.surface_count);
 158    blob_write_uint32(blob, shader->bind_map.sampler_count);
 159    blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
 160                     shader->bind_map.surface_count *
 161                     sizeof(*shader->bind_map.surface_to_descriptor));
 162    blob_write_bytes(blob, shader->bind_map.sampler_to_descriptor,
 163                     shader->bind_map.sampler_count *
 164                     sizeof(*shader->bind_map.sampler_to_descriptor));
 165    blob_write_bytes(blob, shader->bind_map.push_ranges,
 166                     sizeof(shader->bind_map.push_ranges));
 167
 168    return !blob->out_of_memory;
 169 }
 170
 171 static struct anv_shader_bin *
 172 anv_shader_bin_create_from_blob(struct anv_device *device,
 173                                 struct blob_reader *blob)
 174 {
 175    gl_shader_stage stage = blob_read_uint32(blob);
 176
 177    uint32_t key_size = blob_read_uint32(blob);
 178    const void *key_data = blob_read_bytes(blob, key_size);
 179
 180    uint32_t kernel_size = blob_read_uint32(blob);
 181    const void *kernel_data = blob_read_bytes(blob, kernel_size);
 182
 183    uint32_t prog_data_size = blob_read_uint32(blob);
 184    const struct brw_stage_prog_data *prog_data =
 185       blob_read_bytes(blob, prog_data_size);
 186    if (blob->overrun)
 187       return NULL;
 188
 189    uint32_t num_stats = blob_read_uint32(blob);
 190    const struct brw_compile_stats *stats =
 191       blob_read_bytes(blob, num_stats * sizeof(stats[0]));
 192
 193    const nir_xfb_info *xfb_info = NULL;
 194    uint32_t xfb_size = blob_read_uint32(blob);
 195    if (xfb_size)
 196       xfb_info = blob_read_bytes(blob, xfb_size);
 197
 198    struct anv_pipeline_bind_map bind_map;
 199    blob_copy_bytes(blob, bind_map.surface_sha1, sizeof(bind_map.surface_sha1));
 200    blob_copy_bytes(blob, bind_map.sampler_sha1, sizeof(bind_map.sampler_sha1));
 201    blob_copy_bytes(blob, bind_map.push_sha1, sizeof(bind_map.push_sha1));
 202    bind_map.surface_count = blob_read_uint32(blob);
 203    bind_map.sampler_count = blob_read_uint32(blob);
 204    bind_map.surface_to_descriptor = (void *)
 205       blob_read_bytes(blob, bind_map.surface_count *
 206                             sizeof(*bind_map.surface_to_descriptor));
 207    bind_map.sampler_to_descriptor = (void *)
 208       blob_read_bytes(blob, bind_map.sampler_count *
 209                             sizeof(*bind_map.sampler_to_descriptor));
 210    blob_copy_bytes(blob, bind_map.push_ranges, sizeof(bind_map.push_ranges));
 211
 212    if (blob->overrun)
 213       return NULL;
 214
 215    return anv_shader_bin_create(device, stage,
 216                                 key_data, key_size,
 217                                 kernel_data, kernel_size,
 218                                 prog_data, prog_data_size,
 219                                 stats, num_stats, xfb_info, &bind_map);
 220 }
 221
 222 /* Remaining work:
 223  *
 224  * - Compact binding table layout so it's tight and not dependent on
 225  *   descriptor set layout.
 226  *
 227  * - Review prog_data struct for size and cacheability: struct
 228  *   brw_stage_prog_data has binding_table which uses a lot of uint32_t for 8
 229  *   bit quantities etc; use bit fields for all bools, eg dual_src_blend.
 230  */
 231
 232 static uint32_t
 233 shader_bin_key_hash_func(const void *void_key)
 234 {
 235    const struct anv_shader_bin_key *key = void_key;
 236    return _mesa_hash_data(key->data, key->size);
 237 }
 238
 239 static bool
 240 shader_bin_key_compare_func(const void *void_a, const void *void_b)
 241 {
 242    const struct anv_shader_bin_key *a = void_a, *b = void_b;
 243    if (a->size != b->size)
 244       return false;
 245
 246    return memcmp(a->data, b->data, a->size) == 0;
 247 }
 248
 249 static uint32_t
 250 sha1_hash_func(const void *sha1)
 251 {
 252    return _mesa_hash_data(sha1, 20);
 253 }
 254
 255 static bool
 256 sha1_compare_func(const void *sha1_a, const void *sha1_b)
 257 {
 258    return memcmp(sha1_a, sha1_b, 20) == 0;
 259 }
 260
 261 void
 262 anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
 263                         struct anv_device *device,
 264                         bool cache_enabled,
 265                         bool external_sync)
 266 {
 267    vk_object_base_init(&device->vk, &cache->base,
 268                        VK_OBJECT_TYPE_PIPELINE_CACHE);
 269    cache->device = device;
 270    cache->external_sync = external_sync;
 271    pthread_mutex_init(&cache->mutex, NULL);
 272
 273    if (cache_enabled) {
 274       cache->cache = _mesa_hash_table_create(NULL, shader_bin_key_hash_func,
 275                                              shader_bin_key_compare_func);
 276       cache->nir_cache = _mesa_hash_table_create(NULL, sha1_hash_func,
 277                                                  sha1_compare_func);
 278    } else {
 279       cache->cache = NULL;
 280       cache->nir_cache = NULL;
 281    }
 282 }
 283
 284 void
 285 anv_pipeline_cache_finish(struct anv_pipeline_cache *cache)
 286 {
 287    pthread_mutex_destroy(&cache->mutex);
 288
 289    if (cache->cache) {
 290       /* This is a bit unfortunate.  In order to keep things from randomly
 291        * going away, the shader cache has to hold a reference to all shader
 292        * binaries it contains.  We unref them when we destroy the cache.
 293        */
 294       hash_table_foreach(cache->cache, entry)
 295          anv_shader_bin_unref(cache->device, entry->data);
 296
 297       _mesa_hash_table_destroy(cache->cache, NULL);
 298    }
 299
 300    if (cache->nir_cache) {
 301       hash_table_foreach(cache->nir_cache, entry)
 302          ralloc_free(entry->data);
 303
 304       _mesa_hash_table_destroy(cache->nir_cache, NULL);
 305    }
 306
 307    vk_object_base_finish(&cache->base);
 308 }
 309
 310 static struct anv_shader_bin *
 311 anv_pipeline_cache_search_locked(struct anv_pipeline_cache *cache,
 312                                  const void *key_data, uint32_t key_size)
 313 {
 314    uint32_t vla[1 + DIV_ROUND_UP(key_size, sizeof(uint32_t))];
 315    struct anv_shader_bin_key *key = (void *)vla;
 316    key->size = key_size;
 317    memcpy(key->data, key_data, key_size);
 318
 319    struct hash_entry *entry = _mesa_hash_table_search(cache->cache, key);
 320    if (entry)
 321       return entry->data;
 322    else
 323       return NULL;
 324 }
 325
 326 static inline void
 327 anv_cache_lock(struct anv_pipeline_cache *cache)
 328 {
 329    if (!cache->external_sync)
 330       pthread_mutex_lock(&cache->mutex);
 331 }
 332
 333 static inline void
 334 anv_cache_unlock(struct anv_pipeline_cache *cache)
 335 {
 336    if (!cache->external_sync)
 337       pthread_mutex_unlock(&cache->mutex);
 338 }
 339
 340 struct anv_shader_bin *
 341 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
 342                           const void *key_data, uint32_t key_size)
 343 {
 344    if (!cache->cache)
 345       return NULL;
 346
 347    anv_cache_lock(cache);
 348
 349    struct anv_shader_bin *shader =
 350       anv_pipeline_cache_search_locked(cache, key_data, key_size);
 351
 352    anv_cache_unlock(cache);
 353
 354    /* We increment refcount before handing it to the caller */
 355    if (shader)
 356       anv_shader_bin_ref(shader);
 357
 358    return shader;
 359 }
 360
 361 static void
 362 anv_pipeline_cache_add_shader_bin(struct anv_pipeline_cache *cache,
 363                                   struct anv_shader_bin *bin)
 364 {
 365    if (!cache->cache)
 366       return;
 367
 368    anv_cache_lock(cache);
 369
 370    struct hash_entry *entry = _mesa_hash_table_search(cache->cache, bin->key);
 371    if (entry == NULL) {
 372       /* Take a reference for the cache */
 373       anv_shader_bin_ref(bin);
 374       _mesa_hash_table_insert(cache->cache, bin->key, bin);
 375    }
 376
 377    anv_cache_unlock(cache);
 378 }
 379
 380 static struct anv_shader_bin *
 381 anv_pipeline_cache_add_shader_locked(struct anv_pipeline_cache *cache,
 382                                      gl_shader_stage stage,
 383                                      const void *key_data, uint32_t key_size,
 384                                      const void *kernel_data,
 385                                      uint32_t kernel_size,
 386                                      const struct brw_stage_prog_data *prog_data,
 387                                      uint32_t prog_data_size,
 388                                      const struct brw_compile_stats *stats,
 389                                      uint32_t num_stats,
 390                                      const nir_xfb_info *xfb_info,
 391                                      const struct anv_pipeline_bind_map *bind_map)
 392 {
 393    struct anv_shader_bin *shader =
 394       anv_pipeline_cache_search_locked(cache, key_data, key_size);
 395    if (shader)
 396       return shader;
 397
 398    struct anv_shader_bin *bin =
 399       anv_shader_bin_create(cache->device, stage,
 400                             key_data, key_size,
 401                             kernel_data, kernel_size,
 402                             prog_data, prog_data_size,
 403                             stats, num_stats, xfb_info, bind_map);
 404    if (!bin)
 405       return NULL;
 406
 407    _mesa_hash_table_insert(cache->cache, bin->key, bin);
 408
 409    return bin;
 410 }
 411
 412 struct anv_shader_bin *
 413 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
 414                                  gl_shader_stage stage,
 415                                  const void *key_data, uint32_t key_size,
 416                                  const void *kernel_data, uint32_t kernel_size,
 417                                  const struct brw_stage_prog_data *prog_data,
 418                                  uint32_t prog_data_size,
 419                                  const struct brw_compile_stats *stats,
 420                                  uint32_t num_stats,
 421                                  const nir_xfb_info *xfb_info,
 422                                  const struct anv_pipeline_bind_map *bind_map)
 423 {
 424    if (cache->cache) {
 425       anv_cache_lock(cache);
 426
 427       struct anv_shader_bin *bin =
 428          anv_pipeline_cache_add_shader_locked(cache, stage, key_data, key_size,
 429                                               kernel_data, kernel_size,
 430                                               prog_data, prog_data_size,
 431                                               stats, num_stats,
 432                                               xfb_info, bind_map);
 433
 434       anv_cache_unlock(cache);
 435
 436       /* We increment refcount before handing it to the caller */
 437       if (bin)
 438          anv_shader_bin_ref(bin);
 439
 440       return bin;
 441    } else {
 442       /* In this case, we're not caching it so the caller owns it entirely */
 443       return anv_shader_bin_create(cache->device, stage,
 444                                    key_data, key_size,
 445                                    kernel_data, kernel_size,
 446                                    prog_data, prog_data_size,
 447                                    stats, num_stats,
 448                                    xfb_info, bind_map);
 449    }
 450 }
 451
 452 static void
 453 anv_pipeline_cache_load(struct anv_pipeline_cache *cache,
 454                         const void *data, size_t size)
 455 {
 456    struct anv_device *device = cache->device;
 457    struct anv_physical_device *pdevice = device->physical;
 458
 459    if (cache->cache == NULL)
 460       return;
 461
 462    struct blob_reader blob;
 463    blob_reader_init(&blob, data, size);
 464
 465    struct vk_pipeline_cache_header header;
 466    blob_copy_bytes(&blob, &header, sizeof(header));
 467    uint32_t count = blob_read_uint32(&blob);
 468    if (blob.overrun)
 469       return;
 470
 471    if (header.header_size < sizeof(header))
 472       return;
 473    if (header.header_version != VK_PIPELINE_CACHE_HEADER_VERSION_ONE)
 474       return;
 475    if (header.vendor_id != 0x8086)
 476       return;
 477    if (header.device_id != device->info.chipset_id)
 478       return;
 479    if (memcmp(header.uuid, pdevice->pipeline_cache_uuid, VK_UUID_SIZE) != 0)
 480       return;
 481
 482    for (uint32_t i = 0; i < count; i++) {
 483       struct anv_shader_bin *bin =
 484          anv_shader_bin_create_from_blob(device, &blob);
 485       if (!bin)
 486          break;
 487       _mesa_hash_table_insert(cache->cache, bin->key, bin);
 488    }
 489 }
 490
 491 VkResult anv_CreatePipelineCache(
 492     VkDevice                                    _device,
 493     const VkPipelineCacheCreateInfo*            pCreateInfo,
 494     const VkAllocationCallbacks*                pAllocator,
 495     VkPipelineCache*                            pPipelineCache)
 496 {
 497    ANV_FROM_HANDLE(anv_device, device, _device);
 498    struct anv_pipeline_cache *cache;
 499
 500    assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
 501    assert(pCreateInfo->flags == 0);
 502
 503    cache = vk_alloc2(&device->vk.alloc, pAllocator,
 504                        sizeof(*cache), 8,
 505                        VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 506    if (cache == NULL)
 507       return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 508
 509    anv_pipeline_cache_init(cache, device,
 510                            device->physical->instance->pipeline_cache_enabled,
 511                            pCreateInfo->flags & VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT);
 512
 513    if (pCreateInfo->initialDataSize > 0)
 514       anv_pipeline_cache_load(cache,
 515                               pCreateInfo->pInitialData,
 516                               pCreateInfo->initialDataSize);
 517
 518    *pPipelineCache = anv_pipeline_cache_to_handle(cache);
 519
 520    return VK_SUCCESS;
 521 }
 522
 523 void anv_DestroyPipelineCache(
 524     VkDevice                                    _device,
 525     VkPipelineCache                             _cache,
 526     const VkAllocationCallbacks*                pAllocator)
 527 {
 528    ANV_FROM_HANDLE(anv_device, device, _device);
 529    ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
 530
 531    if (!cache)
 532       return;
 533
 534    anv_pipeline_cache_finish(cache);
 535
 536    vk_free2(&device->vk.alloc, pAllocator, cache);
 537 }
 538
 539 VkResult anv_GetPipelineCacheData(
 540     VkDevice                                    _device,
 541     VkPipelineCache                             _cache,
 542     size_t*                                     pDataSize,
 543     void*                                       pData)
 544 {
 545    ANV_FROM_HANDLE(anv_device, device, _device);
 546    ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
 547
 548    struct blob blob;
 549    if (pData) {
 550       blob_init_fixed(&blob, pData, *pDataSize);
 551    } else {
 552       blob_init_fixed(&blob, NULL, SIZE_MAX);
 553    }
 554
 555    struct vk_pipeline_cache_header header = {
 556       .header_size = sizeof(struct vk_pipeline_cache_header),
 557       .header_version = VK_PIPELINE_CACHE_HEADER_VERSION_ONE,
 558       .vendor_id = 0x8086,
 559       .device_id = device->info.chipset_id,
 560    };
 561    memcpy(header.uuid, device->physical->pipeline_cache_uuid, VK_UUID_SIZE);
 562    blob_write_bytes(&blob, &header, sizeof(header));
 563
 564    uint32_t count = 0;
 565    intptr_t count_offset = blob_reserve_uint32(&blob);
 566    if (count_offset < 0) {
 567       *pDataSize = 0;
 568       blob_finish(&blob);
 569       return VK_INCOMPLETE;
 570    }
 571
 572    VkResult result = VK_SUCCESS;
 573    if (cache->cache) {
 574       hash_table_foreach(cache->cache, entry) {
 575          struct anv_shader_bin *shader = entry->data;
 576
 577          size_t save_size = blob.size;
 578          if (!anv_shader_bin_write_to_blob(shader, &blob)) {
 579             /* If it fails reset to the previous size and bail */
 580             blob.size = save_size;
 581             result = VK_INCOMPLETE;
 582             break;
 583          }
 584
 585          count++;
 586       }
 587    }
 588
 589    blob_overwrite_uint32(&blob, count_offset, count);
 590
 591    *pDataSize = blob.size;
 592
 593    blob_finish(&blob);
 594
 595    return result;
 596 }
 597
 598 VkResult anv_MergePipelineCaches(
 599     VkDevice                                    _device,
 600     VkPipelineCache                             destCache,
 601     uint32_t                                    srcCacheCount,
 602     const VkPipelineCache*                      pSrcCaches)
 603 {
 604    ANV_FROM_HANDLE(anv_pipeline_cache, dst, destCache);
 605
 606    if (!dst->cache)
 607       return VK_SUCCESS;
 608
 609    for (uint32_t i = 0; i < srcCacheCount; i++) {
 610       ANV_FROM_HANDLE(anv_pipeline_cache, src, pSrcCaches[i]);
 611       if (!src->cache)
 612          continue;
 613
 614       hash_table_foreach(src->cache, entry) {
 615          struct anv_shader_bin *bin = entry->data;
 616          assert(bin);
 617
 618          if (_mesa_hash_table_search(dst->cache, bin->key))
 619             continue;
 620
 621          anv_shader_bin_ref(bin);
 622          _mesa_hash_table_insert(dst->cache, bin->key, bin);
 623       }
 624    }
 625
 626    return VK_SUCCESS;
 627 }
 628
 629 struct anv_shader_bin *
 630 anv_device_search_for_kernel(struct anv_device *device,
 631                              struct anv_pipeline_cache *cache,
 632                              const void *key_data, uint32_t key_size,
 633                              bool *user_cache_hit)
 634 {
 635    struct anv_shader_bin *bin;
 636
 637    *user_cache_hit = false;
 638
 639    if (cache) {
 640       bin = anv_pipeline_cache_search(cache, key_data, key_size);
 641       if (bin) {
 642          *user_cache_hit = cache != &device->default_pipeline_cache;
 643          return bin;
 644       }
 645    }
 646
 647 #ifdef ENABLE_SHADER_CACHE
 648    struct disk_cache *disk_cache = device->physical->disk_cache;
 649    if (disk_cache && device->physical->instance->pipeline_cache_enabled) {
 650       cache_key cache_key;
 651       disk_cache_compute_key(disk_cache, key_data, key_size, cache_key);
 652
 653       size_t buffer_size;
 654       uint8_t *buffer = disk_cache_get(disk_cache, cache_key, &buffer_size);
 655       if (buffer) {
 656          struct blob_reader blob;
 657          blob_reader_init(&blob, buffer, buffer_size);
 658          bin = anv_shader_bin_create_from_blob(device, &blob);
 659          free(buffer);
 660
 661          if (bin) {
 662             if (cache)
 663                anv_pipeline_cache_add_shader_bin(cache, bin);
 664             return bin;
 665          }
 666       }
 667    }
 668 #endif
 669
 670    return NULL;
 671 }
 672
 673 struct anv_shader_bin *
 674 anv_device_upload_kernel(struct anv_device *device,
 675                          struct anv_pipeline_cache *cache,
 676                          gl_shader_stage stage,
 677                          const void *key_data, uint32_t key_size,
 678                          const void *kernel_data, uint32_t kernel_size,
 679                          const struct brw_stage_prog_data *prog_data,
 680                          uint32_t prog_data_size,
 681                          const struct brw_compile_stats *stats,
 682                          uint32_t num_stats,
 683                          const nir_xfb_info *xfb_info,
 684                          const struct anv_pipeline_bind_map *bind_map)
 685 {
 686    struct anv_shader_bin *bin;
 687    if (cache) {
 688       bin = anv_pipeline_cache_upload_kernel(cache, stage, key_data, key_size,
 689                                              kernel_data, kernel_size,
 690                                              prog_data, prog_data_size,
 691                                              stats, num_stats,
 692                                              xfb_info, bind_map);
 693    } else {
 694       bin = anv_shader_bin_create(device, stage, key_data, key_size,
 695                                   kernel_data, kernel_size,
 696                                   prog_data, prog_data_size,
 697                                   stats, num_stats,
 698                                   xfb_info, bind_map);
 699    }
 700
 701    if (bin == NULL)
 702       return NULL;
 703
 704 #ifdef ENABLE_SHADER_CACHE
 705    struct disk_cache *disk_cache = device->physical->disk_cache;
 706    if (disk_cache) {
 707       struct blob binary;
 708       blob_init(&binary);
 709       if (anv_shader_bin_write_to_blob(bin, &binary)) {
 710          cache_key cache_key;
 711          disk_cache_compute_key(disk_cache, key_data, key_size, cache_key);
 712
 713          disk_cache_put(disk_cache, cache_key, binary.data, binary.size, NULL);
 714       }
 715
 716       blob_finish(&binary);
 717    }
 718 #endif
 719
 720    return bin;
 721 }
 722
 723 struct serialized_nir {
 724    unsigned char sha1_key[20];
 725    size_t size;
 726    char data[0];
 727 };
 728
 729 struct nir_shader *
 730 anv_device_search_for_nir(struct anv_device *device,
 731                           struct anv_pipeline_cache *cache,
 732                           const nir_shader_compiler_options *nir_options,
 733                           unsigned char sha1_key[20],
 734                           void *mem_ctx)
 735 {
 736    if (cache && cache->nir_cache) {
 737       const struct serialized_nir *snir = NULL;
 738
 739       anv_cache_lock(cache);
 740       struct hash_entry *entry =
 741          _mesa_hash_table_search(cache->nir_cache, sha1_key);
 742       if (entry)
 743          snir = entry->data;
 744       anv_cache_unlock(cache);
 745
 746       if (snir) {
 747          struct blob_reader blob;
 748          blob_reader_init(&blob, snir->data, snir->size);
 749
 750          nir_shader *nir = nir_deserialize(mem_ctx, nir_options, &blob);
 751          if (blob.overrun) {
 752             ralloc_free(nir);
 753          } else {
 754             return nir;
 755          }
 756       }
 757    }
 758
 759    return NULL;
 760 }
 761
 762 void
 763 anv_device_upload_nir(struct anv_device *device,
 764                       struct anv_pipeline_cache *cache,
 765                       const struct nir_shader *nir,
 766                       unsigned char sha1_key[20])
 767 {
 768    if (cache && cache->nir_cache) {
 769       anv_cache_lock(cache);
 770       struct hash_entry *entry =
 771          _mesa_hash_table_search(cache->nir_cache, sha1_key);
 772       anv_cache_unlock(cache);
 773       if (entry)
 774          return;
 775
 776       struct blob blob;
 777       blob_init(&blob);
 778
 779       nir_serialize(&blob, nir, false);
 780       if (blob.out_of_memory) {
 781          blob_finish(&blob);
 782          return;
 783       }
 784
 785       anv_cache_lock(cache);
 786       /* Because ralloc isn't thread-safe, we have to do all this inside the
 787        * lock.  We could unlock for the big memcpy but it's probably not worth
 788        * the hassle.
 789        */
 790       entry = _mesa_hash_table_search(cache->nir_cache, sha1_key);
 791       if (entry) {
 792          blob_finish(&blob);
 793          anv_cache_unlock(cache);
 794          return;
 795       }
 796
 797       struct serialized_nir *snir =
 798          ralloc_size(cache->nir_cache, sizeof(*snir) + blob.size);
 799       memcpy(snir->sha1_key, sha1_key, 20);
 800       snir->size = blob.size;
 801       memcpy(snir->data, blob.data, blob.size);
 802
 803       blob_finish(&blob);
 804
 805       _mesa_hash_table_insert(cache->nir_cache, snir->sha1_key, snir);
 806
 807       anv_cache_unlock(cache);
 808    }
 809 }