739b76ce04ff97974b06d99de802a0d321690f8e
[mesa.git] / src / intel / vulkan / anv_pipeline_cache.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/blob.h"
25 #include "util/hash_table.h"
26 #include "util/debug.h"
27 #include "util/disk_cache.h"
28 #include "util/mesa-sha1.h"
29 #include "nir/nir_serialize.h"
30 #include "anv_private.h"
31 #include "nir/nir_xfb_info.h"
32 #include "vulkan/util/vk_util.h"
33
34 struct anv_shader_bin *
35 anv_shader_bin_create(struct anv_device *device,
36 gl_shader_stage stage,
37 const void *key_data, uint32_t key_size,
38 const void *kernel_data, uint32_t kernel_size,
39 const struct brw_stage_prog_data *prog_data_in,
40 uint32_t prog_data_size,
41 const struct brw_compile_stats *stats, uint32_t num_stats,
42 const nir_xfb_info *xfb_info_in,
43 const struct anv_pipeline_bind_map *bind_map)
44 {
45 struct anv_shader_bin *shader;
46 struct anv_shader_bin_key *key;
47 struct brw_stage_prog_data *prog_data;
48 struct brw_shader_reloc *prog_data_relocs;
49 uint32_t *prog_data_param;
50 nir_xfb_info *xfb_info;
51 struct anv_pipeline_binding *surface_to_descriptor, *sampler_to_descriptor;
52
53 ANV_MULTIALLOC(ma);
54 anv_multialloc_add(&ma, &shader, 1);
55 anv_multialloc_add_size(&ma, &key, sizeof(*key) + key_size);
56 anv_multialloc_add_size(&ma, &prog_data, prog_data_size);
57 anv_multialloc_add(&ma, &prog_data_relocs, prog_data_in->num_relocs);
58 anv_multialloc_add(&ma, &prog_data_param, prog_data_in->nr_params);
59 if (xfb_info_in) {
60 uint32_t xfb_info_size = nir_xfb_info_size(xfb_info_in->output_count);
61 anv_multialloc_add_size(&ma, &xfb_info, xfb_info_size);
62 }
63 anv_multialloc_add(&ma, &surface_to_descriptor,
64 bind_map->surface_count);
65 anv_multialloc_add(&ma, &sampler_to_descriptor,
66 bind_map->sampler_count);
67
68 if (!anv_multialloc_alloc(&ma, &device->vk.alloc,
69 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE))
70 return NULL;
71
72 shader->ref_cnt = 1;
73
74 shader->stage = stage;
75
76 key->size = key_size;
77 memcpy(key->data, key_data, key_size);
78 shader->key = key;
79
80 shader->kernel =
81 anv_state_pool_alloc(&device->instruction_state_pool, kernel_size, 64);
82 memcpy(shader->kernel.map, kernel_data, kernel_size);
83 shader->kernel_size = kernel_size;
84
85 memcpy(prog_data, prog_data_in, prog_data_size);
86 typed_memcpy(prog_data_relocs, prog_data_in->relocs,
87 prog_data_in->num_relocs);
88 prog_data->relocs = prog_data_relocs;
89 memset(prog_data_param, 0,
90 prog_data->nr_params * sizeof(*prog_data_param));
91 prog_data->param = prog_data_param;
92 shader->prog_data = prog_data;
93 shader->prog_data_size = prog_data_size;
94
95 assert(num_stats <= ARRAY_SIZE(shader->stats));
96 typed_memcpy(shader->stats, stats, num_stats);
97 shader->num_stats = num_stats;
98
99 if (xfb_info_in) {
100 *xfb_info = *xfb_info_in;
101 typed_memcpy(xfb_info->outputs, xfb_info_in->outputs,
102 xfb_info_in->output_count);
103 shader->xfb_info = xfb_info;
104 } else {
105 shader->xfb_info = NULL;
106 }
107
108 shader->bind_map = *bind_map;
109 typed_memcpy(surface_to_descriptor, bind_map->surface_to_descriptor,
110 bind_map->surface_count);
111 shader->bind_map.surface_to_descriptor = surface_to_descriptor;
112 typed_memcpy(sampler_to_descriptor, bind_map->sampler_to_descriptor,
113 bind_map->sampler_count);
114 shader->bind_map.sampler_to_descriptor = sampler_to_descriptor;
115
116 return shader;
117 }
118
119 void
120 anv_shader_bin_destroy(struct anv_device *device,
121 struct anv_shader_bin *shader)
122 {
123 assert(shader->ref_cnt == 0);
124 anv_state_pool_free(&device->instruction_state_pool, shader->kernel);
125 vk_free(&device->vk.alloc, shader);
126 }
127
128 static bool
129 anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
130 struct blob *blob)
131 {
132 blob_write_uint32(blob, shader->stage);
133
134 blob_write_uint32(blob, shader->key->size);
135 blob_write_bytes(blob, shader->key->data, shader->key->size);
136
137 blob_write_uint32(blob, shader->kernel_size);
138 blob_write_bytes(blob, shader->kernel.map, shader->kernel_size);
139
140 blob_write_uint32(blob, shader->prog_data_size);
141 blob_write_bytes(blob, shader->prog_data, shader->prog_data_size);
142 blob_write_bytes(blob, shader->prog_data->relocs,
143 shader->prog_data->num_relocs *
144 sizeof(shader->prog_data->relocs[0]));
145
146 blob_write_uint32(blob, shader->num_stats);
147 blob_write_bytes(blob, shader->stats,
148 shader->num_stats * sizeof(shader->stats[0]));
149
150 if (shader->xfb_info) {
151 uint32_t xfb_info_size =
152 nir_xfb_info_size(shader->xfb_info->output_count);
153 blob_write_uint32(blob, xfb_info_size);
154 blob_write_bytes(blob, shader->xfb_info, xfb_info_size);
155 } else {
156 blob_write_uint32(blob, 0);
157 }
158
159 blob_write_bytes(blob, shader->bind_map.surface_sha1,
160 sizeof(shader->bind_map.surface_sha1));
161 blob_write_bytes(blob, shader->bind_map.sampler_sha1,
162 sizeof(shader->bind_map.sampler_sha1));
163 blob_write_bytes(blob, shader->bind_map.push_sha1,
164 sizeof(shader->bind_map.push_sha1));
165 blob_write_uint32(blob, shader->bind_map.surface_count);
166 blob_write_uint32(blob, shader->bind_map.sampler_count);
167 blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
168 shader->bind_map.surface_count *
169 sizeof(*shader->bind_map.surface_to_descriptor));
170 blob_write_bytes(blob, shader->bind_map.sampler_to_descriptor,
171 shader->bind_map.sampler_count *
172 sizeof(*shader->bind_map.sampler_to_descriptor));
173 blob_write_bytes(blob, shader->bind_map.push_ranges,
174 sizeof(shader->bind_map.push_ranges));
175
176 return !blob->out_of_memory;
177 }
178
179 static struct anv_shader_bin *
180 anv_shader_bin_create_from_blob(struct anv_device *device,
181 struct blob_reader *blob)
182 {
183 gl_shader_stage stage = blob_read_uint32(blob);
184
185 uint32_t key_size = blob_read_uint32(blob);
186 const void *key_data = blob_read_bytes(blob, key_size);
187
188 uint32_t kernel_size = blob_read_uint32(blob);
189 const void *kernel_data = blob_read_bytes(blob, kernel_size);
190
191 uint32_t prog_data_size = blob_read_uint32(blob);
192 const void *prog_data_bytes = blob_read_bytes(blob, prog_data_size);
193 if (blob->overrun)
194 return NULL;
195
196 union brw_any_prog_data prog_data;
197 memcpy(&prog_data, prog_data_bytes,
198 MIN2(sizeof(prog_data), prog_data_size));
199 prog_data.base.relocs =
200 blob_read_bytes(blob, prog_data.base.num_relocs *
201 sizeof(prog_data.base.relocs[0]));
202
203 uint32_t num_stats = blob_read_uint32(blob);
204 const struct brw_compile_stats *stats =
205 blob_read_bytes(blob, num_stats * sizeof(stats[0]));
206
207 const nir_xfb_info *xfb_info = NULL;
208 uint32_t xfb_size = blob_read_uint32(blob);
209 if (xfb_size)
210 xfb_info = blob_read_bytes(blob, xfb_size);
211
212 struct anv_pipeline_bind_map bind_map;
213 blob_copy_bytes(blob, bind_map.surface_sha1, sizeof(bind_map.surface_sha1));
214 blob_copy_bytes(blob, bind_map.sampler_sha1, sizeof(bind_map.sampler_sha1));
215 blob_copy_bytes(blob, bind_map.push_sha1, sizeof(bind_map.push_sha1));
216 bind_map.surface_count = blob_read_uint32(blob);
217 bind_map.sampler_count = blob_read_uint32(blob);
218 bind_map.surface_to_descriptor = (void *)
219 blob_read_bytes(blob, bind_map.surface_count *
220 sizeof(*bind_map.surface_to_descriptor));
221 bind_map.sampler_to_descriptor = (void *)
222 blob_read_bytes(blob, bind_map.sampler_count *
223 sizeof(*bind_map.sampler_to_descriptor));
224 blob_copy_bytes(blob, bind_map.push_ranges, sizeof(bind_map.push_ranges));
225
226 if (blob->overrun)
227 return NULL;
228
229 return anv_shader_bin_create(device, stage,
230 key_data, key_size,
231 kernel_data, kernel_size,
232 &prog_data.base, prog_data_size,
233 stats, num_stats, xfb_info, &bind_map);
234 }
235
236 /* Remaining work:
237 *
238 * - Compact binding table layout so it's tight and not dependent on
239 * descriptor set layout.
240 *
241 * - Review prog_data struct for size and cacheability: struct
242 * brw_stage_prog_data has binding_table which uses a lot of uint32_t for 8
243 * bit quantities etc; use bit fields for all bools, eg dual_src_blend.
244 */
245
246 static uint32_t
247 shader_bin_key_hash_func(const void *void_key)
248 {
249 const struct anv_shader_bin_key *key = void_key;
250 return _mesa_hash_data(key->data, key->size);
251 }
252
253 static bool
254 shader_bin_key_compare_func(const void *void_a, const void *void_b)
255 {
256 const struct anv_shader_bin_key *a = void_a, *b = void_b;
257 if (a->size != b->size)
258 return false;
259
260 return memcmp(a->data, b->data, a->size) == 0;
261 }
262
263 static uint32_t
264 sha1_hash_func(const void *sha1)
265 {
266 return _mesa_hash_data(sha1, 20);
267 }
268
269 static bool
270 sha1_compare_func(const void *sha1_a, const void *sha1_b)
271 {
272 return memcmp(sha1_a, sha1_b, 20) == 0;
273 }
274
275 void
276 anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
277 struct anv_device *device,
278 bool cache_enabled,
279 bool external_sync)
280 {
281 vk_object_base_init(&device->vk, &cache->base,
282 VK_OBJECT_TYPE_PIPELINE_CACHE);
283 cache->device = device;
284 cache->external_sync = external_sync;
285 pthread_mutex_init(&cache->mutex, NULL);
286
287 if (cache_enabled) {
288 cache->cache = _mesa_hash_table_create(NULL, shader_bin_key_hash_func,
289 shader_bin_key_compare_func);
290 cache->nir_cache = _mesa_hash_table_create(NULL, sha1_hash_func,
291 sha1_compare_func);
292 } else {
293 cache->cache = NULL;
294 cache->nir_cache = NULL;
295 }
296 }
297
298 void
299 anv_pipeline_cache_finish(struct anv_pipeline_cache *cache)
300 {
301 pthread_mutex_destroy(&cache->mutex);
302
303 if (cache->cache) {
304 /* This is a bit unfortunate. In order to keep things from randomly
305 * going away, the shader cache has to hold a reference to all shader
306 * binaries it contains. We unref them when we destroy the cache.
307 */
308 hash_table_foreach(cache->cache, entry)
309 anv_shader_bin_unref(cache->device, entry->data);
310
311 _mesa_hash_table_destroy(cache->cache, NULL);
312 }
313
314 if (cache->nir_cache) {
315 hash_table_foreach(cache->nir_cache, entry)
316 ralloc_free(entry->data);
317
318 _mesa_hash_table_destroy(cache->nir_cache, NULL);
319 }
320
321 vk_object_base_finish(&cache->base);
322 }
323
324 static struct anv_shader_bin *
325 anv_pipeline_cache_search_locked(struct anv_pipeline_cache *cache,
326 const void *key_data, uint32_t key_size)
327 {
328 uint32_t vla[1 + DIV_ROUND_UP(key_size, sizeof(uint32_t))];
329 struct anv_shader_bin_key *key = (void *)vla;
330 key->size = key_size;
331 memcpy(key->data, key_data, key_size);
332
333 struct hash_entry *entry = _mesa_hash_table_search(cache->cache, key);
334 if (entry)
335 return entry->data;
336 else
337 return NULL;
338 }
339
340 static inline void
341 anv_cache_lock(struct anv_pipeline_cache *cache)
342 {
343 if (!cache->external_sync)
344 pthread_mutex_lock(&cache->mutex);
345 }
346
347 static inline void
348 anv_cache_unlock(struct anv_pipeline_cache *cache)
349 {
350 if (!cache->external_sync)
351 pthread_mutex_unlock(&cache->mutex);
352 }
353
354 struct anv_shader_bin *
355 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
356 const void *key_data, uint32_t key_size)
357 {
358 if (!cache->cache)
359 return NULL;
360
361 anv_cache_lock(cache);
362
363 struct anv_shader_bin *shader =
364 anv_pipeline_cache_search_locked(cache, key_data, key_size);
365
366 anv_cache_unlock(cache);
367
368 /* We increment refcount before handing it to the caller */
369 if (shader)
370 anv_shader_bin_ref(shader);
371
372 return shader;
373 }
374
375 static void
376 anv_pipeline_cache_add_shader_bin(struct anv_pipeline_cache *cache,
377 struct anv_shader_bin *bin)
378 {
379 if (!cache->cache)
380 return;
381
382 anv_cache_lock(cache);
383
384 struct hash_entry *entry = _mesa_hash_table_search(cache->cache, bin->key);
385 if (entry == NULL) {
386 /* Take a reference for the cache */
387 anv_shader_bin_ref(bin);
388 _mesa_hash_table_insert(cache->cache, bin->key, bin);
389 }
390
391 anv_cache_unlock(cache);
392 }
393
394 static struct anv_shader_bin *
395 anv_pipeline_cache_add_shader_locked(struct anv_pipeline_cache *cache,
396 gl_shader_stage stage,
397 const void *key_data, uint32_t key_size,
398 const void *kernel_data,
399 uint32_t kernel_size,
400 const struct brw_stage_prog_data *prog_data,
401 uint32_t prog_data_size,
402 const struct brw_compile_stats *stats,
403 uint32_t num_stats,
404 const nir_xfb_info *xfb_info,
405 const struct anv_pipeline_bind_map *bind_map)
406 {
407 struct anv_shader_bin *shader =
408 anv_pipeline_cache_search_locked(cache, key_data, key_size);
409 if (shader)
410 return shader;
411
412 struct anv_shader_bin *bin =
413 anv_shader_bin_create(cache->device, stage,
414 key_data, key_size,
415 kernel_data, kernel_size,
416 prog_data, prog_data_size,
417 stats, num_stats, xfb_info, bind_map);
418 if (!bin)
419 return NULL;
420
421 _mesa_hash_table_insert(cache->cache, bin->key, bin);
422
423 return bin;
424 }
425
426 struct anv_shader_bin *
427 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
428 gl_shader_stage stage,
429 const void *key_data, uint32_t key_size,
430 const void *kernel_data, uint32_t kernel_size,
431 const struct brw_stage_prog_data *prog_data,
432 uint32_t prog_data_size,
433 const struct brw_compile_stats *stats,
434 uint32_t num_stats,
435 const nir_xfb_info *xfb_info,
436 const struct anv_pipeline_bind_map *bind_map)
437 {
438 if (cache->cache) {
439 anv_cache_lock(cache);
440
441 struct anv_shader_bin *bin =
442 anv_pipeline_cache_add_shader_locked(cache, stage, key_data, key_size,
443 kernel_data, kernel_size,
444 prog_data, prog_data_size,
445 stats, num_stats,
446 xfb_info, bind_map);
447
448 anv_cache_unlock(cache);
449
450 /* We increment refcount before handing it to the caller */
451 if (bin)
452 anv_shader_bin_ref(bin);
453
454 return bin;
455 } else {
456 /* In this case, we're not caching it so the caller owns it entirely */
457 return anv_shader_bin_create(cache->device, stage,
458 key_data, key_size,
459 kernel_data, kernel_size,
460 prog_data, prog_data_size,
461 stats, num_stats,
462 xfb_info, bind_map);
463 }
464 }
465
466 static void
467 anv_pipeline_cache_load(struct anv_pipeline_cache *cache,
468 const void *data, size_t size)
469 {
470 struct anv_device *device = cache->device;
471 struct anv_physical_device *pdevice = device->physical;
472
473 if (cache->cache == NULL)
474 return;
475
476 struct blob_reader blob;
477 blob_reader_init(&blob, data, size);
478
479 struct vk_pipeline_cache_header header;
480 blob_copy_bytes(&blob, &header, sizeof(header));
481 uint32_t count = blob_read_uint32(&blob);
482 if (blob.overrun)
483 return;
484
485 if (header.header_size < sizeof(header))
486 return;
487 if (header.header_version != VK_PIPELINE_CACHE_HEADER_VERSION_ONE)
488 return;
489 if (header.vendor_id != 0x8086)
490 return;
491 if (header.device_id != device->info.chipset_id)
492 return;
493 if (memcmp(header.uuid, pdevice->pipeline_cache_uuid, VK_UUID_SIZE) != 0)
494 return;
495
496 for (uint32_t i = 0; i < count; i++) {
497 struct anv_shader_bin *bin =
498 anv_shader_bin_create_from_blob(device, &blob);
499 if (!bin)
500 break;
501 _mesa_hash_table_insert(cache->cache, bin->key, bin);
502 }
503 }
504
505 VkResult anv_CreatePipelineCache(
506 VkDevice _device,
507 const VkPipelineCacheCreateInfo* pCreateInfo,
508 const VkAllocationCallbacks* pAllocator,
509 VkPipelineCache* pPipelineCache)
510 {
511 ANV_FROM_HANDLE(anv_device, device, _device);
512 struct anv_pipeline_cache *cache;
513
514 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
515 assert(pCreateInfo->flags == 0);
516
517 cache = vk_alloc2(&device->vk.alloc, pAllocator,
518 sizeof(*cache), 8,
519 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
520 if (cache == NULL)
521 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
522
523 anv_pipeline_cache_init(cache, device,
524 device->physical->instance->pipeline_cache_enabled,
525 pCreateInfo->flags & VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT);
526
527 if (pCreateInfo->initialDataSize > 0)
528 anv_pipeline_cache_load(cache,
529 pCreateInfo->pInitialData,
530 pCreateInfo->initialDataSize);
531
532 *pPipelineCache = anv_pipeline_cache_to_handle(cache);
533
534 return VK_SUCCESS;
535 }
536
537 void anv_DestroyPipelineCache(
538 VkDevice _device,
539 VkPipelineCache _cache,
540 const VkAllocationCallbacks* pAllocator)
541 {
542 ANV_FROM_HANDLE(anv_device, device, _device);
543 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
544
545 if (!cache)
546 return;
547
548 anv_pipeline_cache_finish(cache);
549
550 vk_free2(&device->vk.alloc, pAllocator, cache);
551 }
552
553 VkResult anv_GetPipelineCacheData(
554 VkDevice _device,
555 VkPipelineCache _cache,
556 size_t* pDataSize,
557 void* pData)
558 {
559 ANV_FROM_HANDLE(anv_device, device, _device);
560 ANV_FROM_HANDLE(anv_pipeline_cache, cache, _cache);
561
562 struct blob blob;
563 if (pData) {
564 blob_init_fixed(&blob, pData, *pDataSize);
565 } else {
566 blob_init_fixed(&blob, NULL, SIZE_MAX);
567 }
568
569 struct vk_pipeline_cache_header header = {
570 .header_size = sizeof(struct vk_pipeline_cache_header),
571 .header_version = VK_PIPELINE_CACHE_HEADER_VERSION_ONE,
572 .vendor_id = 0x8086,
573 .device_id = device->info.chipset_id,
574 };
575 memcpy(header.uuid, device->physical->pipeline_cache_uuid, VK_UUID_SIZE);
576 blob_write_bytes(&blob, &header, sizeof(header));
577
578 uint32_t count = 0;
579 intptr_t count_offset = blob_reserve_uint32(&blob);
580 if (count_offset < 0) {
581 *pDataSize = 0;
582 blob_finish(&blob);
583 return VK_INCOMPLETE;
584 }
585
586 VkResult result = VK_SUCCESS;
587 if (cache->cache) {
588 hash_table_foreach(cache->cache, entry) {
589 struct anv_shader_bin *shader = entry->data;
590
591 size_t save_size = blob.size;
592 if (!anv_shader_bin_write_to_blob(shader, &blob)) {
593 /* If it fails reset to the previous size and bail */
594 blob.size = save_size;
595 result = VK_INCOMPLETE;
596 break;
597 }
598
599 count++;
600 }
601 }
602
603 blob_overwrite_uint32(&blob, count_offset, count);
604
605 *pDataSize = blob.size;
606
607 blob_finish(&blob);
608
609 return result;
610 }
611
612 VkResult anv_MergePipelineCaches(
613 VkDevice _device,
614 VkPipelineCache destCache,
615 uint32_t srcCacheCount,
616 const VkPipelineCache* pSrcCaches)
617 {
618 ANV_FROM_HANDLE(anv_pipeline_cache, dst, destCache);
619
620 if (!dst->cache)
621 return VK_SUCCESS;
622
623 for (uint32_t i = 0; i < srcCacheCount; i++) {
624 ANV_FROM_HANDLE(anv_pipeline_cache, src, pSrcCaches[i]);
625 if (!src->cache)
626 continue;
627
628 hash_table_foreach(src->cache, entry) {
629 struct anv_shader_bin *bin = entry->data;
630 assert(bin);
631
632 if (_mesa_hash_table_search(dst->cache, bin->key))
633 continue;
634
635 anv_shader_bin_ref(bin);
636 _mesa_hash_table_insert(dst->cache, bin->key, bin);
637 }
638 }
639
640 return VK_SUCCESS;
641 }
642
643 struct anv_shader_bin *
644 anv_device_search_for_kernel(struct anv_device *device,
645 struct anv_pipeline_cache *cache,
646 const void *key_data, uint32_t key_size,
647 bool *user_cache_hit)
648 {
649 struct anv_shader_bin *bin;
650
651 *user_cache_hit = false;
652
653 if (cache) {
654 bin = anv_pipeline_cache_search(cache, key_data, key_size);
655 if (bin) {
656 *user_cache_hit = cache != &device->default_pipeline_cache;
657 return bin;
658 }
659 }
660
661 #ifdef ENABLE_SHADER_CACHE
662 struct disk_cache *disk_cache = device->physical->disk_cache;
663 if (disk_cache && device->physical->instance->pipeline_cache_enabled) {
664 cache_key cache_key;
665 disk_cache_compute_key(disk_cache, key_data, key_size, cache_key);
666
667 size_t buffer_size;
668 uint8_t *buffer = disk_cache_get(disk_cache, cache_key, &buffer_size);
669 if (buffer) {
670 struct blob_reader blob;
671 blob_reader_init(&blob, buffer, buffer_size);
672 bin = anv_shader_bin_create_from_blob(device, &blob);
673 free(buffer);
674
675 if (bin) {
676 if (cache)
677 anv_pipeline_cache_add_shader_bin(cache, bin);
678 return bin;
679 }
680 }
681 }
682 #endif
683
684 return NULL;
685 }
686
687 struct anv_shader_bin *
688 anv_device_upload_kernel(struct anv_device *device,
689 struct anv_pipeline_cache *cache,
690 gl_shader_stage stage,
691 const void *key_data, uint32_t key_size,
692 const void *kernel_data, uint32_t kernel_size,
693 const struct brw_stage_prog_data *prog_data,
694 uint32_t prog_data_size,
695 const struct brw_compile_stats *stats,
696 uint32_t num_stats,
697 const nir_xfb_info *xfb_info,
698 const struct anv_pipeline_bind_map *bind_map)
699 {
700 struct anv_shader_bin *bin;
701 if (cache) {
702 bin = anv_pipeline_cache_upload_kernel(cache, stage, key_data, key_size,
703 kernel_data, kernel_size,
704 prog_data, prog_data_size,
705 stats, num_stats,
706 xfb_info, bind_map);
707 } else {
708 bin = anv_shader_bin_create(device, stage, key_data, key_size,
709 kernel_data, kernel_size,
710 prog_data, prog_data_size,
711 stats, num_stats,
712 xfb_info, bind_map);
713 }
714
715 if (bin == NULL)
716 return NULL;
717
718 #ifdef ENABLE_SHADER_CACHE
719 struct disk_cache *disk_cache = device->physical->disk_cache;
720 if (disk_cache) {
721 struct blob binary;
722 blob_init(&binary);
723 if (anv_shader_bin_write_to_blob(bin, &binary)) {
724 cache_key cache_key;
725 disk_cache_compute_key(disk_cache, key_data, key_size, cache_key);
726
727 disk_cache_put(disk_cache, cache_key, binary.data, binary.size, NULL);
728 }
729
730 blob_finish(&binary);
731 }
732 #endif
733
734 return bin;
735 }
736
737 struct serialized_nir {
738 unsigned char sha1_key[20];
739 size_t size;
740 char data[0];
741 };
742
743 struct nir_shader *
744 anv_device_search_for_nir(struct anv_device *device,
745 struct anv_pipeline_cache *cache,
746 const nir_shader_compiler_options *nir_options,
747 unsigned char sha1_key[20],
748 void *mem_ctx)
749 {
750 if (cache && cache->nir_cache) {
751 const struct serialized_nir *snir = NULL;
752
753 anv_cache_lock(cache);
754 struct hash_entry *entry =
755 _mesa_hash_table_search(cache->nir_cache, sha1_key);
756 if (entry)
757 snir = entry->data;
758 anv_cache_unlock(cache);
759
760 if (snir) {
761 struct blob_reader blob;
762 blob_reader_init(&blob, snir->data, snir->size);
763
764 nir_shader *nir = nir_deserialize(mem_ctx, nir_options, &blob);
765 if (blob.overrun) {
766 ralloc_free(nir);
767 } else {
768 return nir;
769 }
770 }
771 }
772
773 return NULL;
774 }
775
776 void
777 anv_device_upload_nir(struct anv_device *device,
778 struct anv_pipeline_cache *cache,
779 const struct nir_shader *nir,
780 unsigned char sha1_key[20])
781 {
782 if (cache && cache->nir_cache) {
783 anv_cache_lock(cache);
784 struct hash_entry *entry =
785 _mesa_hash_table_search(cache->nir_cache, sha1_key);
786 anv_cache_unlock(cache);
787 if (entry)
788 return;
789
790 struct blob blob;
791 blob_init(&blob);
792
793 nir_serialize(&blob, nir, false);
794 if (blob.out_of_memory) {
795 blob_finish(&blob);
796 return;
797 }
798
799 anv_cache_lock(cache);
800 /* Because ralloc isn't thread-safe, we have to do all this inside the
801 * lock. We could unlock for the big memcpy but it's probably not worth
802 * the hassle.
803 */
804 entry = _mesa_hash_table_search(cache->nir_cache, sha1_key);
805 if (entry) {
806 blob_finish(&blob);
807 anv_cache_unlock(cache);
808 return;
809 }
810
811 struct serialized_nir *snir =
812 ralloc_size(cache->nir_cache, sizeof(*snir) + blob.size);
813 memcpy(snir->sha1_key, sha1_key, 20);
814 snir->size = blob.size;
815 memcpy(snir->data, blob.data, blob.size);
816
817 blob_finish(&blob);
818
819 _mesa_hash_table_insert(cache->nir_cache, snir->sha1_key, snir);
820
821 anv_cache_unlock(cache);
822 }
823 }