2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "anv_private.h"
30 * - Compact binding table layout so it's tight and not dependent on
31 * descriptor set layout.
33 * - Review prog_data struct for size and cacheability: struct
34 * brw_stage_prog_data has binding_table which uses a lot of uint32_t for 8
35 * bit quantities etc; param, pull_param, and image_params are pointers, we
36 * just need the compation map. use bit fields for all bools, eg
41 anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
42 struct anv_device
*device
)
44 cache
->device
= device
;
45 anv_state_stream_init(&cache
->program_stream
,
46 &device
->instruction_block_pool
);
47 pthread_mutex_init(&cache
->mutex
, NULL
);
49 cache
->kernel_count
= 0;
50 cache
->total_size
= 0;
51 cache
->table_size
= 1024;
52 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
53 cache
->hash_table
= malloc(byte_size
);
55 /* We don't consider allocation failure fatal, we just start with a 0-sized
57 if (cache
->hash_table
== NULL
)
58 cache
->table_size
= 0;
60 memset(cache
->hash_table
, 0xff, byte_size
);
64 anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
)
66 anv_state_stream_finish(&cache
->program_stream
);
67 pthread_mutex_destroy(&cache
->mutex
);
68 free(cache
->hash_table
);
72 unsigned char sha1
[20];
73 uint32_t prog_data_size
;
77 /* kernel follows prog_data at next 64 byte aligned address */
81 entry_size(struct cache_entry
*entry
)
83 /* This returns the number of bytes needed to serialize an entry, which
84 * doesn't include the alignment padding bytes.
87 return sizeof(*entry
) + entry
->prog_data_size
+ entry
->kernel_size
;
91 anv_hash_shader(unsigned char *hash
, const void *key
, size_t key_size
,
92 struct anv_shader_module
*module
,
93 const char *entrypoint
,
94 const VkSpecializationInfo
*spec_info
)
96 struct mesa_sha1
*ctx
;
98 ctx
= _mesa_sha1_init();
99 _mesa_sha1_update(ctx
, key
, key_size
);
100 _mesa_sha1_update(ctx
, module
->sha1
, sizeof(module
->sha1
));
101 _mesa_sha1_update(ctx
, entrypoint
, strlen(entrypoint
));
102 /* hash in shader stage, pipeline layout? */
104 _mesa_sha1_update(ctx
, spec_info
->pMapEntries
,
105 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
106 _mesa_sha1_update(ctx
, spec_info
->pData
, spec_info
->dataSize
);
108 _mesa_sha1_final(ctx
, hash
);
112 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
113 const unsigned char *sha1
,
114 const struct brw_stage_prog_data
**prog_data
)
116 const uint32_t mask
= cache
->table_size
- 1;
117 const uint32_t start
= (*(uint32_t *) sha1
);
119 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
120 const uint32_t index
= (start
+ i
) & mask
;
121 const uint32_t offset
= cache
->hash_table
[index
];
126 struct cache_entry
*entry
=
127 cache
->program_stream
.block_pool
->map
+ offset
;
128 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
130 *prog_data
= (const struct brw_stage_prog_data
*) entry
->prog_data
;
132 const uint32_t preamble_size
=
133 align_u32(sizeof(*entry
) + entry
->prog_data_size
, 64);
135 return offset
+ preamble_size
;
143 anv_pipeline_cache_add_entry(struct anv_pipeline_cache
*cache
,
144 struct cache_entry
*entry
, uint32_t entry_offset
)
146 const uint32_t mask
= cache
->table_size
- 1;
147 const uint32_t start
= (*(uint32_t *) entry
->sha1
);
149 /* We'll always be able to insert when we get here. */
150 assert(cache
->kernel_count
< cache
->table_size
/ 2);
152 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
153 const uint32_t index
= (start
+ i
) & mask
;
154 if (cache
->hash_table
[index
] == ~0) {
155 cache
->hash_table
[index
] = entry_offset
;
160 cache
->total_size
+= entry_size(entry
);
161 cache
->kernel_count
++;
165 anv_pipeline_cache_grow(struct anv_pipeline_cache
*cache
)
167 const uint32_t table_size
= cache
->table_size
* 2;
168 const uint32_t old_table_size
= cache
->table_size
;
169 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
171 uint32_t *old_table
= cache
->hash_table
;
173 table
= malloc(byte_size
);
175 return VK_ERROR_OUT_OF_HOST_MEMORY
;
177 cache
->hash_table
= table
;
178 cache
->table_size
= table_size
;
179 cache
->kernel_count
= 0;
180 cache
->total_size
= 0;
182 memset(cache
->hash_table
, 0xff, byte_size
);
183 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
184 const uint32_t offset
= old_table
[i
];
188 struct cache_entry
*entry
=
189 cache
->program_stream
.block_pool
->map
+ offset
;
190 anv_pipeline_cache_add_entry(cache
, entry
, offset
);
199 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
200 const unsigned char *sha1
,
201 const void *kernel
, size_t kernel_size
,
202 const struct brw_stage_prog_data
**prog_data
,
203 size_t prog_data_size
)
205 pthread_mutex_lock(&cache
->mutex
);
206 struct cache_entry
*entry
;
208 const uint32_t preamble_size
=
209 align_u32(sizeof(*entry
) + prog_data_size
, 64);
211 const uint32_t size
= preamble_size
+ kernel_size
;
213 assert(size
< cache
->program_stream
.block_pool
->block_size
);
214 const struct anv_state state
=
215 anv_state_stream_alloc(&cache
->program_stream
, size
, 64);
218 entry
->prog_data_size
= prog_data_size
;
219 memcpy(entry
->prog_data
, *prog_data
, prog_data_size
);
220 *prog_data
= (const struct brw_stage_prog_data
*) entry
->prog_data
;
221 entry
->kernel_size
= kernel_size
;
223 if (sha1
&& env_var_as_boolean("ANV_ENABLE_PIPELINE_CACHE", false)) {
224 assert(anv_pipeline_cache_search(cache
, sha1
, NULL
) == NO_KERNEL
);
226 memcpy(entry
->sha1
, sha1
, sizeof(entry
->sha1
));
227 if (cache
->kernel_count
== cache
->table_size
/ 2)
228 anv_pipeline_cache_grow(cache
);
230 /* Failing to grow that hash table isn't fatal, but may mean we don't
231 * have enough space to add this new kernel. Only add it if there's room.
233 if (cache
->kernel_count
< cache
->table_size
/ 2)
234 anv_pipeline_cache_add_entry(cache
, entry
, state
.offset
);
237 pthread_mutex_unlock(&cache
->mutex
);
239 memcpy(state
.map
+ preamble_size
, kernel
, kernel_size
);
241 if (!cache
->device
->info
.has_llc
)
242 anv_state_clflush(state
);
244 return state
.offset
+ preamble_size
;
247 struct cache_header
{
248 uint32_t header_size
;
249 uint32_t header_version
;
252 uint8_t uuid
[VK_UUID_SIZE
];
256 anv_pipeline_cache_load(struct anv_pipeline_cache
*cache
,
257 const void *data
, size_t size
)
259 struct anv_device
*device
= cache
->device
;
260 struct cache_header header
;
261 uint8_t uuid
[VK_UUID_SIZE
];
263 if (size
< sizeof(header
))
265 memcpy(&header
, data
, sizeof(header
));
266 if (header
.header_size
< sizeof(header
))
268 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
270 if (header
.vendor_id
!= 0x8086)
272 if (header
.device_id
!= device
->chipset_id
)
274 anv_device_get_cache_uuid(uuid
);
275 if (memcmp(header
.uuid
, uuid
, VK_UUID_SIZE
) != 0)
278 const void *end
= data
+ size
;
279 const void *p
= data
+ header
.header_size
;
282 /* The kernels aren't 64 byte aligned in the serialized format so
283 * they're always right after the prog_data.
285 const struct cache_entry
*entry
= p
;
286 const void *kernel
= &entry
->prog_data
[entry
->prog_data_size
];
288 const struct brw_stage_prog_data
*prog_data
=
289 (const struct brw_stage_prog_data
*) entry
->prog_data
;
291 anv_pipeline_cache_upload_kernel(cache
, entry
->sha1
,
292 kernel
, entry
->kernel_size
,
294 entry
->prog_data_size
);
295 p
= kernel
+ entry
->kernel_size
;
299 VkResult
anv_CreatePipelineCache(
301 const VkPipelineCacheCreateInfo
* pCreateInfo
,
302 const VkAllocationCallbacks
* pAllocator
,
303 VkPipelineCache
* pPipelineCache
)
305 ANV_FROM_HANDLE(anv_device
, device
, _device
);
306 struct anv_pipeline_cache
*cache
;
308 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
309 assert(pCreateInfo
->flags
== 0);
311 cache
= anv_alloc2(&device
->alloc
, pAllocator
,
313 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
315 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
317 anv_pipeline_cache_init(cache
, device
);
319 if (pCreateInfo
->initialDataSize
> 0)
320 anv_pipeline_cache_load(cache
,
321 pCreateInfo
->pInitialData
,
322 pCreateInfo
->initialDataSize
);
324 *pPipelineCache
= anv_pipeline_cache_to_handle(cache
);
329 void anv_DestroyPipelineCache(
331 VkPipelineCache _cache
,
332 const VkAllocationCallbacks
* pAllocator
)
334 ANV_FROM_HANDLE(anv_device
, device
, _device
);
335 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
337 anv_pipeline_cache_finish(cache
);
339 anv_free2(&device
->alloc
, pAllocator
, cache
);
342 VkResult
anv_GetPipelineCacheData(
344 VkPipelineCache _cache
,
348 ANV_FROM_HANDLE(anv_device
, device
, _device
);
349 ANV_FROM_HANDLE(anv_pipeline_cache
, cache
, _cache
);
350 struct cache_header
*header
;
352 const size_t size
= sizeof(*header
) + cache
->total_size
;
359 if (*pDataSize
< sizeof(*header
)) {
361 return VK_INCOMPLETE
;
364 void *p
= pData
, *end
= pData
+ *pDataSize
;
366 header
->header_size
= sizeof(*header
);
367 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
368 header
->vendor_id
= 0x8086;
369 header
->device_id
= device
->chipset_id
;
370 anv_device_get_cache_uuid(header
->uuid
);
371 p
+= header
->header_size
;
373 struct cache_entry
*entry
;
374 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
375 if (cache
->hash_table
[i
] == ~0)
378 entry
= cache
->program_stream
.block_pool
->map
+ cache
->hash_table
[i
];
379 if (end
< p
+ entry_size(entry
))
382 memcpy(p
, entry
, sizeof(*entry
) + entry
->prog_data_size
);
383 p
+= sizeof(*entry
) + entry
->prog_data_size
;
385 void *kernel
= (void *) entry
+
386 align_u32(sizeof(*entry
) + entry
->prog_data_size
, 64);
388 memcpy(p
, kernel
, entry
->kernel_size
);
389 p
+= entry
->kernel_size
;
392 *pDataSize
= p
- pData
;
398 anv_pipeline_cache_merge(struct anv_pipeline_cache
*dst
,
399 struct anv_pipeline_cache
*src
)
401 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
402 if (src
->hash_table
[i
] == ~0)
405 struct cache_entry
*entry
=
406 src
->program_stream
.block_pool
->map
+ src
->hash_table
[i
];
408 if (anv_pipeline_cache_search(dst
, entry
->sha1
, NULL
) != NO_KERNEL
)
411 const void *kernel
= (void *) entry
+
412 align_u32(sizeof(*entry
) + entry
->prog_data_size
, 64);
413 const struct brw_stage_prog_data
*prog_data
=
414 (const struct brw_stage_prog_data
*) entry
->prog_data
;
416 anv_pipeline_cache_upload_kernel(dst
, entry
->sha1
,
417 kernel
, entry
->kernel_size
,
418 &prog_data
, entry
->prog_data_size
);
422 VkResult
anv_MergePipelineCaches(
424 VkPipelineCache destCache
,
425 uint32_t srcCacheCount
,
426 const VkPipelineCache
* pSrcCaches
)
428 ANV_FROM_HANDLE(anv_pipeline_cache
, dst
, destCache
);
430 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
431 ANV_FROM_HANDLE(anv_pipeline_cache
, src
, pSrcCaches
[i
]);
433 anv_pipeline_cache_merge(dst
, src
);