anv: fix alignments for uniform buffers
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include "drm-uapi/i915_drm.h"
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #ifndef NDEBUG
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
41 #endif
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
61 #include "util/vma.h"
62 #include "util/xmlconfig.h"
63 #include "vk_alloc.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 struct anv_batch;
75 struct anv_buffer;
76 struct anv_buffer_view;
77 struct anv_image_view;
78 struct anv_instance;
79
80 struct gen_aux_map_context;
81 struct gen_perf_config;
82
83 #include <vulkan/vulkan.h>
84 #include <vulkan/vulkan_intel.h>
85 #include <vulkan/vk_icd.h>
86
87 #include "anv_android.h"
88 #include "anv_entrypoints.h"
89 #include "anv_extensions.h"
90 #include "isl/isl.h"
91
92 #include "dev/gen_debug.h"
93 #include "common/intel_log.h"
94 #include "wsi_common.h"
95
96 #define NSEC_PER_SEC 1000000000ull
97
98 /* anv Virtual Memory Layout
99 * =========================
100 *
101 * When the anv driver is determining the virtual graphics addresses of memory
102 * objects itself using the softpin mechanism, the following memory ranges
103 * will be used.
104 *
105 * Three special considerations to notice:
106 *
107 * (1) the dynamic state pool is located within the same 4 GiB as the low
108 * heap. This is to work around a VF cache issue described in a comment in
109 * anv_physical_device_init_heaps.
110 *
111 * (2) the binding table pool is located at lower addresses than the surface
112 * state pool, within a 4 GiB range. This allows surface state base addresses
113 * to cover both binding tables (16 bit offsets) and surface states (32 bit
114 * offsets).
115 *
116 * (3) the last 4 GiB of the address space is withheld from the high
117 * heap. Various hardware units will read past the end of an object for
118 * various reasons. This healthy margin prevents reads from wrapping around
119 * 48-bit addresses.
120 */
121 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
122 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
123 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
124 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
125 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
126 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
127 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
128 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
129 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
130 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
131 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
133 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134
135 #define LOW_HEAP_SIZE \
136 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
137 #define DYNAMIC_STATE_POOL_SIZE \
138 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
139 #define BINDING_TABLE_POOL_SIZE \
140 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
141 #define SURFACE_STATE_POOL_SIZE \
142 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
143 #define INSTRUCTION_STATE_POOL_SIZE \
144 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
145 #define CLIENT_VISIBLE_HEAP_SIZE \
146 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147
148 /* Allowing different clear colors requires us to perform a depth resolve at
149 * the end of certain render passes. This is because while slow clears store
150 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
151 * See the PRMs for examples describing when additional resolves would be
152 * necessary. To enable fast clears without requiring extra resolves, we set
153 * the clear value to a globally-defined one. We could allow different values
154 * if the user doesn't expect coherent data during or after a render passes
155 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
156 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
157 * 1.0f seems to be the only value used. The only application that doesn't set
158 * this value does so through the usage of an seemingly uninitialized clear
159 * value.
160 */
161 #define ANV_HZ_FC_VAL 1.0f
162
163 #define MAX_VBS 28
164 #define MAX_XFB_BUFFERS 4
165 #define MAX_XFB_STREAMS 4
166 #define MAX_SETS 8
167 #define MAX_RTS 8
168 #define MAX_VIEWPORTS 16
169 #define MAX_SCISSORS 16
170 #define MAX_PUSH_CONSTANTS_SIZE 128
171 #define MAX_DYNAMIC_BUFFERS 16
172 #define MAX_IMAGES 64
173 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
174 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
175 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
177 * use 64 here to avoid cache issues. This could most likely bring it back to
178 * 32 if we had different virtual addresses for the different views on a given
179 * GEM object.
180 */
181 #define ANV_UBO_ALIGNMENT 64
182 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
183 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
184
185 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
186 *
187 * "The surface state model is used when a Binding Table Index (specified
188 * in the message descriptor) of less than 240 is specified. In this model,
189 * the Binding Table Index is used to index into the binding table, and the
190 * binding table entry contains a pointer to the SURFACE_STATE."
191 *
192 * Binding table values above 240 are used for various things in the hardware
193 * such as stateless, stateless with incoherent cache, SLM, and bindless.
194 */
195 #define MAX_BINDING_TABLE_SIZE 240
196
197 /* The kernel relocation API has a limitation of a 32-bit delta value
198 * applied to the address before it is written which, in spite of it being
199 * unsigned, is treated as signed . Because of the way that this maps to
200 * the Vulkan API, we cannot handle an offset into a buffer that does not
201 * fit into a signed 32 bits. The only mechanism we have for dealing with
202 * this at the moment is to limit all VkDeviceMemory objects to a maximum
203 * of 2GB each. The Vulkan spec allows us to do this:
204 *
205 * "Some platforms may have a limit on the maximum size of a single
206 * allocation. For example, certain systems may fail to create
207 * allocations with a size greater than or equal to 4GB. Such a limit is
208 * implementation-dependent, and if such a failure occurs then the error
209 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
210 *
211 * We don't use vk_error here because it's not an error so much as an
212 * indication to the application that the allocation is too large.
213 */
214 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
215
216 #define ANV_SVGS_VB_INDEX MAX_VBS
217 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
218
219 /* We reserve this MI ALU register for the purpose of handling predication.
220 * Other code which uses the MI ALU should leave it alone.
221 */
222 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
223
224 /* For gen12 we set the streamout buffers using 4 separate commands
225 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
226 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
227 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
228 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
229 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
230 * 3DSTATE_SO_BUFFER_INDEX_0.
231 */
232 #define SO_BUFFER_INDEX_0_CMD 0x60
233 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
234
235 static inline uint32_t
236 align_down_npot_u32(uint32_t v, uint32_t a)
237 {
238 return v - (v % a);
239 }
240
241 static inline uint32_t
242 align_down_u32(uint32_t v, uint32_t a)
243 {
244 assert(a != 0 && a == (a & -a));
245 return v & ~(a - 1);
246 }
247
248 static inline uint32_t
249 align_u32(uint32_t v, uint32_t a)
250 {
251 assert(a != 0 && a == (a & -a));
252 return align_down_u32(v + a - 1, a);
253 }
254
255 static inline uint64_t
256 align_down_u64(uint64_t v, uint64_t a)
257 {
258 assert(a != 0 && a == (a & -a));
259 return v & ~(a - 1);
260 }
261
262 static inline uint64_t
263 align_u64(uint64_t v, uint64_t a)
264 {
265 return align_down_u64(v + a - 1, a);
266 }
267
268 static inline int32_t
269 align_i32(int32_t v, int32_t a)
270 {
271 assert(a != 0 && a == (a & -a));
272 return (v + a - 1) & ~(a - 1);
273 }
274
275 /** Alignment must be a power of 2. */
276 static inline bool
277 anv_is_aligned(uintmax_t n, uintmax_t a)
278 {
279 assert(a == (a & -a));
280 return (n & (a - 1)) == 0;
281 }
282
283 static inline uint32_t
284 anv_minify(uint32_t n, uint32_t levels)
285 {
286 if (unlikely(n == 0))
287 return 0;
288 else
289 return MAX2(n >> levels, 1);
290 }
291
292 static inline float
293 anv_clamp_f(float f, float min, float max)
294 {
295 assert(min < max);
296
297 if (f > max)
298 return max;
299 else if (f < min)
300 return min;
301 else
302 return f;
303 }
304
305 static inline bool
306 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
307 {
308 if (*inout_mask & clear_mask) {
309 *inout_mask &= ~clear_mask;
310 return true;
311 } else {
312 return false;
313 }
314 }
315
316 static inline union isl_color_value
317 vk_to_isl_color(VkClearColorValue color)
318 {
319 return (union isl_color_value) {
320 .u32 = {
321 color.uint32[0],
322 color.uint32[1],
323 color.uint32[2],
324 color.uint32[3],
325 },
326 };
327 }
328
329 static inline void *anv_unpack_ptr(uintptr_t ptr, int bits, int *flags)
330 {
331 uintptr_t mask = (1ull << bits) - 1;
332 *flags = ptr & mask;
333 return (void *) (ptr & ~mask);
334 }
335
336 static inline uintptr_t anv_pack_ptr(void *ptr, int bits, int flags)
337 {
338 uintptr_t value = (uintptr_t) ptr;
339 uintptr_t mask = (1ull << bits) - 1;
340 return value | (mask & flags);
341 }
342
343 #define for_each_bit(b, dword) \
344 for (uint32_t __dword = (dword); \
345 (b) = __builtin_ffs(__dword) - 1, __dword; \
346 __dword &= ~(1 << (b)))
347
348 #define typed_memcpy(dest, src, count) ({ \
349 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
350 memcpy((dest), (src), (count) * sizeof(*(src))); \
351 })
352
353 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
354 * to be added here in order to utilize mapping in debug/error/perf macros.
355 */
356 #define REPORT_OBJECT_TYPE(o) \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
384 __builtin_choose_expr ( \
385 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
386 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
387 __builtin_choose_expr ( \
388 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
389 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
390 __builtin_choose_expr ( \
391 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
392 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
393 __builtin_choose_expr ( \
394 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
395 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
396 __builtin_choose_expr ( \
397 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
398 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
399 __builtin_choose_expr ( \
400 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
401 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
402 __builtin_choose_expr ( \
403 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
404 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
405 __builtin_choose_expr ( \
406 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
407 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
408 __builtin_choose_expr ( \
409 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
410 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
411 __builtin_choose_expr ( \
412 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
413 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
414 __builtin_choose_expr ( \
415 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
416 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
417 __builtin_choose_expr ( \
418 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
419 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
420 __builtin_choose_expr ( \
421 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
422 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
423 __builtin_choose_expr ( \
424 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
425 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
426 __builtin_choose_expr ( \
427 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
428 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
429 __builtin_choose_expr ( \
430 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
431 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
432 __builtin_choose_expr ( \
433 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
434 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
435 __builtin_choose_expr ( \
436 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
437 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
438 __builtin_choose_expr ( \
439 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
440 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
441 __builtin_choose_expr ( \
442 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
443 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
444 __builtin_choose_expr ( \
445 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
446 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
447 __builtin_choose_expr ( \
448 __builtin_types_compatible_p (__typeof (o), void*), \
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
450 /* The void expression results in a compile-time error \
451 when assigning the result to something. */ \
452 (void)0)))))))))))))))))))))))))))))))
453
454 /* Whenever we generate an error, pass it through this function. Useful for
455 * debugging, where we can break on it. Only call at error site, not when
456 * propagating errors. Might be useful to plug in a stack trace here.
457 */
458
459 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
460 VkDebugReportObjectTypeEXT type, VkResult error,
461 const char *file, int line, const char *format,
462 va_list args);
463
464 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
465 VkDebugReportObjectTypeEXT type, VkResult error,
466 const char *file, int line, const char *format, ...)
467 anv_printflike(7, 8);
468
469 #ifdef DEBUG
470 #define vk_error(error) __vk_errorf(NULL, NULL,\
471 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
472 error, __FILE__, __LINE__, NULL)
473 #define vk_errorfi(instance, obj, error, format, ...)\
474 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
475 __FILE__, __LINE__, format, ## __VA_ARGS__)
476 #define vk_errorf(device, obj, error, format, ...)\
477 vk_errorfi(anv_device_instance_or_null(device),\
478 obj, error, format, ## __VA_ARGS__)
479 #else
480 #define vk_error(error) error
481 #define vk_errorfi(instance, obj, error, format, ...) error
482 #define vk_errorf(device, obj, error, format, ...) error
483 #endif
484
485 /**
486 * Warn on ignored extension structs.
487 *
488 * The Vulkan spec requires us to ignore unsupported or unknown structs in
489 * a pNext chain. In debug mode, emitting warnings for ignored structs may
490 * help us discover structs that we should not have ignored.
491 *
492 *
493 * From the Vulkan 1.0.38 spec:
494 *
495 * Any component of the implementation (the loader, any enabled layers,
496 * and drivers) must skip over, without processing (other than reading the
497 * sType and pNext members) any chained structures with sType values not
498 * defined by extensions supported by that component.
499 */
500 #define anv_debug_ignored_stype(sType) \
501 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
502
503 void __anv_perf_warn(struct anv_device *device, const void *object,
504 VkDebugReportObjectTypeEXT type, const char *file,
505 int line, const char *format, ...)
506 anv_printflike(6, 7);
507 void anv_loge(const char *format, ...) anv_printflike(1, 2);
508 void anv_loge_v(const char *format, va_list va);
509
510 /**
511 * Print a FINISHME message, including its source location.
512 */
513 #define anv_finishme(format, ...) \
514 do { \
515 static bool reported = false; \
516 if (!reported) { \
517 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
518 ##__VA_ARGS__); \
519 reported = true; \
520 } \
521 } while (0)
522
523 /**
524 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
525 */
526 #define anv_perf_warn(instance, obj, format, ...) \
527 do { \
528 static bool reported = false; \
529 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
530 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
531 format, ##__VA_ARGS__); \
532 reported = true; \
533 } \
534 } while (0)
535
536 /* A non-fatal assert. Useful for debugging. */
537 #ifdef DEBUG
538 #define anv_assert(x) ({ \
539 if (unlikely(!(x))) \
540 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
541 })
542 #else
543 #define anv_assert(x)
544 #endif
545
546 /* A multi-pointer allocator
547 *
548 * When copying data structures from the user (such as a render pass), it's
549 * common to need to allocate data for a bunch of different things. Instead
550 * of doing several allocations and having to handle all of the error checking
551 * that entails, it can be easier to do a single allocation. This struct
552 * helps facilitate that. The intended usage looks like this:
553 *
554 * ANV_MULTIALLOC(ma)
555 * anv_multialloc_add(&ma, &main_ptr, 1);
556 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
557 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
558 *
559 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
560 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
561 */
562 struct anv_multialloc {
563 size_t size;
564 size_t align;
565
566 uint32_t ptr_count;
567 void **ptrs[8];
568 };
569
570 #define ANV_MULTIALLOC_INIT \
571 ((struct anv_multialloc) { 0, })
572
573 #define ANV_MULTIALLOC(_name) \
574 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
575
576 __attribute__((always_inline))
577 static inline void
578 _anv_multialloc_add(struct anv_multialloc *ma,
579 void **ptr, size_t size, size_t align)
580 {
581 size_t offset = align_u64(ma->size, align);
582 ma->size = offset + size;
583 ma->align = MAX2(ma->align, align);
584
585 /* Store the offset in the pointer. */
586 *ptr = (void *)(uintptr_t)offset;
587
588 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
589 ma->ptrs[ma->ptr_count++] = ptr;
590 }
591
592 #define anv_multialloc_add_size(_ma, _ptr, _size) \
593 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
594
595 #define anv_multialloc_add(_ma, _ptr, _count) \
596 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
597
598 __attribute__((always_inline))
599 static inline void *
600 anv_multialloc_alloc(struct anv_multialloc *ma,
601 const VkAllocationCallbacks *alloc,
602 VkSystemAllocationScope scope)
603 {
604 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
605 if (!ptr)
606 return NULL;
607
608 /* Fill out each of the pointers with their final value.
609 *
610 * for (uint32_t i = 0; i < ma->ptr_count; i++)
611 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
612 *
613 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
614 * constant, GCC is incapable of figuring this out and unrolling the loop
615 * so we have to give it a little help.
616 */
617 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
618 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
619 if ((_i) < ma->ptr_count) \
620 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
621 _ANV_MULTIALLOC_UPDATE_POINTER(0);
622 _ANV_MULTIALLOC_UPDATE_POINTER(1);
623 _ANV_MULTIALLOC_UPDATE_POINTER(2);
624 _ANV_MULTIALLOC_UPDATE_POINTER(3);
625 _ANV_MULTIALLOC_UPDATE_POINTER(4);
626 _ANV_MULTIALLOC_UPDATE_POINTER(5);
627 _ANV_MULTIALLOC_UPDATE_POINTER(6);
628 _ANV_MULTIALLOC_UPDATE_POINTER(7);
629 #undef _ANV_MULTIALLOC_UPDATE_POINTER
630
631 return ptr;
632 }
633
634 __attribute__((always_inline))
635 static inline void *
636 anv_multialloc_alloc2(struct anv_multialloc *ma,
637 const VkAllocationCallbacks *parent_alloc,
638 const VkAllocationCallbacks *alloc,
639 VkSystemAllocationScope scope)
640 {
641 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
642 }
643
644 struct anv_bo {
645 uint32_t gem_handle;
646
647 uint32_t refcount;
648
649 /* Index into the current validation list. This is used by the
650 * validation list building alrogithm to track which buffers are already
651 * in the validation list so that we can ensure uniqueness.
652 */
653 uint32_t index;
654
655 /* Index for use with util_sparse_array_free_list */
656 uint32_t free_index;
657
658 /* Last known offset. This value is provided by the kernel when we
659 * execbuf and is used as the presumed offset for the next bunch of
660 * relocations.
661 */
662 uint64_t offset;
663
664 /** Size of the buffer not including implicit aux */
665 uint64_t size;
666
667 /* Map for internally mapped BOs.
668 *
669 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
670 */
671 void *map;
672
673 /** Size of the implicit CCS range at the end of the buffer
674 *
675 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
676 * page of main surface data maps to a 256B chunk of CCS data and that
677 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
678 * addresses in the main surface to virtual memory addresses for CCS data.
679 *
680 * Because we can't change these maps around easily and because Vulkan
681 * allows two VkImages to be bound to overlapping memory regions (as long
682 * as the app is careful), it's not feasible to make this mapping part of
683 * the image. (On Gen11 and earlier, the mapping was provided via
684 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
685 * Instead, we attach the CCS data directly to the buffer object and setup
686 * the AUX table mapping at BO creation time.
687 *
688 * This field is for internal tracking use by the BO allocator only and
689 * should not be touched by other parts of the code. If something wants to
690 * know if a BO has implicit CCS data, it should instead look at the
691 * has_implicit_ccs boolean below.
692 *
693 * This data is not included in maps of this buffer.
694 */
695 uint32_t _ccs_size;
696
697 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
698 uint32_t flags;
699
700 /** True if this BO may be shared with other processes */
701 bool is_external:1;
702
703 /** True if this BO is a wrapper
704 *
705 * When set to true, none of the fields in this BO are meaningful except
706 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
707 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
708 * is set in the physical device.
709 */
710 bool is_wrapper:1;
711
712 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
713 bool has_fixed_address:1;
714
715 /** True if this BO wraps a host pointer */
716 bool from_host_ptr:1;
717
718 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
719 bool has_client_visible_address:1;
720
721 /** True if this BO has implicit CCS data attached to it */
722 bool has_implicit_ccs:1;
723 };
724
725 static inline struct anv_bo *
726 anv_bo_ref(struct anv_bo *bo)
727 {
728 p_atomic_inc(&bo->refcount);
729 return bo;
730 }
731
732 static inline struct anv_bo *
733 anv_bo_unwrap(struct anv_bo *bo)
734 {
735 while (bo->is_wrapper)
736 bo = bo->map;
737 return bo;
738 }
739
740 /* Represents a lock-free linked list of "free" things. This is used by
741 * both the block pool and the state pools. Unfortunately, in order to
742 * solve the ABA problem, we can't use a single uint32_t head.
743 */
744 union anv_free_list {
745 struct {
746 uint32_t offset;
747
748 /* A simple count that is incremented every time the head changes. */
749 uint32_t count;
750 };
751 /* Make sure it's aligned to 64 bits. This will make atomic operations
752 * faster on 32 bit platforms.
753 */
754 uint64_t u64 __attribute__ ((aligned (8)));
755 };
756
757 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
758
759 struct anv_block_state {
760 union {
761 struct {
762 uint32_t next;
763 uint32_t end;
764 };
765 /* Make sure it's aligned to 64 bits. This will make atomic operations
766 * faster on 32 bit platforms.
767 */
768 uint64_t u64 __attribute__ ((aligned (8)));
769 };
770 };
771
772 #define anv_block_pool_foreach_bo(bo, pool) \
773 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
774 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
775 _pp_bo++)
776
777 #define ANV_MAX_BLOCK_POOL_BOS 20
778
779 struct anv_block_pool {
780 struct anv_device *device;
781 bool use_softpin;
782
783 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
784 * around the actual BO so that we grow the pool after the wrapper BO has
785 * been put in a relocation list. This is only used in the non-softpin
786 * case.
787 */
788 struct anv_bo wrapper_bo;
789
790 struct anv_bo *bos[ANV_MAX_BLOCK_POOL_BOS];
791 struct anv_bo *bo;
792 uint32_t nbos;
793
794 uint64_t size;
795
796 /* The address where the start of the pool is pinned. The various bos that
797 * are created as the pool grows will have addresses in the range
798 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
799 */
800 uint64_t start_address;
801
802 /* The offset from the start of the bo to the "center" of the block
803 * pool. Pointers to allocated blocks are given by
804 * bo.map + center_bo_offset + offsets.
805 */
806 uint32_t center_bo_offset;
807
808 /* Current memory map of the block pool. This pointer may or may not
809 * point to the actual beginning of the block pool memory. If
810 * anv_block_pool_alloc_back has ever been called, then this pointer
811 * will point to the "center" position of the buffer and all offsets
812 * (negative or positive) given out by the block pool alloc functions
813 * will be valid relative to this pointer.
814 *
815 * In particular, map == bo.map + center_offset
816 *
817 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
818 * since it will handle the softpin case as well, where this points to NULL.
819 */
820 void *map;
821 int fd;
822
823 /**
824 * Array of mmaps and gem handles owned by the block pool, reclaimed when
825 * the block pool is destroyed.
826 */
827 struct u_vector mmap_cleanups;
828
829 struct anv_block_state state;
830
831 struct anv_block_state back_state;
832 };
833
834 /* Block pools are backed by a fixed-size 1GB memfd */
835 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
836
837 /* The center of the block pool is also the middle of the memfd. This may
838 * change in the future if we decide differently for some reason.
839 */
840 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
841
842 static inline uint32_t
843 anv_block_pool_size(struct anv_block_pool *pool)
844 {
845 return pool->state.end + pool->back_state.end;
846 }
847
848 struct anv_state {
849 int32_t offset;
850 uint32_t alloc_size;
851 void *map;
852 uint32_t idx;
853 };
854
855 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
856
857 struct anv_fixed_size_state_pool {
858 union anv_free_list free_list;
859 struct anv_block_state block;
860 };
861
862 #define ANV_MIN_STATE_SIZE_LOG2 6
863 #define ANV_MAX_STATE_SIZE_LOG2 21
864
865 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
866
867 struct anv_free_entry {
868 uint32_t next;
869 struct anv_state state;
870 };
871
872 struct anv_state_table {
873 struct anv_device *device;
874 int fd;
875 struct anv_free_entry *map;
876 uint32_t size;
877 struct anv_block_state state;
878 struct u_vector cleanups;
879 };
880
881 struct anv_state_pool {
882 struct anv_block_pool block_pool;
883
884 struct anv_state_table table;
885
886 /* The size of blocks which will be allocated from the block pool */
887 uint32_t block_size;
888
889 /** Free list for "back" allocations */
890 union anv_free_list back_alloc_free_list;
891
892 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
893 };
894
895 struct anv_state_stream {
896 struct anv_state_pool *state_pool;
897
898 /* The size of blocks to allocate from the state pool */
899 uint32_t block_size;
900
901 /* Current block we're allocating from */
902 struct anv_state block;
903
904 /* Offset into the current block at which to allocate the next state */
905 uint32_t next;
906
907 /* List of all blocks allocated from this pool */
908 struct util_dynarray all_blocks;
909 };
910
911 /* The block_pool functions exported for testing only. The block pool should
912 * only be used via a state pool (see below).
913 */
914 VkResult anv_block_pool_init(struct anv_block_pool *pool,
915 struct anv_device *device,
916 uint64_t start_address,
917 uint32_t initial_size);
918 void anv_block_pool_finish(struct anv_block_pool *pool);
919 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
920 uint32_t block_size, uint32_t *padding);
921 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
922 uint32_t block_size);
923 void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset, uint32_t
924 size);
925
926 VkResult anv_state_pool_init(struct anv_state_pool *pool,
927 struct anv_device *device,
928 uint64_t start_address,
929 uint32_t block_size);
930 void anv_state_pool_finish(struct anv_state_pool *pool);
931 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
932 uint32_t state_size, uint32_t alignment);
933 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
934 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
935 void anv_state_stream_init(struct anv_state_stream *stream,
936 struct anv_state_pool *state_pool,
937 uint32_t block_size);
938 void anv_state_stream_finish(struct anv_state_stream *stream);
939 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
940 uint32_t size, uint32_t alignment);
941
942 VkResult anv_state_table_init(struct anv_state_table *table,
943 struct anv_device *device,
944 uint32_t initial_entries);
945 void anv_state_table_finish(struct anv_state_table *table);
946 VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx,
947 uint32_t count);
948 void anv_free_list_push(union anv_free_list *list,
949 struct anv_state_table *table,
950 uint32_t idx, uint32_t count);
951 struct anv_state* anv_free_list_pop(union anv_free_list *list,
952 struct anv_state_table *table);
953
954
955 static inline struct anv_state *
956 anv_state_table_get(struct anv_state_table *table, uint32_t idx)
957 {
958 return &table->map[idx].state;
959 }
960 /**
961 * Implements a pool of re-usable BOs. The interface is identical to that
962 * of block_pool except that each block is its own BO.
963 */
964 struct anv_bo_pool {
965 struct anv_device *device;
966
967 struct util_sparse_array_free_list free_list[16];
968 };
969
970 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
971 void anv_bo_pool_finish(struct anv_bo_pool *pool);
972 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, uint32_t size,
973 struct anv_bo **bo_out);
974 void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
975
976 struct anv_scratch_pool {
977 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
978 struct anv_bo *bos[16][MESA_SHADER_STAGES];
979 };
980
981 void anv_scratch_pool_init(struct anv_device *device,
982 struct anv_scratch_pool *pool);
983 void anv_scratch_pool_finish(struct anv_device *device,
984 struct anv_scratch_pool *pool);
985 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
986 struct anv_scratch_pool *pool,
987 gl_shader_stage stage,
988 unsigned per_thread_scratch);
989
990 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
991 struct anv_bo_cache {
992 struct util_sparse_array bo_map;
993 pthread_mutex_t mutex;
994 };
995
996 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
997 void anv_bo_cache_finish(struct anv_bo_cache *cache);
998
999 struct anv_memory_type {
1000 /* Standard bits passed on to the client */
1001 VkMemoryPropertyFlags propertyFlags;
1002 uint32_t heapIndex;
1003 };
1004
1005 struct anv_memory_heap {
1006 /* Standard bits passed on to the client */
1007 VkDeviceSize size;
1008 VkMemoryHeapFlags flags;
1009
1010 /* Driver-internal book-keeping */
1011 VkDeviceSize used;
1012 };
1013
1014 struct anv_physical_device {
1015 struct vk_object_base base;
1016
1017 /* Link in anv_instance::physical_devices */
1018 struct list_head link;
1019
1020 struct anv_instance * instance;
1021 bool no_hw;
1022 char path[20];
1023 const char * name;
1024 struct {
1025 uint16_t domain;
1026 uint8_t bus;
1027 uint8_t device;
1028 uint8_t function;
1029 } pci_info;
1030 struct gen_device_info info;
1031 /** Amount of "GPU memory" we want to advertise
1032 *
1033 * Clearly, this value is bogus since Intel is a UMA architecture. On
1034 * gen7 platforms, we are limited by GTT size unless we want to implement
1035 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1036 * practically unlimited. However, we will never report more than 3/4 of
1037 * the total system ram to try and avoid running out of RAM.
1038 */
1039 bool supports_48bit_addresses;
1040 struct brw_compiler * compiler;
1041 struct isl_device isl_dev;
1042 struct gen_perf_config * perf;
1043 int cmd_parser_version;
1044 bool has_softpin;
1045 bool has_exec_async;
1046 bool has_exec_capture;
1047 bool has_exec_fence;
1048 bool has_syncobj;
1049 bool has_syncobj_wait;
1050 bool has_context_priority;
1051 bool has_context_isolation;
1052 bool has_mem_available;
1053 bool has_mmap_offset;
1054 uint64_t gtt_size;
1055
1056 bool use_softpin;
1057 bool always_use_bindless;
1058
1059 /** True if we can access buffers using A64 messages */
1060 bool has_a64_buffer_access;
1061 /** True if we can use bindless access for images */
1062 bool has_bindless_images;
1063 /** True if we can use bindless access for samplers */
1064 bool has_bindless_samplers;
1065
1066 /** True if this device has implicit AUX
1067 *
1068 * If true, CCS is handled as an implicit attachment to the BO rather than
1069 * as an explicitly bound surface.
1070 */
1071 bool has_implicit_ccs;
1072
1073 bool always_flush_cache;
1074
1075 struct anv_device_extension_table supported_extensions;
1076
1077 uint32_t eu_total;
1078 uint32_t subslice_total;
1079
1080 struct {
1081 uint32_t type_count;
1082 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
1083 uint32_t heap_count;
1084 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
1085 } memory;
1086
1087 uint8_t driver_build_sha1[20];
1088 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
1089 uint8_t driver_uuid[VK_UUID_SIZE];
1090 uint8_t device_uuid[VK_UUID_SIZE];
1091
1092 struct disk_cache * disk_cache;
1093
1094 struct wsi_device wsi_device;
1095 int local_fd;
1096 int master_fd;
1097 };
1098
1099 struct anv_app_info {
1100 const char* app_name;
1101 uint32_t app_version;
1102 const char* engine_name;
1103 uint32_t engine_version;
1104 uint32_t api_version;
1105 };
1106
1107 struct anv_instance {
1108 struct vk_object_base base;
1109
1110 VkAllocationCallbacks alloc;
1111
1112 struct anv_app_info app_info;
1113
1114 struct anv_instance_extension_table enabled_extensions;
1115 struct anv_instance_dispatch_table dispatch;
1116 struct anv_physical_device_dispatch_table physical_device_dispatch;
1117 struct anv_device_dispatch_table device_dispatch;
1118
1119 bool physical_devices_enumerated;
1120 struct list_head physical_devices;
1121
1122 bool pipeline_cache_enabled;
1123
1124 struct vk_debug_report_instance debug_report_callbacks;
1125
1126 struct driOptionCache dri_options;
1127 struct driOptionCache available_dri_options;
1128 };
1129
1130 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
1131 void anv_finish_wsi(struct anv_physical_device *physical_device);
1132
1133 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
1134 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
1135 const char *name);
1136
1137 struct anv_queue_submit {
1138 struct anv_cmd_buffer * cmd_buffer;
1139
1140 uint32_t fence_count;
1141 uint32_t fence_array_length;
1142 struct drm_i915_gem_exec_fence * fences;
1143
1144 uint32_t temporary_semaphore_count;
1145 uint32_t temporary_semaphore_array_length;
1146 struct anv_semaphore_impl * temporary_semaphores;
1147
1148 /* Semaphores to be signaled with a SYNC_FD. */
1149 struct anv_semaphore ** sync_fd_semaphores;
1150 uint32_t sync_fd_semaphore_count;
1151 uint32_t sync_fd_semaphore_array_length;
1152
1153 /* Allocated only with non shareable timelines. */
1154 struct anv_timeline ** wait_timelines;
1155 uint32_t wait_timeline_count;
1156 uint32_t wait_timeline_array_length;
1157 uint64_t * wait_timeline_values;
1158
1159 struct anv_timeline ** signal_timelines;
1160 uint32_t signal_timeline_count;
1161 uint32_t signal_timeline_array_length;
1162 uint64_t * signal_timeline_values;
1163
1164 int in_fence;
1165 bool need_out_fence;
1166 int out_fence;
1167
1168 uint32_t fence_bo_count;
1169 uint32_t fence_bo_array_length;
1170 /* An array of struct anv_bo pointers with lower bit used as a flag to
1171 * signal we will wait on that BO (see anv_(un)pack_ptr).
1172 */
1173 uintptr_t * fence_bos;
1174
1175 const VkAllocationCallbacks * alloc;
1176 VkSystemAllocationScope alloc_scope;
1177
1178 struct anv_bo * simple_bo;
1179 uint32_t simple_bo_size;
1180
1181 struct list_head link;
1182 };
1183
1184 struct anv_queue {
1185 struct vk_object_base base;
1186
1187 struct anv_device * device;
1188
1189 /*
1190 * A list of struct anv_queue_submit to be submitted to i915.
1191 */
1192 struct list_head queued_submits;
1193
1194 VkDeviceQueueCreateFlags flags;
1195 };
1196
1197 struct anv_pipeline_cache {
1198 struct vk_object_base base;
1199 struct anv_device * device;
1200 pthread_mutex_t mutex;
1201
1202 struct hash_table * nir_cache;
1203
1204 struct hash_table * cache;
1205 };
1206
1207 struct nir_xfb_info;
1208 struct anv_pipeline_bind_map;
1209
1210 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
1211 struct anv_device *device,
1212 bool cache_enabled);
1213 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
1214
1215 struct anv_shader_bin *
1216 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
1217 const void *key, uint32_t key_size);
1218 struct anv_shader_bin *
1219 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
1220 gl_shader_stage stage,
1221 const void *key_data, uint32_t key_size,
1222 const void *kernel_data, uint32_t kernel_size,
1223 const void *constant_data,
1224 uint32_t constant_data_size,
1225 const struct brw_stage_prog_data *prog_data,
1226 uint32_t prog_data_size,
1227 const struct brw_compile_stats *stats,
1228 uint32_t num_stats,
1229 const struct nir_xfb_info *xfb_info,
1230 const struct anv_pipeline_bind_map *bind_map);
1231
1232 struct anv_shader_bin *
1233 anv_device_search_for_kernel(struct anv_device *device,
1234 struct anv_pipeline_cache *cache,
1235 const void *key_data, uint32_t key_size,
1236 bool *user_cache_bit);
1237
1238 struct anv_shader_bin *
1239 anv_device_upload_kernel(struct anv_device *device,
1240 struct anv_pipeline_cache *cache,
1241 gl_shader_stage stage,
1242 const void *key_data, uint32_t key_size,
1243 const void *kernel_data, uint32_t kernel_size,
1244 const void *constant_data,
1245 uint32_t constant_data_size,
1246 const struct brw_stage_prog_data *prog_data,
1247 uint32_t prog_data_size,
1248 const struct brw_compile_stats *stats,
1249 uint32_t num_stats,
1250 const struct nir_xfb_info *xfb_info,
1251 const struct anv_pipeline_bind_map *bind_map);
1252
1253 struct nir_shader;
1254 struct nir_shader_compiler_options;
1255
1256 struct nir_shader *
1257 anv_device_search_for_nir(struct anv_device *device,
1258 struct anv_pipeline_cache *cache,
1259 const struct nir_shader_compiler_options *nir_options,
1260 unsigned char sha1_key[20],
1261 void *mem_ctx);
1262
1263 void
1264 anv_device_upload_nir(struct anv_device *device,
1265 struct anv_pipeline_cache *cache,
1266 const struct nir_shader *nir,
1267 unsigned char sha1_key[20]);
1268
1269 struct anv_device {
1270 struct vk_device vk;
1271
1272 struct anv_physical_device * physical;
1273 bool no_hw;
1274 struct gen_device_info info;
1275 struct isl_device isl_dev;
1276 int context_id;
1277 int fd;
1278 bool can_chain_batches;
1279 bool robust_buffer_access;
1280 struct anv_device_extension_table enabled_extensions;
1281 struct anv_device_dispatch_table dispatch;
1282
1283 pthread_mutex_t vma_mutex;
1284 struct util_vma_heap vma_lo;
1285 struct util_vma_heap vma_cva;
1286 struct util_vma_heap vma_hi;
1287
1288 /** List of all anv_device_memory objects */
1289 struct list_head memory_objects;
1290
1291 struct anv_bo_pool batch_bo_pool;
1292
1293 struct anv_bo_cache bo_cache;
1294
1295 struct anv_state_pool dynamic_state_pool;
1296 struct anv_state_pool instruction_state_pool;
1297 struct anv_state_pool binding_table_pool;
1298 struct anv_state_pool surface_state_pool;
1299
1300 /** BO used for various workarounds
1301 *
1302 * There are a number of workarounds on our hardware which require writing
1303 * data somewhere and it doesn't really matter where. For that, we use
1304 * this BO and just write to the first dword or so.
1305 *
1306 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1307 * For that, we use the high bytes (>= 1024) of the workaround BO.
1308 */
1309 struct anv_bo * workaround_bo;
1310 struct anv_bo * trivial_batch_bo;
1311 struct anv_bo * hiz_clear_bo;
1312 struct anv_state null_surface_state;
1313
1314 struct anv_pipeline_cache default_pipeline_cache;
1315 struct blorp_context blorp;
1316
1317 struct anv_state border_colors;
1318
1319 struct anv_state slice_hash;
1320
1321 struct anv_queue queue;
1322
1323 struct anv_scratch_pool scratch_pool;
1324
1325 pthread_mutex_t mutex;
1326 pthread_cond_t queue_submit;
1327 int _lost;
1328
1329 struct gen_batch_decode_ctx decoder_ctx;
1330 /*
1331 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1332 * the cmd_buffer's list.
1333 */
1334 struct anv_cmd_buffer *cmd_buffer_being_decoded;
1335
1336 int perf_fd; /* -1 if no opened */
1337 uint64_t perf_metric; /* 0 if unset */
1338
1339 struct gen_aux_map_context *aux_map_ctx;
1340 };
1341
1342 static inline struct anv_instance *
1343 anv_device_instance_or_null(const struct anv_device *device)
1344 {
1345 return device ? device->physical->instance : NULL;
1346 }
1347
1348 static inline struct anv_state_pool *
1349 anv_binding_table_pool(struct anv_device *device)
1350 {
1351 if (device->physical->use_softpin)
1352 return &device->binding_table_pool;
1353 else
1354 return &device->surface_state_pool;
1355 }
1356
1357 static inline struct anv_state
1358 anv_binding_table_pool_alloc(struct anv_device *device) {
1359 if (device->physical->use_softpin)
1360 return anv_state_pool_alloc(&device->binding_table_pool,
1361 device->binding_table_pool.block_size, 0);
1362 else
1363 return anv_state_pool_alloc_back(&device->surface_state_pool);
1364 }
1365
1366 static inline void
1367 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1368 anv_state_pool_free(anv_binding_table_pool(device), state);
1369 }
1370
1371 static inline uint32_t
1372 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1373 {
1374 if (bo->is_external)
1375 return device->isl_dev.mocs.external;
1376 else
1377 return device->isl_dev.mocs.internal;
1378 }
1379
1380 void anv_device_init_blorp(struct anv_device *device);
1381 void anv_device_finish_blorp(struct anv_device *device);
1382
1383 void _anv_device_set_all_queue_lost(struct anv_device *device);
1384 VkResult _anv_device_set_lost(struct anv_device *device,
1385 const char *file, int line,
1386 const char *msg, ...)
1387 anv_printflike(4, 5);
1388 VkResult _anv_queue_set_lost(struct anv_queue *queue,
1389 const char *file, int line,
1390 const char *msg, ...)
1391 anv_printflike(4, 5);
1392 #define anv_device_set_lost(dev, ...) \
1393 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1394 #define anv_queue_set_lost(queue, ...) \
1395 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1396
1397 static inline bool
1398 anv_device_is_lost(struct anv_device *device)
1399 {
1400 return unlikely(p_atomic_read(&device->_lost));
1401 }
1402
1403 VkResult anv_device_query_status(struct anv_device *device);
1404
1405
1406 enum anv_bo_alloc_flags {
1407 /** Specifies that the BO must have a 32-bit address
1408 *
1409 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1410 */
1411 ANV_BO_ALLOC_32BIT_ADDRESS = (1 << 0),
1412
1413 /** Specifies that the BO may be shared externally */
1414 ANV_BO_ALLOC_EXTERNAL = (1 << 1),
1415
1416 /** Specifies that the BO should be mapped */
1417 ANV_BO_ALLOC_MAPPED = (1 << 2),
1418
1419 /** Specifies that the BO should be snooped so we get coherency */
1420 ANV_BO_ALLOC_SNOOPED = (1 << 3),
1421
1422 /** Specifies that the BO should be captured in error states */
1423 ANV_BO_ALLOC_CAPTURE = (1 << 4),
1424
1425 /** Specifies that the BO will have an address assigned by the caller
1426 *
1427 * Such BOs do not exist in any VMA heap.
1428 */
1429 ANV_BO_ALLOC_FIXED_ADDRESS = (1 << 5),
1430
1431 /** Enables implicit synchronization on the BO
1432 *
1433 * This is the opposite of EXEC_OBJECT_ASYNC.
1434 */
1435 ANV_BO_ALLOC_IMPLICIT_SYNC = (1 << 6),
1436
1437 /** Enables implicit synchronization on the BO
1438 *
1439 * This is equivalent to EXEC_OBJECT_WRITE.
1440 */
1441 ANV_BO_ALLOC_IMPLICIT_WRITE = (1 << 7),
1442
1443 /** Has an address which is visible to the client */
1444 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS = (1 << 8),
1445
1446 /** This buffer has implicit CCS data attached to it */
1447 ANV_BO_ALLOC_IMPLICIT_CCS = (1 << 9),
1448 };
1449
1450 VkResult anv_device_alloc_bo(struct anv_device *device, uint64_t size,
1451 enum anv_bo_alloc_flags alloc_flags,
1452 uint64_t explicit_address,
1453 struct anv_bo **bo);
1454 VkResult anv_device_import_bo_from_host_ptr(struct anv_device *device,
1455 void *host_ptr, uint32_t size,
1456 enum anv_bo_alloc_flags alloc_flags,
1457 uint64_t client_address,
1458 struct anv_bo **bo_out);
1459 VkResult anv_device_import_bo(struct anv_device *device, int fd,
1460 enum anv_bo_alloc_flags alloc_flags,
1461 uint64_t client_address,
1462 struct anv_bo **bo);
1463 VkResult anv_device_export_bo(struct anv_device *device,
1464 struct anv_bo *bo, int *fd_out);
1465 void anv_device_release_bo(struct anv_device *device,
1466 struct anv_bo *bo);
1467
1468 static inline struct anv_bo *
1469 anv_device_lookup_bo(struct anv_device *device, uint32_t gem_handle)
1470 {
1471 return util_sparse_array_get(&device->bo_cache.bo_map, gem_handle);
1472 }
1473
1474 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1475 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1476 int64_t timeout);
1477
1478 VkResult anv_queue_init(struct anv_device *device, struct anv_queue *queue);
1479 void anv_queue_finish(struct anv_queue *queue);
1480
1481 VkResult anv_queue_execbuf_locked(struct anv_queue *queue, struct anv_queue_submit *submit);
1482 VkResult anv_queue_submit_simple_batch(struct anv_queue *queue,
1483 struct anv_batch *batch);
1484
1485 uint64_t anv_gettime_ns(void);
1486 uint64_t anv_get_absolute_timeout(uint64_t timeout);
1487
1488 void* anv_gem_mmap(struct anv_device *device,
1489 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1490 void anv_gem_munmap(struct anv_device *device, void *p, uint64_t size);
1491 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1492 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1493 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1494 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1495 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1496 int anv_gem_execbuffer(struct anv_device *device,
1497 struct drm_i915_gem_execbuffer2 *execbuf);
1498 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1499 uint32_t stride, uint32_t tiling);
1500 int anv_gem_create_context(struct anv_device *device);
1501 bool anv_gem_has_context_priority(int fd);
1502 int anv_gem_destroy_context(struct anv_device *device, int context);
1503 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1504 uint64_t value);
1505 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1506 uint64_t *value);
1507 int anv_gem_get_param(int fd, uint32_t param);
1508 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1509 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1510 int anv_gem_get_aperture(int fd, uint64_t *size);
1511 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1512 uint32_t *active, uint32_t *pending);
1513 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1514 int anv_gem_reg_read(struct anv_device *device,
1515 uint32_t offset, uint64_t *result);
1516 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1517 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1518 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1519 uint32_t read_domains, uint32_t write_domain);
1520 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1521 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1522 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1523 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1524 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1525 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1526 uint32_t handle);
1527 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1528 uint32_t handle, int fd);
1529 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1530 bool anv_gem_supports_syncobj_wait(int fd);
1531 int anv_gem_syncobj_wait(struct anv_device *device,
1532 uint32_t *handles, uint32_t num_handles,
1533 int64_t abs_timeout_ns, bool wait_all);
1534
1535 uint64_t anv_vma_alloc(struct anv_device *device,
1536 uint64_t size, uint64_t align,
1537 enum anv_bo_alloc_flags alloc_flags,
1538 uint64_t client_address);
1539 void anv_vma_free(struct anv_device *device,
1540 uint64_t address, uint64_t size);
1541
1542 struct anv_reloc_list {
1543 uint32_t num_relocs;
1544 uint32_t array_length;
1545 struct drm_i915_gem_relocation_entry * relocs;
1546 struct anv_bo ** reloc_bos;
1547 uint32_t dep_words;
1548 BITSET_WORD * deps;
1549 };
1550
1551 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1552 const VkAllocationCallbacks *alloc);
1553 void anv_reloc_list_finish(struct anv_reloc_list *list,
1554 const VkAllocationCallbacks *alloc);
1555
1556 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1557 const VkAllocationCallbacks *alloc,
1558 uint32_t offset, struct anv_bo *target_bo,
1559 uint32_t delta, uint64_t *address_u64_out);
1560
1561 struct anv_batch_bo {
1562 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1563 struct list_head link;
1564
1565 struct anv_bo * bo;
1566
1567 /* Bytes actually consumed in this batch BO */
1568 uint32_t length;
1569
1570 struct anv_reloc_list relocs;
1571 };
1572
1573 struct anv_batch {
1574 const VkAllocationCallbacks * alloc;
1575
1576 void * start;
1577 void * end;
1578 void * next;
1579
1580 struct anv_reloc_list * relocs;
1581
1582 /* This callback is called (with the associated user data) in the event
1583 * that the batch runs out of space.
1584 */
1585 VkResult (*extend_cb)(struct anv_batch *, void *);
1586 void * user_data;
1587
1588 /**
1589 * Current error status of the command buffer. Used to track inconsistent
1590 * or incomplete command buffer states that are the consequence of run-time
1591 * errors such as out of memory scenarios. We want to track this in the
1592 * batch because the command buffer object is not visible to some parts
1593 * of the driver.
1594 */
1595 VkResult status;
1596 };
1597
1598 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1599 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1600 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1601 void *location, struct anv_bo *bo, uint32_t offset);
1602
1603 static inline VkResult
1604 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1605 {
1606 assert(error != VK_SUCCESS);
1607 if (batch->status == VK_SUCCESS)
1608 batch->status = error;
1609 return batch->status;
1610 }
1611
1612 static inline bool
1613 anv_batch_has_error(struct anv_batch *batch)
1614 {
1615 return batch->status != VK_SUCCESS;
1616 }
1617
1618 struct anv_address {
1619 struct anv_bo *bo;
1620 uint32_t offset;
1621 };
1622
1623 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1624
1625 static inline bool
1626 anv_address_is_null(struct anv_address addr)
1627 {
1628 return addr.bo == NULL && addr.offset == 0;
1629 }
1630
1631 static inline uint64_t
1632 anv_address_physical(struct anv_address addr)
1633 {
1634 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1635 return gen_canonical_address(addr.bo->offset + addr.offset);
1636 else
1637 return gen_canonical_address(addr.offset);
1638 }
1639
1640 static inline struct anv_address
1641 anv_address_add(struct anv_address addr, uint64_t offset)
1642 {
1643 addr.offset += offset;
1644 return addr;
1645 }
1646
1647 static inline void
1648 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1649 {
1650 unsigned reloc_size = 0;
1651 if (device->info.gen >= 8) {
1652 reloc_size = sizeof(uint64_t);
1653 *(uint64_t *)p = gen_canonical_address(v);
1654 } else {
1655 reloc_size = sizeof(uint32_t);
1656 *(uint32_t *)p = v;
1657 }
1658
1659 if (flush && !device->info.has_llc)
1660 gen_flush_range(p, reloc_size);
1661 }
1662
1663 static inline uint64_t
1664 _anv_combine_address(struct anv_batch *batch, void *location,
1665 const struct anv_address address, uint32_t delta)
1666 {
1667 if (address.bo == NULL) {
1668 return address.offset + delta;
1669 } else {
1670 assert(batch->start <= location && location < batch->end);
1671
1672 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1673 }
1674 }
1675
1676 #define __gen_address_type struct anv_address
1677 #define __gen_user_data struct anv_batch
1678 #define __gen_combine_address _anv_combine_address
1679
1680 /* Wrapper macros needed to work around preprocessor argument issues. In
1681 * particular, arguments don't get pre-evaluated if they are concatenated.
1682 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1683 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1684 * We can work around this easily enough with these helpers.
1685 */
1686 #define __anv_cmd_length(cmd) cmd ## _length
1687 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1688 #define __anv_cmd_header(cmd) cmd ## _header
1689 #define __anv_cmd_pack(cmd) cmd ## _pack
1690 #define __anv_reg_num(reg) reg ## _num
1691
1692 #define anv_pack_struct(dst, struc, ...) do { \
1693 struct struc __template = { \
1694 __VA_ARGS__ \
1695 }; \
1696 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1697 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1698 } while (0)
1699
1700 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1701 void *__dst = anv_batch_emit_dwords(batch, n); \
1702 if (__dst) { \
1703 struct cmd __template = { \
1704 __anv_cmd_header(cmd), \
1705 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1706 __VA_ARGS__ \
1707 }; \
1708 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1709 } \
1710 __dst; \
1711 })
1712
1713 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1714 do { \
1715 uint32_t *dw; \
1716 \
1717 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1718 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1719 if (!dw) \
1720 break; \
1721 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1722 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1723 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1724 } while (0)
1725
1726 #define anv_batch_emit(batch, cmd, name) \
1727 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1728 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1729 __builtin_expect(_dst != NULL, 1); \
1730 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1731 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1732 _dst = NULL; \
1733 }))
1734
1735 struct anv_device_memory {
1736 struct vk_object_base base;
1737
1738 struct list_head link;
1739
1740 struct anv_bo * bo;
1741 struct anv_memory_type * type;
1742 VkDeviceSize map_size;
1743 void * map;
1744
1745 /* If set, we are holding reference to AHardwareBuffer
1746 * which we must release when memory is freed.
1747 */
1748 struct AHardwareBuffer * ahw;
1749
1750 /* If set, this memory comes from a host pointer. */
1751 void * host_ptr;
1752 };
1753
1754 /**
1755 * Header for Vertex URB Entry (VUE)
1756 */
1757 struct anv_vue_header {
1758 uint32_t Reserved;
1759 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1760 uint32_t ViewportIndex;
1761 float PointWidth;
1762 };
1763
1764 /** Struct representing a sampled image descriptor
1765 *
1766 * This descriptor layout is used for sampled images, bare sampler, and
1767 * combined image/sampler descriptors.
1768 */
1769 struct anv_sampled_image_descriptor {
1770 /** Bindless image handle
1771 *
1772 * This is expected to already be shifted such that the 20-bit
1773 * SURFACE_STATE table index is in the top 20 bits.
1774 */
1775 uint32_t image;
1776
1777 /** Bindless sampler handle
1778 *
1779 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1780 * to the dynamic state base address.
1781 */
1782 uint32_t sampler;
1783 };
1784
1785 struct anv_texture_swizzle_descriptor {
1786 /** Texture swizzle
1787 *
1788 * See also nir_intrinsic_channel_select_intel
1789 */
1790 uint8_t swizzle[4];
1791
1792 /** Unused padding to ensure the struct is a multiple of 64 bits */
1793 uint32_t _pad;
1794 };
1795
1796 /** Struct representing a storage image descriptor */
1797 struct anv_storage_image_descriptor {
1798 /** Bindless image handles
1799 *
1800 * These are expected to already be shifted such that the 20-bit
1801 * SURFACE_STATE table index is in the top 20 bits.
1802 */
1803 uint32_t read_write;
1804 uint32_t write_only;
1805 };
1806
1807 /** Struct representing a address/range descriptor
1808 *
1809 * The fields of this struct correspond directly to the data layout of
1810 * nir_address_format_64bit_bounded_global addresses. The last field is the
1811 * offset in the NIR address so it must be zero so that when you load the
1812 * descriptor you get a pointer to the start of the range.
1813 */
1814 struct anv_address_range_descriptor {
1815 uint64_t address;
1816 uint32_t range;
1817 uint32_t zero;
1818 };
1819
1820 enum anv_descriptor_data {
1821 /** The descriptor contains a BTI reference to a surface state */
1822 ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0),
1823 /** The descriptor contains a BTI reference to a sampler state */
1824 ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1),
1825 /** The descriptor contains an actual buffer view */
1826 ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2),
1827 /** The descriptor contains auxiliary image layout data */
1828 ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3),
1829 /** The descriptor contains auxiliary image layout data */
1830 ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4),
1831 /** anv_address_range_descriptor with a buffer address and range */
1832 ANV_DESCRIPTOR_ADDRESS_RANGE = (1 << 5),
1833 /** Bindless surface handle */
1834 ANV_DESCRIPTOR_SAMPLED_IMAGE = (1 << 6),
1835 /** Storage image handles */
1836 ANV_DESCRIPTOR_STORAGE_IMAGE = (1 << 7),
1837 /** Storage image handles */
1838 ANV_DESCRIPTOR_TEXTURE_SWIZZLE = (1 << 8),
1839 };
1840
1841 struct anv_descriptor_set_binding_layout {
1842 #ifndef NDEBUG
1843 /* The type of the descriptors in this binding */
1844 VkDescriptorType type;
1845 #endif
1846
1847 /* Flags provided when this binding was created */
1848 VkDescriptorBindingFlagsEXT flags;
1849
1850 /* Bitfield representing the type of data this descriptor contains */
1851 enum anv_descriptor_data data;
1852
1853 /* Maximum number of YCbCr texture/sampler planes */
1854 uint8_t max_plane_count;
1855
1856 /* Number of array elements in this binding (or size in bytes for inline
1857 * uniform data)
1858 */
1859 uint16_t array_size;
1860
1861 /* Index into the flattend descriptor set */
1862 uint16_t descriptor_index;
1863
1864 /* Index into the dynamic state array for a dynamic buffer */
1865 int16_t dynamic_offset_index;
1866
1867 /* Index into the descriptor set buffer views */
1868 int16_t buffer_view_index;
1869
1870 /* Offset into the descriptor buffer where this descriptor lives */
1871 uint32_t descriptor_offset;
1872
1873 /* Immutable samplers (or NULL if no immutable samplers) */
1874 struct anv_sampler **immutable_samplers;
1875 };
1876
1877 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout);
1878
1879 unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice,
1880 VkDescriptorType type);
1881
1882 bool anv_descriptor_supports_bindless(const struct anv_physical_device *pdevice,
1883 const struct anv_descriptor_set_binding_layout *binding,
1884 bool sampler);
1885
1886 bool anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice,
1887 const struct anv_descriptor_set_binding_layout *binding,
1888 bool sampler);
1889
1890 struct anv_descriptor_set_layout {
1891 struct vk_object_base base;
1892
1893 /* Descriptor set layouts can be destroyed at almost any time */
1894 uint32_t ref_cnt;
1895
1896 /* Number of bindings in this descriptor set */
1897 uint16_t binding_count;
1898
1899 /* Total size of the descriptor set with room for all array entries */
1900 uint16_t size;
1901
1902 /* Shader stages affected by this descriptor set */
1903 uint16_t shader_stages;
1904
1905 /* Number of buffer views in this descriptor set */
1906 uint16_t buffer_view_count;
1907
1908 /* Number of dynamic offsets used by this descriptor set */
1909 uint16_t dynamic_offset_count;
1910
1911 /* For each shader stage, which offsets apply to that stage */
1912 uint16_t stage_dynamic_offsets[MESA_SHADER_STAGES];
1913
1914 /* Size of the descriptor buffer for this descriptor set */
1915 uint32_t descriptor_buffer_size;
1916
1917 /* Bindings in this descriptor set */
1918 struct anv_descriptor_set_binding_layout binding[0];
1919 };
1920
1921 void anv_descriptor_set_layout_destroy(struct anv_device *device,
1922 struct anv_descriptor_set_layout *layout);
1923
1924 static inline void
1925 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1926 {
1927 assert(layout && layout->ref_cnt >= 1);
1928 p_atomic_inc(&layout->ref_cnt);
1929 }
1930
1931 static inline void
1932 anv_descriptor_set_layout_unref(struct anv_device *device,
1933 struct anv_descriptor_set_layout *layout)
1934 {
1935 assert(layout && layout->ref_cnt >= 1);
1936 if (p_atomic_dec_zero(&layout->ref_cnt))
1937 anv_descriptor_set_layout_destroy(device, layout);
1938 }
1939
1940 struct anv_descriptor {
1941 VkDescriptorType type;
1942
1943 union {
1944 struct {
1945 VkImageLayout layout;
1946 struct anv_image_view *image_view;
1947 struct anv_sampler *sampler;
1948 };
1949
1950 struct {
1951 struct anv_buffer *buffer;
1952 uint64_t offset;
1953 uint64_t range;
1954 };
1955
1956 struct anv_buffer_view *buffer_view;
1957 };
1958 };
1959
1960 struct anv_descriptor_set {
1961 struct vk_object_base base;
1962
1963 struct anv_descriptor_pool *pool;
1964 struct anv_descriptor_set_layout *layout;
1965 uint32_t size;
1966
1967 /* State relative to anv_descriptor_pool::bo */
1968 struct anv_state desc_mem;
1969 /* Surface state for the descriptor buffer */
1970 struct anv_state desc_surface_state;
1971
1972 uint32_t buffer_view_count;
1973 struct anv_buffer_view *buffer_views;
1974
1975 /* Link to descriptor pool's desc_sets list . */
1976 struct list_head pool_link;
1977
1978 struct anv_descriptor descriptors[0];
1979 };
1980
1981 struct anv_buffer_view {
1982 struct vk_object_base base;
1983
1984 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1985 uint64_t range; /**< VkBufferViewCreateInfo::range */
1986
1987 struct anv_address address;
1988
1989 struct anv_state surface_state;
1990 struct anv_state storage_surface_state;
1991 struct anv_state writeonly_storage_surface_state;
1992
1993 struct brw_image_param storage_image_param;
1994 };
1995
1996 struct anv_push_descriptor_set {
1997 struct anv_descriptor_set set;
1998
1999 /* Put this field right behind anv_descriptor_set so it fills up the
2000 * descriptors[0] field. */
2001 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
2002
2003 /** True if the descriptor set buffer has been referenced by a draw or
2004 * dispatch command.
2005 */
2006 bool set_used_on_gpu;
2007
2008 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
2009 };
2010
2011 struct anv_descriptor_pool {
2012 struct vk_object_base base;
2013
2014 uint32_t size;
2015 uint32_t next;
2016 uint32_t free_list;
2017
2018 struct anv_bo *bo;
2019 struct util_vma_heap bo_heap;
2020
2021 struct anv_state_stream surface_state_stream;
2022 void *surface_state_free_list;
2023
2024 struct list_head desc_sets;
2025
2026 char data[0];
2027 };
2028
2029 enum anv_descriptor_template_entry_type {
2030 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
2031 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
2032 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2033 };
2034
2035 struct anv_descriptor_template_entry {
2036 /* The type of descriptor in this entry */
2037 VkDescriptorType type;
2038
2039 /* Binding in the descriptor set */
2040 uint32_t binding;
2041
2042 /* Offset at which to write into the descriptor set binding */
2043 uint32_t array_element;
2044
2045 /* Number of elements to write into the descriptor set binding */
2046 uint32_t array_count;
2047
2048 /* Offset into the user provided data */
2049 size_t offset;
2050
2051 /* Stride between elements into the user provided data */
2052 size_t stride;
2053 };
2054
2055 struct anv_descriptor_update_template {
2056 struct vk_object_base base;
2057
2058 VkPipelineBindPoint bind_point;
2059
2060 /* The descriptor set this template corresponds to. This value is only
2061 * valid if the template was created with the templateType
2062 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2063 */
2064 uint8_t set;
2065
2066 /* Number of entries in this template */
2067 uint32_t entry_count;
2068
2069 /* Entries of the template */
2070 struct anv_descriptor_template_entry entries[0];
2071 };
2072
2073 size_t
2074 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
2075
2076 void
2077 anv_descriptor_set_write_image_view(struct anv_device *device,
2078 struct anv_descriptor_set *set,
2079 const VkDescriptorImageInfo * const info,
2080 VkDescriptorType type,
2081 uint32_t binding,
2082 uint32_t element);
2083
2084 void
2085 anv_descriptor_set_write_buffer_view(struct anv_device *device,
2086 struct anv_descriptor_set *set,
2087 VkDescriptorType type,
2088 struct anv_buffer_view *buffer_view,
2089 uint32_t binding,
2090 uint32_t element);
2091
2092 void
2093 anv_descriptor_set_write_buffer(struct anv_device *device,
2094 struct anv_descriptor_set *set,
2095 struct anv_state_stream *alloc_stream,
2096 VkDescriptorType type,
2097 struct anv_buffer *buffer,
2098 uint32_t binding,
2099 uint32_t element,
2100 VkDeviceSize offset,
2101 VkDeviceSize range);
2102 void
2103 anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
2104 struct anv_descriptor_set *set,
2105 uint32_t binding,
2106 const void *data,
2107 size_t offset,
2108 size_t size);
2109
2110 void
2111 anv_descriptor_set_write_template(struct anv_device *device,
2112 struct anv_descriptor_set *set,
2113 struct anv_state_stream *alloc_stream,
2114 const struct anv_descriptor_update_template *template,
2115 const void *data);
2116
2117 VkResult
2118 anv_descriptor_set_create(struct anv_device *device,
2119 struct anv_descriptor_pool *pool,
2120 struct anv_descriptor_set_layout *layout,
2121 struct anv_descriptor_set **out_set);
2122
2123 void
2124 anv_descriptor_set_destroy(struct anv_device *device,
2125 struct anv_descriptor_pool *pool,
2126 struct anv_descriptor_set *set);
2127
2128 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2129 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2130 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2131 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2132 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2133 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2134
2135 struct anv_pipeline_binding {
2136 /** Index in the descriptor set
2137 *
2138 * This is a flattened index; the descriptor set layout is already taken
2139 * into account.
2140 */
2141 uint32_t index;
2142
2143 /** The descriptor set this surface corresponds to.
2144 *
2145 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2146 * binding is not a normal descriptor set but something else.
2147 */
2148 uint8_t set;
2149
2150 union {
2151 /** Plane in the binding index for images */
2152 uint8_t plane;
2153
2154 /** Input attachment index (relative to the subpass) */
2155 uint8_t input_attachment_index;
2156
2157 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2158 uint8_t dynamic_offset_index;
2159 };
2160
2161 /** For a storage image, whether it is write-only */
2162 uint8_t write_only;
2163
2164 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2165 * assuming POD zero-initialization.
2166 */
2167 uint8_t pad;
2168 };
2169
2170 struct anv_push_range {
2171 /** Index in the descriptor set */
2172 uint32_t index;
2173
2174 /** Descriptor set index */
2175 uint8_t set;
2176
2177 /** Dynamic offset index (for dynamic UBOs) */
2178 uint8_t dynamic_offset_index;
2179
2180 /** Start offset in units of 32B */
2181 uint8_t start;
2182
2183 /** Range in units of 32B */
2184 uint8_t length;
2185 };
2186
2187 struct anv_pipeline_layout {
2188 struct vk_object_base base;
2189
2190 struct {
2191 struct anv_descriptor_set_layout *layout;
2192 uint32_t dynamic_offset_start;
2193 } set[MAX_SETS];
2194
2195 uint32_t num_sets;
2196
2197 unsigned char sha1[20];
2198 };
2199
2200 struct anv_buffer {
2201 struct vk_object_base base;
2202
2203 struct anv_device * device;
2204 VkDeviceSize size;
2205
2206 VkBufferUsageFlags usage;
2207
2208 /* Set when bound */
2209 struct anv_address address;
2210 };
2211
2212 static inline uint64_t
2213 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
2214 {
2215 assert(offset <= buffer->size);
2216 if (range == VK_WHOLE_SIZE) {
2217 return buffer->size - offset;
2218 } else {
2219 assert(range + offset >= range);
2220 assert(range + offset <= buffer->size);
2221 return range;
2222 }
2223 }
2224
2225 enum anv_cmd_dirty_bits {
2226 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2227 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2228 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2229 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2230 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2231 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2232 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2233 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2234 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2235 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
2236 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
2237 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
2238 ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
2239 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2240 };
2241 typedef uint32_t anv_cmd_dirty_mask_t;
2242
2243 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2244 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2245 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2246 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2247 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2248 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2249 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2250 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2251 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2252 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2253 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2254
2255 static inline enum anv_cmd_dirty_bits
2256 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
2257 {
2258 switch (vk_state) {
2259 case VK_DYNAMIC_STATE_VIEWPORT:
2260 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2261 case VK_DYNAMIC_STATE_SCISSOR:
2262 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
2263 case VK_DYNAMIC_STATE_LINE_WIDTH:
2264 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2265 case VK_DYNAMIC_STATE_DEPTH_BIAS:
2266 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2267 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
2268 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2269 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
2270 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2271 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
2272 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2273 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
2274 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2275 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2276 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2277 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
2278 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
2279 default:
2280 assert(!"Unsupported dynamic state");
2281 return 0;
2282 }
2283 }
2284
2285
2286 enum anv_pipe_bits {
2287 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
2288 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
2289 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
2290 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
2291 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
2292 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
2293 ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
2294 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
2295 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
2296 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
2297 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
2298 ANV_PIPE_CS_STALL_BIT = (1 << 20),
2299 ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
2300
2301 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2302 * a flush has happened but not a CS stall. The next time we do any sort
2303 * of invalidation we need to insert a CS stall at that time. Otherwise,
2304 * we would have to CS stall on every flush which could be bad.
2305 */
2306 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT = (1 << 22),
2307
2308 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2309 * target operations related to transfer commands with VkBuffer as
2310 * destination are ongoing. Some operations like copies on the command
2311 * streamer might need to be aware of this to trigger the appropriate stall
2312 * before they can proceed with the copy.
2313 */
2314 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 23),
2315
2316 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2317 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2318 * done by writing the AUX-TT register.
2319 */
2320 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 24),
2321
2322 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2323 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2324 * implement a workaround for Gen9.
2325 */
2326 ANV_PIPE_POST_SYNC_BIT = (1 << 25),
2327 };
2328
2329 #define ANV_PIPE_FLUSH_BITS ( \
2330 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2331 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2332 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2333 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2334
2335 #define ANV_PIPE_STALL_BITS ( \
2336 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2337 ANV_PIPE_DEPTH_STALL_BIT | \
2338 ANV_PIPE_CS_STALL_BIT)
2339
2340 #define ANV_PIPE_INVALIDATE_BITS ( \
2341 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2342 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2343 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2344 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2345 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2346 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2347 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2348
2349 static inline enum anv_pipe_bits
2350 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
2351 {
2352 enum anv_pipe_bits pipe_bits = 0;
2353
2354 unsigned b;
2355 for_each_bit(b, flags) {
2356 switch ((VkAccessFlagBits)(1 << b)) {
2357 case VK_ACCESS_SHADER_WRITE_BIT:
2358 /* We're transitioning a buffer that was previously used as write
2359 * destination through the data port. To make its content available
2360 * to future operations, flush the data cache.
2361 */
2362 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2363 break;
2364 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2365 /* We're transitioning a buffer that was previously used as render
2366 * target. To make its content available to future operations, flush
2367 * the render target cache.
2368 */
2369 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2370 break;
2371 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2372 /* We're transitioning a buffer that was previously used as depth
2373 * buffer. To make its content available to future operations, flush
2374 * the depth cache.
2375 */
2376 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2377 break;
2378 case VK_ACCESS_TRANSFER_WRITE_BIT:
2379 /* We're transitioning a buffer that was previously used as a
2380 * transfer write destination. Generic write operations include color
2381 * & depth operations as well as buffer operations like :
2382 * - vkCmdClearColorImage()
2383 * - vkCmdClearDepthStencilImage()
2384 * - vkCmdBlitImage()
2385 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2386 *
2387 * Most of these operations are implemented using Blorp which writes
2388 * through the render target, so flush that cache to make it visible
2389 * to future operations. And for depth related operations we also
2390 * need to flush the depth cache.
2391 */
2392 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2393 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2394 break;
2395 case VK_ACCESS_MEMORY_WRITE_BIT:
2396 /* We're transitioning a buffer for generic write operations. Flush
2397 * all the caches.
2398 */
2399 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2400 break;
2401 default:
2402 break; /* Nothing to do */
2403 }
2404 }
2405
2406 return pipe_bits;
2407 }
2408
2409 static inline enum anv_pipe_bits
2410 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
2411 {
2412 enum anv_pipe_bits pipe_bits = 0;
2413
2414 unsigned b;
2415 for_each_bit(b, flags) {
2416 switch ((VkAccessFlagBits)(1 << b)) {
2417 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2418 /* Indirect draw commands take a buffer as input that we're going to
2419 * read from the command streamer to load some of the HW registers
2420 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2421 * command streamer stall so that all the cache flushes have
2422 * completed before the command streamer loads from memory.
2423 */
2424 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2425 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2426 * through a vertex buffer, so invalidate that cache.
2427 */
2428 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2429 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2430 * UBO from the buffer, so we need to invalidate constant cache.
2431 */
2432 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2433 break;
2434 case VK_ACCESS_INDEX_READ_BIT:
2435 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2436 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2437 * commands, so we invalidate the VF cache to make sure there is no
2438 * stale data when we start rendering.
2439 */
2440 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2441 break;
2442 case VK_ACCESS_UNIFORM_READ_BIT:
2443 /* We transitioning a buffer to be used as uniform data. Because
2444 * uniform is accessed through the data port & sampler, we need to
2445 * invalidate the texture cache (sampler) & constant cache (data
2446 * port) to avoid stale data.
2447 */
2448 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2449 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2450 break;
2451 case VK_ACCESS_SHADER_READ_BIT:
2452 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2453 case VK_ACCESS_TRANSFER_READ_BIT:
2454 /* Transitioning a buffer to be read through the sampler, so
2455 * invalidate the texture cache, we don't want any stale data.
2456 */
2457 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2458 break;
2459 case VK_ACCESS_MEMORY_READ_BIT:
2460 /* Transitioning a buffer for generic read, invalidate all the
2461 * caches.
2462 */
2463 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
2464 break;
2465 case VK_ACCESS_MEMORY_WRITE_BIT:
2466 /* Generic write, make sure all previously written things land in
2467 * memory.
2468 */
2469 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2470 break;
2471 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
2472 /* Transitioning a buffer for conditional rendering. We'll load the
2473 * content of this buffer into HW registers using the command
2474 * streamer, so we need to stall the command streamer to make sure
2475 * any in-flight flush operations have completed.
2476 */
2477 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2478 break;
2479 default:
2480 break; /* Nothing to do */
2481 }
2482 }
2483
2484 return pipe_bits;
2485 }
2486
2487 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2488 VK_IMAGE_ASPECT_COLOR_BIT | \
2489 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2490 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2491 VK_IMAGE_ASPECT_PLANE_2_BIT)
2492 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2493 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2494 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2495 VK_IMAGE_ASPECT_PLANE_2_BIT)
2496
2497 struct anv_vertex_binding {
2498 struct anv_buffer * buffer;
2499 VkDeviceSize offset;
2500 };
2501
2502 struct anv_xfb_binding {
2503 struct anv_buffer * buffer;
2504 VkDeviceSize offset;
2505 VkDeviceSize size;
2506 };
2507
2508 struct anv_push_constants {
2509 /** Push constant data provided by the client through vkPushConstants */
2510 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
2511
2512 /** Dynamic offsets for dynamic UBOs and SSBOs */
2513 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2514
2515 uint64_t push_reg_mask;
2516
2517 /** Pad out to a multiple of 32 bytes */
2518 uint32_t pad[2];
2519
2520 struct {
2521 /** Base workgroup ID
2522 *
2523 * Used for vkCmdDispatchBase.
2524 */
2525 uint32_t base_work_group_id[3];
2526
2527 /** Subgroup ID
2528 *
2529 * This is never set by software but is implicitly filled out when
2530 * uploading the push constants for compute shaders.
2531 */
2532 uint32_t subgroup_id;
2533 } cs;
2534 };
2535
2536 struct anv_dynamic_state {
2537 struct {
2538 uint32_t count;
2539 VkViewport viewports[MAX_VIEWPORTS];
2540 } viewport;
2541
2542 struct {
2543 uint32_t count;
2544 VkRect2D scissors[MAX_SCISSORS];
2545 } scissor;
2546
2547 float line_width;
2548
2549 struct {
2550 float bias;
2551 float clamp;
2552 float slope;
2553 } depth_bias;
2554
2555 float blend_constants[4];
2556
2557 struct {
2558 float min;
2559 float max;
2560 } depth_bounds;
2561
2562 struct {
2563 uint32_t front;
2564 uint32_t back;
2565 } stencil_compare_mask;
2566
2567 struct {
2568 uint32_t front;
2569 uint32_t back;
2570 } stencil_write_mask;
2571
2572 struct {
2573 uint32_t front;
2574 uint32_t back;
2575 } stencil_reference;
2576
2577 struct {
2578 uint32_t factor;
2579 uint16_t pattern;
2580 } line_stipple;
2581 };
2582
2583 extern const struct anv_dynamic_state default_dynamic_state;
2584
2585 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state *dest,
2586 const struct anv_dynamic_state *src,
2587 uint32_t copy_mask);
2588
2589 struct anv_surface_state {
2590 struct anv_state state;
2591 /** Address of the surface referred to by this state
2592 *
2593 * This address is relative to the start of the BO.
2594 */
2595 struct anv_address address;
2596 /* Address of the aux surface, if any
2597 *
2598 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2599 *
2600 * With the exception of gen8, the bottom 12 bits of this address' offset
2601 * include extra aux information.
2602 */
2603 struct anv_address aux_address;
2604 /* Address of the clear color, if any
2605 *
2606 * This address is relative to the start of the BO.
2607 */
2608 struct anv_address clear_address;
2609 };
2610
2611 /**
2612 * Attachment state when recording a renderpass instance.
2613 *
2614 * The clear value is valid only if there exists a pending clear.
2615 */
2616 struct anv_attachment_state {
2617 enum isl_aux_usage aux_usage;
2618 struct anv_surface_state color;
2619 struct anv_surface_state input;
2620
2621 VkImageLayout current_layout;
2622 VkImageLayout current_stencil_layout;
2623 VkImageAspectFlags pending_clear_aspects;
2624 VkImageAspectFlags pending_load_aspects;
2625 bool fast_clear;
2626 VkClearValue clear_value;
2627
2628 /* When multiview is active, attachments with a renderpass clear
2629 * operation have their respective layers cleared on the first
2630 * subpass that uses them, and only in that subpass. We keep track
2631 * of this using a bitfield to indicate which layers of an attachment
2632 * have not been cleared yet when multiview is active.
2633 */
2634 uint32_t pending_clear_views;
2635 struct anv_image_view * image_view;
2636 };
2637
2638 /** State tracking for vertex buffer flushes
2639 *
2640 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2641 * addresses. If you happen to have two vertex buffers which get placed
2642 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2643 * collisions. In order to solve this problem, we track vertex address ranges
2644 * which are live in the cache and invalidate the cache if one ever exceeds 32
2645 * bits.
2646 */
2647 struct anv_vb_cache_range {
2648 /* Virtual address at which the live vertex buffer cache range starts for
2649 * this vertex buffer index.
2650 */
2651 uint64_t start;
2652
2653 /* Virtual address of the byte after where vertex buffer cache range ends.
2654 * This is exclusive such that end - start is the size of the range.
2655 */
2656 uint64_t end;
2657 };
2658
2659 /** State tracking for particular pipeline bind point
2660 *
2661 * This struct is the base struct for anv_cmd_graphics_state and
2662 * anv_cmd_compute_state. These are used to track state which is bound to a
2663 * particular type of pipeline. Generic state that applies per-stage such as
2664 * binding table offsets and push constants is tracked generically with a
2665 * per-stage array in anv_cmd_state.
2666 */
2667 struct anv_cmd_pipeline_state {
2668 struct anv_descriptor_set *descriptors[MAX_SETS];
2669 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2670 };
2671
2672 /** State tracking for graphics pipeline
2673 *
2674 * This has anv_cmd_pipeline_state as a base struct to track things which get
2675 * bound to a graphics pipeline. Along with general pipeline bind point state
2676 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2677 * state which is graphics-specific.
2678 */
2679 struct anv_cmd_graphics_state {
2680 struct anv_cmd_pipeline_state base;
2681
2682 struct anv_graphics_pipeline *pipeline;
2683
2684 anv_cmd_dirty_mask_t dirty;
2685 uint32_t vb_dirty;
2686
2687 struct anv_vb_cache_range ib_bound_range;
2688 struct anv_vb_cache_range ib_dirty_range;
2689 struct anv_vb_cache_range vb_bound_ranges[33];
2690 struct anv_vb_cache_range vb_dirty_ranges[33];
2691
2692 struct anv_dynamic_state dynamic;
2693
2694 struct {
2695 struct anv_buffer *index_buffer;
2696 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2697 uint32_t index_offset;
2698 } gen7;
2699 };
2700
2701 /** State tracking for compute pipeline
2702 *
2703 * This has anv_cmd_pipeline_state as a base struct to track things which get
2704 * bound to a compute pipeline. Along with general pipeline bind point state
2705 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2706 * state which is compute-specific.
2707 */
2708 struct anv_cmd_compute_state {
2709 struct anv_cmd_pipeline_state base;
2710
2711 struct anv_compute_pipeline *pipeline;
2712
2713 bool pipeline_dirty;
2714
2715 struct anv_address num_workgroups;
2716 };
2717
2718 /** State required while building cmd buffer */
2719 struct anv_cmd_state {
2720 /* PIPELINE_SELECT.PipelineSelection */
2721 uint32_t current_pipeline;
2722 const struct gen_l3_config * current_l3_config;
2723 uint32_t last_aux_map_state;
2724
2725 struct anv_cmd_graphics_state gfx;
2726 struct anv_cmd_compute_state compute;
2727
2728 enum anv_pipe_bits pending_pipe_bits;
2729 VkShaderStageFlags descriptors_dirty;
2730 VkShaderStageFlags push_constants_dirty;
2731
2732 struct anv_framebuffer * framebuffer;
2733 struct anv_render_pass * pass;
2734 struct anv_subpass * subpass;
2735 VkRect2D render_area;
2736 uint32_t restart_index;
2737 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2738 bool xfb_enabled;
2739 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
2740 VkShaderStageFlags push_constant_stages;
2741 struct anv_push_constants push_constants[MESA_SHADER_STAGES];
2742 struct anv_state binding_tables[MESA_SHADER_STAGES];
2743 struct anv_state samplers[MESA_SHADER_STAGES];
2744
2745 unsigned char sampler_sha1s[MESA_SHADER_STAGES][20];
2746 unsigned char surface_sha1s[MESA_SHADER_STAGES][20];
2747 unsigned char push_sha1s[MESA_SHADER_STAGES][20];
2748
2749 /**
2750 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2751 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2752 * and before invoking the secondary in ExecuteCommands.
2753 */
2754 bool pma_fix_enabled;
2755
2756 /**
2757 * Whether or not we know for certain that HiZ is enabled for the current
2758 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2759 * enabled or not, this will be false.
2760 */
2761 bool hiz_enabled;
2762
2763 bool conditional_render_enabled;
2764
2765 /**
2766 * Last rendering scale argument provided to
2767 * genX(cmd_buffer_emit_hashing_mode)().
2768 */
2769 unsigned current_hash_scale;
2770
2771 /**
2772 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2773 * valid only when recording a render pass instance.
2774 */
2775 struct anv_attachment_state * attachments;
2776
2777 /**
2778 * Surface states for color render targets. These are stored in a single
2779 * flat array. For depth-stencil attachments, the surface state is simply
2780 * left blank.
2781 */
2782 struct anv_state attachment_states;
2783
2784 /**
2785 * A null surface state of the right size to match the framebuffer. This
2786 * is one of the states in attachment_states.
2787 */
2788 struct anv_state null_surface_state;
2789 };
2790
2791 struct anv_cmd_pool {
2792 struct vk_object_base base;
2793 VkAllocationCallbacks alloc;
2794 struct list_head cmd_buffers;
2795 };
2796
2797 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2798
2799 enum anv_cmd_buffer_exec_mode {
2800 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2801 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2802 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2803 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2804 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2805 };
2806
2807 struct anv_cmd_buffer {
2808 struct vk_object_base base;
2809
2810 struct anv_device * device;
2811
2812 struct anv_cmd_pool * pool;
2813 struct list_head pool_link;
2814
2815 struct anv_batch batch;
2816
2817 /* Fields required for the actual chain of anv_batch_bo's.
2818 *
2819 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2820 */
2821 struct list_head batch_bos;
2822 enum anv_cmd_buffer_exec_mode exec_mode;
2823
2824 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2825 * referenced by this command buffer
2826 *
2827 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2828 */
2829 struct u_vector seen_bbos;
2830
2831 /* A vector of int32_t's for every block of binding tables.
2832 *
2833 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2834 */
2835 struct u_vector bt_block_states;
2836 struct anv_state bt_next;
2837
2838 struct anv_reloc_list surface_relocs;
2839 /** Last seen surface state block pool center bo offset */
2840 uint32_t last_ss_pool_center;
2841
2842 /* Serial for tracking buffer completion */
2843 uint32_t serial;
2844
2845 /* Stream objects for storing temporary data */
2846 struct anv_state_stream surface_state_stream;
2847 struct anv_state_stream dynamic_state_stream;
2848
2849 VkCommandBufferUsageFlags usage_flags;
2850 VkCommandBufferLevel level;
2851
2852 struct anv_cmd_state state;
2853
2854 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2855 uint64_t intel_perf_marker;
2856 };
2857
2858 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2859 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2860 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2861 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
2862 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
2863 struct anv_cmd_buffer *secondary);
2864 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
2865 VkResult anv_cmd_buffer_execbuf(struct anv_queue *queue,
2866 struct anv_cmd_buffer *cmd_buffer,
2867 const VkSemaphore *in_semaphores,
2868 const uint64_t *in_wait_values,
2869 uint32_t num_in_semaphores,
2870 const VkSemaphore *out_semaphores,
2871 const uint64_t *out_signal_values,
2872 uint32_t num_out_semaphores,
2873 VkFence fence);
2874
2875 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
2876
2877 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
2878 const void *data, uint32_t size, uint32_t alignment);
2879 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
2880 uint32_t *a, uint32_t *b,
2881 uint32_t dwords, uint32_t alignment);
2882
2883 struct anv_address
2884 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
2885 struct anv_state
2886 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
2887 uint32_t entries, uint32_t *state_offset);
2888 struct anv_state
2889 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
2890 struct anv_state
2891 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
2892 uint32_t size, uint32_t alignment);
2893
2894 VkResult
2895 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
2896
2897 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
2898 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
2899 bool depth_clamp_enable);
2900 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
2901
2902 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
2903 struct anv_render_pass *pass,
2904 struct anv_framebuffer *framebuffer,
2905 const VkClearValue *clear_values);
2906
2907 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
2908
2909 struct anv_state
2910 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
2911 gl_shader_stage stage);
2912 struct anv_state
2913 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
2914
2915 const struct anv_image_view *
2916 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
2917
2918 VkResult
2919 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
2920 uint32_t num_entries,
2921 uint32_t *state_offset,
2922 struct anv_state *bt_state);
2923
2924 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
2925
2926 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer);
2927
2928 enum anv_fence_type {
2929 ANV_FENCE_TYPE_NONE = 0,
2930 ANV_FENCE_TYPE_BO,
2931 ANV_FENCE_TYPE_WSI_BO,
2932 ANV_FENCE_TYPE_SYNCOBJ,
2933 ANV_FENCE_TYPE_WSI,
2934 };
2935
2936 enum anv_bo_fence_state {
2937 /** Indicates that this is a new (or newly reset fence) */
2938 ANV_BO_FENCE_STATE_RESET,
2939
2940 /** Indicates that this fence has been submitted to the GPU but is still
2941 * (as far as we know) in use by the GPU.
2942 */
2943 ANV_BO_FENCE_STATE_SUBMITTED,
2944
2945 ANV_BO_FENCE_STATE_SIGNALED,
2946 };
2947
2948 struct anv_fence_impl {
2949 enum anv_fence_type type;
2950
2951 union {
2952 /** Fence implementation for BO fences
2953 *
2954 * These fences use a BO and a set of CPU-tracked state flags. The BO
2955 * is added to the object list of the last execbuf call in a QueueSubmit
2956 * and is marked EXEC_WRITE. The state flags track when the BO has been
2957 * submitted to the kernel. We need to do this because Vulkan lets you
2958 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2959 * will say it's idle in this case.
2960 */
2961 struct {
2962 struct anv_bo *bo;
2963 enum anv_bo_fence_state state;
2964 } bo;
2965
2966 /** DRM syncobj handle for syncobj-based fences */
2967 uint32_t syncobj;
2968
2969 /** WSI fence */
2970 struct wsi_fence *fence_wsi;
2971 };
2972 };
2973
2974 struct anv_fence {
2975 struct vk_object_base base;
2976
2977 /* Permanent fence state. Every fence has some form of permanent state
2978 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2979 * cross-process fences) or it could just be a dummy for use internally.
2980 */
2981 struct anv_fence_impl permanent;
2982
2983 /* Temporary fence state. A fence *may* have temporary state. That state
2984 * is added to the fence by an import operation and is reset back to
2985 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2986 * state cannot be signaled because the fence must already be signaled
2987 * before the temporary state can be exported from the fence in the other
2988 * process and imported here.
2989 */
2990 struct anv_fence_impl temporary;
2991 };
2992
2993 void anv_fence_reset_temporary(struct anv_device *device,
2994 struct anv_fence *fence);
2995
2996 struct anv_event {
2997 struct vk_object_base base;
2998 uint64_t semaphore;
2999 struct anv_state state;
3000 };
3001
3002 enum anv_semaphore_type {
3003 ANV_SEMAPHORE_TYPE_NONE = 0,
3004 ANV_SEMAPHORE_TYPE_DUMMY,
3005 ANV_SEMAPHORE_TYPE_BO,
3006 ANV_SEMAPHORE_TYPE_WSI_BO,
3007 ANV_SEMAPHORE_TYPE_SYNC_FILE,
3008 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
3009 ANV_SEMAPHORE_TYPE_TIMELINE,
3010 };
3011
3012 struct anv_timeline_point {
3013 struct list_head link;
3014
3015 uint64_t serial;
3016
3017 /* Number of waiter on this point, when > 0 the point should not be garbage
3018 * collected.
3019 */
3020 int waiting;
3021
3022 /* BO used for synchronization. */
3023 struct anv_bo *bo;
3024 };
3025
3026 struct anv_timeline {
3027 pthread_mutex_t mutex;
3028 pthread_cond_t cond;
3029
3030 uint64_t highest_past;
3031 uint64_t highest_pending;
3032
3033 struct list_head points;
3034 struct list_head free_points;
3035 };
3036
3037 struct anv_semaphore_impl {
3038 enum anv_semaphore_type type;
3039
3040 union {
3041 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3042 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3043 * object list on any execbuf2 calls for which this semaphore is used as
3044 * a wait or signal fence. When used as a signal fence or when type ==
3045 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3046 */
3047 struct anv_bo *bo;
3048
3049 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3050 * If the semaphore is in the unsignaled state due to either just being
3051 * created or because it has been used for a wait, fd will be -1.
3052 */
3053 int fd;
3054
3055 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3056 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3057 * import so we don't need to bother with a userspace cache.
3058 */
3059 uint32_t syncobj;
3060
3061 /* Non shareable timeline semaphore
3062 *
3063 * Used when kernel don't have support for timeline semaphores.
3064 */
3065 struct anv_timeline timeline;
3066 };
3067 };
3068
3069 struct anv_semaphore {
3070 struct vk_object_base base;
3071
3072 uint32_t refcount;
3073
3074 /* Permanent semaphore state. Every semaphore has some form of permanent
3075 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3076 * (for cross-process semaphores0 or it could just be a dummy for use
3077 * internally.
3078 */
3079 struct anv_semaphore_impl permanent;
3080
3081 /* Temporary semaphore state. A semaphore *may* have temporary state.
3082 * That state is added to the semaphore by an import operation and is reset
3083 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3084 * semaphore with temporary state cannot be signaled because the semaphore
3085 * must already be signaled before the temporary state can be exported from
3086 * the semaphore in the other process and imported here.
3087 */
3088 struct anv_semaphore_impl temporary;
3089 };
3090
3091 void anv_semaphore_reset_temporary(struct anv_device *device,
3092 struct anv_semaphore *semaphore);
3093
3094 struct anv_shader_module {
3095 struct vk_object_base base;
3096
3097 unsigned char sha1[20];
3098 uint32_t size;
3099 char data[0];
3100 };
3101
3102 static inline gl_shader_stage
3103 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
3104 {
3105 assert(__builtin_popcount(vk_stage) == 1);
3106 return ffs(vk_stage) - 1;
3107 }
3108
3109 static inline VkShaderStageFlagBits
3110 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
3111 {
3112 return (1 << mesa_stage);
3113 }
3114
3115 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3116
3117 #define anv_foreach_stage(stage, stage_bits) \
3118 for (gl_shader_stage stage, \
3119 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3120 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3121 __tmp &= ~(1 << (stage)))
3122
3123 struct anv_pipeline_bind_map {
3124 unsigned char surface_sha1[20];
3125 unsigned char sampler_sha1[20];
3126 unsigned char push_sha1[20];
3127
3128 uint32_t surface_count;
3129 uint32_t sampler_count;
3130
3131 struct anv_pipeline_binding * surface_to_descriptor;
3132 struct anv_pipeline_binding * sampler_to_descriptor;
3133
3134 struct anv_push_range push_ranges[4];
3135 };
3136
3137 struct anv_shader_bin_key {
3138 uint32_t size;
3139 uint8_t data[0];
3140 };
3141
3142 struct anv_shader_bin {
3143 uint32_t ref_cnt;
3144
3145 gl_shader_stage stage;
3146
3147 const struct anv_shader_bin_key *key;
3148
3149 struct anv_state kernel;
3150 uint32_t kernel_size;
3151
3152 struct anv_state constant_data;
3153 uint32_t constant_data_size;
3154
3155 const struct brw_stage_prog_data *prog_data;
3156 uint32_t prog_data_size;
3157
3158 struct brw_compile_stats stats[3];
3159 uint32_t num_stats;
3160
3161 struct nir_xfb_info *xfb_info;
3162
3163 struct anv_pipeline_bind_map bind_map;
3164 };
3165
3166 struct anv_shader_bin *
3167 anv_shader_bin_create(struct anv_device *device,
3168 gl_shader_stage stage,
3169 const void *key, uint32_t key_size,
3170 const void *kernel, uint32_t kernel_size,
3171 const void *constant_data, uint32_t constant_data_size,
3172 const struct brw_stage_prog_data *prog_data,
3173 uint32_t prog_data_size,
3174 const struct brw_compile_stats *stats, uint32_t num_stats,
3175 const struct nir_xfb_info *xfb_info,
3176 const struct anv_pipeline_bind_map *bind_map);
3177
3178 void
3179 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
3180
3181 static inline void
3182 anv_shader_bin_ref(struct anv_shader_bin *shader)
3183 {
3184 assert(shader && shader->ref_cnt >= 1);
3185 p_atomic_inc(&shader->ref_cnt);
3186 }
3187
3188 static inline void
3189 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
3190 {
3191 assert(shader && shader->ref_cnt >= 1);
3192 if (p_atomic_dec_zero(&shader->ref_cnt))
3193 anv_shader_bin_destroy(device, shader);
3194 }
3195
3196 struct anv_pipeline_executable {
3197 gl_shader_stage stage;
3198
3199 struct brw_compile_stats stats;
3200
3201 char *nir;
3202 char *disasm;
3203 };
3204
3205 enum anv_pipeline_type {
3206 ANV_PIPELINE_GRAPHICS,
3207 ANV_PIPELINE_COMPUTE,
3208 };
3209
3210 struct anv_pipeline {
3211 struct vk_object_base base;
3212
3213 struct anv_device * device;
3214
3215 struct anv_batch batch;
3216 struct anv_reloc_list batch_relocs;
3217
3218 void * mem_ctx;
3219
3220 enum anv_pipeline_type type;
3221 VkPipelineCreateFlags flags;
3222
3223 struct util_dynarray executables;
3224
3225 const struct gen_l3_config * l3_config;
3226 };
3227
3228 struct anv_graphics_pipeline {
3229 struct anv_pipeline base;
3230
3231 uint32_t batch_data[512];
3232
3233 anv_cmd_dirty_mask_t dynamic_state_mask;
3234 struct anv_dynamic_state dynamic_state;
3235
3236 uint32_t topology;
3237
3238 struct anv_subpass * subpass;
3239
3240 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
3241
3242 VkShaderStageFlags active_stages;
3243
3244 bool primitive_restart;
3245 bool writes_depth;
3246 bool depth_test_enable;
3247 bool writes_stencil;
3248 bool stencil_test_enable;
3249 bool depth_clamp_enable;
3250 bool depth_clip_enable;
3251 bool sample_shading_enable;
3252 bool kill_pixel;
3253 bool depth_bounds_test_enable;
3254
3255 /* When primitive replication is used, subpass->view_mask will describe what
3256 * views to replicate.
3257 */
3258 bool use_primitive_replication;
3259
3260 struct anv_state blend_state;
3261
3262 uint32_t vb_used;
3263 struct anv_pipeline_vertex_binding {
3264 uint32_t stride;
3265 bool instanced;
3266 uint32_t instance_divisor;
3267 } vb[MAX_VBS];
3268
3269 struct {
3270 uint32_t sf[7];
3271 uint32_t depth_stencil_state[3];
3272 } gen7;
3273
3274 struct {
3275 uint32_t sf[4];
3276 uint32_t raster[5];
3277 uint32_t wm_depth_stencil[3];
3278 } gen8;
3279
3280 struct {
3281 uint32_t wm_depth_stencil[4];
3282 } gen9;
3283 };
3284
3285 struct anv_compute_pipeline {
3286 struct anv_pipeline base;
3287
3288 struct anv_shader_bin * cs;
3289 uint32_t cs_right_mask;
3290 uint32_t batch_data[9];
3291 uint32_t interface_descriptor_data[8];
3292 };
3293
3294 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3295 static inline struct anv_##pipe_type##_pipeline * \
3296 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3297 { \
3298 assert(pipeline->type == pipe_enum); \
3299 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3300 }
3301
3302 ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS)
3303 ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE)
3304
3305 static inline bool
3306 anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
3307 gl_shader_stage stage)
3308 {
3309 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
3310 }
3311
3312 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3313 static inline const struct brw_##prefix##_prog_data * \
3314 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3315 { \
3316 if (anv_pipeline_has_stage(pipeline, stage)) { \
3317 return (const struct brw_##prefix##_prog_data *) \
3318 pipeline->shaders[stage]->prog_data; \
3319 } else { \
3320 return NULL; \
3321 } \
3322 }
3323
3324 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
3325 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
3326 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
3327 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
3328 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
3329
3330 static inline const struct brw_cs_prog_data *
3331 get_cs_prog_data(const struct anv_compute_pipeline *pipeline)
3332 {
3333 assert(pipeline->cs);
3334 return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
3335 }
3336
3337 static inline const struct brw_vue_prog_data *
3338 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
3339 {
3340 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
3341 return &get_gs_prog_data(pipeline)->base;
3342 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
3343 return &get_tes_prog_data(pipeline)->base;
3344 else
3345 return &get_vs_prog_data(pipeline)->base;
3346 }
3347
3348 VkResult
3349 anv_pipeline_init(struct anv_graphics_pipeline *pipeline, struct anv_device *device,
3350 struct anv_pipeline_cache *cache,
3351 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3352 const VkAllocationCallbacks *alloc);
3353
3354 VkResult
3355 anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
3356 struct anv_pipeline_cache *cache,
3357 const VkComputePipelineCreateInfo *info,
3358 const struct anv_shader_module *module,
3359 const char *entrypoint,
3360 const VkSpecializationInfo *spec_info);
3361
3362 uint32_t
3363 anv_cs_workgroup_size(const struct anv_compute_pipeline *pipeline);
3364
3365 uint32_t
3366 anv_cs_threads(const struct anv_compute_pipeline *pipeline);
3367
3368 struct anv_format_plane {
3369 enum isl_format isl_format:16;
3370 struct isl_swizzle swizzle;
3371
3372 /* Whether this plane contains chroma channels */
3373 bool has_chroma;
3374
3375 /* For downscaling of YUV planes */
3376 uint8_t denominator_scales[2];
3377
3378 /* How to map sampled ycbcr planes to a single 4 component element. */
3379 struct isl_swizzle ycbcr_swizzle;
3380
3381 /* What aspect is associated to this plane */
3382 VkImageAspectFlags aspect;
3383 };
3384
3385
3386 struct anv_format {
3387 struct anv_format_plane planes[3];
3388 VkFormat vk_format;
3389 uint8_t n_planes;
3390 bool can_ycbcr;
3391 };
3392
3393 /**
3394 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3395 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3396 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3397 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3398 */
3399 static inline uint32_t
3400 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
3401 VkImageAspectFlags aspect_mask)
3402 {
3403 switch (aspect_mask) {
3404 case VK_IMAGE_ASPECT_COLOR_BIT:
3405 case VK_IMAGE_ASPECT_DEPTH_BIT:
3406 case VK_IMAGE_ASPECT_PLANE_0_BIT:
3407 return 0;
3408 case VK_IMAGE_ASPECT_STENCIL_BIT:
3409 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
3410 return 0;
3411 /* Fall-through */
3412 case VK_IMAGE_ASPECT_PLANE_1_BIT:
3413 return 1;
3414 case VK_IMAGE_ASPECT_PLANE_2_BIT:
3415 return 2;
3416 default:
3417 /* Purposefully assert with depth/stencil aspects. */
3418 unreachable("invalid image aspect");
3419 }
3420 }
3421
3422 static inline VkImageAspectFlags
3423 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
3424 uint32_t plane)
3425 {
3426 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
3427 if (util_bitcount(image_aspects) > 1)
3428 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
3429 return VK_IMAGE_ASPECT_COLOR_BIT;
3430 }
3431 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
3432 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
3433 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
3434 return VK_IMAGE_ASPECT_STENCIL_BIT;
3435 }
3436
3437 #define anv_foreach_image_aspect_bit(b, image, aspects) \