anv: Implement VK_EXT_custom_border_color
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include "drm-uapi/i915_drm.h"
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #ifndef NDEBUG
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
41 #endif
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
61 #include "util/vma.h"
62 #include "util/xmlconfig.h"
63 #include "vk_alloc.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 struct anv_batch;
75 struct anv_buffer;
76 struct anv_buffer_view;
77 struct anv_image_view;
78 struct anv_instance;
79
80 struct gen_aux_map_context;
81 struct gen_perf_config;
82
83 #include <vulkan/vulkan.h>
84 #include <vulkan/vulkan_intel.h>
85 #include <vulkan/vk_icd.h>
86
87 #include "anv_android.h"
88 #include "anv_entrypoints.h"
89 #include "anv_extensions.h"
90 #include "isl/isl.h"
91
92 #include "dev/gen_debug.h"
93 #include "common/intel_log.h"
94 #include "wsi_common.h"
95
96 #define NSEC_PER_SEC 1000000000ull
97
98 /* anv Virtual Memory Layout
99 * =========================
100 *
101 * When the anv driver is determining the virtual graphics addresses of memory
102 * objects itself using the softpin mechanism, the following memory ranges
103 * will be used.
104 *
105 * Three special considerations to notice:
106 *
107 * (1) the dynamic state pool is located within the same 4 GiB as the low
108 * heap. This is to work around a VF cache issue described in a comment in
109 * anv_physical_device_init_heaps.
110 *
111 * (2) the binding table pool is located at lower addresses than the surface
112 * state pool, within a 4 GiB range. This allows surface state base addresses
113 * to cover both binding tables (16 bit offsets) and surface states (32 bit
114 * offsets).
115 *
116 * (3) the last 4 GiB of the address space is withheld from the high
117 * heap. Various hardware units will read past the end of an object for
118 * various reasons. This healthy margin prevents reads from wrapping around
119 * 48-bit addresses.
120 */
121 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
122 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
123 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
124 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
125 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
126 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
127 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
128 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
129 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
130 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
131 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
133 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134
135 #define LOW_HEAP_SIZE \
136 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
137 #define DYNAMIC_STATE_POOL_SIZE \
138 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
139 #define BINDING_TABLE_POOL_SIZE \
140 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
141 #define SURFACE_STATE_POOL_SIZE \
142 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
143 #define INSTRUCTION_STATE_POOL_SIZE \
144 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
145 #define CLIENT_VISIBLE_HEAP_SIZE \
146 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147
148 /* Allowing different clear colors requires us to perform a depth resolve at
149 * the end of certain render passes. This is because while slow clears store
150 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
151 * See the PRMs for examples describing when additional resolves would be
152 * necessary. To enable fast clears without requiring extra resolves, we set
153 * the clear value to a globally-defined one. We could allow different values
154 * if the user doesn't expect coherent data during or after a render passes
155 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
156 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
157 * 1.0f seems to be the only value used. The only application that doesn't set
158 * this value does so through the usage of an seemingly uninitialized clear
159 * value.
160 */
161 #define ANV_HZ_FC_VAL 1.0f
162
163 #define MAX_VBS 28
164 #define MAX_XFB_BUFFERS 4
165 #define MAX_XFB_STREAMS 4
166 #define MAX_SETS 8
167 #define MAX_RTS 8
168 #define MAX_VIEWPORTS 16
169 #define MAX_SCISSORS 16
170 #define MAX_PUSH_CONSTANTS_SIZE 128
171 #define MAX_DYNAMIC_BUFFERS 16
172 #define MAX_IMAGES 64
173 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
174 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
175 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
177 * use 64 here to avoid cache issues. This could most likely bring it back to
178 * 32 if we had different virtual addresses for the different views on a given
179 * GEM object.
180 */
181 #define ANV_UBO_ALIGNMENT 64
182 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
183 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
184
185 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
186 *
187 * "The surface state model is used when a Binding Table Index (specified
188 * in the message descriptor) of less than 240 is specified. In this model,
189 * the Binding Table Index is used to index into the binding table, and the
190 * binding table entry contains a pointer to the SURFACE_STATE."
191 *
192 * Binding table values above 240 are used for various things in the hardware
193 * such as stateless, stateless with incoherent cache, SLM, and bindless.
194 */
195 #define MAX_BINDING_TABLE_SIZE 240
196
197 /* The kernel relocation API has a limitation of a 32-bit delta value
198 * applied to the address before it is written which, in spite of it being
199 * unsigned, is treated as signed . Because of the way that this maps to
200 * the Vulkan API, we cannot handle an offset into a buffer that does not
201 * fit into a signed 32 bits. The only mechanism we have for dealing with
202 * this at the moment is to limit all VkDeviceMemory objects to a maximum
203 * of 2GB each. The Vulkan spec allows us to do this:
204 *
205 * "Some platforms may have a limit on the maximum size of a single
206 * allocation. For example, certain systems may fail to create
207 * allocations with a size greater than or equal to 4GB. Such a limit is
208 * implementation-dependent, and if such a failure occurs then the error
209 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
210 *
211 * We don't use vk_error here because it's not an error so much as an
212 * indication to the application that the allocation is too large.
213 */
214 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
215
216 #define ANV_SVGS_VB_INDEX MAX_VBS
217 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
218
219 /* We reserve this MI ALU register for the purpose of handling predication.
220 * Other code which uses the MI ALU should leave it alone.
221 */
222 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
223
224 /* For gen12 we set the streamout buffers using 4 separate commands
225 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
226 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
227 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
228 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
229 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
230 * 3DSTATE_SO_BUFFER_INDEX_0.
231 */
232 #define SO_BUFFER_INDEX_0_CMD 0x60
233 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
234
235 static inline uint32_t
236 align_down_npot_u32(uint32_t v, uint32_t a)
237 {
238 return v - (v % a);
239 }
240
241 static inline uint32_t
242 align_down_u32(uint32_t v, uint32_t a)
243 {
244 assert(a != 0 && a == (a & -a));
245 return v & ~(a - 1);
246 }
247
248 static inline uint32_t
249 align_u32(uint32_t v, uint32_t a)
250 {
251 assert(a != 0 && a == (a & -a));
252 return align_down_u32(v + a - 1, a);
253 }
254
255 static inline uint64_t
256 align_down_u64(uint64_t v, uint64_t a)
257 {
258 assert(a != 0 && a == (a & -a));
259 return v & ~(a - 1);
260 }
261
262 static inline uint64_t
263 align_u64(uint64_t v, uint64_t a)
264 {
265 return align_down_u64(v + a - 1, a);
266 }
267
268 static inline int32_t
269 align_i32(int32_t v, int32_t a)
270 {
271 assert(a != 0 && a == (a & -a));
272 return (v + a - 1) & ~(a - 1);
273 }
274
275 /** Alignment must be a power of 2. */
276 static inline bool
277 anv_is_aligned(uintmax_t n, uintmax_t a)
278 {
279 assert(a == (a & -a));
280 return (n & (a - 1)) == 0;
281 }
282
283 static inline uint32_t
284 anv_minify(uint32_t n, uint32_t levels)
285 {
286 if (unlikely(n == 0))
287 return 0;
288 else
289 return MAX2(n >> levels, 1);
290 }
291
292 static inline float
293 anv_clamp_f(float f, float min, float max)
294 {
295 assert(min < max);
296
297 if (f > max)
298 return max;
299 else if (f < min)
300 return min;
301 else
302 return f;
303 }
304
305 static inline bool
306 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
307 {
308 if (*inout_mask & clear_mask) {
309 *inout_mask &= ~clear_mask;
310 return true;
311 } else {
312 return false;
313 }
314 }
315
316 static inline union isl_color_value
317 vk_to_isl_color(VkClearColorValue color)
318 {
319 return (union isl_color_value) {
320 .u32 = {
321 color.uint32[0],
322 color.uint32[1],
323 color.uint32[2],
324 color.uint32[3],
325 },
326 };
327 }
328
329 static inline void *anv_unpack_ptr(uintptr_t ptr, int bits, int *flags)
330 {
331 uintptr_t mask = (1ull << bits) - 1;
332 *flags = ptr & mask;
333 return (void *) (ptr & ~mask);
334 }
335
336 static inline uintptr_t anv_pack_ptr(void *ptr, int bits, int flags)
337 {
338 uintptr_t value = (uintptr_t) ptr;
339 uintptr_t mask = (1ull << bits) - 1;
340 return value | (mask & flags);
341 }
342
343 #define for_each_bit(b, dword) \
344 for (uint32_t __dword = (dword); \
345 (b) = __builtin_ffs(__dword) - 1, __dword; \
346 __dword &= ~(1 << (b)))
347
348 #define typed_memcpy(dest, src, count) ({ \
349 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
350 memcpy((dest), (src), (count) * sizeof(*(src))); \
351 })
352
353 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
354 * to be added here in order to utilize mapping in debug/error/perf macros.
355 */
356 #define REPORT_OBJECT_TYPE(o) \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
384 __builtin_choose_expr ( \
385 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
386 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
387 __builtin_choose_expr ( \
388 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
389 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
390 __builtin_choose_expr ( \
391 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
392 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
393 __builtin_choose_expr ( \
394 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
395 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
396 __builtin_choose_expr ( \
397 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
398 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
399 __builtin_choose_expr ( \
400 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
401 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
402 __builtin_choose_expr ( \
403 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
404 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
405 __builtin_choose_expr ( \
406 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
407 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
408 __builtin_choose_expr ( \
409 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
410 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
411 __builtin_choose_expr ( \
412 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
413 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
414 __builtin_choose_expr ( \
415 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
416 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
417 __builtin_choose_expr ( \
418 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
419 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
420 __builtin_choose_expr ( \
421 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
422 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
423 __builtin_choose_expr ( \
424 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
425 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
426 __builtin_choose_expr ( \
427 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
428 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
429 __builtin_choose_expr ( \
430 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
431 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
432 __builtin_choose_expr ( \
433 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
434 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
435 __builtin_choose_expr ( \
436 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
437 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
438 __builtin_choose_expr ( \
439 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
440 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
441 __builtin_choose_expr ( \
442 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
443 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
444 __builtin_choose_expr ( \
445 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
446 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
447 __builtin_choose_expr ( \
448 __builtin_types_compatible_p (__typeof (o), void*), \
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
450 /* The void expression results in a compile-time error \
451 when assigning the result to something. */ \
452 (void)0)))))))))))))))))))))))))))))))
453
454 /* Whenever we generate an error, pass it through this function. Useful for
455 * debugging, where we can break on it. Only call at error site, not when
456 * propagating errors. Might be useful to plug in a stack trace here.
457 */
458
459 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
460 VkDebugReportObjectTypeEXT type, VkResult error,
461 const char *file, int line, const char *format,
462 va_list args);
463
464 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
465 VkDebugReportObjectTypeEXT type, VkResult error,
466 const char *file, int line, const char *format, ...)
467 anv_printflike(7, 8);
468
469 #ifdef DEBUG
470 #define vk_error(error) __vk_errorf(NULL, NULL,\
471 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
472 error, __FILE__, __LINE__, NULL)
473 #define vk_errorfi(instance, obj, error, format, ...)\
474 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
475 __FILE__, __LINE__, format, ## __VA_ARGS__)
476 #define vk_errorf(device, obj, error, format, ...)\
477 vk_errorfi(anv_device_instance_or_null(device),\
478 obj, error, format, ## __VA_ARGS__)
479 #else
480 #define vk_error(error) error
481 #define vk_errorfi(instance, obj, error, format, ...) error
482 #define vk_errorf(device, obj, error, format, ...) error
483 #endif
484
485 /**
486 * Warn on ignored extension structs.
487 *
488 * The Vulkan spec requires us to ignore unsupported or unknown structs in
489 * a pNext chain. In debug mode, emitting warnings for ignored structs may
490 * help us discover structs that we should not have ignored.
491 *
492 *
493 * From the Vulkan 1.0.38 spec:
494 *
495 * Any component of the implementation (the loader, any enabled layers,
496 * and drivers) must skip over, without processing (other than reading the
497 * sType and pNext members) any chained structures with sType values not
498 * defined by extensions supported by that component.
499 */
500 #define anv_debug_ignored_stype(sType) \
501 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
502
503 void __anv_perf_warn(struct anv_device *device, const void *object,
504 VkDebugReportObjectTypeEXT type, const char *file,
505 int line, const char *format, ...)
506 anv_printflike(6, 7);
507 void anv_loge(const char *format, ...) anv_printflike(1, 2);
508 void anv_loge_v(const char *format, va_list va);
509
510 /**
511 * Print a FINISHME message, including its source location.
512 */
513 #define anv_finishme(format, ...) \
514 do { \
515 static bool reported = false; \
516 if (!reported) { \
517 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
518 ##__VA_ARGS__); \
519 reported = true; \
520 } \
521 } while (0)
522
523 /**
524 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
525 */
526 #define anv_perf_warn(instance, obj, format, ...) \
527 do { \
528 static bool reported = false; \
529 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
530 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
531 format, ##__VA_ARGS__); \
532 reported = true; \
533 } \
534 } while (0)
535
536 /* A non-fatal assert. Useful for debugging. */
537 #ifdef DEBUG
538 #define anv_assert(x) ({ \
539 if (unlikely(!(x))) \
540 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
541 })
542 #else
543 #define anv_assert(x)
544 #endif
545
546 /* A multi-pointer allocator
547 *
548 * When copying data structures from the user (such as a render pass), it's
549 * common to need to allocate data for a bunch of different things. Instead
550 * of doing several allocations and having to handle all of the error checking
551 * that entails, it can be easier to do a single allocation. This struct
552 * helps facilitate that. The intended usage looks like this:
553 *
554 * ANV_MULTIALLOC(ma)
555 * anv_multialloc_add(&ma, &main_ptr, 1);
556 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
557 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
558 *
559 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
560 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
561 */
562 struct anv_multialloc {
563 size_t size;
564 size_t align;
565
566 uint32_t ptr_count;
567 void **ptrs[8];
568 };
569
570 #define ANV_MULTIALLOC_INIT \
571 ((struct anv_multialloc) { 0, })
572
573 #define ANV_MULTIALLOC(_name) \
574 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
575
576 __attribute__((always_inline))
577 static inline void
578 _anv_multialloc_add(struct anv_multialloc *ma,
579 void **ptr, size_t size, size_t align)
580 {
581 size_t offset = align_u64(ma->size, align);
582 ma->size = offset + size;
583 ma->align = MAX2(ma->align, align);
584
585 /* Store the offset in the pointer. */
586 *ptr = (void *)(uintptr_t)offset;
587
588 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
589 ma->ptrs[ma->ptr_count++] = ptr;
590 }
591
592 #define anv_multialloc_add_size(_ma, _ptr, _size) \
593 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
594
595 #define anv_multialloc_add(_ma, _ptr, _count) \
596 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
597
598 __attribute__((always_inline))
599 static inline void *
600 anv_multialloc_alloc(struct anv_multialloc *ma,
601 const VkAllocationCallbacks *alloc,
602 VkSystemAllocationScope scope)
603 {
604 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
605 if (!ptr)
606 return NULL;
607
608 /* Fill out each of the pointers with their final value.
609 *
610 * for (uint32_t i = 0; i < ma->ptr_count; i++)
611 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
612 *
613 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
614 * constant, GCC is incapable of figuring this out and unrolling the loop
615 * so we have to give it a little help.
616 */
617 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
618 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
619 if ((_i) < ma->ptr_count) \
620 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
621 _ANV_MULTIALLOC_UPDATE_POINTER(0);
622 _ANV_MULTIALLOC_UPDATE_POINTER(1);
623 _ANV_MULTIALLOC_UPDATE_POINTER(2);
624 _ANV_MULTIALLOC_UPDATE_POINTER(3);
625 _ANV_MULTIALLOC_UPDATE_POINTER(4);
626 _ANV_MULTIALLOC_UPDATE_POINTER(5);
627 _ANV_MULTIALLOC_UPDATE_POINTER(6);
628 _ANV_MULTIALLOC_UPDATE_POINTER(7);
629 #undef _ANV_MULTIALLOC_UPDATE_POINTER
630
631 return ptr;
632 }
633
634 __attribute__((always_inline))
635 static inline void *
636 anv_multialloc_alloc2(struct anv_multialloc *ma,
637 const VkAllocationCallbacks *parent_alloc,
638 const VkAllocationCallbacks *alloc,
639 VkSystemAllocationScope scope)
640 {
641 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
642 }
643
644 struct anv_bo {
645 uint32_t gem_handle;
646
647 uint32_t refcount;
648
649 /* Index into the current validation list. This is used by the
650 * validation list building alrogithm to track which buffers are already
651 * in the validation list so that we can ensure uniqueness.
652 */
653 uint32_t index;
654
655 /* Index for use with util_sparse_array_free_list */
656 uint32_t free_index;
657
658 /* Last known offset. This value is provided by the kernel when we
659 * execbuf and is used as the presumed offset for the next bunch of
660 * relocations.
661 */
662 uint64_t offset;
663
664 /** Size of the buffer not including implicit aux */
665 uint64_t size;
666
667 /* Map for internally mapped BOs.
668 *
669 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
670 */
671 void *map;
672
673 /** Size of the implicit CCS range at the end of the buffer
674 *
675 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
676 * page of main surface data maps to a 256B chunk of CCS data and that
677 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
678 * addresses in the main surface to virtual memory addresses for CCS data.
679 *
680 * Because we can't change these maps around easily and because Vulkan
681 * allows two VkImages to be bound to overlapping memory regions (as long
682 * as the app is careful), it's not feasible to make this mapping part of
683 * the image. (On Gen11 and earlier, the mapping was provided via
684 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
685 * Instead, we attach the CCS data directly to the buffer object and setup
686 * the AUX table mapping at BO creation time.
687 *
688 * This field is for internal tracking use by the BO allocator only and
689 * should not be touched by other parts of the code. If something wants to
690 * know if a BO has implicit CCS data, it should instead look at the
691 * has_implicit_ccs boolean below.
692 *
693 * This data is not included in maps of this buffer.
694 */
695 uint32_t _ccs_size;
696
697 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
698 uint32_t flags;
699
700 /** True if this BO may be shared with other processes */
701 bool is_external:1;
702
703 /** True if this BO is a wrapper
704 *
705 * When set to true, none of the fields in this BO are meaningful except
706 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
707 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
708 * is set in the physical device.
709 */
710 bool is_wrapper:1;
711
712 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
713 bool has_fixed_address:1;
714
715 /** True if this BO wraps a host pointer */
716 bool from_host_ptr:1;
717
718 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
719 bool has_client_visible_address:1;
720
721 /** True if this BO has implicit CCS data attached to it */
722 bool has_implicit_ccs:1;
723 };
724
725 static inline struct anv_bo *
726 anv_bo_ref(struct anv_bo *bo)
727 {
728 p_atomic_inc(&bo->refcount);
729 return bo;
730 }
731
732 static inline struct anv_bo *
733 anv_bo_unwrap(struct anv_bo *bo)
734 {
735 while (bo->is_wrapper)
736 bo = bo->map;
737 return bo;
738 }
739
740 /* Represents a lock-free linked list of "free" things. This is used by
741 * both the block pool and the state pools. Unfortunately, in order to
742 * solve the ABA problem, we can't use a single uint32_t head.
743 */
744 union anv_free_list {
745 struct {
746 uint32_t offset;
747
748 /* A simple count that is incremented every time the head changes. */
749 uint32_t count;
750 };
751 /* Make sure it's aligned to 64 bits. This will make atomic operations
752 * faster on 32 bit platforms.
753 */
754 uint64_t u64 __attribute__ ((aligned (8)));
755 };
756
757 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
758
759 struct anv_block_state {
760 union {
761 struct {
762 uint32_t next;
763 uint32_t end;
764 };
765 /* Make sure it's aligned to 64 bits. This will make atomic operations
766 * faster on 32 bit platforms.
767 */
768 uint64_t u64 __attribute__ ((aligned (8)));
769 };
770 };
771
772 #define anv_block_pool_foreach_bo(bo, pool) \
773 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
774 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
775 _pp_bo++)
776
777 #define ANV_MAX_BLOCK_POOL_BOS 20
778
779 struct anv_block_pool {
780 struct anv_device *device;
781 bool use_softpin;
782
783 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
784 * around the actual BO so that we grow the pool after the wrapper BO has
785 * been put in a relocation list. This is only used in the non-softpin
786 * case.
787 */
788 struct anv_bo wrapper_bo;
789
790 struct anv_bo *bos[ANV_MAX_BLOCK_POOL_BOS];
791 struct anv_bo *bo;
792 uint32_t nbos;
793
794 uint64_t size;
795
796 /* The address where the start of the pool is pinned. The various bos that
797 * are created as the pool grows will have addresses in the range
798 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
799 */
800 uint64_t start_address;
801
802 /* The offset from the start of the bo to the "center" of the block
803 * pool. Pointers to allocated blocks are given by
804 * bo.map + center_bo_offset + offsets.
805 */
806 uint32_t center_bo_offset;
807
808 /* Current memory map of the block pool. This pointer may or may not
809 * point to the actual beginning of the block pool memory. If
810 * anv_block_pool_alloc_back has ever been called, then this pointer
811 * will point to the "center" position of the buffer and all offsets
812 * (negative or positive) given out by the block pool alloc functions
813 * will be valid relative to this pointer.
814 *
815 * In particular, map == bo.map + center_offset
816 *
817 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
818 * since it will handle the softpin case as well, where this points to NULL.
819 */
820 void *map;
821 int fd;
822
823 /**
824 * Array of mmaps and gem handles owned by the block pool, reclaimed when
825 * the block pool is destroyed.
826 */
827 struct u_vector mmap_cleanups;
828
829 struct anv_block_state state;
830
831 struct anv_block_state back_state;
832 };
833
834 /* Block pools are backed by a fixed-size 1GB memfd */
835 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
836
837 /* The center of the block pool is also the middle of the memfd. This may
838 * change in the future if we decide differently for some reason.
839 */
840 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
841
842 static inline uint32_t
843 anv_block_pool_size(struct anv_block_pool *pool)
844 {
845 return pool->state.end + pool->back_state.end;
846 }
847
848 struct anv_state {
849 int32_t offset;
850 uint32_t alloc_size;
851 void *map;
852 uint32_t idx;
853 };
854
855 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
856
857 struct anv_fixed_size_state_pool {
858 union anv_free_list free_list;
859 struct anv_block_state block;
860 };
861
862 #define ANV_MIN_STATE_SIZE_LOG2 6
863 #define ANV_MAX_STATE_SIZE_LOG2 21
864
865 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
866
867 struct anv_free_entry {
868 uint32_t next;
869 struct anv_state state;
870 };
871
872 struct anv_state_table {
873 struct anv_device *device;
874 int fd;
875 struct anv_free_entry *map;
876 uint32_t size;
877 struct anv_block_state state;
878 struct u_vector cleanups;
879 };
880
881 struct anv_state_pool {
882 struct anv_block_pool block_pool;
883
884 /* Offset into the relevant state base address where the state pool starts
885 * allocating memory.
886 */
887 int32_t start_offset;
888
889 struct anv_state_table table;
890
891 /* The size of blocks which will be allocated from the block pool */
892 uint32_t block_size;
893
894 /** Free list for "back" allocations */
895 union anv_free_list back_alloc_free_list;
896
897 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
898 };
899
900 struct anv_state_reserved_pool {
901 struct anv_state_pool *pool;
902 union anv_free_list reserved_blocks;
903 uint32_t count;
904 };
905
906 struct anv_state_stream {
907 struct anv_state_pool *state_pool;
908
909 /* The size of blocks to allocate from the state pool */
910 uint32_t block_size;
911
912 /* Current block we're allocating from */
913 struct anv_state block;
914
915 /* Offset into the current block at which to allocate the next state */
916 uint32_t next;
917
918 /* List of all blocks allocated from this pool */
919 struct util_dynarray all_blocks;
920 };
921
922 /* The block_pool functions exported for testing only. The block pool should
923 * only be used via a state pool (see below).
924 */
925 VkResult anv_block_pool_init(struct anv_block_pool *pool,
926 struct anv_device *device,
927 uint64_t start_address,
928 uint32_t initial_size);
929 void anv_block_pool_finish(struct anv_block_pool *pool);
930 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
931 uint32_t block_size, uint32_t *padding);
932 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
933 uint32_t block_size);
934 void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset, uint32_t
935 size);
936
937 VkResult anv_state_pool_init(struct anv_state_pool *pool,
938 struct anv_device *device,
939 uint64_t base_address,
940 int32_t start_offset,
941 uint32_t block_size);
942 void anv_state_pool_finish(struct anv_state_pool *pool);
943 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
944 uint32_t state_size, uint32_t alignment);
945 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
946 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
947 void anv_state_stream_init(struct anv_state_stream *stream,
948 struct anv_state_pool *state_pool,
949 uint32_t block_size);
950 void anv_state_stream_finish(struct anv_state_stream *stream);
951 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
952 uint32_t size, uint32_t alignment);
953
954 void anv_state_reserved_pool_init(struct anv_state_reserved_pool *pool,
955 struct anv_state_pool *parent,
956 uint32_t count, uint32_t size,
957 uint32_t alignment);
958 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool *pool);
959 struct anv_state anv_state_reserved_pool_alloc(struct anv_state_reserved_pool *pool);
960 void anv_state_reserved_pool_free(struct anv_state_reserved_pool *pool,
961 struct anv_state state);
962
963 VkResult anv_state_table_init(struct anv_state_table *table,
964 struct anv_device *device,
965 uint32_t initial_entries);
966 void anv_state_table_finish(struct anv_state_table *table);
967 VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx,
968 uint32_t count);
969 void anv_free_list_push(union anv_free_list *list,
970 struct anv_state_table *table,
971 uint32_t idx, uint32_t count);
972 struct anv_state* anv_free_list_pop(union anv_free_list *list,
973 struct anv_state_table *table);
974
975
976 static inline struct anv_state *
977 anv_state_table_get(struct anv_state_table *table, uint32_t idx)
978 {
979 return &table->map[idx].state;
980 }
981 /**
982 * Implements a pool of re-usable BOs. The interface is identical to that
983 * of block_pool except that each block is its own BO.
984 */
985 struct anv_bo_pool {
986 struct anv_device *device;
987
988 struct util_sparse_array_free_list free_list[16];
989 };
990
991 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
992 void anv_bo_pool_finish(struct anv_bo_pool *pool);
993 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, uint32_t size,
994 struct anv_bo **bo_out);
995 void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
996
997 struct anv_scratch_pool {
998 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
999 struct anv_bo *bos[16][MESA_SHADER_STAGES];
1000 };
1001
1002 void anv_scratch_pool_init(struct anv_device *device,
1003 struct anv_scratch_pool *pool);
1004 void anv_scratch_pool_finish(struct anv_device *device,
1005 struct anv_scratch_pool *pool);
1006 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
1007 struct anv_scratch_pool *pool,
1008 gl_shader_stage stage,
1009 unsigned per_thread_scratch);
1010
1011 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1012 struct anv_bo_cache {
1013 struct util_sparse_array bo_map;
1014 pthread_mutex_t mutex;
1015 };
1016
1017 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
1018 void anv_bo_cache_finish(struct anv_bo_cache *cache);
1019
1020 struct anv_memory_type {
1021 /* Standard bits passed on to the client */
1022 VkMemoryPropertyFlags propertyFlags;
1023 uint32_t heapIndex;
1024 };
1025
1026 struct anv_memory_heap {
1027 /* Standard bits passed on to the client */
1028 VkDeviceSize size;
1029 VkMemoryHeapFlags flags;
1030
1031 /* Driver-internal book-keeping */
1032 VkDeviceSize used;
1033 };
1034
1035 struct anv_physical_device {
1036 struct vk_object_base base;
1037
1038 /* Link in anv_instance::physical_devices */
1039 struct list_head link;
1040
1041 struct anv_instance * instance;
1042 bool no_hw;
1043 char path[20];
1044 const char * name;
1045 struct {
1046 uint16_t domain;
1047 uint8_t bus;
1048 uint8_t device;
1049 uint8_t function;
1050 } pci_info;
1051 struct gen_device_info info;
1052 /** Amount of "GPU memory" we want to advertise
1053 *
1054 * Clearly, this value is bogus since Intel is a UMA architecture. On
1055 * gen7 platforms, we are limited by GTT size unless we want to implement
1056 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1057 * practically unlimited. However, we will never report more than 3/4 of
1058 * the total system ram to try and avoid running out of RAM.
1059 */
1060 bool supports_48bit_addresses;
1061 struct brw_compiler * compiler;
1062 struct isl_device isl_dev;
1063 struct gen_perf_config * perf;
1064 int cmd_parser_version;
1065 bool has_softpin;
1066 bool has_exec_async;
1067 bool has_exec_capture;
1068 bool has_exec_fence;
1069 bool has_syncobj;
1070 bool has_syncobj_wait;
1071 bool has_context_priority;
1072 bool has_context_isolation;
1073 bool has_mem_available;
1074 bool has_mmap_offset;
1075 uint64_t gtt_size;
1076
1077 bool use_softpin;
1078 bool always_use_bindless;
1079
1080 /** True if we can access buffers using A64 messages */
1081 bool has_a64_buffer_access;
1082 /** True if we can use bindless access for images */
1083 bool has_bindless_images;
1084 /** True if we can use bindless access for samplers */
1085 bool has_bindless_samplers;
1086
1087 /** True if this device has implicit AUX
1088 *
1089 * If true, CCS is handled as an implicit attachment to the BO rather than
1090 * as an explicitly bound surface.
1091 */
1092 bool has_implicit_ccs;
1093
1094 bool always_flush_cache;
1095
1096 struct anv_device_extension_table supported_extensions;
1097
1098 uint32_t eu_total;
1099 uint32_t subslice_total;
1100
1101 struct {
1102 uint32_t type_count;
1103 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
1104 uint32_t heap_count;
1105 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
1106 } memory;
1107
1108 uint8_t driver_build_sha1[20];
1109 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
1110 uint8_t driver_uuid[VK_UUID_SIZE];
1111 uint8_t device_uuid[VK_UUID_SIZE];
1112
1113 struct disk_cache * disk_cache;
1114
1115 struct wsi_device wsi_device;
1116 int local_fd;
1117 int master_fd;
1118 };
1119
1120 struct anv_app_info {
1121 const char* app_name;
1122 uint32_t app_version;
1123 const char* engine_name;
1124 uint32_t engine_version;
1125 uint32_t api_version;
1126 };
1127
1128 struct anv_instance {
1129 struct vk_object_base base;
1130
1131 VkAllocationCallbacks alloc;
1132
1133 struct anv_app_info app_info;
1134
1135 struct anv_instance_extension_table enabled_extensions;
1136 struct anv_instance_dispatch_table dispatch;
1137 struct anv_physical_device_dispatch_table physical_device_dispatch;
1138 struct anv_device_dispatch_table device_dispatch;
1139
1140 bool physical_devices_enumerated;
1141 struct list_head physical_devices;
1142
1143 bool pipeline_cache_enabled;
1144
1145 struct vk_debug_report_instance debug_report_callbacks;
1146
1147 struct driOptionCache dri_options;
1148 struct driOptionCache available_dri_options;
1149 };
1150
1151 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
1152 void anv_finish_wsi(struct anv_physical_device *physical_device);
1153
1154 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
1155 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
1156 const char *name);
1157
1158 struct anv_queue_submit {
1159 struct anv_cmd_buffer * cmd_buffer;
1160
1161 uint32_t fence_count;
1162 uint32_t fence_array_length;
1163 struct drm_i915_gem_exec_fence * fences;
1164
1165 uint32_t temporary_semaphore_count;
1166 uint32_t temporary_semaphore_array_length;
1167 struct anv_semaphore_impl * temporary_semaphores;
1168
1169 /* Semaphores to be signaled with a SYNC_FD. */
1170 struct anv_semaphore ** sync_fd_semaphores;
1171 uint32_t sync_fd_semaphore_count;
1172 uint32_t sync_fd_semaphore_array_length;
1173
1174 /* Allocated only with non shareable timelines. */
1175 struct anv_timeline ** wait_timelines;
1176 uint32_t wait_timeline_count;
1177 uint32_t wait_timeline_array_length;
1178 uint64_t * wait_timeline_values;
1179
1180 struct anv_timeline ** signal_timelines;
1181 uint32_t signal_timeline_count;
1182 uint32_t signal_timeline_array_length;
1183 uint64_t * signal_timeline_values;
1184
1185 int in_fence;
1186 bool need_out_fence;
1187 int out_fence;
1188
1189 uint32_t fence_bo_count;
1190 uint32_t fence_bo_array_length;
1191 /* An array of struct anv_bo pointers with lower bit used as a flag to
1192 * signal we will wait on that BO (see anv_(un)pack_ptr).
1193 */
1194 uintptr_t * fence_bos;
1195
1196 const VkAllocationCallbacks * alloc;
1197 VkSystemAllocationScope alloc_scope;
1198
1199 struct anv_bo * simple_bo;
1200 uint32_t simple_bo_size;
1201
1202 struct list_head link;
1203 };
1204
1205 struct anv_queue {
1206 struct vk_object_base base;
1207
1208 struct anv_device * device;
1209
1210 /*
1211 * A list of struct anv_queue_submit to be submitted to i915.
1212 */
1213 struct list_head queued_submits;
1214
1215 VkDeviceQueueCreateFlags flags;
1216 };
1217
1218 struct anv_pipeline_cache {
1219 struct vk_object_base base;
1220 struct anv_device * device;
1221 pthread_mutex_t mutex;
1222
1223 struct hash_table * nir_cache;
1224
1225 struct hash_table * cache;
1226 };
1227
1228 struct nir_xfb_info;
1229 struct anv_pipeline_bind_map;
1230
1231 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
1232 struct anv_device *device,
1233 bool cache_enabled);
1234 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
1235
1236 struct anv_shader_bin *
1237 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
1238 const void *key, uint32_t key_size);
1239 struct anv_shader_bin *
1240 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
1241 gl_shader_stage stage,
1242 const void *key_data, uint32_t key_size,
1243 const void *kernel_data, uint32_t kernel_size,
1244 const void *constant_data,
1245 uint32_t constant_data_size,
1246 const struct brw_stage_prog_data *prog_data,
1247 uint32_t prog_data_size,
1248 const struct brw_compile_stats *stats,
1249 uint32_t num_stats,
1250 const struct nir_xfb_info *xfb_info,
1251 const struct anv_pipeline_bind_map *bind_map);
1252
1253 struct anv_shader_bin *
1254 anv_device_search_for_kernel(struct anv_device *device,
1255 struct anv_pipeline_cache *cache,
1256 const void *key_data, uint32_t key_size,
1257 bool *user_cache_bit);
1258
1259 struct anv_shader_bin *
1260 anv_device_upload_kernel(struct anv_device *device,
1261 struct anv_pipeline_cache *cache,
1262 gl_shader_stage stage,
1263 const void *key_data, uint32_t key_size,
1264 const void *kernel_data, uint32_t kernel_size,
1265 const void *constant_data,
1266 uint32_t constant_data_size,
1267 const struct brw_stage_prog_data *prog_data,
1268 uint32_t prog_data_size,
1269 const struct brw_compile_stats *stats,
1270 uint32_t num_stats,
1271 const struct nir_xfb_info *xfb_info,
1272 const struct anv_pipeline_bind_map *bind_map);
1273
1274 struct nir_shader;
1275 struct nir_shader_compiler_options;
1276
1277 struct nir_shader *
1278 anv_device_search_for_nir(struct anv_device *device,
1279 struct anv_pipeline_cache *cache,
1280 const struct nir_shader_compiler_options *nir_options,
1281 unsigned char sha1_key[20],
1282 void *mem_ctx);
1283
1284 void
1285 anv_device_upload_nir(struct anv_device *device,
1286 struct anv_pipeline_cache *cache,
1287 const struct nir_shader *nir,
1288 unsigned char sha1_key[20]);
1289
1290 struct anv_device {
1291 struct vk_device vk;
1292
1293 struct anv_physical_device * physical;
1294 bool no_hw;
1295 struct gen_device_info info;
1296 struct isl_device isl_dev;
1297 int context_id;
1298 int fd;
1299 bool can_chain_batches;
1300 bool robust_buffer_access;
1301 struct anv_device_extension_table enabled_extensions;
1302 struct anv_device_dispatch_table dispatch;
1303
1304 pthread_mutex_t vma_mutex;
1305 struct util_vma_heap vma_lo;
1306 struct util_vma_heap vma_cva;
1307 struct util_vma_heap vma_hi;
1308
1309 /** List of all anv_device_memory objects */
1310 struct list_head memory_objects;
1311
1312 struct anv_bo_pool batch_bo_pool;
1313
1314 struct anv_bo_cache bo_cache;
1315
1316 struct anv_state_pool dynamic_state_pool;
1317 struct anv_state_pool instruction_state_pool;
1318 struct anv_state_pool binding_table_pool;
1319 struct anv_state_pool surface_state_pool;
1320
1321 struct anv_state_reserved_pool custom_border_colors;
1322
1323 /** BO used for various workarounds
1324 *
1325 * There are a number of workarounds on our hardware which require writing
1326 * data somewhere and it doesn't really matter where. For that, we use
1327 * this BO and just write to the first dword or so.
1328 *
1329 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1330 * For that, we use the high bytes (>= 1024) of the workaround BO.
1331 */
1332 struct anv_bo * workaround_bo;
1333 struct anv_bo * trivial_batch_bo;
1334 struct anv_bo * hiz_clear_bo;
1335 struct anv_state null_surface_state;
1336
1337 struct anv_pipeline_cache default_pipeline_cache;
1338 struct blorp_context blorp;
1339
1340 struct anv_state border_colors;
1341
1342 struct anv_state slice_hash;
1343
1344 struct anv_queue queue;
1345
1346 struct anv_scratch_pool scratch_pool;
1347
1348 pthread_mutex_t mutex;
1349 pthread_cond_t queue_submit;
1350 int _lost;
1351
1352 struct gen_batch_decode_ctx decoder_ctx;
1353 /*
1354 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1355 * the cmd_buffer's list.
1356 */
1357 struct anv_cmd_buffer *cmd_buffer_being_decoded;
1358
1359 int perf_fd; /* -1 if no opened */
1360 uint64_t perf_metric; /* 0 if unset */
1361
1362 struct gen_aux_map_context *aux_map_ctx;
1363 };
1364
1365 static inline struct anv_instance *
1366 anv_device_instance_or_null(const struct anv_device *device)
1367 {
1368 return device ? device->physical->instance : NULL;
1369 }
1370
1371 static inline struct anv_state_pool *
1372 anv_binding_table_pool(struct anv_device *device)
1373 {
1374 if (device->physical->use_softpin)
1375 return &device->binding_table_pool;
1376 else
1377 return &device->surface_state_pool;
1378 }
1379
1380 static inline struct anv_state
1381 anv_binding_table_pool_alloc(struct anv_device *device) {
1382 if (device->physical->use_softpin)
1383 return anv_state_pool_alloc(&device->binding_table_pool,
1384 device->binding_table_pool.block_size, 0);
1385 else
1386 return anv_state_pool_alloc_back(&device->surface_state_pool);
1387 }
1388
1389 static inline void
1390 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1391 anv_state_pool_free(anv_binding_table_pool(device), state);
1392 }
1393
1394 static inline uint32_t
1395 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1396 {
1397 if (bo->is_external)
1398 return device->isl_dev.mocs.external;
1399 else
1400 return device->isl_dev.mocs.internal;
1401 }
1402
1403 void anv_device_init_blorp(struct anv_device *device);
1404 void anv_device_finish_blorp(struct anv_device *device);
1405
1406 void _anv_device_set_all_queue_lost(struct anv_device *device);
1407 VkResult _anv_device_set_lost(struct anv_device *device,
1408 const char *file, int line,
1409 const char *msg, ...)
1410 anv_printflike(4, 5);
1411 VkResult _anv_queue_set_lost(struct anv_queue *queue,
1412 const char *file, int line,
1413 const char *msg, ...)
1414 anv_printflike(4, 5);
1415 #define anv_device_set_lost(dev, ...) \
1416 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1417 #define anv_queue_set_lost(queue, ...) \
1418 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1419
1420 static inline bool
1421 anv_device_is_lost(struct anv_device *device)
1422 {
1423 return unlikely(p_atomic_read(&device->_lost));
1424 }
1425
1426 VkResult anv_device_query_status(struct anv_device *device);
1427
1428
1429 enum anv_bo_alloc_flags {
1430 /** Specifies that the BO must have a 32-bit address
1431 *
1432 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1433 */
1434 ANV_BO_ALLOC_32BIT_ADDRESS = (1 << 0),
1435
1436 /** Specifies that the BO may be shared externally */
1437 ANV_BO_ALLOC_EXTERNAL = (1 << 1),
1438
1439 /** Specifies that the BO should be mapped */
1440 ANV_BO_ALLOC_MAPPED = (1 << 2),
1441
1442 /** Specifies that the BO should be snooped so we get coherency */
1443 ANV_BO_ALLOC_SNOOPED = (1 << 3),
1444
1445 /** Specifies that the BO should be captured in error states */
1446 ANV_BO_ALLOC_CAPTURE = (1 << 4),
1447
1448 /** Specifies that the BO will have an address assigned by the caller
1449 *
1450 * Such BOs do not exist in any VMA heap.
1451 */
1452 ANV_BO_ALLOC_FIXED_ADDRESS = (1 << 5),
1453
1454 /** Enables implicit synchronization on the BO
1455 *
1456 * This is the opposite of EXEC_OBJECT_ASYNC.
1457 */
1458 ANV_BO_ALLOC_IMPLICIT_SYNC = (1 << 6),
1459
1460 /** Enables implicit synchronization on the BO
1461 *
1462 * This is equivalent to EXEC_OBJECT_WRITE.
1463 */
1464 ANV_BO_ALLOC_IMPLICIT_WRITE = (1 << 7),
1465
1466 /** Has an address which is visible to the client */
1467 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS = (1 << 8),
1468
1469 /** This buffer has implicit CCS data attached to it */
1470 ANV_BO_ALLOC_IMPLICIT_CCS = (1 << 9),
1471 };
1472
1473 VkResult anv_device_alloc_bo(struct anv_device *device, uint64_t size,
1474 enum anv_bo_alloc_flags alloc_flags,
1475 uint64_t explicit_address,
1476 struct anv_bo **bo);
1477 VkResult anv_device_import_bo_from_host_ptr(struct anv_device *device,
1478 void *host_ptr, uint32_t size,
1479 enum anv_bo_alloc_flags alloc_flags,
1480 uint64_t client_address,
1481 struct anv_bo **bo_out);
1482 VkResult anv_device_import_bo(struct anv_device *device, int fd,
1483 enum anv_bo_alloc_flags alloc_flags,
1484 uint64_t client_address,
1485 struct anv_bo **bo);
1486 VkResult anv_device_export_bo(struct anv_device *device,
1487 struct anv_bo *bo, int *fd_out);
1488 void anv_device_release_bo(struct anv_device *device,
1489 struct anv_bo *bo);
1490
1491 static inline struct anv_bo *
1492 anv_device_lookup_bo(struct anv_device *device, uint32_t gem_handle)
1493 {
1494 return util_sparse_array_get(&device->bo_cache.bo_map, gem_handle);
1495 }
1496
1497 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1498 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1499 int64_t timeout);
1500
1501 VkResult anv_queue_init(struct anv_device *device, struct anv_queue *queue);
1502 void anv_queue_finish(struct anv_queue *queue);
1503
1504 VkResult anv_queue_execbuf_locked(struct anv_queue *queue, struct anv_queue_submit *submit);
1505 VkResult anv_queue_submit_simple_batch(struct anv_queue *queue,
1506 struct anv_batch *batch);
1507
1508 uint64_t anv_gettime_ns(void);
1509 uint64_t anv_get_absolute_timeout(uint64_t timeout);
1510
1511 void* anv_gem_mmap(struct anv_device *device,
1512 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1513 void anv_gem_munmap(struct anv_device *device, void *p, uint64_t size);
1514 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1515 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1516 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1517 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1518 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1519 int anv_gem_execbuffer(struct anv_device *device,
1520 struct drm_i915_gem_execbuffer2 *execbuf);
1521 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1522 uint32_t stride, uint32_t tiling);
1523 int anv_gem_create_context(struct anv_device *device);
1524 bool anv_gem_has_context_priority(int fd);
1525 int anv_gem_destroy_context(struct anv_device *device, int context);
1526 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1527 uint64_t value);
1528 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1529 uint64_t *value);
1530 int anv_gem_get_param(int fd, uint32_t param);
1531 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1532 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1533 int anv_gem_get_aperture(int fd, uint64_t *size);
1534 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1535 uint32_t *active, uint32_t *pending);
1536 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1537 int anv_gem_reg_read(struct anv_device *device,
1538 uint32_t offset, uint64_t *result);
1539 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1540 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1541 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1542 uint32_t read_domains, uint32_t write_domain);
1543 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1544 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1545 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1546 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1547 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1548 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1549 uint32_t handle);
1550 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1551 uint32_t handle, int fd);
1552 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1553 bool anv_gem_supports_syncobj_wait(int fd);
1554 int anv_gem_syncobj_wait(struct anv_device *device,
1555 uint32_t *handles, uint32_t num_handles,
1556 int64_t abs_timeout_ns, bool wait_all);
1557
1558 uint64_t anv_vma_alloc(struct anv_device *device,
1559 uint64_t size, uint64_t align,
1560 enum anv_bo_alloc_flags alloc_flags,
1561 uint64_t client_address);
1562 void anv_vma_free(struct anv_device *device,
1563 uint64_t address, uint64_t size);
1564
1565 struct anv_reloc_list {
1566 uint32_t num_relocs;
1567 uint32_t array_length;
1568 struct drm_i915_gem_relocation_entry * relocs;
1569 struct anv_bo ** reloc_bos;
1570 uint32_t dep_words;
1571 BITSET_WORD * deps;
1572 };
1573
1574 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1575 const VkAllocationCallbacks *alloc);
1576 void anv_reloc_list_finish(struct anv_reloc_list *list,
1577 const VkAllocationCallbacks *alloc);
1578
1579 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1580 const VkAllocationCallbacks *alloc,
1581 uint32_t offset, struct anv_bo *target_bo,
1582 uint32_t delta, uint64_t *address_u64_out);
1583
1584 struct anv_batch_bo {
1585 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1586 struct list_head link;
1587
1588 struct anv_bo * bo;
1589
1590 /* Bytes actually consumed in this batch BO */
1591 uint32_t length;
1592
1593 struct anv_reloc_list relocs;
1594 };
1595
1596 struct anv_batch {
1597 const VkAllocationCallbacks * alloc;
1598
1599 void * start;
1600 void * end;
1601 void * next;
1602
1603 struct anv_reloc_list * relocs;
1604
1605 /* This callback is called (with the associated user data) in the event
1606 * that the batch runs out of space.
1607 */
1608 VkResult (*extend_cb)(struct anv_batch *, void *);
1609 void * user_data;
1610
1611 /**
1612 * Current error status of the command buffer. Used to track inconsistent
1613 * or incomplete command buffer states that are the consequence of run-time
1614 * errors such as out of memory scenarios. We want to track this in the
1615 * batch because the command buffer object is not visible to some parts
1616 * of the driver.
1617 */
1618 VkResult status;
1619 };
1620
1621 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1622 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1623 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1624 void *location, struct anv_bo *bo, uint32_t offset);
1625
1626 static inline VkResult
1627 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1628 {
1629 assert(error != VK_SUCCESS);
1630 if (batch->status == VK_SUCCESS)
1631 batch->status = error;
1632 return batch->status;
1633 }
1634
1635 static inline bool
1636 anv_batch_has_error(struct anv_batch *batch)
1637 {
1638 return batch->status != VK_SUCCESS;
1639 }
1640
1641 struct anv_address {
1642 struct anv_bo *bo;
1643 uint32_t offset;
1644 };
1645
1646 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1647
1648 static inline bool
1649 anv_address_is_null(struct anv_address addr)
1650 {
1651 return addr.bo == NULL && addr.offset == 0;
1652 }
1653
1654 static inline uint64_t
1655 anv_address_physical(struct anv_address addr)
1656 {
1657 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1658 return gen_canonical_address(addr.bo->offset + addr.offset);
1659 else
1660 return gen_canonical_address(addr.offset);
1661 }
1662
1663 static inline struct anv_address
1664 anv_address_add(struct anv_address addr, uint64_t offset)
1665 {
1666 addr.offset += offset;
1667 return addr;
1668 }
1669
1670 static inline void
1671 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1672 {
1673 unsigned reloc_size = 0;
1674 if (device->info.gen >= 8) {
1675 reloc_size = sizeof(uint64_t);
1676 *(uint64_t *)p = gen_canonical_address(v);
1677 } else {
1678 reloc_size = sizeof(uint32_t);
1679 *(uint32_t *)p = v;
1680 }
1681
1682 if (flush && !device->info.has_llc)
1683 gen_flush_range(p, reloc_size);
1684 }
1685
1686 static inline uint64_t
1687 _anv_combine_address(struct anv_batch *batch, void *location,
1688 const struct anv_address address, uint32_t delta)
1689 {
1690 if (address.bo == NULL) {
1691 return address.offset + delta;
1692 } else {
1693 assert(batch->start <= location && location < batch->end);
1694
1695 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1696 }
1697 }
1698
1699 #define __gen_address_type struct anv_address
1700 #define __gen_user_data struct anv_batch
1701 #define __gen_combine_address _anv_combine_address
1702
1703 /* Wrapper macros needed to work around preprocessor argument issues. In
1704 * particular, arguments don't get pre-evaluated if they are concatenated.
1705 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1706 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1707 * We can work around this easily enough with these helpers.
1708 */
1709 #define __anv_cmd_length(cmd) cmd ## _length
1710 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1711 #define __anv_cmd_header(cmd) cmd ## _header
1712 #define __anv_cmd_pack(cmd) cmd ## _pack
1713 #define __anv_reg_num(reg) reg ## _num
1714
1715 #define anv_pack_struct(dst, struc, ...) do { \
1716 struct struc __template = { \
1717 __VA_ARGS__ \
1718 }; \
1719 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1720 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1721 } while (0)
1722
1723 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1724 void *__dst = anv_batch_emit_dwords(batch, n); \
1725 if (__dst) { \
1726 struct cmd __template = { \
1727 __anv_cmd_header(cmd), \
1728 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1729 __VA_ARGS__ \
1730 }; \
1731 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1732 } \
1733 __dst; \
1734 })
1735
1736 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1737 do { \
1738 uint32_t *dw; \
1739 \
1740 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1741 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1742 if (!dw) \
1743 break; \
1744 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1745 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1746 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1747 } while (0)
1748
1749 #define anv_batch_emit(batch, cmd, name) \
1750 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1751 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1752 __builtin_expect(_dst != NULL, 1); \
1753 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1754 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1755 _dst = NULL; \
1756 }))
1757
1758 struct anv_device_memory {
1759 struct vk_object_base base;
1760
1761 struct list_head link;
1762
1763 struct anv_bo * bo;
1764 struct anv_memory_type * type;
1765 VkDeviceSize map_size;
1766 void * map;
1767
1768 /* If set, we are holding reference to AHardwareBuffer
1769 * which we must release when memory is freed.
1770 */
1771 struct AHardwareBuffer * ahw;
1772
1773 /* If set, this memory comes from a host pointer. */
1774 void * host_ptr;
1775 };
1776
1777 /**
1778 * Header for Vertex URB Entry (VUE)
1779 */
1780 struct anv_vue_header {
1781 uint32_t Reserved;
1782 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1783 uint32_t ViewportIndex;
1784 float PointWidth;
1785 };
1786
1787 /** Struct representing a sampled image descriptor
1788 *
1789 * This descriptor layout is used for sampled images, bare sampler, and
1790 * combined image/sampler descriptors.
1791 */
1792 struct anv_sampled_image_descriptor {
1793 /** Bindless image handle
1794 *
1795 * This is expected to already be shifted such that the 20-bit
1796 * SURFACE_STATE table index is in the top 20 bits.
1797 */
1798 uint32_t image;
1799
1800 /** Bindless sampler handle
1801 *
1802 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1803 * to the dynamic state base address.
1804 */
1805 uint32_t sampler;
1806 };
1807
1808 struct anv_texture_swizzle_descriptor {
1809 /** Texture swizzle
1810 *
1811 * See also nir_intrinsic_channel_select_intel
1812 */
1813 uint8_t swizzle[4];
1814
1815 /** Unused padding to ensure the struct is a multiple of 64 bits */
1816 uint32_t _pad;
1817 };
1818
1819 /** Struct representing a storage image descriptor */
1820 struct anv_storage_image_descriptor {
1821 /** Bindless image handles
1822 *
1823 * These are expected to already be shifted such that the 20-bit
1824 * SURFACE_STATE table index is in the top 20 bits.
1825 */
1826 uint32_t read_write;
1827 uint32_t write_only;
1828 };
1829
1830 /** Struct representing a address/range descriptor
1831 *
1832 * The fields of this struct correspond directly to the data layout of
1833 * nir_address_format_64bit_bounded_global addresses. The last field is the
1834 * offset in the NIR address so it must be zero so that when you load the
1835 * descriptor you get a pointer to the start of the range.
1836 */
1837 struct anv_address_range_descriptor {
1838 uint64_t address;
1839 uint32_t range;
1840 uint32_t zero;
1841 };
1842
1843 enum anv_descriptor_data {
1844 /** The descriptor contains a BTI reference to a surface state */
1845 ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0),
1846 /** The descriptor contains a BTI reference to a sampler state */
1847 ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1),
1848 /** The descriptor contains an actual buffer view */
1849 ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2),
1850 /** The descriptor contains auxiliary image layout data */
1851 ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3),
1852 /** The descriptor contains auxiliary image layout data */
1853 ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4),
1854 /** anv_address_range_descriptor with a buffer address and range */
1855 ANV_DESCRIPTOR_ADDRESS_RANGE = (1 << 5),
1856 /** Bindless surface handle */
1857 ANV_DESCRIPTOR_SAMPLED_IMAGE = (1 << 6),
1858 /** Storage image handles */
1859 ANV_DESCRIPTOR_STORAGE_IMAGE = (1 << 7),
1860 /** Storage image handles */
1861 ANV_DESCRIPTOR_TEXTURE_SWIZZLE = (1 << 8),
1862 };
1863
1864 struct anv_descriptor_set_binding_layout {
1865 #ifndef NDEBUG
1866 /* The type of the descriptors in this binding */
1867 VkDescriptorType type;
1868 #endif
1869
1870 /* Flags provided when this binding was created */
1871 VkDescriptorBindingFlagsEXT flags;
1872
1873 /* Bitfield representing the type of data this descriptor contains */
1874 enum anv_descriptor_data data;
1875
1876 /* Maximum number of YCbCr texture/sampler planes */
1877 uint8_t max_plane_count;
1878
1879 /* Number of array elements in this binding (or size in bytes for inline
1880 * uniform data)
1881 */
1882 uint16_t array_size;
1883
1884 /* Index into the flattend descriptor set */
1885 uint16_t descriptor_index;
1886
1887 /* Index into the dynamic state array for a dynamic buffer */
1888 int16_t dynamic_offset_index;
1889
1890 /* Index into the descriptor set buffer views */
1891 int16_t buffer_view_index;
1892
1893 /* Offset into the descriptor buffer where this descriptor lives */
1894 uint32_t descriptor_offset;
1895
1896 /* Immutable samplers (or NULL if no immutable samplers) */
1897 struct anv_sampler **immutable_samplers;
1898 };
1899
1900 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout);
1901
1902 unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice,
1903 VkDescriptorType type);
1904
1905 bool anv_descriptor_supports_bindless(const struct anv_physical_device *pdevice,
1906 const struct anv_descriptor_set_binding_layout *binding,
1907 bool sampler);
1908
1909 bool anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice,
1910 const struct anv_descriptor_set_binding_layout *binding,
1911 bool sampler);
1912
1913 struct anv_descriptor_set_layout {
1914 struct vk_object_base base;
1915
1916 /* Descriptor set layouts can be destroyed at almost any time */
1917 uint32_t ref_cnt;
1918
1919 /* Number of bindings in this descriptor set */
1920 uint16_t binding_count;
1921
1922 /* Total size of the descriptor set with room for all array entries */
1923 uint16_t size;
1924
1925 /* Shader stages affected by this descriptor set */
1926 uint16_t shader_stages;
1927
1928 /* Number of buffer views in this descriptor set */
1929 uint16_t buffer_view_count;
1930
1931 /* Number of dynamic offsets used by this descriptor set */
1932 uint16_t dynamic_offset_count;
1933
1934 /* For each shader stage, which offsets apply to that stage */
1935 uint16_t stage_dynamic_offsets[MESA_SHADER_STAGES];
1936
1937 /* Size of the descriptor buffer for this descriptor set */
1938 uint32_t descriptor_buffer_size;
1939
1940 /* Bindings in this descriptor set */
1941 struct anv_descriptor_set_binding_layout binding[0];
1942 };
1943
1944 void anv_descriptor_set_layout_destroy(struct anv_device *device,
1945 struct anv_descriptor_set_layout *layout);
1946
1947 static inline void
1948 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1949 {
1950 assert(layout && layout->ref_cnt >= 1);
1951 p_atomic_inc(&layout->ref_cnt);
1952 }
1953
1954 static inline void
1955 anv_descriptor_set_layout_unref(struct anv_device *device,
1956 struct anv_descriptor_set_layout *layout)
1957 {
1958 assert(layout && layout->ref_cnt >= 1);
1959 if (p_atomic_dec_zero(&layout->ref_cnt))
1960 anv_descriptor_set_layout_destroy(device, layout);
1961 }
1962
1963 struct anv_descriptor {
1964 VkDescriptorType type;
1965
1966 union {
1967 struct {
1968 VkImageLayout layout;
1969 struct anv_image_view *image_view;
1970 struct anv_sampler *sampler;
1971 };
1972
1973 struct {
1974 struct anv_buffer *buffer;
1975 uint64_t offset;
1976 uint64_t range;
1977 };
1978
1979 struct anv_buffer_view *buffer_view;
1980 };
1981 };
1982
1983 struct anv_descriptor_set {
1984 struct vk_object_base base;
1985
1986 struct anv_descriptor_pool *pool;
1987 struct anv_descriptor_set_layout *layout;
1988 uint32_t size;
1989
1990 /* State relative to anv_descriptor_pool::bo */
1991 struct anv_state desc_mem;
1992 /* Surface state for the descriptor buffer */
1993 struct anv_state desc_surface_state;
1994
1995 uint32_t buffer_view_count;
1996 struct anv_buffer_view *buffer_views;
1997
1998 /* Link to descriptor pool's desc_sets list . */
1999 struct list_head pool_link;
2000
2001 struct anv_descriptor descriptors[0];
2002 };
2003
2004 struct anv_buffer_view {
2005 struct vk_object_base base;
2006
2007 enum isl_format format; /**< VkBufferViewCreateInfo::format */
2008 uint64_t range; /**< VkBufferViewCreateInfo::range */
2009
2010 struct anv_address address;
2011
2012 struct anv_state surface_state;
2013 struct anv_state storage_surface_state;
2014 struct anv_state writeonly_storage_surface_state;
2015
2016 struct brw_image_param storage_image_param;
2017 };
2018
2019 struct anv_push_descriptor_set {
2020 struct anv_descriptor_set set;
2021
2022 /* Put this field right behind anv_descriptor_set so it fills up the
2023 * descriptors[0] field. */
2024 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
2025
2026 /** True if the descriptor set buffer has been referenced by a draw or
2027 * dispatch command.
2028 */
2029 bool set_used_on_gpu;
2030
2031 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
2032 };
2033
2034 struct anv_descriptor_pool {
2035 struct vk_object_base base;
2036
2037 uint32_t size;
2038 uint32_t next;
2039 uint32_t free_list;
2040
2041 struct anv_bo *bo;
2042 struct util_vma_heap bo_heap;
2043
2044 struct anv_state_stream surface_state_stream;
2045 void *surface_state_free_list;
2046
2047 struct list_head desc_sets;
2048
2049 char data[0];
2050 };
2051
2052 enum anv_descriptor_template_entry_type {
2053 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
2054 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
2055 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2056 };
2057
2058 struct anv_descriptor_template_entry {
2059 /* The type of descriptor in this entry */
2060 VkDescriptorType type;
2061
2062 /* Binding in the descriptor set */
2063 uint32_t binding;
2064
2065 /* Offset at which to write into the descriptor set binding */
2066 uint32_t array_element;
2067
2068 /* Number of elements to write into the descriptor set binding */
2069 uint32_t array_count;
2070
2071 /* Offset into the user provided data */
2072 size_t offset;
2073
2074 /* Stride between elements into the user provided data */
2075 size_t stride;
2076 };
2077
2078 struct anv_descriptor_update_template {
2079 struct vk_object_base base;
2080
2081 VkPipelineBindPoint bind_point;
2082
2083 /* The descriptor set this template corresponds to. This value is only
2084 * valid if the template was created with the templateType
2085 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2086 */
2087 uint8_t set;
2088
2089 /* Number of entries in this template */
2090 uint32_t entry_count;
2091
2092 /* Entries of the template */
2093 struct anv_descriptor_template_entry entries[0];
2094 };
2095
2096 size_t
2097 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
2098
2099 void
2100 anv_descriptor_set_write_image_view(struct anv_device *device,
2101 struct anv_descriptor_set *set,
2102 const VkDescriptorImageInfo * const info,
2103 VkDescriptorType type,
2104 uint32_t binding,
2105 uint32_t element);
2106
2107 void
2108 anv_descriptor_set_write_buffer_view(struct anv_device *device,
2109 struct anv_descriptor_set *set,
2110 VkDescriptorType type,
2111 struct anv_buffer_view *buffer_view,
2112 uint32_t binding,
2113 uint32_t element);
2114
2115 void
2116 anv_descriptor_set_write_buffer(struct anv_device *device,
2117 struct anv_descriptor_set *set,
2118 struct anv_state_stream *alloc_stream,
2119 VkDescriptorType type,
2120 struct anv_buffer *buffer,
2121 uint32_t binding,
2122 uint32_t element,
2123 VkDeviceSize offset,
2124 VkDeviceSize range);
2125 void
2126 anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
2127 struct anv_descriptor_set *set,
2128 uint32_t binding,
2129 const void *data,
2130 size_t offset,
2131 size_t size);
2132
2133 void
2134 anv_descriptor_set_write_template(struct anv_device *device,
2135 struct anv_descriptor_set *set,
2136 struct anv_state_stream *alloc_stream,
2137 const struct anv_descriptor_update_template *template,
2138 const void *data);
2139
2140 VkResult
2141 anv_descriptor_set_create(struct anv_device *device,
2142 struct anv_descriptor_pool *pool,
2143 struct anv_descriptor_set_layout *layout,
2144 struct anv_descriptor_set **out_set);
2145
2146 void
2147 anv_descriptor_set_destroy(struct anv_device *device,
2148 struct anv_descriptor_pool *pool,
2149 struct anv_descriptor_set *set);
2150
2151 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2152 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2153 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2154 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2155 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2156 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2157
2158 struct anv_pipeline_binding {
2159 /** Index in the descriptor set
2160 *
2161 * This is a flattened index; the descriptor set layout is already taken
2162 * into account.
2163 */
2164 uint32_t index;
2165
2166 /** The descriptor set this surface corresponds to.
2167 *
2168 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2169 * binding is not a normal descriptor set but something else.
2170 */
2171 uint8_t set;
2172
2173 union {
2174 /** Plane in the binding index for images */
2175 uint8_t plane;
2176
2177 /** Input attachment index (relative to the subpass) */
2178 uint8_t input_attachment_index;
2179
2180 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2181 uint8_t dynamic_offset_index;
2182 };
2183
2184 /** For a storage image, whether it is write-only */
2185 uint8_t write_only;
2186
2187 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2188 * assuming POD zero-initialization.
2189 */
2190 uint8_t pad;
2191 };
2192
2193 struct anv_push_range {
2194 /** Index in the descriptor set */
2195 uint32_t index;
2196
2197 /** Descriptor set index */
2198 uint8_t set;
2199
2200 /** Dynamic offset index (for dynamic UBOs) */
2201 uint8_t dynamic_offset_index;
2202
2203 /** Start offset in units of 32B */
2204 uint8_t start;
2205
2206 /** Range in units of 32B */
2207 uint8_t length;
2208 };
2209
2210 struct anv_pipeline_layout {
2211 struct vk_object_base base;
2212
2213 struct {
2214 struct anv_descriptor_set_layout *layout;
2215 uint32_t dynamic_offset_start;
2216 } set[MAX_SETS];
2217
2218 uint32_t num_sets;
2219
2220 unsigned char sha1[20];
2221 };
2222
2223 struct anv_buffer {
2224 struct vk_object_base base;
2225
2226 struct anv_device * device;
2227 VkDeviceSize size;
2228
2229 VkBufferUsageFlags usage;
2230
2231 /* Set when bound */
2232 struct anv_address address;
2233 };
2234
2235 static inline uint64_t
2236 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
2237 {
2238 assert(offset <= buffer->size);
2239 if (range == VK_WHOLE_SIZE) {
2240 return buffer->size - offset;
2241 } else {
2242 assert(range + offset >= range);
2243 assert(range + offset <= buffer->size);
2244 return range;
2245 }
2246 }
2247
2248 enum anv_cmd_dirty_bits {
2249 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2250 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2251 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2252 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2253 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2254 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2255 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2256 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2257 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2258 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
2259 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
2260 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
2261 ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
2262 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2263 };
2264 typedef uint32_t anv_cmd_dirty_mask_t;
2265
2266 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2267 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2268 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2269 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2270 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2271 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2272 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2273 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2274 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2275 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2276 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2277
2278 static inline enum anv_cmd_dirty_bits
2279 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
2280 {
2281 switch (vk_state) {
2282 case VK_DYNAMIC_STATE_VIEWPORT:
2283 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2284 case VK_DYNAMIC_STATE_SCISSOR:
2285 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
2286 case VK_DYNAMIC_STATE_LINE_WIDTH:
2287 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2288 case VK_DYNAMIC_STATE_DEPTH_BIAS:
2289 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2290 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
2291 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2292 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
2293 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2294 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
2295 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2296 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
2297 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2298 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2299 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2300 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
2301 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
2302 default:
2303 assert(!"Unsupported dynamic state");
2304 return 0;
2305 }
2306 }
2307
2308
2309 enum anv_pipe_bits {
2310 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
2311 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
2312 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
2313 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
2314 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
2315 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
2316 ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
2317 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
2318 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
2319 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
2320 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
2321 ANV_PIPE_CS_STALL_BIT = (1 << 20),
2322 ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
2323
2324 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2325 * a flush has happened but not a CS stall. The next time we do any sort
2326 * of invalidation we need to insert a CS stall at that time. Otherwise,
2327 * we would have to CS stall on every flush which could be bad.
2328 */
2329 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT = (1 << 22),
2330
2331 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2332 * target operations related to transfer commands with VkBuffer as
2333 * destination are ongoing. Some operations like copies on the command
2334 * streamer might need to be aware of this to trigger the appropriate stall
2335 * before they can proceed with the copy.
2336 */
2337 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 23),
2338
2339 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2340 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2341 * done by writing the AUX-TT register.
2342 */
2343 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 24),
2344
2345 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2346 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2347 * implement a workaround for Gen9.
2348 */
2349 ANV_PIPE_POST_SYNC_BIT = (1 << 25),
2350 };
2351
2352 #define ANV_PIPE_FLUSH_BITS ( \
2353 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2354 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2355 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2356 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2357
2358 #define ANV_PIPE_STALL_BITS ( \
2359 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2360 ANV_PIPE_DEPTH_STALL_BIT | \
2361 ANV_PIPE_CS_STALL_BIT)
2362
2363 #define ANV_PIPE_INVALIDATE_BITS ( \
2364 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2365 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2366 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2367 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2368 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2369 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2370 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2371
2372 static inline enum anv_pipe_bits
2373 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
2374 {
2375 enum anv_pipe_bits pipe_bits = 0;
2376
2377 unsigned b;
2378 for_each_bit(b, flags) {
2379 switch ((VkAccessFlagBits)(1 << b)) {
2380 case VK_ACCESS_SHADER_WRITE_BIT:
2381 /* We're transitioning a buffer that was previously used as write
2382 * destination through the data port. To make its content available
2383 * to future operations, flush the data cache.
2384 */
2385 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2386 break;
2387 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2388 /* We're transitioning a buffer that was previously used as render
2389 * target. To make its content available to future operations, flush
2390 * the render target cache.
2391 */
2392 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2393 break;
2394 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2395 /* We're transitioning a buffer that was previously used as depth
2396 * buffer. To make its content available to future operations, flush
2397 * the depth cache.
2398 */
2399 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2400 break;
2401 case VK_ACCESS_TRANSFER_WRITE_BIT:
2402 /* We're transitioning a buffer that was previously used as a
2403 * transfer write destination. Generic write operations include color
2404 * & depth operations as well as buffer operations like :
2405 * - vkCmdClearColorImage()
2406 * - vkCmdClearDepthStencilImage()
2407 * - vkCmdBlitImage()
2408 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2409 *
2410 * Most of these operations are implemented using Blorp which writes
2411 * through the render target, so flush that cache to make it visible
2412 * to future operations. And for depth related operations we also
2413 * need to flush the depth cache.
2414 */
2415 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2416 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2417 break;
2418 case VK_ACCESS_MEMORY_WRITE_BIT:
2419 /* We're transitioning a buffer for generic write operations. Flush
2420 * all the caches.
2421 */
2422 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2423 break;
2424 default:
2425 break; /* Nothing to do */
2426 }
2427 }
2428
2429 return pipe_bits;
2430 }
2431
2432 static inline enum anv_pipe_bits
2433 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
2434 {
2435 enum anv_pipe_bits pipe_bits = 0;
2436
2437 unsigned b;
2438 for_each_bit(b, flags) {
2439 switch ((VkAccessFlagBits)(1 << b)) {
2440 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2441 /* Indirect draw commands take a buffer as input that we're going to
2442 * read from the command streamer to load some of the HW registers
2443 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2444 * command streamer stall so that all the cache flushes have
2445 * completed before the command streamer loads from memory.
2446 */
2447 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2448 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2449 * through a vertex buffer, so invalidate that cache.
2450 */
2451 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2452 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2453 * UBO from the buffer, so we need to invalidate constant cache.
2454 */
2455 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2456 break;
2457 case VK_ACCESS_INDEX_READ_BIT:
2458 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2459 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2460 * commands, so we invalidate the VF cache to make sure there is no
2461 * stale data when we start rendering.
2462 */
2463 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2464 break;
2465 case VK_ACCESS_UNIFORM_READ_BIT:
2466 /* We transitioning a buffer to be used as uniform data. Because
2467 * uniform is accessed through the data port & sampler, we need to
2468 * invalidate the texture cache (sampler) & constant cache (data
2469 * port) to avoid stale data.
2470 */
2471 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2472 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2473 break;
2474 case VK_ACCESS_SHADER_READ_BIT:
2475 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2476 case VK_ACCESS_TRANSFER_READ_BIT:
2477 /* Transitioning a buffer to be read through the sampler, so
2478 * invalidate the texture cache, we don't want any stale data.
2479 */
2480 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2481 break;
2482 case VK_ACCESS_MEMORY_READ_BIT:
2483 /* Transitioning a buffer for generic read, invalidate all the
2484 * caches.
2485 */
2486 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
2487 break;
2488 case VK_ACCESS_MEMORY_WRITE_BIT:
2489 /* Generic write, make sure all previously written things land in
2490 * memory.
2491 */
2492 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2493 break;
2494 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
2495 /* Transitioning a buffer for conditional rendering. We'll load the
2496 * content of this buffer into HW registers using the command
2497 * streamer, so we need to stall the command streamer to make sure
2498 * any in-flight flush operations have completed.
2499 */
2500 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2501 break;
2502 default:
2503 break; /* Nothing to do */
2504 }
2505 }
2506
2507 return pipe_bits;
2508 }
2509
2510 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2511 VK_IMAGE_ASPECT_COLOR_BIT | \
2512 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2513 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2514 VK_IMAGE_ASPECT_PLANE_2_BIT)
2515 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2516 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2517 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2518 VK_IMAGE_ASPECT_PLANE_2_BIT)
2519
2520 struct anv_vertex_binding {
2521 struct anv_buffer * buffer;
2522 VkDeviceSize offset;
2523 };
2524
2525 struct anv_xfb_binding {
2526 struct anv_buffer * buffer;
2527 VkDeviceSize offset;
2528 VkDeviceSize size;
2529 };
2530
2531 struct anv_push_constants {
2532 /** Push constant data provided by the client through vkPushConstants */
2533 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
2534
2535 /** Dynamic offsets for dynamic UBOs and SSBOs */
2536 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2537
2538 uint64_t push_reg_mask;
2539
2540 /** Pad out to a multiple of 32 bytes */
2541 uint32_t pad[2];
2542
2543 struct {
2544 /** Base workgroup ID
2545 *
2546 * Used for vkCmdDispatchBase.
2547 */
2548 uint32_t base_work_group_id[3];
2549
2550 /** Subgroup ID
2551 *
2552 * This is never set by software but is implicitly filled out when
2553 * uploading the push constants for compute shaders.
2554 */
2555 uint32_t subgroup_id;
2556 } cs;
2557 };
2558
2559 struct anv_dynamic_state {
2560 struct {
2561 uint32_t count;
2562 VkViewport viewports[MAX_VIEWPORTS];
2563 } viewport;
2564
2565 struct {
2566 uint32_t count;
2567 VkRect2D scissors[MAX_SCISSORS];
2568 } scissor;
2569
2570 float line_width;
2571
2572 struct {
2573 float bias;
2574 float clamp;
2575 float slope;
2576 } depth_bias;
2577
2578 float blend_constants[4];
2579
2580 struct {
2581 float min;
2582 float max;
2583 } depth_bounds;
2584
2585 struct {
2586 uint32_t front;
2587 uint32_t back;
2588 } stencil_compare_mask;
2589
2590 struct {
2591 uint32_t front;
2592 uint32_t back;
2593 } stencil_write_mask;
2594
2595 struct {
2596 uint32_t front;
2597 uint32_t back;
2598 } stencil_reference;
2599
2600 struct {
2601 uint32_t factor;
2602 uint16_t pattern;
2603 } line_stipple;
2604 };
2605
2606 extern const struct anv_dynamic_state default_dynamic_state;
2607
2608 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state *dest,
2609 const struct anv_dynamic_state *src,
2610 uint32_t copy_mask);
2611
2612 struct anv_surface_state {
2613 struct anv_state state;
2614 /** Address of the surface referred to by this state
2615 *
2616 * This address is relative to the start of the BO.
2617 */
2618 struct anv_address address;
2619 /* Address of the aux surface, if any
2620 *
2621 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2622 *
2623 * With the exception of gen8, the bottom 12 bits of this address' offset
2624 * include extra aux information.
2625 */
2626 struct anv_address aux_address;
2627 /* Address of the clear color, if any
2628 *
2629 * This address is relative to the start of the BO.
2630 */
2631 struct anv_address clear_address;
2632 };
2633
2634 /**
2635 * Attachment state when recording a renderpass instance.
2636 *
2637 * The clear value is valid only if there exists a pending clear.
2638 */
2639 struct anv_attachment_state {
2640 enum isl_aux_usage aux_usage;
2641 struct anv_surface_state color;
2642 struct anv_surface_state input;
2643
2644 VkImageLayout current_layout;
2645 VkImageLayout current_stencil_layout;
2646 VkImageAspectFlags pending_clear_aspects;
2647 VkImageAspectFlags pending_load_aspects;
2648 bool fast_clear;
2649 VkClearValue clear_value;
2650
2651 /* When multiview is active, attachments with a renderpass clear
2652 * operation have their respective layers cleared on the first
2653 * subpass that uses them, and only in that subpass. We keep track
2654 * of this using a bitfield to indicate which layers of an attachment
2655 * have not been cleared yet when multiview is active.
2656 */
2657 uint32_t pending_clear_views;
2658 struct anv_image_view * image_view;
2659 };
2660
2661 /** State tracking for vertex buffer flushes
2662 *
2663 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2664 * addresses. If you happen to have two vertex buffers which get placed
2665 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2666 * collisions. In order to solve this problem, we track vertex address ranges
2667 * which are live in the cache and invalidate the cache if one ever exceeds 32
2668 * bits.
2669 */
2670 struct anv_vb_cache_range {
2671 /* Virtual address at which the live vertex buffer cache range starts for
2672 * this vertex buffer index.
2673 */
2674 uint64_t start;
2675
2676 /* Virtual address of the byte after where vertex buffer cache range ends.
2677 * This is exclusive such that end - start is the size of the range.
2678 */
2679 uint64_t end;
2680 };
2681
2682 /** State tracking for particular pipeline bind point
2683 *
2684 * This struct is the base struct for anv_cmd_graphics_state and
2685 * anv_cmd_compute_state. These are used to track state which is bound to a
2686 * particular type of pipeline. Generic state that applies per-stage such as
2687 * binding table offsets and push constants is tracked generically with a
2688 * per-stage array in anv_cmd_state.
2689 */
2690 struct anv_cmd_pipeline_state {
2691 struct anv_descriptor_set *descriptors[MAX_SETS];
2692 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2693 };
2694
2695 /** State tracking for graphics pipeline
2696 *
2697 * This has anv_cmd_pipeline_state as a base struct to track things which get
2698 * bound to a graphics pipeline. Along with general pipeline bind point state
2699 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2700 * state which is graphics-specific.
2701 */
2702 struct anv_cmd_graphics_state {
2703 struct anv_cmd_pipeline_state base;
2704
2705 struct anv_graphics_pipeline *pipeline;
2706
2707 anv_cmd_dirty_mask_t dirty;
2708 uint32_t vb_dirty;
2709
2710 struct anv_vb_cache_range ib_bound_range;
2711 struct anv_vb_cache_range ib_dirty_range;
2712 struct anv_vb_cache_range vb_bound_ranges[33];
2713 struct anv_vb_cache_range vb_dirty_ranges[33];
2714
2715 struct anv_dynamic_state dynamic;
2716
2717 struct {
2718 struct anv_buffer *index_buffer;
2719 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2720 uint32_t index_offset;
2721 } gen7;
2722 };
2723
2724 /** State tracking for compute pipeline
2725 *
2726 * This has anv_cmd_pipeline_state as a base struct to track things which get
2727 * bound to a compute pipeline. Along with general pipeline bind point state
2728 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2729 * state which is compute-specific.
2730 */
2731 struct anv_cmd_compute_state {
2732 struct anv_cmd_pipeline_state base;
2733
2734 struct anv_compute_pipeline *pipeline;
2735
2736 bool pipeline_dirty;
2737
2738 struct anv_address num_workgroups;
2739 };
2740
2741 /** State required while building cmd buffer */
2742 struct anv_cmd_state {
2743 /* PIPELINE_SELECT.PipelineSelection */
2744 uint32_t current_pipeline;
2745 const struct gen_l3_config * current_l3_config;
2746 uint32_t last_aux_map_state;
2747
2748 struct anv_cmd_graphics_state gfx;
2749 struct anv_cmd_compute_state compute;
2750
2751 enum anv_pipe_bits pending_pipe_bits;
2752 VkShaderStageFlags descriptors_dirty;
2753 VkShaderStageFlags push_constants_dirty;
2754
2755 struct anv_framebuffer * framebuffer;
2756 struct anv_render_pass * pass;
2757 struct anv_subpass * subpass;
2758 VkRect2D render_area;
2759 uint32_t restart_index;
2760 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2761 bool xfb_enabled;
2762 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
2763 VkShaderStageFlags push_constant_stages;
2764 struct anv_push_constants push_constants[MESA_SHADER_STAGES];
2765 struct anv_state binding_tables[MESA_SHADER_STAGES];
2766 struct anv_state samplers[MESA_SHADER_STAGES];
2767
2768 unsigned char sampler_sha1s[MESA_SHADER_STAGES][20];
2769 unsigned char surface_sha1s[MESA_SHADER_STAGES][20];
2770 unsigned char push_sha1s[MESA_SHADER_STAGES][20];
2771
2772 /**
2773 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2774 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2775 * and before invoking the secondary in ExecuteCommands.
2776 */
2777 bool pma_fix_enabled;
2778
2779 /**
2780 * Whether or not we know for certain that HiZ is enabled for the current
2781 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2782 * enabled or not, this will be false.
2783 */
2784 bool hiz_enabled;
2785
2786 bool conditional_render_enabled;
2787
2788 /**
2789 * Last rendering scale argument provided to
2790 * genX(cmd_buffer_emit_hashing_mode)().
2791 */
2792 unsigned current_hash_scale;
2793
2794 /**
2795 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2796 * valid only when recording a render pass instance.
2797 */
2798 struct anv_attachment_state * attachments;
2799
2800 /**
2801 * Surface states for color render targets. These are stored in a single
2802 * flat array. For depth-stencil attachments, the surface state is simply
2803 * left blank.
2804 */
2805 struct anv_state attachment_states;
2806
2807 /**
2808 * A null surface state of the right size to match the framebuffer. This
2809 * is one of the states in attachment_states.
2810 */
2811 struct anv_state null_surface_state;
2812 };
2813
2814 struct anv_cmd_pool {
2815 struct vk_object_base base;
2816 VkAllocationCallbacks alloc;
2817 struct list_head cmd_buffers;
2818 };
2819
2820 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2821
2822 enum anv_cmd_buffer_exec_mode {
2823 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2824 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2825 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2826 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2827 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2828 };
2829
2830 struct anv_cmd_buffer {
2831 struct vk_object_base base;
2832
2833 struct anv_device * device;
2834
2835 struct anv_cmd_pool * pool;
2836 struct list_head pool_link;
2837
2838 struct anv_batch batch;
2839
2840 /* Fields required for the actual chain of anv_batch_bo's.
2841 *
2842 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2843 */
2844 struct list_head batch_bos;
2845 enum anv_cmd_buffer_exec_mode exec_mode;
2846
2847 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2848 * referenced by this command buffer
2849 *
2850 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2851 */
2852 struct u_vector seen_bbos;
2853
2854 /* A vector of int32_t's for every block of binding tables.
2855 *
2856 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2857 */
2858 struct u_vector bt_block_states;
2859 struct anv_state bt_next;
2860
2861 struct anv_reloc_list surface_relocs;
2862 /** Last seen surface state block pool center bo offset */
2863 uint32_t last_ss_pool_center;
2864
2865 /* Serial for tracking buffer completion */
2866 uint32_t serial;
2867
2868 /* Stream objects for storing temporary data */
2869 struct anv_state_stream surface_state_stream;
2870 struct anv_state_stream dynamic_state_stream;
2871
2872 VkCommandBufferUsageFlags usage_flags;
2873 VkCommandBufferLevel level;
2874
2875 struct anv_cmd_state state;
2876
2877 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2878 uint64_t intel_perf_marker;
2879 };
2880
2881 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2882 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2883 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2884 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
2885 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
2886 struct anv_cmd_buffer *secondary);
2887 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
2888 VkResult anv_cmd_buffer_execbuf(struct anv_queue *queue,
2889 struct anv_cmd_buffer *cmd_buffer,
2890 const VkSemaphore *in_semaphores,
2891 const uint64_t *in_wait_values,
2892 uint32_t num_in_semaphores,
2893 const VkSemaphore *out_semaphores,
2894 const uint64_t *out_signal_values,
2895 uint32_t num_out_semaphores,
2896 VkFence fence);
2897
2898 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
2899
2900 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
2901 const void *data, uint32_t size, uint32_t alignment);
2902 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
2903 uint32_t *a, uint32_t *b,
2904 uint32_t dwords, uint32_t alignment);
2905
2906 struct anv_address
2907 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
2908 struct anv_state
2909 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
2910 uint32_t entries, uint32_t *state_offset);
2911 struct anv_state
2912 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
2913 struct anv_state
2914 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
2915 uint32_t size, uint32_t alignment);
2916
2917 VkResult
2918 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
2919
2920 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
2921 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
2922 bool depth_clamp_enable);
2923 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
2924
2925 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
2926 struct anv_render_pass *pass,
2927 struct anv_framebuffer *framebuffer,
2928 const VkClearValue *clear_values);
2929
2930 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
2931
2932 struct anv_state
2933 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
2934 gl_shader_stage stage);
2935 struct anv_state
2936 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
2937
2938 const struct anv_image_view *
2939 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
2940
2941 VkResult
2942 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
2943 uint32_t num_entries,
2944 uint32_t *state_offset,
2945 struct anv_state *bt_state);
2946
2947 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
2948
2949 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer);
2950
2951 enum anv_fence_type {
2952 ANV_FENCE_TYPE_NONE = 0,
2953 ANV_FENCE_TYPE_BO,
2954 ANV_FENCE_TYPE_WSI_BO,
2955 ANV_FENCE_TYPE_SYNCOBJ,
2956 ANV_FENCE_TYPE_WSI,
2957 };
2958
2959 enum anv_bo_fence_state {
2960 /** Indicates that this is a new (or newly reset fence) */
2961 ANV_BO_FENCE_STATE_RESET,
2962
2963 /** Indicates that this fence has been submitted to the GPU but is still
2964 * (as far as we know) in use by the GPU.
2965 */
2966 ANV_BO_FENCE_STATE_SUBMITTED,
2967
2968 ANV_BO_FENCE_STATE_SIGNALED,
2969 };
2970
2971 struct anv_fence_impl {
2972 enum anv_fence_type type;
2973
2974 union {
2975 /** Fence implementation for BO fences
2976 *
2977 * These fences use a BO and a set of CPU-tracked state flags. The BO
2978 * is added to the object list of the last execbuf call in a QueueSubmit
2979 * and is marked EXEC_WRITE. The state flags track when the BO has been
2980 * submitted to the kernel. We need to do this because Vulkan lets you
2981 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2982 * will say it's idle in this case.
2983 */
2984 struct {
2985 struct anv_bo *bo;
2986 enum anv_bo_fence_state state;
2987 } bo;
2988
2989 /** DRM syncobj handle for syncobj-based fences */
2990 uint32_t syncobj;
2991
2992 /** WSI fence */
2993 struct wsi_fence *fence_wsi;
2994 };
2995 };
2996
2997 struct anv_fence {
2998 struct vk_object_base base;
2999
3000 /* Permanent fence state. Every fence has some form of permanent state
3001 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3002 * cross-process fences) or it could just be a dummy for use internally.
3003 */
3004 struct anv_fence_impl permanent;
3005
3006 /* Temporary fence state. A fence *may* have temporary state. That state
3007 * is added to the fence by an import operation and is reset back to
3008 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3009 * state cannot be signaled because the fence must already be signaled
3010 * before the temporary state can be exported from the fence in the other
3011 * process and imported here.
3012 */
3013 struct anv_fence_impl temporary;
3014 };
3015
3016 void anv_fence_reset_temporary(struct anv_device *device,
3017 struct anv_fence *fence);
3018
3019 struct anv_event {
3020 struct vk_object_base base;
3021 uint64_t semaphore;
3022 struct anv_state state;
3023 };
3024
3025 enum anv_semaphore_type {
3026 ANV_SEMAPHORE_TYPE_NONE = 0,
3027 ANV_SEMAPHORE_TYPE_DUMMY,
3028 ANV_SEMAPHORE_TYPE_BO,
3029 ANV_SEMAPHORE_TYPE_WSI_BO,
3030 ANV_SEMAPHORE_TYPE_SYNC_FILE,
3031 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
3032 ANV_SEMAPHORE_TYPE_TIMELINE,
3033 };
3034
3035 struct anv_timeline_point {
3036 struct list_head link;
3037
3038 uint64_t serial;
3039
3040 /* Number of waiter on this point, when > 0 the point should not be garbage
3041 * collected.
3042 */
3043 int waiting;
3044
3045 /* BO used for synchronization. */
3046 struct anv_bo *bo;
3047 };
3048
3049 struct anv_timeline {
3050 pthread_mutex_t mutex;
3051 pthread_cond_t cond;
3052
3053 uint64_t highest_past;
3054 uint64_t highest_pending;
3055
3056 struct list_head points;
3057 struct list_head free_points;
3058 };
3059
3060 struct anv_semaphore_impl {
3061 enum anv_semaphore_type type;
3062
3063 union {
3064 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3065 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3066 * object list on any execbuf2 calls for which this semaphore is used as
3067 * a wait or signal fence. When used as a signal fence or when type ==
3068 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3069 */
3070 struct anv_bo *bo;
3071
3072 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3073 * If the semaphore is in the unsignaled state due to either just being
3074 * created or because it has been used for a wait, fd will be -1.
3075 */
3076 int fd;
3077
3078 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3079 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3080 * import so we don't need to bother with a userspace cache.
3081 */
3082 uint32_t syncobj;
3083
3084 /* Non shareable timeline semaphore
3085 *
3086 * Used when kernel don't have support for timeline semaphores.
3087 */
3088 struct anv_timeline timeline;
3089 };
3090 };
3091
3092 struct anv_semaphore {
3093 struct vk_object_base base;
3094
3095 uint32_t refcount;
3096
3097 /* Permanent semaphore state. Every semaphore has some form of permanent
3098 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3099 * (for cross-process semaphores0 or it could just be a dummy for use
3100 * internally.
3101 */
3102 struct anv_semaphore_impl permanent;
3103
3104 /* Temporary semaphore state. A semaphore *may* have temporary state.
3105 * That state is added to the semaphore by an import operation and is reset
3106 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3107 * semaphore with temporary state cannot be signaled because the semaphore
3108 * must already be signaled before the temporary state can be exported from
3109 * the semaphore in the other process and imported here.
3110 */
3111 struct anv_semaphore_impl temporary;
3112 };
3113
3114 void anv_semaphore_reset_temporary(struct anv_device *device,
3115 struct anv_semaphore *semaphore);
3116
3117 struct anv_shader_module {
3118 struct vk_object_base base;
3119
3120 unsigned char sha1[20];
3121 uint32_t size;
3122 char data[0];
3123 };
3124
3125 static inline gl_shader_stage
3126 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
3127 {
3128 assert(__builtin_popcount(vk_stage) == 1);
3129 return ffs(vk_stage) - 1;
3130 }
3131
3132 static inline VkShaderStageFlagBits
3133 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
3134 {
3135 return (1 << mesa_stage);
3136 }
3137
3138 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3139
3140 #define anv_foreach_stage(stage, stage_bits) \
3141 for (gl_shader_stage stage, \
3142 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3143 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3144 __tmp &= ~(1 << (stage)))
3145
3146 struct anv_pipeline_bind_map {
3147 unsigned char surface_sha1[20];
3148 unsigned char sampler_sha1[20];
3149 unsigned char push_sha1[20];
3150
3151 uint32_t surface_count;
3152 uint32_t sampler_count;
3153
3154 struct anv_pipeline_binding * surface_to_descriptor;
3155 struct anv_pipeline_binding * sampler_to_descriptor;
3156
3157 struct anv_push_range push_ranges[4];
3158 };
3159
3160 struct anv_shader_bin_key {
3161 uint32_t size;
3162 uint8_t data[0];
3163 };
3164
3165 struct anv_shader_bin {
3166 uint32_t ref_cnt;
3167
3168 gl_shader_stage stage;
3169
3170 const struct anv_shader_bin_key *key;
3171
3172 struct anv_state kernel;
3173 uint32_t kernel_size;
3174
3175 struct anv_state constant_data;
3176 uint32_t constant_data_size;
3177
3178 const struct brw_stage_prog_data *prog_data;
3179 uint32_t prog_data_size;
3180
3181 struct brw_compile_stats stats[3];
3182 uint32_t num_stats;
3183
3184 struct nir_xfb_info *xfb_info;
3185
3186 struct anv_pipeline_bind_map bind_map;
3187 };
3188
3189 struct anv_shader_bin *
3190 anv_shader_bin_create(struct anv_device *device,
3191 gl_shader_stage stage,
3192 const void *key, uint32_t key_size,
3193 const void *kernel, uint32_t kernel_size,
3194 const void *constant_data, uint32_t constant_data_size,
3195 const struct brw_stage_prog_data *prog_data,
3196 uint32_t prog_data_size,
3197 const struct brw_compile_stats *stats, uint32_t num_stats,
3198 const struct nir_xfb_info *xfb_info,
3199 const struct anv_pipeline_bind_map *bind_map);
3200
3201 void
3202 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
3203
3204 static inline void
3205 anv_shader_bin_ref(struct anv_shader_bin *shader)
3206 {
3207 assert(shader && shader->ref_cnt >= 1);
3208 p_atomic_inc(&shader->ref_cnt);
3209 }
3210
3211 static inline void
3212 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
3213 {
3214 assert(shader && shader->ref_cnt >= 1);
3215 if (p_atomic_dec_zero(&shader->ref_cnt))
3216 anv_shader_bin_destroy(device, shader);
3217 }
3218
3219 struct anv_pipeline_executable {
3220 gl_shader_stage stage;
3221
3222 struct brw_compile_stats stats;
3223
3224 char *nir;
3225 char *disasm;
3226 };
3227
3228 enum anv_pipeline_type {
3229 ANV_PIPELINE_GRAPHICS,
3230 ANV_PIPELINE_COMPUTE,
3231 };
3232
3233 struct anv_pipeline {
3234 struct vk_object_base base;
3235
3236 struct anv_device * device;
3237
3238 struct anv_batch batch;
3239 struct anv_reloc_list batch_relocs;
3240
3241 void * mem_ctx;
3242
3243 enum anv_pipeline_type type;
3244 VkPipelineCreateFlags flags;
3245
3246 struct util_dynarray executables;
3247
3248 const struct gen_l3_config * l3_config;
3249 };
3250
3251 struct anv_graphics_pipeline {
3252 struct anv_pipeline base;
3253
3254 uint32_t batch_data[512];
3255
3256 anv_cmd_dirty_mask_t dynamic_state_mask;
3257 struct anv_dynamic_state dynamic_state;
3258
3259 uint32_t topology;
3260
3261 struct anv_subpass * subpass;
3262
3263 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
3264
3265 VkShaderStageFlags active_stages;
3266
3267 bool primitive_restart;
3268 bool writes_depth;
3269 bool depth_test_enable;
3270 bool writes_stencil;
3271 bool stencil_test_enable;
3272 bool depth_clamp_enable;
3273 bool depth_clip_enable;
3274 bool sample_shading_enable;
3275 bool kill_pixel;
3276 bool depth_bounds_test_enable;
3277
3278 /* When primitive replication is used, subpass->view_mask will describe what
3279 * views to replicate.
3280 */
3281 bool use_primitive_replication;
3282
3283 struct anv_state blend_state;
3284
3285 uint32_t vb_used;
3286 struct anv_pipeline_vertex_binding {
3287 uint32_t stride;
3288 bool instanced;
3289 uint32_t instance_divisor;
3290 } vb[MAX_VBS];
3291
3292 struct {
3293 uint32_t sf[7];
3294 uint32_t depth_stencil_state[3];
3295 } gen7;
3296
3297 struct {
3298 uint32_t sf[4];
3299 uint32_t raster[5];
3300 uint32_t wm_depth_stencil[3];
3301 } gen8;
3302
3303 struct {
3304 uint32_t wm_depth_stencil[4];
3305 } gen9;
3306 };
3307
3308 struct anv_compute_pipeline {
3309 struct anv_pipeline base;
3310
3311 struct anv_shader_bin * cs;
3312 uint32_t cs_right_mask;
3313 uint32_t batch_data[9];
3314 uint32_t interface_descriptor_data[8];
3315 };
3316
3317 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3318 static inline struct anv_##pipe_type##_pipeline * \
3319 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3320 { \
3321 assert(pipeline->type == pipe_enum); \
3322 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3323 }
3324
3325 ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS)
3326 ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE)
3327
3328 static inline bool
3329 anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
3330 gl_shader_stage stage)
3331 {
3332 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
3333 }
3334
3335 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3336 static inline const struct brw_##prefix##_prog_data * \
3337 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3338 { \
3339 if (anv_pipeline_has_stage(pipeline, stage)) { \
3340 return (const struct brw_##prefix##_prog_data *) \
3341 pipeline->shaders[stage]->prog_data; \
3342 } else { \
3343 return NULL; \
3344 } \
3345 }
3346
3347 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
3348 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
3349 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
3350 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
3351 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
3352
3353 static inline const struct brw_cs_prog_data *
3354 get_cs_prog_data(const struct anv_compute_pipeline *pipeline)
3355 {
3356 assert(pipeline->cs);
3357 return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
3358 }
3359
3360 static inline const struct brw_vue_prog_data *
3361 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
3362 {
3363 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
3364 return &get_gs_prog_data(pipeline)->base;
3365 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
3366 return &get_tes_prog_data(pipeline)->base;
3367 else
3368 return &get_vs_prog_data(pipeline)->base;
3369 }
3370
3371 VkResult
3372 anv_pipeline_init(struct anv_graphics_pipeline *pipeline, struct anv_device *device,
3373 struct anv_pipeline_cache *cache,
3374 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3375 const VkAllocationCallbacks *alloc);
3376
3377 VkResult
3378 anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
3379 struct anv_pipeline_cache *cache,
3380 const VkComputePipelineCreateInfo *info,
3381 const struct anv_shader_module *module,
3382 const char *entrypoint,
3383 const VkSpecializationInfo *spec_info);
3384
3385 uint32_t
3386 anv_cs_workgroup_size(const struct anv_compute_pipeline *pipeline);
3387
3388 uint32_t
3389 anv_cs_threads(const struct anv_compute_pipeline *pipeline);
3390
3391 struct anv_format_plane {
3392 enum isl_format isl_format:16;
3393 struct isl_swizzle swizzle;
3394
3395 /* Whether this plane contains chroma channels */
3396 bool has_chroma;
3397
3398 /* For downscaling of YUV planes */
3399 uint8_t denominator_scales[2];
3400
3401 /* How to map sampled ycbcr planes to a single 4 component element. */
3402 struct isl_swizzle ycbcr_swizzle;
3403
3404 /* What aspect is associated to this plane */
3405 VkImageAspectFlags aspect;
3406 };
3407
3408
3409 struct anv_format {
3410 struct anv_format_plane planes[3];
3411 VkFormat vk_format;
3412 uint8_t n_planes;
3413 bool can_ycbcr;
3414 };
3415
3416 /**
3417 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3418 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3419 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3420 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3421 */
3422 static inline uint32_t
3423 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
3424 VkImageAspectFlags aspect_mask)
3425 {
3426 switch (aspect_mask) {
3427 case VK_IMAGE_ASPECT_COLOR_BIT:
3428 case VK_IMAGE_ASPECT_DEPTH_BIT:
3429 case VK_IMAGE_ASPECT_PLANE_0_BIT:
3430 return 0;
3431 case VK_IMAGE_ASPECT_STENCIL_BIT:
3432 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
3433 return 0;
3434 /* Fall-through */
3435 case VK_IMAGE_ASPECT_PLANE_1_BIT:
3436 return 1;