46f64cfd8b2bacb877f29a539250c51f932a904c
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include "drm-uapi/i915_drm.h"
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #ifndef NDEBUG
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
41 #endif
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
61 #include "util/vma.h"
62 #include "util/xmlconfig.h"
63 #include "vk_alloc.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 struct anv_batch;
75 struct anv_buffer;
76 struct anv_buffer_view;
77 struct anv_image_view;
78 struct anv_instance;
79
80 struct gen_aux_map_context;
81 struct gen_perf_config;
82 struct gen_perf_counter_pass;
83 struct gen_perf_query_result;
84
85 #include <vulkan/vulkan.h>
86 #include <vulkan/vulkan_intel.h>
87 #include <vulkan/vk_icd.h>
88
89 #include "anv_android.h"
90 #include "anv_entrypoints.h"
91 #include "anv_extensions.h"
92 #include "isl/isl.h"
93
94 #include "dev/gen_debug.h"
95 #include "common/intel_log.h"
96 #include "wsi_common.h"
97
98 #define NSEC_PER_SEC 1000000000ull
99
100 /* anv Virtual Memory Layout
101 * =========================
102 *
103 * When the anv driver is determining the virtual graphics addresses of memory
104 * objects itself using the softpin mechanism, the following memory ranges
105 * will be used.
106 *
107 * Three special considerations to notice:
108 *
109 * (1) the dynamic state pool is located within the same 4 GiB as the low
110 * heap. This is to work around a VF cache issue described in a comment in
111 * anv_physical_device_init_heaps.
112 *
113 * (2) the binding table pool is located at lower addresses than the surface
114 * state pool, within a 4 GiB range. This allows surface state base addresses
115 * to cover both binding tables (16 bit offsets) and surface states (32 bit
116 * offsets).
117 *
118 * (3) the last 4 GiB of the address space is withheld from the high
119 * heap. Various hardware units will read past the end of an object for
120 * various reasons. This healthy margin prevents reads from wrapping around
121 * 48-bit addresses.
122 */
123 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
124 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
125 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
126 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
127 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
128 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
129 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
130 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
131 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
132 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
133 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
134 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
135 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
136
137 #define LOW_HEAP_SIZE \
138 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
139 #define DYNAMIC_STATE_POOL_SIZE \
140 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
141 #define BINDING_TABLE_POOL_SIZE \
142 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
143 #define SURFACE_STATE_POOL_SIZE \
144 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
145 #define INSTRUCTION_STATE_POOL_SIZE \
146 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
147 #define CLIENT_VISIBLE_HEAP_SIZE \
148 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
149
150 /* Allowing different clear colors requires us to perform a depth resolve at
151 * the end of certain render passes. This is because while slow clears store
152 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
153 * See the PRMs for examples describing when additional resolves would be
154 * necessary. To enable fast clears without requiring extra resolves, we set
155 * the clear value to a globally-defined one. We could allow different values
156 * if the user doesn't expect coherent data during or after a render passes
157 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
158 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
159 * 1.0f seems to be the only value used. The only application that doesn't set
160 * this value does so through the usage of an seemingly uninitialized clear
161 * value.
162 */
163 #define ANV_HZ_FC_VAL 1.0f
164
165 #define MAX_VBS 28
166 #define MAX_XFB_BUFFERS 4
167 #define MAX_XFB_STREAMS 4
168 #define MAX_SETS 8
169 #define MAX_RTS 8
170 #define MAX_VIEWPORTS 16
171 #define MAX_SCISSORS 16
172 #define MAX_PUSH_CONSTANTS_SIZE 128
173 #define MAX_DYNAMIC_BUFFERS 16
174 #define MAX_IMAGES 64
175 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
176 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
177 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
178 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
179 * use 64 here to avoid cache issues. This could most likely bring it back to
180 * 32 if we had different virtual addresses for the different views on a given
181 * GEM object.
182 */
183 #define ANV_UBO_ALIGNMENT 64
184 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
185 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
186
187 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
188 *
189 * "The surface state model is used when a Binding Table Index (specified
190 * in the message descriptor) of less than 240 is specified. In this model,
191 * the Binding Table Index is used to index into the binding table, and the
192 * binding table entry contains a pointer to the SURFACE_STATE."
193 *
194 * Binding table values above 240 are used for various things in the hardware
195 * such as stateless, stateless with incoherent cache, SLM, and bindless.
196 */
197 #define MAX_BINDING_TABLE_SIZE 240
198
199 /* The kernel relocation API has a limitation of a 32-bit delta value
200 * applied to the address before it is written which, in spite of it being
201 * unsigned, is treated as signed . Because of the way that this maps to
202 * the Vulkan API, we cannot handle an offset into a buffer that does not
203 * fit into a signed 32 bits. The only mechanism we have for dealing with
204 * this at the moment is to limit all VkDeviceMemory objects to a maximum
205 * of 2GB each. The Vulkan spec allows us to do this:
206 *
207 * "Some platforms may have a limit on the maximum size of a single
208 * allocation. For example, certain systems may fail to create
209 * allocations with a size greater than or equal to 4GB. Such a limit is
210 * implementation-dependent, and if such a failure occurs then the error
211 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
212 *
213 * We don't use vk_error here because it's not an error so much as an
214 * indication to the application that the allocation is too large.
215 */
216 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
217
218 #define ANV_SVGS_VB_INDEX MAX_VBS
219 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
220
221 /* We reserve this MI ALU register for the purpose of handling predication.
222 * Other code which uses the MI ALU should leave it alone.
223 */
224 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
225
226 /* We reserve this MI ALU register to pass around an offset computed from
227 * VkPerformanceQuerySubmitInfoKHR::counterPassIndex VK_KHR_performance_query.
228 * Other code which uses the MI ALU should leave it alone.
229 */
230 #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
231
232 /* For gen12 we set the streamout buffers using 4 separate commands
233 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
234 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
235 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
236 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
237 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
238 * 3DSTATE_SO_BUFFER_INDEX_0.
239 */
240 #define SO_BUFFER_INDEX_0_CMD 0x60
241 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
242
243 static inline uint32_t
244 align_down_npot_u32(uint32_t v, uint32_t a)
245 {
246 return v - (v % a);
247 }
248
249 static inline uint32_t
250 align_down_u32(uint32_t v, uint32_t a)
251 {
252 assert(a != 0 && a == (a & -a));
253 return v & ~(a - 1);
254 }
255
256 static inline uint32_t
257 align_u32(uint32_t v, uint32_t a)
258 {
259 assert(a != 0 && a == (a & -a));
260 return align_down_u32(v + a - 1, a);
261 }
262
263 static inline uint64_t
264 align_down_u64(uint64_t v, uint64_t a)
265 {
266 assert(a != 0 && a == (a & -a));
267 return v & ~(a - 1);
268 }
269
270 static inline uint64_t
271 align_u64(uint64_t v, uint64_t a)
272 {
273 return align_down_u64(v + a - 1, a);
274 }
275
276 static inline int32_t
277 align_i32(int32_t v, int32_t a)
278 {
279 assert(a != 0 && a == (a & -a));
280 return (v + a - 1) & ~(a - 1);
281 }
282
283 /** Alignment must be a power of 2. */
284 static inline bool
285 anv_is_aligned(uintmax_t n, uintmax_t a)
286 {
287 assert(a == (a & -a));
288 return (n & (a - 1)) == 0;
289 }
290
291 static inline uint32_t
292 anv_minify(uint32_t n, uint32_t levels)
293 {
294 if (unlikely(n == 0))
295 return 0;
296 else
297 return MAX2(n >> levels, 1);
298 }
299
300 static inline float
301 anv_clamp_f(float f, float min, float max)
302 {
303 assert(min < max);
304
305 if (f > max)
306 return max;
307 else if (f < min)
308 return min;
309 else
310 return f;
311 }
312
313 static inline bool
314 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
315 {
316 if (*inout_mask & clear_mask) {
317 *inout_mask &= ~clear_mask;
318 return true;
319 } else {
320 return false;
321 }
322 }
323
324 static inline union isl_color_value
325 vk_to_isl_color(VkClearColorValue color)
326 {
327 return (union isl_color_value) {
328 .u32 = {
329 color.uint32[0],
330 color.uint32[1],
331 color.uint32[2],
332 color.uint32[3],
333 },
334 };
335 }
336
337 static inline void *anv_unpack_ptr(uintptr_t ptr, int bits, int *flags)
338 {
339 uintptr_t mask = (1ull << bits) - 1;
340 *flags = ptr & mask;
341 return (void *) (ptr & ~mask);
342 }
343
344 static inline uintptr_t anv_pack_ptr(void *ptr, int bits, int flags)
345 {
346 uintptr_t value = (uintptr_t) ptr;
347 uintptr_t mask = (1ull << bits) - 1;
348 return value | (mask & flags);
349 }
350
351 #define for_each_bit(b, dword) \
352 for (uint32_t __dword = (dword); \
353 (b) = __builtin_ffs(__dword) - 1, __dword; \
354 __dword &= ~(1 << (b)))
355
356 #define typed_memcpy(dest, src, count) ({ \
357 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
358 memcpy((dest), (src), (count) * sizeof(*(src))); \
359 })
360
361 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
362 * to be added here in order to utilize mapping in debug/error/perf macros.
363 */
364 #define REPORT_OBJECT_TYPE(o) \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
443 __builtin_choose_expr ( \
444 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
445 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
446 __builtin_choose_expr ( \
447 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
448 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
449 __builtin_choose_expr ( \
450 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
451 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
452 __builtin_choose_expr ( \
453 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
454 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
455 __builtin_choose_expr ( \
456 __builtin_types_compatible_p (__typeof (o), void*), \
457 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
458 /* The void expression results in a compile-time error \
459 when assigning the result to something. */ \
460 (void)0)))))))))))))))))))))))))))))))
461
462 /* Whenever we generate an error, pass it through this function. Useful for
463 * debugging, where we can break on it. Only call at error site, not when
464 * propagating errors. Might be useful to plug in a stack trace here.
465 */
466
467 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
468 VkDebugReportObjectTypeEXT type, VkResult error,
469 const char *file, int line, const char *format,
470 va_list args);
471
472 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
473 VkDebugReportObjectTypeEXT type, VkResult error,
474 const char *file, int line, const char *format, ...)
475 anv_printflike(7, 8);
476
477 #ifdef DEBUG
478 #define vk_error(error) __vk_errorf(NULL, NULL,\
479 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
480 error, __FILE__, __LINE__, NULL)
481 #define vk_errorfi(instance, obj, error, format, ...)\
482 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
483 __FILE__, __LINE__, format, ## __VA_ARGS__)
484 #define vk_errorf(device, obj, error, format, ...)\
485 vk_errorfi(anv_device_instance_or_null(device),\
486 obj, error, format, ## __VA_ARGS__)
487 #else
488 #define vk_error(error) error
489 #define vk_errorfi(instance, obj, error, format, ...) error
490 #define vk_errorf(device, obj, error, format, ...) error
491 #endif
492
493 /**
494 * Warn on ignored extension structs.
495 *
496 * The Vulkan spec requires us to ignore unsupported or unknown structs in
497 * a pNext chain. In debug mode, emitting warnings for ignored structs may
498 * help us discover structs that we should not have ignored.
499 *
500 *
501 * From the Vulkan 1.0.38 spec:
502 *
503 * Any component of the implementation (the loader, any enabled layers,
504 * and drivers) must skip over, without processing (other than reading the
505 * sType and pNext members) any chained structures with sType values not
506 * defined by extensions supported by that component.
507 */
508 #define anv_debug_ignored_stype(sType) \
509 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
510
511 void __anv_perf_warn(struct anv_device *device, const void *object,
512 VkDebugReportObjectTypeEXT type, const char *file,
513 int line, const char *format, ...)
514 anv_printflike(6, 7);
515 void anv_loge(const char *format, ...) anv_printflike(1, 2);
516 void anv_loge_v(const char *format, va_list va);
517
518 /**
519 * Print a FINISHME message, including its source location.
520 */
521 #define anv_finishme(format, ...) \
522 do { \
523 static bool reported = false; \
524 if (!reported) { \
525 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
526 ##__VA_ARGS__); \
527 reported = true; \
528 } \
529 } while (0)
530
531 /**
532 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
533 */
534 #define anv_perf_warn(instance, obj, format, ...) \
535 do { \
536 static bool reported = false; \
537 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
538 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
539 format, ##__VA_ARGS__); \
540 reported = true; \
541 } \
542 } while (0)
543
544 /* A non-fatal assert. Useful for debugging. */
545 #ifdef DEBUG
546 #define anv_assert(x) ({ \
547 if (unlikely(!(x))) \
548 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
549 })
550 #else
551 #define anv_assert(x)
552 #endif
553
554 /* A multi-pointer allocator
555 *
556 * When copying data structures from the user (such as a render pass), it's
557 * common to need to allocate data for a bunch of different things. Instead
558 * of doing several allocations and having to handle all of the error checking
559 * that entails, it can be easier to do a single allocation. This struct
560 * helps facilitate that. The intended usage looks like this:
561 *
562 * ANV_MULTIALLOC(ma)
563 * anv_multialloc_add(&ma, &main_ptr, 1);
564 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
565 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
566 *
567 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
568 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
569 */
570 struct anv_multialloc {
571 size_t size;
572 size_t align;
573
574 uint32_t ptr_count;
575 void **ptrs[8];
576 };
577
578 #define ANV_MULTIALLOC_INIT \
579 ((struct anv_multialloc) { 0, })
580
581 #define ANV_MULTIALLOC(_name) \
582 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
583
584 __attribute__((always_inline))
585 static inline void
586 _anv_multialloc_add(struct anv_multialloc *ma,
587 void **ptr, size_t size, size_t align)
588 {
589 size_t offset = align_u64(ma->size, align);
590 ma->size = offset + size;
591 ma->align = MAX2(ma->align, align);
592
593 /* Store the offset in the pointer. */
594 *ptr = (void *)(uintptr_t)offset;
595
596 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
597 ma->ptrs[ma->ptr_count++] = ptr;
598 }
599
600 #define anv_multialloc_add_size(_ma, _ptr, _size) \
601 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
602
603 #define anv_multialloc_add(_ma, _ptr, _count) \
604 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
605
606 __attribute__((always_inline))
607 static inline void *
608 anv_multialloc_alloc(struct anv_multialloc *ma,
609 const VkAllocationCallbacks *alloc,
610 VkSystemAllocationScope scope)
611 {
612 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
613 if (!ptr)
614 return NULL;
615
616 /* Fill out each of the pointers with their final value.
617 *
618 * for (uint32_t i = 0; i < ma->ptr_count; i++)
619 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
620 *
621 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
622 * constant, GCC is incapable of figuring this out and unrolling the loop
623 * so we have to give it a little help.
624 */
625 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
626 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
627 if ((_i) < ma->ptr_count) \
628 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
629 _ANV_MULTIALLOC_UPDATE_POINTER(0);
630 _ANV_MULTIALLOC_UPDATE_POINTER(1);
631 _ANV_MULTIALLOC_UPDATE_POINTER(2);
632 _ANV_MULTIALLOC_UPDATE_POINTER(3);
633 _ANV_MULTIALLOC_UPDATE_POINTER(4);
634 _ANV_MULTIALLOC_UPDATE_POINTER(5);
635 _ANV_MULTIALLOC_UPDATE_POINTER(6);
636 _ANV_MULTIALLOC_UPDATE_POINTER(7);
637 #undef _ANV_MULTIALLOC_UPDATE_POINTER
638
639 return ptr;
640 }
641
642 __attribute__((always_inline))
643 static inline void *
644 anv_multialloc_alloc2(struct anv_multialloc *ma,
645 const VkAllocationCallbacks *parent_alloc,
646 const VkAllocationCallbacks *alloc,
647 VkSystemAllocationScope scope)
648 {
649 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
650 }
651
652 struct anv_bo {
653 uint32_t gem_handle;
654
655 uint32_t refcount;
656
657 /* Index into the current validation list. This is used by the
658 * validation list building alrogithm to track which buffers are already
659 * in the validation list so that we can ensure uniqueness.
660 */
661 uint32_t index;
662
663 /* Index for use with util_sparse_array_free_list */
664 uint32_t free_index;
665
666 /* Last known offset. This value is provided by the kernel when we
667 * execbuf and is used as the presumed offset for the next bunch of
668 * relocations.
669 */
670 uint64_t offset;
671
672 /** Size of the buffer not including implicit aux */
673 uint64_t size;
674
675 /* Map for internally mapped BOs.
676 *
677 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
678 */
679 void *map;
680
681 /** Size of the implicit CCS range at the end of the buffer
682 *
683 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
684 * page of main surface data maps to a 256B chunk of CCS data and that
685 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
686 * addresses in the main surface to virtual memory addresses for CCS data.
687 *
688 * Because we can't change these maps around easily and because Vulkan
689 * allows two VkImages to be bound to overlapping memory regions (as long
690 * as the app is careful), it's not feasible to make this mapping part of
691 * the image. (On Gen11 and earlier, the mapping was provided via
692 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
693 * Instead, we attach the CCS data directly to the buffer object and setup
694 * the AUX table mapping at BO creation time.
695 *
696 * This field is for internal tracking use by the BO allocator only and
697 * should not be touched by other parts of the code. If something wants to
698 * know if a BO has implicit CCS data, it should instead look at the
699 * has_implicit_ccs boolean below.
700 *
701 * This data is not included in maps of this buffer.
702 */
703 uint32_t _ccs_size;
704
705 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
706 uint32_t flags;
707
708 /** True if this BO may be shared with other processes */
709 bool is_external:1;
710
711 /** True if this BO is a wrapper
712 *
713 * When set to true, none of the fields in this BO are meaningful except
714 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
715 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
716 * is set in the physical device.
717 */
718 bool is_wrapper:1;
719
720 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
721 bool has_fixed_address:1;
722
723 /** True if this BO wraps a host pointer */
724 bool from_host_ptr:1;
725
726 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
727 bool has_client_visible_address:1;
728
729 /** True if this BO has implicit CCS data attached to it */
730 bool has_implicit_ccs:1;
731 };
732
733 static inline struct anv_bo *
734 anv_bo_ref(struct anv_bo *bo)
735 {
736 p_atomic_inc(&bo->refcount);
737 return bo;
738 }
739
740 static inline struct anv_bo *
741 anv_bo_unwrap(struct anv_bo *bo)
742 {
743 while (bo->is_wrapper)
744 bo = bo->map;
745 return bo;
746 }
747
748 /* Represents a lock-free linked list of "free" things. This is used by
749 * both the block pool and the state pools. Unfortunately, in order to
750 * solve the ABA problem, we can't use a single uint32_t head.
751 */
752 union anv_free_list {
753 struct {
754 uint32_t offset;
755
756 /* A simple count that is incremented every time the head changes. */
757 uint32_t count;
758 };
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
761 */
762 uint64_t u64 __attribute__ ((aligned (8)));
763 };
764
765 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
766
767 struct anv_block_state {
768 union {
769 struct {
770 uint32_t next;
771 uint32_t end;
772 };
773 /* Make sure it's aligned to 64 bits. This will make atomic operations
774 * faster on 32 bit platforms.
775 */
776 uint64_t u64 __attribute__ ((aligned (8)));
777 };
778 };
779
780 #define anv_block_pool_foreach_bo(bo, pool) \
781 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
782 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
783 _pp_bo++)
784
785 #define ANV_MAX_BLOCK_POOL_BOS 20
786
787 struct anv_block_pool {
788 struct anv_device *device;
789 bool use_softpin;
790
791 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
792 * around the actual BO so that we grow the pool after the wrapper BO has
793 * been put in a relocation list. This is only used in the non-softpin
794 * case.
795 */
796 struct anv_bo wrapper_bo;
797
798 struct anv_bo *bos[ANV_MAX_BLOCK_POOL_BOS];
799 struct anv_bo *bo;
800 uint32_t nbos;
801
802 uint64_t size;
803
804 /* The address where the start of the pool is pinned. The various bos that
805 * are created as the pool grows will have addresses in the range
806 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
807 */
808 uint64_t start_address;
809
810 /* The offset from the start of the bo to the "center" of the block
811 * pool. Pointers to allocated blocks are given by
812 * bo.map + center_bo_offset + offsets.
813 */
814 uint32_t center_bo_offset;
815
816 /* Current memory map of the block pool. This pointer may or may not
817 * point to the actual beginning of the block pool memory. If
818 * anv_block_pool_alloc_back has ever been called, then this pointer
819 * will point to the "center" position of the buffer and all offsets
820 * (negative or positive) given out by the block pool alloc functions
821 * will be valid relative to this pointer.
822 *
823 * In particular, map == bo.map + center_offset
824 *
825 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
826 * since it will handle the softpin case as well, where this points to NULL.
827 */
828 void *map;
829 int fd;
830
831 /**
832 * Array of mmaps and gem handles owned by the block pool, reclaimed when
833 * the block pool is destroyed.
834 */
835 struct u_vector mmap_cleanups;
836
837 struct anv_block_state state;
838
839 struct anv_block_state back_state;
840 };
841
842 /* Block pools are backed by a fixed-size 1GB memfd */
843 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
844
845 /* The center of the block pool is also the middle of the memfd. This may
846 * change in the future if we decide differently for some reason.
847 */
848 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
849
850 static inline uint32_t
851 anv_block_pool_size(struct anv_block_pool *pool)
852 {
853 return pool->state.end + pool->back_state.end;
854 }
855
856 struct anv_state {
857 int32_t offset;
858 uint32_t alloc_size;
859 void *map;
860 uint32_t idx;
861 };
862
863 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
864
865 struct anv_fixed_size_state_pool {
866 union anv_free_list free_list;
867 struct anv_block_state block;
868 };
869
870 #define ANV_MIN_STATE_SIZE_LOG2 6
871 #define ANV_MAX_STATE_SIZE_LOG2 21
872
873 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
874
875 struct anv_free_entry {
876 uint32_t next;
877 struct anv_state state;
878 };
879
880 struct anv_state_table {
881 struct anv_device *device;
882 int fd;
883 struct anv_free_entry *map;
884 uint32_t size;
885 struct anv_block_state state;
886 struct u_vector cleanups;
887 };
888
889 struct anv_state_pool {
890 struct anv_block_pool block_pool;
891
892 /* Offset into the relevant state base address where the state pool starts
893 * allocating memory.
894 */
895 int32_t start_offset;
896
897 struct anv_state_table table;
898
899 /* The size of blocks which will be allocated from the block pool */
900 uint32_t block_size;
901
902 /** Free list for "back" allocations */
903 union anv_free_list back_alloc_free_list;
904
905 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
906 };
907
908 struct anv_state_reserved_pool {
909 struct anv_state_pool *pool;
910 union anv_free_list reserved_blocks;
911 uint32_t count;
912 };
913
914 struct anv_state_stream {
915 struct anv_state_pool *state_pool;
916
917 /* The size of blocks to allocate from the state pool */
918 uint32_t block_size;
919
920 /* Current block we're allocating from */
921 struct anv_state block;
922
923 /* Offset into the current block at which to allocate the next state */
924 uint32_t next;
925
926 /* List of all blocks allocated from this pool */
927 struct util_dynarray all_blocks;
928 };
929
930 /* The block_pool functions exported for testing only. The block pool should
931 * only be used via a state pool (see below).
932 */
933 VkResult anv_block_pool_init(struct anv_block_pool *pool,
934 struct anv_device *device,
935 uint64_t start_address,
936 uint32_t initial_size);
937 void anv_block_pool_finish(struct anv_block_pool *pool);
938 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
939 uint32_t block_size, uint32_t *padding);
940 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
941 uint32_t block_size);
942 void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset, uint32_t
943 size);
944
945 VkResult anv_state_pool_init(struct anv_state_pool *pool,
946 struct anv_device *device,
947 uint64_t base_address,
948 int32_t start_offset,
949 uint32_t block_size);
950 void anv_state_pool_finish(struct anv_state_pool *pool);
951 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
952 uint32_t state_size, uint32_t alignment);
953 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
954 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
955 void anv_state_stream_init(struct anv_state_stream *stream,
956 struct anv_state_pool *state_pool,
957 uint32_t block_size);
958 void anv_state_stream_finish(struct anv_state_stream *stream);
959 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
960 uint32_t size, uint32_t alignment);
961
962 void anv_state_reserved_pool_init(struct anv_state_reserved_pool *pool,
963 struct anv_state_pool *parent,
964 uint32_t count, uint32_t size,
965 uint32_t alignment);
966 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool *pool);
967 struct anv_state anv_state_reserved_pool_alloc(struct anv_state_reserved_pool *pool);
968 void anv_state_reserved_pool_free(struct anv_state_reserved_pool *pool,
969 struct anv_state state);
970
971 VkResult anv_state_table_init(struct anv_state_table *table,
972 struct anv_device *device,
973 uint32_t initial_entries);
974 void anv_state_table_finish(struct anv_state_table *table);
975 VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx,
976 uint32_t count);
977 void anv_free_list_push(union anv_free_list *list,
978 struct anv_state_table *table,
979 uint32_t idx, uint32_t count);
980 struct anv_state* anv_free_list_pop(union anv_free_list *list,
981 struct anv_state_table *table);
982
983
984 static inline struct anv_state *
985 anv_state_table_get(struct anv_state_table *table, uint32_t idx)
986 {
987 return &table->map[idx].state;
988 }
989 /**
990 * Implements a pool of re-usable BOs. The interface is identical to that
991 * of block_pool except that each block is its own BO.
992 */
993 struct anv_bo_pool {
994 struct anv_device *device;
995
996 struct util_sparse_array_free_list free_list[16];
997 };
998
999 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
1000 void anv_bo_pool_finish(struct anv_bo_pool *pool);
1001 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, uint32_t size,
1002 struct anv_bo **bo_out);
1003 void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
1004
1005 struct anv_scratch_pool {
1006 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
1007 struct anv_bo *bos[16][MESA_SHADER_STAGES];
1008 };
1009
1010 void anv_scratch_pool_init(struct anv_device *device,
1011 struct anv_scratch_pool *pool);
1012 void anv_scratch_pool_finish(struct anv_device *device,
1013 struct anv_scratch_pool *pool);
1014 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
1015 struct anv_scratch_pool *pool,
1016 gl_shader_stage stage,
1017 unsigned per_thread_scratch);
1018
1019 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1020 struct anv_bo_cache {
1021 struct util_sparse_array bo_map;
1022 pthread_mutex_t mutex;
1023 };
1024
1025 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
1026 void anv_bo_cache_finish(struct anv_bo_cache *cache);
1027
1028 struct anv_memory_type {
1029 /* Standard bits passed on to the client */
1030 VkMemoryPropertyFlags propertyFlags;
1031 uint32_t heapIndex;
1032 };
1033
1034 struct anv_memory_heap {
1035 /* Standard bits passed on to the client */
1036 VkDeviceSize size;
1037 VkMemoryHeapFlags flags;
1038
1039 /** Driver-internal book-keeping.
1040 *
1041 * Align it to 64 bits to make atomic operations faster on 32 bit platforms.
1042 */
1043 VkDeviceSize used __attribute__ ((aligned (8)));
1044 };
1045
1046 struct anv_physical_device {
1047 struct vk_object_base base;
1048
1049 /* Link in anv_instance::physical_devices */
1050 struct list_head link;
1051
1052 struct anv_instance * instance;
1053 bool no_hw;
1054 char path[20];
1055 const char * name;
1056 struct {
1057 uint16_t domain;
1058 uint8_t bus;
1059 uint8_t device;
1060 uint8_t function;
1061 } pci_info;
1062 struct gen_device_info info;
1063 /** Amount of "GPU memory" we want to advertise
1064 *
1065 * Clearly, this value is bogus since Intel is a UMA architecture. On
1066 * gen7 platforms, we are limited by GTT size unless we want to implement
1067 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1068 * practically unlimited. However, we will never report more than 3/4 of
1069 * the total system ram to try and avoid running out of RAM.
1070 */
1071 bool supports_48bit_addresses;
1072 struct brw_compiler * compiler;
1073 struct isl_device isl_dev;
1074 struct gen_perf_config * perf;
1075 int cmd_parser_version;
1076 bool has_softpin;
1077 bool has_exec_async;
1078 bool has_exec_capture;
1079 bool has_exec_fence;
1080 bool has_syncobj;
1081 bool has_syncobj_wait;
1082 bool has_syncobj_wait_available;
1083 bool has_context_priority;
1084 bool has_context_isolation;
1085 bool has_thread_submit;
1086 bool has_mem_available;
1087 bool has_mmap_offset;
1088 uint64_t gtt_size;
1089
1090 bool use_softpin;
1091 bool always_use_bindless;
1092 bool use_call_secondary;
1093
1094 /** True if we can access buffers using A64 messages */
1095 bool has_a64_buffer_access;
1096 /** True if we can use bindless access for images */
1097 bool has_bindless_images;
1098 /** True if we can use bindless access for samplers */
1099 bool has_bindless_samplers;
1100 /** True if we can use timeline semaphores through execbuf */
1101 bool has_exec_timeline;
1102
1103 /** True if we can read the GPU timestamp register
1104 *
1105 * When running in a virtual context, the timestamp register is unreadable
1106 * on Gen12+.
1107 */
1108 bool has_reg_timestamp;
1109
1110 /** True if this device has implicit AUX
1111 *
1112 * If true, CCS is handled as an implicit attachment to the BO rather than
1113 * as an explicitly bound surface.
1114 */
1115 bool has_implicit_ccs;
1116
1117 bool always_flush_cache;
1118
1119 struct anv_device_extension_table supported_extensions;
1120
1121 uint32_t eu_total;
1122 uint32_t subslice_total;
1123
1124 struct {
1125 uint32_t type_count;
1126 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
1127 uint32_t heap_count;
1128 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
1129 } memory;
1130
1131 uint8_t driver_build_sha1[20];
1132 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
1133 uint8_t driver_uuid[VK_UUID_SIZE];
1134 uint8_t device_uuid[VK_UUID_SIZE];
1135
1136 struct disk_cache * disk_cache;
1137
1138 struct wsi_device wsi_device;
1139 int local_fd;
1140 int master_fd;
1141 };
1142
1143 struct anv_app_info {
1144 const char* app_name;
1145 uint32_t app_version;
1146 const char* engine_name;
1147 uint32_t engine_version;
1148 uint32_t api_version;
1149 };
1150
1151 struct anv_instance {
1152 struct vk_object_base base;
1153
1154 VkAllocationCallbacks alloc;
1155
1156 struct anv_app_info app_info;
1157
1158 struct anv_instance_extension_table enabled_extensions;
1159 struct anv_instance_dispatch_table dispatch;
1160 struct anv_physical_device_dispatch_table physical_device_dispatch;
1161 struct anv_device_dispatch_table device_dispatch;
1162
1163 bool physical_devices_enumerated;
1164 struct list_head physical_devices;
1165
1166 bool pipeline_cache_enabled;
1167
1168 struct vk_debug_report_instance debug_report_callbacks;
1169
1170 struct driOptionCache dri_options;
1171 struct driOptionCache available_dri_options;
1172 };
1173
1174 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
1175 void anv_finish_wsi(struct anv_physical_device *physical_device);
1176
1177 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
1178 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
1179 const char *name);
1180
1181 struct anv_queue_submit {
1182 struct anv_cmd_buffer * cmd_buffer;
1183
1184 uint32_t fence_count;
1185 uint32_t fence_array_length;
1186 struct drm_i915_gem_exec_fence * fences;
1187 uint64_t * fence_values;
1188
1189 uint32_t temporary_semaphore_count;
1190 uint32_t temporary_semaphore_array_length;
1191 struct anv_semaphore_impl * temporary_semaphores;
1192
1193 /* Semaphores to be signaled with a SYNC_FD. */
1194 struct anv_semaphore ** sync_fd_semaphores;
1195 uint32_t sync_fd_semaphore_count;
1196 uint32_t sync_fd_semaphore_array_length;
1197
1198 /* Allocated only with non shareable timelines. */
1199 union {
1200 struct anv_timeline ** wait_timelines;
1201 uint32_t * wait_timeline_syncobjs;
1202 };
1203 uint32_t wait_timeline_count;
1204 uint32_t wait_timeline_array_length;
1205 uint64_t * wait_timeline_values;
1206
1207 struct anv_timeline ** signal_timelines;
1208 uint32_t signal_timeline_count;
1209 uint32_t signal_timeline_array_length;
1210 uint64_t * signal_timeline_values;
1211
1212 int in_fence;
1213 bool need_out_fence;
1214 int out_fence;
1215
1216 uint32_t fence_bo_count;
1217 uint32_t fence_bo_array_length;
1218 /* An array of struct anv_bo pointers with lower bit used as a flag to
1219 * signal we will wait on that BO (see anv_(un)pack_ptr).
1220 */
1221 uintptr_t * fence_bos;
1222
1223 int perf_query_pass;
1224
1225 const VkAllocationCallbacks * alloc;
1226 VkSystemAllocationScope alloc_scope;
1227
1228 struct anv_bo * simple_bo;
1229 uint32_t simple_bo_size;
1230
1231 struct list_head link;
1232 };
1233
1234 struct anv_queue {
1235 struct vk_object_base base;
1236
1237 struct anv_device * device;
1238
1239 VkDeviceQueueCreateFlags flags;
1240
1241 /* Set once from the device api calls. */
1242 bool lost_signaled;
1243
1244 /* Only set once atomically by the queue */
1245 int lost;
1246 int error_line;
1247 const char * error_file;
1248 char error_msg[80];
1249
1250 /*
1251 * This mutext protects the variables below.
1252 */
1253 pthread_mutex_t mutex;
1254
1255 pthread_t thread;
1256 pthread_cond_t cond;
1257
1258 /*
1259 * A list of struct anv_queue_submit to be submitted to i915.
1260 */
1261 struct list_head queued_submits;
1262
1263 /* Set to true to stop the submission thread */
1264 bool quit;
1265 };
1266
1267 struct anv_pipeline_cache {
1268 struct vk_object_base base;
1269 struct anv_device * device;
1270 pthread_mutex_t mutex;
1271
1272 struct hash_table * nir_cache;
1273
1274 struct hash_table * cache;
1275
1276 bool external_sync;
1277 };
1278
1279 struct nir_xfb_info;
1280 struct anv_pipeline_bind_map;
1281
1282 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
1283 struct anv_device *device,
1284 bool cache_enabled,
1285 bool external_sync);
1286 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
1287
1288 struct anv_shader_bin *
1289 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
1290 const void *key, uint32_t key_size);
1291 struct anv_shader_bin *
1292 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
1293 gl_shader_stage stage,
1294 const void *key_data, uint32_t key_size,
1295 const void *kernel_data, uint32_t kernel_size,
1296 const void *constant_data,
1297 uint32_t constant_data_size,
1298 const struct brw_stage_prog_data *prog_data,
1299 uint32_t prog_data_size,
1300 const struct brw_compile_stats *stats,
1301 uint32_t num_stats,
1302 const struct nir_xfb_info *xfb_info,
1303 const struct anv_pipeline_bind_map *bind_map);
1304
1305 struct anv_shader_bin *
1306 anv_device_search_for_kernel(struct anv_device *device,
1307 struct anv_pipeline_cache *cache,
1308 const void *key_data, uint32_t key_size,
1309 bool *user_cache_bit);
1310
1311 struct anv_shader_bin *
1312 anv_device_upload_kernel(struct anv_device *device,
1313 struct anv_pipeline_cache *cache,
1314 gl_shader_stage stage,
1315 const void *key_data, uint32_t key_size,
1316 const void *kernel_data, uint32_t kernel_size,
1317 const void *constant_data,
1318 uint32_t constant_data_size,
1319 const struct brw_stage_prog_data *prog_data,
1320 uint32_t prog_data_size,
1321 const struct brw_compile_stats *stats,
1322 uint32_t num_stats,
1323 const struct nir_xfb_info *xfb_info,
1324 const struct anv_pipeline_bind_map *bind_map);
1325
1326 struct nir_shader;
1327 struct nir_shader_compiler_options;
1328
1329 struct nir_shader *
1330 anv_device_search_for_nir(struct anv_device *device,
1331 struct anv_pipeline_cache *cache,
1332 const struct nir_shader_compiler_options *nir_options,
1333 unsigned char sha1_key[20],
1334 void *mem_ctx);
1335
1336 void
1337 anv_device_upload_nir(struct anv_device *device,
1338 struct anv_pipeline_cache *cache,
1339 const struct nir_shader *nir,
1340 unsigned char sha1_key[20]);
1341
1342 struct anv_address {
1343 struct anv_bo *bo;
1344 uint32_t offset;
1345 };
1346
1347 struct anv_device {
1348 struct vk_device vk;
1349
1350 struct anv_physical_device * physical;
1351 bool no_hw;
1352 struct gen_device_info info;
1353 struct isl_device isl_dev;
1354 int context_id;
1355 int fd;
1356 bool can_chain_batches;
1357 bool robust_buffer_access;
1358 bool has_thread_submit;
1359 struct anv_device_extension_table enabled_extensions;
1360 struct anv_device_dispatch_table dispatch;
1361
1362 pthread_mutex_t vma_mutex;
1363 struct util_vma_heap vma_lo;
1364 struct util_vma_heap vma_cva;
1365 struct util_vma_heap vma_hi;
1366
1367 /** List of all anv_device_memory objects */
1368 struct list_head memory_objects;
1369
1370 struct anv_bo_pool batch_bo_pool;
1371
1372 struct anv_bo_cache bo_cache;
1373
1374 struct anv_state_pool dynamic_state_pool;
1375 struct anv_state_pool instruction_state_pool;
1376 struct anv_state_pool binding_table_pool;
1377 struct anv_state_pool surface_state_pool;
1378
1379 struct anv_state_reserved_pool custom_border_colors;
1380
1381 /** BO used for various workarounds
1382 *
1383 * There are a number of workarounds on our hardware which require writing
1384 * data somewhere and it doesn't really matter where. For that, we use
1385 * this BO and just write to the first dword or so.
1386 *
1387 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1388 * For that, we use the high bytes (>= 1024) of the workaround BO.
1389 */
1390 struct anv_bo * workaround_bo;
1391 struct anv_address workaround_address;
1392
1393 struct anv_bo * trivial_batch_bo;
1394 struct anv_bo * hiz_clear_bo;
1395 struct anv_state null_surface_state;
1396
1397 struct anv_pipeline_cache default_pipeline_cache;
1398 struct blorp_context blorp;
1399
1400 struct anv_state border_colors;
1401
1402 struct anv_state slice_hash;
1403
1404 struct anv_queue queue;
1405
1406 struct anv_scratch_pool scratch_pool;
1407
1408 pthread_mutex_t mutex;
1409 pthread_cond_t queue_submit;
1410 int _lost;
1411 int lost_reported;
1412
1413 struct gen_batch_decode_ctx decoder_ctx;
1414 /*
1415 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1416 * the cmd_buffer's list.
1417 */
1418 struct anv_cmd_buffer *cmd_buffer_being_decoded;
1419
1420 int perf_fd; /* -1 if no opened */
1421 uint64_t perf_metric; /* 0 if unset */
1422
1423 struct gen_aux_map_context *aux_map_ctx;
1424
1425 struct gen_debug_block_frame *debug_frame_desc;
1426 };
1427
1428 static inline struct anv_instance *
1429 anv_device_instance_or_null(const struct anv_device *device)
1430 {
1431 return device ? device->physical->instance : NULL;
1432 }
1433
1434 static inline struct anv_state_pool *
1435 anv_binding_table_pool(struct anv_device *device)
1436 {
1437 if (device->physical->use_softpin)
1438 return &device->binding_table_pool;
1439 else
1440 return &device->surface_state_pool;
1441 }
1442
1443 static inline struct anv_state
1444 anv_binding_table_pool_alloc(struct anv_device *device) {
1445 if (device->physical->use_softpin)
1446 return anv_state_pool_alloc(&device->binding_table_pool,
1447 device->binding_table_pool.block_size, 0);
1448 else
1449 return anv_state_pool_alloc_back(&device->surface_state_pool);
1450 }
1451
1452 static inline void
1453 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1454 anv_state_pool_free(anv_binding_table_pool(device), state);
1455 }
1456
1457 static inline uint32_t
1458 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1459 {
1460 if (bo->is_external)
1461 return device->isl_dev.mocs.external;
1462 else
1463 return device->isl_dev.mocs.internal;
1464 }
1465
1466 void anv_device_init_blorp(struct anv_device *device);
1467 void anv_device_finish_blorp(struct anv_device *device);
1468
1469 void _anv_device_report_lost(struct anv_device *device);
1470 VkResult _anv_device_set_lost(struct anv_device *device,
1471 const char *file, int line,
1472 const char *msg, ...)
1473 anv_printflike(4, 5);
1474 VkResult _anv_queue_set_lost(struct anv_queue *queue,
1475 const char *file, int line,
1476 const char *msg, ...)
1477 anv_printflike(4, 5);
1478 #define anv_device_set_lost(dev, ...) \
1479 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1480 #define anv_queue_set_lost(queue, ...) \
1481 (queue)->device->has_thread_submit ? \
1482 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__) : \
1483 _anv_device_set_lost(queue->device, __FILE__, __LINE__, __VA_ARGS__)
1484
1485 static inline bool
1486 anv_device_is_lost(struct anv_device *device)
1487 {
1488 int lost = p_atomic_read(&device->_lost);
1489 if (unlikely(lost && !device->lost_reported))
1490 _anv_device_report_lost(device);
1491 return lost;
1492 }
1493
1494 VkResult anv_device_query_status(struct anv_device *device);
1495
1496
1497 enum anv_bo_alloc_flags {
1498 /** Specifies that the BO must have a 32-bit address
1499 *
1500 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1501 */
1502 ANV_BO_ALLOC_32BIT_ADDRESS = (1 << 0),
1503
1504 /** Specifies that the BO may be shared externally */
1505 ANV_BO_ALLOC_EXTERNAL = (1 << 1),
1506
1507 /** Specifies that the BO should be mapped */
1508 ANV_BO_ALLOC_MAPPED = (1 << 2),
1509
1510 /** Specifies that the BO should be snooped so we get coherency */
1511 ANV_BO_ALLOC_SNOOPED = (1 << 3),
1512
1513 /** Specifies that the BO should be captured in error states */
1514 ANV_BO_ALLOC_CAPTURE = (1 << 4),
1515
1516 /** Specifies that the BO will have an address assigned by the caller
1517 *
1518 * Such BOs do not exist in any VMA heap.
1519 */
1520 ANV_BO_ALLOC_FIXED_ADDRESS = (1 << 5),
1521
1522 /** Enables implicit synchronization on the BO
1523 *
1524 * This is the opposite of EXEC_OBJECT_ASYNC.
1525 */
1526 ANV_BO_ALLOC_IMPLICIT_SYNC = (1 << 6),
1527
1528 /** Enables implicit synchronization on the BO
1529 *
1530 * This is equivalent to EXEC_OBJECT_WRITE.
1531 */
1532 ANV_BO_ALLOC_IMPLICIT_WRITE = (1 << 7),
1533
1534 /** Has an address which is visible to the client */
1535 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS = (1 << 8),
1536
1537 /** This buffer has implicit CCS data attached to it */
1538 ANV_BO_ALLOC_IMPLICIT_CCS = (1 << 9),
1539 };
1540
1541 VkResult anv_device_alloc_bo(struct anv_device *device, uint64_t size,
1542 enum anv_bo_alloc_flags alloc_flags,
1543 uint64_t explicit_address,
1544 struct anv_bo **bo);
1545 VkResult anv_device_import_bo_from_host_ptr(struct anv_device *device,
1546 void *host_ptr, uint32_t size,
1547 enum anv_bo_alloc_flags alloc_flags,
1548 uint64_t client_address,
1549 struct anv_bo **bo_out);
1550 VkResult anv_device_import_bo(struct anv_device *device, int fd,
1551 enum anv_bo_alloc_flags alloc_flags,
1552 uint64_t client_address,
1553 struct anv_bo **bo);
1554 VkResult anv_device_export_bo(struct anv_device *device,
1555 struct anv_bo *bo, int *fd_out);
1556 void anv_device_release_bo(struct anv_device *device,
1557 struct anv_bo *bo);
1558
1559 static inline struct anv_bo *
1560 anv_device_lookup_bo(struct anv_device *device, uint32_t gem_handle)
1561 {
1562 return util_sparse_array_get(&device->bo_cache.bo_map, gem_handle);
1563 }
1564
1565 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1566 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1567 int64_t timeout);
1568
1569 VkResult anv_queue_init(struct anv_device *device, struct anv_queue *queue);
1570 void anv_queue_finish(struct anv_queue *queue);
1571
1572 VkResult anv_queue_execbuf_locked(struct anv_queue *queue, struct anv_queue_submit *submit);
1573 VkResult anv_queue_submit_simple_batch(struct anv_queue *queue,
1574 struct anv_batch *batch);
1575
1576 uint64_t anv_gettime_ns(void);
1577 uint64_t anv_get_absolute_timeout(uint64_t timeout);
1578
1579 void* anv_gem_mmap(struct anv_device *device,
1580 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1581 void anv_gem_munmap(struct anv_device *device, void *p, uint64_t size);
1582 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1583 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1584 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1585 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1586 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1587 int anv_gem_execbuffer(struct anv_device *device,
1588 struct drm_i915_gem_execbuffer2 *execbuf);
1589 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1590 uint32_t stride, uint32_t tiling);
1591 int anv_gem_create_context(struct anv_device *device);
1592 bool anv_gem_has_context_priority(int fd);
1593 int anv_gem_destroy_context(struct anv_device *device, int context);
1594 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1595 uint64_t value);
1596 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1597 uint64_t *value);
1598 int anv_gem_get_param(int fd, uint32_t param);
1599 uint64_t anv_gem_get_drm_cap(int fd, uint32_t capability);
1600 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1601 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1602 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1603 uint32_t *active, uint32_t *pending);
1604 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1605 int anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result);
1606 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1607 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1608 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1609 uint32_t read_domains, uint32_t write_domain);
1610 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1611 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1612 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1613 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1614 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1615 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1616 uint32_t handle);
1617 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1618 uint32_t handle, int fd);
1619 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1620 bool anv_gem_supports_syncobj_wait(int fd);
1621 int anv_gem_syncobj_wait(struct anv_device *device,
1622 const uint32_t *handles, uint32_t num_handles,
1623 int64_t abs_timeout_ns, bool wait_all);
1624 int anv_gem_syncobj_timeline_wait(struct anv_device *device,
1625 const uint32_t *handles, const uint64_t *points,
1626 uint32_t num_items, int64_t abs_timeout_ns,
1627 bool wait_all, bool wait_materialize);
1628 int anv_gem_syncobj_timeline_signal(struct anv_device *device,
1629 const uint32_t *handles, const uint64_t *points,
1630 uint32_t num_items);
1631 int anv_gem_syncobj_timeline_query(struct anv_device *device,
1632 const uint32_t *handles, uint64_t *points,
1633 uint32_t num_items);
1634
1635 uint64_t anv_vma_alloc(struct anv_device *device,
1636 uint64_t size, uint64_t align,
1637 enum anv_bo_alloc_flags alloc_flags,
1638 uint64_t client_address);
1639 void anv_vma_free(struct anv_device *device,
1640 uint64_t address, uint64_t size);
1641
1642 struct anv_reloc_list {
1643 uint32_t num_relocs;
1644 uint32_t array_length;
1645 struct drm_i915_gem_relocation_entry * relocs;
1646 struct anv_bo ** reloc_bos;
1647 uint32_t dep_words;
1648 BITSET_WORD * deps;
1649 };
1650
1651 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1652 const VkAllocationCallbacks *alloc);
1653 void anv_reloc_list_finish(struct anv_reloc_list *list,
1654 const VkAllocationCallbacks *alloc);
1655
1656 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1657 const VkAllocationCallbacks *alloc,
1658 uint32_t offset, struct anv_bo *target_bo,
1659 uint32_t delta, uint64_t *address_u64_out);
1660
1661 struct anv_batch_bo {
1662 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1663 struct list_head link;
1664
1665 struct anv_bo * bo;
1666
1667 /* Bytes actually consumed in this batch BO */
1668 uint32_t length;
1669
1670 struct anv_reloc_list relocs;
1671 };
1672
1673 struct anv_batch {
1674 const VkAllocationCallbacks * alloc;
1675
1676 struct anv_address start_addr;
1677
1678 void * start;
1679 void * end;
1680 void * next;
1681
1682 struct anv_reloc_list * relocs;
1683
1684 /* This callback is called (with the associated user data) in the event
1685 * that the batch runs out of space.
1686 */
1687 VkResult (*extend_cb)(struct anv_batch *, void *);
1688 void * user_data;
1689
1690 /**
1691 * Current error status of the command buffer. Used to track inconsistent
1692 * or incomplete command buffer states that are the consequence of run-time
1693 * errors such as out of memory scenarios. We want to track this in the
1694 * batch because the command buffer object is not visible to some parts
1695 * of the driver.
1696 */
1697 VkResult status;
1698 };
1699
1700 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1701 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1702 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1703 void *location, struct anv_bo *bo, uint32_t offset);
1704 struct anv_address anv_batch_address(struct anv_batch *batch, void *batch_location);
1705
1706 static inline void
1707 anv_batch_set_storage(struct anv_batch *batch, struct anv_address addr,
1708 void *map, size_t size)
1709 {
1710 batch->start_addr = addr;
1711 batch->next = batch->start = map;
1712 batch->end = map + size;
1713 }
1714
1715 static inline VkResult
1716 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1717 {
1718 assert(error != VK_SUCCESS);
1719 if (batch->status == VK_SUCCESS)
1720 batch->status = error;
1721 return batch->status;
1722 }
1723
1724 static inline bool
1725 anv_batch_has_error(struct anv_batch *batch)
1726 {
1727 return batch->status != VK_SUCCESS;
1728 }
1729
1730 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1731
1732 static inline bool
1733 anv_address_is_null(struct anv_address addr)
1734 {
1735 return addr.bo == NULL && addr.offset == 0;
1736 }
1737
1738 static inline uint64_t
1739 anv_address_physical(struct anv_address addr)
1740 {
1741 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1742 return gen_canonical_address(addr.bo->offset + addr.offset);
1743 else
1744 return gen_canonical_address(addr.offset);
1745 }
1746
1747 static inline struct anv_address
1748 anv_address_add(struct anv_address addr, uint64_t offset)
1749 {
1750 addr.offset += offset;
1751 return addr;
1752 }
1753
1754 static inline void
1755 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1756 {
1757 unsigned reloc_size = 0;
1758 if (device->info.gen >= 8) {
1759 reloc_size = sizeof(uint64_t);
1760 *(uint64_t *)p = gen_canonical_address(v);
1761 } else {
1762 reloc_size = sizeof(uint32_t);
1763 *(uint32_t *)p = v;
1764 }
1765
1766 if (flush && !device->info.has_llc)
1767 gen_flush_range(p, reloc_size);
1768 }
1769
1770 static inline uint64_t
1771 _anv_combine_address(struct anv_batch *batch, void *location,
1772 const struct anv_address address, uint32_t delta)
1773 {
1774 if (address.bo == NULL) {
1775 return address.offset + delta;
1776 } else {
1777 assert(batch->start <= location && location < batch->end);
1778
1779 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1780 }
1781 }
1782
1783 #define __gen_address_type struct anv_address
1784 #define __gen_user_data struct anv_batch
1785 #define __gen_combine_address _anv_combine_address
1786
1787 /* Wrapper macros needed to work around preprocessor argument issues. In
1788 * particular, arguments don't get pre-evaluated if they are concatenated.
1789 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1790 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1791 * We can work around this easily enough with these helpers.
1792 */
1793 #define __anv_cmd_length(cmd) cmd ## _length
1794 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1795 #define __anv_cmd_header(cmd) cmd ## _header
1796 #define __anv_cmd_pack(cmd) cmd ## _pack
1797 #define __anv_reg_num(reg) reg ## _num
1798
1799 #define anv_pack_struct(dst, struc, ...) do { \
1800 struct struc __template = { \
1801 __VA_ARGS__ \
1802 }; \
1803 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1804 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1805 } while (0)
1806
1807 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1808 void *__dst = anv_batch_emit_dwords(batch, n); \
1809 if (__dst) { \
1810 struct cmd __template = { \
1811 __anv_cmd_header(cmd), \
1812 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1813 __VA_ARGS__ \
1814 }; \
1815 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1816 } \
1817 __dst; \
1818 })
1819
1820 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1821 do { \
1822 uint32_t *dw; \
1823 \
1824 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1825 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1826 if (!dw) \
1827 break; \
1828 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1829 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1830 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1831 } while (0)
1832
1833 #define anv_batch_emit(batch, cmd, name) \
1834 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1835 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1836 __builtin_expect(_dst != NULL, 1); \
1837 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1838 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1839 _dst = NULL; \
1840 }))
1841
1842 /* #define __gen_get_batch_dwords anv_batch_emit_dwords */
1843 /* #define __gen_get_batch_address anv_batch_address */
1844 /* #define __gen_address_value anv_address_physical */
1845 /* #define __gen_address_offset anv_address_add */
1846
1847 struct anv_device_memory {
1848 struct vk_object_base base;
1849
1850 struct list_head link;
1851
1852 struct anv_bo * bo;
1853 struct anv_memory_type * type;
1854 VkDeviceSize map_size;
1855 void * map;
1856
1857 /* If set, we are holding reference to AHardwareBuffer
1858 * which we must release when memory is freed.
1859 */
1860 struct AHardwareBuffer * ahw;
1861
1862 /* If set, this memory comes from a host pointer. */
1863 void * host_ptr;
1864 };
1865
1866 /**
1867 * Header for Vertex URB Entry (VUE)
1868 */
1869 struct anv_vue_header {
1870 uint32_t Reserved;
1871 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1872 uint32_t ViewportIndex;
1873 float PointWidth;
1874 };
1875
1876 /** Struct representing a sampled image descriptor
1877 *
1878 * This descriptor layout is used for sampled images, bare sampler, and
1879 * combined image/sampler descriptors.
1880 */
1881 struct anv_sampled_image_descriptor {
1882 /** Bindless image handle
1883 *
1884 * This is expected to already be shifted such that the 20-bit
1885 * SURFACE_STATE table index is in the top 20 bits.
1886 */
1887 uint32_t image;
1888
1889 /** Bindless sampler handle
1890 *
1891 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1892 * to the dynamic state base address.
1893 */
1894 uint32_t sampler;
1895 };
1896
1897 struct anv_texture_swizzle_descriptor {
1898 /** Texture swizzle
1899 *
1900 * See also nir_intrinsic_channel_select_intel
1901 */
1902 uint8_t swizzle[4];
1903
1904 /** Unused padding to ensure the struct is a multiple of 64 bits */
1905 uint32_t _pad;
1906 };
1907
1908 /** Struct representing a storage image descriptor */
1909 struct anv_storage_image_descriptor {
1910 /** Bindless image handles
1911 *
1912 * These are expected to already be shifted such that the 20-bit
1913 * SURFACE_STATE table index is in the top 20 bits.
1914 */
1915 uint32_t read_write;
1916 uint32_t write_only;
1917 };
1918
1919 /** Struct representing a address/range descriptor
1920 *
1921 * The fields of this struct correspond directly to the data layout of
1922 * nir_address_format_64bit_bounded_global addresses. The last field is the
1923 * offset in the NIR address so it must be zero so that when you load the
1924 * descriptor you get a pointer to the start of the range.
1925 */
1926 struct anv_address_range_descriptor {
1927 uint64_t address;
1928 uint32_t range;
1929 uint32_t zero;
1930 };
1931
1932 enum anv_descriptor_data {
1933 /** The descriptor contains a BTI reference to a surface state */
1934 ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0),
1935 /** The descriptor contains a BTI reference to a sampler state */
1936 ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1),
1937 /** The descriptor contains an actual buffer view */
1938 ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2),
1939 /** The descriptor contains auxiliary image layout data */
1940 ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3),
1941 /** The descriptor contains auxiliary image layout data */
1942 ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4),
1943 /** anv_address_range_descriptor with a buffer address and range */
1944 ANV_DESCRIPTOR_ADDRESS_RANGE = (1 << 5),
1945 /** Bindless surface handle */
1946 ANV_DESCRIPTOR_SAMPLED_IMAGE = (1 << 6),
1947 /** Storage image handles */
1948 ANV_DESCRIPTOR_STORAGE_IMAGE = (1 << 7),
1949 /** Storage image handles */
1950 ANV_DESCRIPTOR_TEXTURE_SWIZZLE = (1 << 8),
1951 };
1952
1953 struct anv_descriptor_set_binding_layout {
1954 #ifndef NDEBUG
1955 /* The type of the descriptors in this binding */
1956 VkDescriptorType type;
1957 #endif
1958
1959 /* Flags provided when this binding was created */
1960 VkDescriptorBindingFlagsEXT flags;
1961
1962 /* Bitfield representing the type of data this descriptor contains */
1963 enum anv_descriptor_data data;
1964
1965 /* Maximum number of YCbCr texture/sampler planes */
1966 uint8_t max_plane_count;
1967
1968 /* Number of array elements in this binding (or size in bytes for inline
1969 * uniform data)
1970 */
1971 uint16_t array_size;
1972
1973 /* Index into the flattend descriptor set */
1974 uint16_t descriptor_index;
1975
1976 /* Index into the dynamic state array for a dynamic buffer */
1977 int16_t dynamic_offset_index;
1978
1979 /* Index into the descriptor set buffer views */
1980 int16_t buffer_view_index;
1981
1982 /* Offset into the descriptor buffer where this descriptor lives */
1983 uint32_t descriptor_offset;
1984
1985 /* Immutable samplers (or NULL if no immutable samplers) */
1986 struct anv_sampler **immutable_samplers;
1987 };
1988
1989 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout);
1990
1991 unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice,
1992 VkDescriptorType type);
1993
1994 bool anv_descriptor_supports_bindless(const struct anv_physical_device *pdevice,
1995 const struct anv_descriptor_set_binding_layout *binding,
1996 bool sampler);
1997
1998 bool anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice,
1999 const struct anv_descriptor_set_binding_layout *binding,
2000 bool sampler);
2001
2002 struct anv_descriptor_set_layout {
2003 struct vk_object_base base;
2004
2005 /* Descriptor set layouts can be destroyed at almost any time */
2006 uint32_t ref_cnt;
2007
2008 /* Number of bindings in this descriptor set */
2009 uint16_t binding_count;
2010
2011 /* Total size of the descriptor set with room for all array entries */
2012 uint16_t size;
2013
2014 /* Shader stages affected by this descriptor set */
2015 uint16_t shader_stages;
2016
2017 /* Number of buffer views in this descriptor set */
2018 uint16_t buffer_view_count;
2019
2020 /* Number of dynamic offsets used by this descriptor set */
2021 uint16_t dynamic_offset_count;
2022
2023 /* For each dynamic buffer, which VkShaderStageFlagBits stages are using
2024 * this buffer
2025 */
2026 VkShaderStageFlags dynamic_offset_stages[MAX_DYNAMIC_BUFFERS];
2027
2028 /* Size of the descriptor buffer for this descriptor set */
2029 uint32_t descriptor_buffer_size;
2030
2031 /* Bindings in this descriptor set */
2032 struct anv_descriptor_set_binding_layout binding[0];
2033 };
2034
2035 void anv_descriptor_set_layout_destroy(struct anv_device *device,
2036 struct anv_descriptor_set_layout *layout);
2037
2038 static inline void
2039 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
2040 {
2041 assert(layout && layout->ref_cnt >= 1);
2042 p_atomic_inc(&layout->ref_cnt);
2043 }
2044
2045 static inline void
2046 anv_descriptor_set_layout_unref(struct anv_device *device,
2047 struct anv_descriptor_set_layout *layout)
2048 {
2049 assert(layout && layout->ref_cnt >= 1);
2050 if (p_atomic_dec_zero(&layout->ref_cnt))
2051 anv_descriptor_set_layout_destroy(device, layout);
2052 }
2053
2054 struct anv_descriptor {
2055 VkDescriptorType type;
2056
2057 union {
2058 struct {
2059 VkImageLayout layout;
2060 struct anv_image_view *image_view;
2061 struct anv_sampler *sampler;
2062 };
2063
2064 struct {
2065 struct anv_buffer *buffer;
2066 uint64_t offset;
2067 uint64_t range;
2068 };
2069
2070 struct anv_buffer_view *buffer_view;
2071 };
2072 };
2073
2074 struct anv_descriptor_set {
2075 struct vk_object_base base;
2076
2077 struct anv_descriptor_pool *pool;
2078 struct anv_descriptor_set_layout *layout;
2079
2080 /* Amount of space occupied in the the pool by this descriptor set. It can
2081 * be larger than the size of the descriptor set.
2082 */
2083 uint32_t size;
2084
2085 /* State relative to anv_descriptor_pool::bo */
2086 struct anv_state desc_mem;
2087 /* Surface state for the descriptor buffer */
2088 struct anv_state desc_surface_state;
2089
2090 uint32_t buffer_view_count;
2091 struct anv_buffer_view *buffer_views;
2092
2093 /* Link to descriptor pool's desc_sets list . */
2094 struct list_head pool_link;
2095
2096 struct anv_descriptor descriptors[0];
2097 };
2098
2099 struct anv_buffer_view {
2100 struct vk_object_base base;
2101
2102 enum isl_format format; /**< VkBufferViewCreateInfo::format */
2103 uint64_t range; /**< VkBufferViewCreateInfo::range */
2104
2105 struct anv_address address;
2106
2107 struct anv_state surface_state;
2108 struct anv_state storage_surface_state;
2109 struct anv_state writeonly_storage_surface_state;
2110
2111 struct brw_image_param storage_image_param;
2112 };
2113
2114 struct anv_push_descriptor_set {
2115 struct anv_descriptor_set set;
2116
2117 /* Put this field right behind anv_descriptor_set so it fills up the
2118 * descriptors[0] field. */
2119 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
2120
2121 /** True if the descriptor set buffer has been referenced by a draw or
2122 * dispatch command.
2123 */
2124 bool set_used_on_gpu;
2125
2126 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
2127 };
2128
2129 struct anv_descriptor_pool {
2130 struct vk_object_base base;
2131
2132 uint32_t size;
2133 uint32_t next;
2134 uint32_t free_list;
2135
2136 struct anv_bo *bo;
2137 struct util_vma_heap bo_heap;
2138
2139 struct anv_state_stream surface_state_stream;
2140 void *surface_state_free_list;
2141
2142 struct list_head desc_sets;
2143
2144 char data[0];
2145 };
2146
2147 enum anv_descriptor_template_entry_type {
2148 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
2149 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
2150 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2151 };
2152
2153 struct anv_descriptor_template_entry {
2154 /* The type of descriptor in this entry */
2155 VkDescriptorType type;
2156
2157 /* Binding in the descriptor set */
2158 uint32_t binding;
2159
2160 /* Offset at which to write into the descriptor set binding */
2161 uint32_t array_element;
2162
2163 /* Number of elements to write into the descriptor set binding */
2164 uint32_t array_count;
2165
2166 /* Offset into the user provided data */
2167 size_t offset;
2168
2169 /* Stride between elements into the user provided data */
2170 size_t stride;
2171 };
2172
2173 struct anv_descriptor_update_template {
2174 struct vk_object_base base;
2175
2176 VkPipelineBindPoint bind_point;
2177
2178 /* The descriptor set this template corresponds to. This value is only
2179 * valid if the template was created with the templateType
2180 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2181 */
2182 uint8_t set;
2183
2184 /* Number of entries in this template */
2185 uint32_t entry_count;
2186
2187 /* Entries of the template */
2188 struct anv_descriptor_template_entry entries[0];
2189 };
2190
2191 size_t
2192 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
2193
2194 void
2195 anv_descriptor_set_write_image_view(struct anv_device *device,
2196 struct anv_descriptor_set *set,
2197 const VkDescriptorImageInfo * const info,
2198 VkDescriptorType type,
2199 uint32_t binding,
2200 uint32_t element);
2201
2202 void
2203 anv_descriptor_set_write_buffer_view(struct anv_device *device,
2204 struct anv_descriptor_set *set,
2205 VkDescriptorType type,
2206 struct anv_buffer_view *buffer_view,
2207 uint32_t binding,
2208 uint32_t element);
2209
2210 void
2211 anv_descriptor_set_write_buffer(struct anv_device *device,
2212 struct anv_descriptor_set *set,
2213 struct anv_state_stream *alloc_stream,
2214 VkDescriptorType type,
2215 struct anv_buffer *buffer,
2216 uint32_t binding,
2217 uint32_t element,
2218 VkDeviceSize offset,
2219 VkDeviceSize range);
2220 void
2221 anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
2222 struct anv_descriptor_set *set,
2223 uint32_t binding,
2224 const void *data,
2225 size_t offset,
2226 size_t size);
2227
2228 void
2229 anv_descriptor_set_write_template(struct anv_device *device,
2230 struct anv_descriptor_set *set,
2231 struct anv_state_stream *alloc_stream,
2232 const struct anv_descriptor_update_template *template,
2233 const void *data);
2234
2235 VkResult
2236 anv_descriptor_set_create(struct anv_device *device,
2237 struct anv_descriptor_pool *pool,
2238 struct anv_descriptor_set_layout *layout,
2239 struct anv_descriptor_set **out_set);
2240
2241 void
2242 anv_descriptor_set_destroy(struct anv_device *device,
2243 struct anv_descriptor_pool *pool,
2244 struct anv_descriptor_set *set);
2245
2246 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2247 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2248 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2249 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2250 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2251 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2252
2253 struct anv_pipeline_binding {
2254 /** Index in the descriptor set
2255 *
2256 * This is a flattened index; the descriptor set layout is already taken
2257 * into account.
2258 */
2259 uint32_t index;
2260
2261 /** The descriptor set this surface corresponds to.
2262 *
2263 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2264 * binding is not a normal descriptor set but something else.
2265 */
2266 uint8_t set;
2267
2268 union {
2269 /** Plane in the binding index for images */
2270 uint8_t plane;
2271
2272 /** Input attachment index (relative to the subpass) */
2273 uint8_t input_attachment_index;
2274
2275 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2276 uint8_t dynamic_offset_index;
2277 };
2278
2279 /** For a storage image, whether it is write-only */
2280 uint8_t write_only;
2281
2282 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2283 * assuming POD zero-initialization.
2284 */
2285 uint8_t pad;
2286 };
2287
2288 struct anv_push_range {
2289 /** Index in the descriptor set */
2290 uint32_t index;
2291
2292 /** Descriptor set index */
2293 uint8_t set;
2294
2295 /** Dynamic offset index (for dynamic UBOs) */
2296 uint8_t dynamic_offset_index;
2297
2298 /** Start offset in units of 32B */
2299 uint8_t start;
2300
2301 /** Range in units of 32B */
2302 uint8_t length;
2303 };
2304
2305 struct anv_pipeline_layout {
2306 struct vk_object_base base;
2307
2308 struct {
2309 struct anv_descriptor_set_layout *layout;
2310 uint32_t dynamic_offset_start;
2311 } set[MAX_SETS];
2312
2313 uint32_t num_sets;
2314
2315 unsigned char sha1[20];
2316 };
2317
2318 struct anv_buffer {
2319 struct vk_object_base base;
2320
2321 struct anv_device * device;
2322 VkDeviceSize size;
2323
2324 VkBufferUsageFlags usage;
2325
2326 /* Set when bound */
2327 struct anv_address address;
2328 };
2329
2330 static inline uint64_t
2331 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
2332 {
2333 assert(offset <= buffer->size);
2334 if (range == VK_WHOLE_SIZE) {
2335 return buffer->size - offset;
2336 } else {
2337 assert(range + offset >= range);
2338 assert(range + offset <= buffer->size);
2339 return range;
2340 }
2341 }
2342
2343 enum anv_cmd_dirty_bits {
2344 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2345 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2346 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2347 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2348 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2349 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2350 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2351 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2352 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2353 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
2354 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
2355 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
2356 ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
2357 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2358 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 14, /* VK_DYNAMIC_STATE_CULL_MODE_EXT */
2359 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 15, /* VK_DYNAMIC_STATE_FRONT_FACE_EXT */
2360 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 16, /* VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT */
2361 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 17, /* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT */
2362 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 18, /* VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT */
2363 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 19, /* VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT */
2364 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 20, /* VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT */
2365 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 21, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT */
2366 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 22, /* VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT */
2367 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 23, /* VK_DYNAMIC_STATE_STENCIL_OP_EXT */
2368 };
2369 typedef uint32_t anv_cmd_dirty_mask_t;
2370
2371 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2372 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2373 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2374 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2375 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2376 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2377 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2378 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2379 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2380 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2381 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE | \
2382 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE | \
2383 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE | \
2384 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | \
2385 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE | \
2386 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | \
2387 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE | \
2388 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | \
2389 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE | \
2390 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE | \
2391 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2392
2393 static inline enum anv_cmd_dirty_bits
2394 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
2395 {
2396 switch (vk_state) {
2397 case VK_DYNAMIC_STATE_VIEWPORT:
2398 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
2399 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2400 case VK_DYNAMIC_STATE_SCISSOR:
2401 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
2402 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
2403 case VK_DYNAMIC_STATE_LINE_WIDTH:
2404 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2405 case VK_DYNAMIC_STATE_DEPTH_BIAS:
2406 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2407 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
2408 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2409 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
2410 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2411 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
2412 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2413 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
2414 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2415 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2416 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2417 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
2418 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
2419 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
2420 return ANV_CMD_DIRTY_DYNAMIC_CULL_MODE;
2421 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
2422 return ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
2423 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
2424 return ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
2425 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
2426 return ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
2427 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
2428 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
2429 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
2430 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
2431 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
2432 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
2433 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
2434 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
2435 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
2436 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
2437 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
2438 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
2439 default:
2440 assert(!"Unsupported dynamic state");
2441 return 0;
2442 }
2443 }
2444
2445
2446 enum anv_pipe_bits {
2447 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
2448 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
2449 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
2450 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
2451 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
2452 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
2453 ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
2454 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
2455 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
2456 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
2457 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
2458 ANV_PIPE_CS_STALL_BIT = (1 << 20),
2459 ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
2460
2461 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2462 * a flush has happened but not a CS stall. The next time we do any sort
2463 * of invalidation we need to insert a CS stall at that time. Otherwise,
2464 * we would have to CS stall on every flush which could be bad.
2465 */
2466 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT = (1 << 22),
2467
2468 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2469 * target operations related to transfer commands with VkBuffer as
2470 * destination are ongoing. Some operations like copies on the command
2471 * streamer might need to be aware of this to trigger the appropriate stall
2472 * before they can proceed with the copy.
2473 */
2474 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 23),
2475
2476 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2477 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2478 * done by writing the AUX-TT register.
2479 */
2480 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 24),
2481
2482 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2483 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2484 * implement a workaround for Gen9.
2485 */
2486 ANV_PIPE_POST_SYNC_BIT = (1 << 25),
2487 };
2488
2489 #define ANV_PIPE_FLUSH_BITS ( \
2490 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2491 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2492 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2493 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2494
2495 #define ANV_PIPE_STALL_BITS ( \
2496 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2497 ANV_PIPE_DEPTH_STALL_BIT | \
2498 ANV_PIPE_CS_STALL_BIT)
2499
2500 #define ANV_PIPE_INVALIDATE_BITS ( \
2501 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2502 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2503 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2504 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2505 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2506 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2507 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2508
2509 static inline enum anv_pipe_bits
2510 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
2511 {
2512 enum anv_pipe_bits pipe_bits = 0;
2513
2514 unsigned b;
2515 for_each_bit(b, flags) {
2516 switch ((VkAccessFlagBits)(1 << b)) {
2517 case VK_ACCESS_SHADER_WRITE_BIT:
2518 /* We're transitioning a buffer that was previously used as write
2519 * destination through the data port. To make its content available
2520 * to future operations, flush the data cache.
2521 */
2522 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2523 break;
2524 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2525 /* We're transitioning a buffer that was previously used as render
2526 * target. To make its content available to future operations, flush
2527 * the render target cache.
2528 */
2529 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2530 break;
2531 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2532 /* We're transitioning a buffer that was previously used as depth
2533 * buffer. To make its content available to future operations, flush
2534 * the depth cache.
2535 */
2536 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2537 break;
2538 case VK_ACCESS_TRANSFER_WRITE_BIT:
2539 /* We're transitioning a buffer that was previously used as a
2540 * transfer write destination. Generic write operations include color
2541 * & depth operations as well as buffer operations like :
2542 * - vkCmdClearColorImage()
2543 * - vkCmdClearDepthStencilImage()
2544 * - vkCmdBlitImage()
2545 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2546 *
2547 * Most of these operations are implemented using Blorp which writes
2548 * through the render target, so flush that cache to make it visible
2549 * to future operations. And for depth related operations we also
2550 * need to flush the depth cache.
2551 */
2552 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2553 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2554 break;
2555 case VK_ACCESS_MEMORY_WRITE_BIT:
2556 /* We're transitioning a buffer for generic write operations. Flush
2557 * all the caches.
2558 */
2559 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2560 break;
2561 default:
2562 break; /* Nothing to do */
2563 }
2564 }
2565
2566 return pipe_bits;
2567 }
2568
2569 static inline enum anv_pipe_bits
2570 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
2571 {
2572 enum anv_pipe_bits pipe_bits = 0;
2573
2574 unsigned b;
2575 for_each_bit(b, flags) {
2576 switch ((VkAccessFlagBits)(1 << b)) {
2577 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2578 /* Indirect draw commands take a buffer as input that we're going to
2579 * read from the command streamer to load some of the HW registers
2580 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2581 * command streamer stall so that all the cache flushes have
2582 * completed before the command streamer loads from memory.
2583 */
2584 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2585 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2586 * through a vertex buffer, so invalidate that cache.
2587 */
2588 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2589 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2590 * UBO from the buffer, so we need to invalidate constant cache.
2591 */
2592 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2593 break;
2594 case VK_ACCESS_INDEX_READ_BIT:
2595 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2596 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2597 * commands, so we invalidate the VF cache to make sure there is no
2598 * stale data when we start rendering.
2599 */
2600 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2601 break;
2602 case VK_ACCESS_UNIFORM_READ_BIT:
2603 /* We transitioning a buffer to be used as uniform data. Because
2604 * uniform is accessed through the data port & sampler, we need to
2605 * invalidate the texture cache (sampler) & constant cache (data
2606 * port) to avoid stale data.
2607 */
2608 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2609 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2610 break;
2611 case VK_ACCESS_SHADER_READ_BIT:
2612 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2613 case VK_ACCESS_TRANSFER_READ_BIT:
2614 /* Transitioning a buffer to be read through the sampler, so
2615 * invalidate the texture cache, we don't want any stale data.
2616 */
2617 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2618 break;
2619 case VK_ACCESS_MEMORY_READ_BIT:
2620 /* Transitioning a buffer for generic read, invalidate all the
2621 * caches.
2622 */
2623 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
2624 break;
2625 case VK_ACCESS_MEMORY_WRITE_BIT:
2626 /* Generic write, make sure all previously written things land in
2627 * memory.
2628 */
2629 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2630 break;
2631 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
2632 /* Transitioning a buffer for conditional rendering. We'll load the
2633 * content of this buffer into HW registers using the command
2634 * streamer, so we need to stall the command streamer to make sure
2635 * any in-flight flush operations have completed.
2636 */
2637 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2638 break;
2639 default:
2640 break; /* Nothing to do */
2641 }
2642 }
2643
2644 return pipe_bits;
2645 }
2646
2647 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2648 VK_IMAGE_ASPECT_COLOR_BIT | \
2649 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2650 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2651 VK_IMAGE_ASPECT_PLANE_2_BIT)
2652 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2653 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2654 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2655 VK_IMAGE_ASPECT_PLANE_2_BIT)
2656
2657 struct anv_vertex_binding {
2658 struct anv_buffer * buffer;
2659 VkDeviceSize offset;
2660 VkDeviceSize stride;
2661 VkDeviceSize size;
2662 };
2663
2664 struct anv_xfb_binding {
2665 struct anv_buffer * buffer;
2666 VkDeviceSize offset;
2667 VkDeviceSize size;
2668 };
2669
2670 struct anv_push_constants {
2671 /** Push constant data provided by the client through vkPushConstants */
2672 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
2673
2674 /** Dynamic offsets for dynamic UBOs and SSBOs */
2675 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2676
2677 /* Robust access pushed registers. */
2678 uint64_t push_reg_mask[MESA_SHADER_STAGES];
2679
2680 /** Pad out to a multiple of 32 bytes */
2681 uint32_t pad[2];
2682
2683 struct {
2684 /** Base workgroup ID
2685 *
2686 * Used for vkCmdDispatchBase.
2687 */
2688 uint32_t base_work_group_id[3];
2689
2690 /** Subgroup ID
2691 *
2692 * This is never set by software but is implicitly filled out when
2693 * uploading the push constants for compute shaders.
2694 */
2695 uint32_t subgroup_id;
2696 } cs;
2697 };
2698
2699 struct anv_dynamic_state {
2700 struct {
2701 uint32_t count;
2702 VkViewport viewports[MAX_VIEWPORTS];
2703 } viewport;
2704
2705 struct {
2706 uint32_t count;
2707 VkRect2D scissors[MAX_SCISSORS];
2708 } scissor;
2709
2710 float line_width;
2711
2712 struct {
2713 float bias;
2714 float clamp;
2715 float slope;
2716 } depth_bias;
2717
2718 float blend_constants[4];
2719
2720 struct {
2721 float min;
2722 float max;
2723 } depth_bounds;
2724
2725 struct {
2726 uint32_t front;
2727 uint32_t back;
2728 } stencil_compare_mask;
2729
2730 struct {
2731 uint32_t front;
2732 uint32_t back;
2733 } stencil_write_mask;
2734
2735 struct {
2736 uint32_t front;
2737 uint32_t back;
2738 } stencil_reference;
2739
2740 struct {
2741 struct {
2742 VkStencilOp fail_op;
2743 VkStencilOp pass_op;
2744 VkStencilOp depth_fail_op;
2745 VkCompareOp compare_op;
2746 } front;
2747 struct {
2748 VkStencilOp fail_op;
2749 VkStencilOp pass_op;
2750 VkStencilOp depth_fail_op;
2751 VkCompareOp compare_op;
2752 } back;
2753 } stencil_op;
2754
2755 struct {
2756 uint32_t factor;
2757 uint16_t pattern;
2758 } line_stipple;
2759
2760 VkCullModeFlags cull_mode;
2761 VkFrontFace front_face;
2762 VkPrimitiveTopology primitive_topology;
2763 bool depth_test_enable;
2764 bool depth_write_enable;
2765 VkCompareOp depth_compare_op;
2766 bool depth_bounds_test_enable;
2767 bool stencil_test_enable;
2768 bool dyn_vbo_stride;
2769 bool dyn_vbo_size;
2770 };
2771
2772 extern const struct anv_dynamic_state default_dynamic_state;
2773
2774 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state *dest,
2775 const struct anv_dynamic_state *src,
2776 uint32_t copy_mask);
2777
2778 struct anv_surface_state {
2779 struct anv_state state;
2780 /** Address of the surface referred to by this state
2781 *
2782 * This address is relative to the start of the BO.
2783 */
2784 struct anv_address address;
2785 /* Address of the aux surface, if any
2786 *
2787 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2788 *
2789 * With the exception of gen8, the bottom 12 bits of this address' offset
2790 * include extra aux information.
2791 */
2792 struct anv_address aux_address;
2793 /* Address of the clear color, if any
2794 *
2795 * This address is relative to the start of the BO.
2796 */
2797 struct anv_address clear_address;
2798 };
2799
2800 /**
2801 * Attachment state when recording a renderpass instance.
2802 *
2803 * The clear value is valid only if there exists a pending clear.
2804 */
2805 struct anv_attachment_state {
2806 enum isl_aux_usage aux_usage;
2807 struct anv_surface_state color;
2808 struct anv_surface_state input;
2809
2810 VkImageLayout current_layout;
2811 VkImageLayout current_stencil_layout;
2812 VkImageAspectFlags pending_clear_aspects;
2813 VkImageAspectFlags pending_load_aspects;
2814 bool fast_clear;
2815 VkClearValue clear_value;
2816
2817 /* When multiview is active, attachments with a renderpass clear
2818 * operation have their respective layers cleared on the first
2819 * subpass that uses them, and only in that subpass. We keep track
2820 * of this using a bitfield to indicate which layers of an attachment
2821 * have not been cleared yet when multiview is active.
2822 */
2823 uint32_t pending_clear_views;
2824 struct anv_image_view * image_view;
2825 };
2826
2827 /** State tracking for vertex buffer flushes
2828 *
2829 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2830 * addresses. If you happen to have two vertex buffers which get placed
2831 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2832 * collisions. In order to solve this problem, we track vertex address ranges
2833 * which are live in the cache and invalidate the cache if one ever exceeds 32
2834 * bits.
2835 */
2836 struct anv_vb_cache_range {
2837 /* Virtual address at which the live vertex buffer cache range starts for
2838 * this vertex buffer index.
2839 */
2840 uint64_t start;
2841
2842 /* Virtual address of the byte after where vertex buffer cache range ends.
2843 * This is exclusive such that end - start is the size of the range.
2844 */
2845 uint64_t end;
2846 };
2847
2848 /** State tracking for particular pipeline bind point
2849 *
2850 * This struct is the base struct for anv_cmd_graphics_state and
2851 * anv_cmd_compute_state. These are used to track state which is bound to a
2852 * particular type of pipeline. Generic state that applies per-stage such as
2853 * binding table offsets and push constants is tracked generically with a
2854 * per-stage array in anv_cmd_state.
2855 */
2856 struct anv_cmd_pipeline_state {
2857 struct anv_descriptor_set *descriptors[MAX_SETS];
2858 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2859
2860 struct anv_push_constants push_constants;
2861
2862 /* Push constant state allocated when flushing push constants. */
2863 struct anv_state push_constants_state;
2864 };
2865
2866 /** State tracking for graphics pipeline
2867 *
2868 * This has anv_cmd_pipeline_state as a base struct to track things which get
2869 * bound to a graphics pipeline. Along with general pipeline bind point state
2870 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2871 * state which is graphics-specific.
2872 */
2873 struct anv_cmd_graphics_state {
2874 struct anv_cmd_pipeline_state base;
2875
2876 struct anv_graphics_pipeline *pipeline;
2877
2878 anv_cmd_dirty_mask_t dirty;
2879 uint32_t vb_dirty;
2880
2881 struct anv_vb_cache_range ib_bound_range;
2882 struct anv_vb_cache_range ib_dirty_range;
2883 struct anv_vb_cache_range vb_bound_ranges[33];
2884 struct anv_vb_cache_range vb_dirty_ranges[33];
2885
2886 VkShaderStageFlags push_constant_stages;
2887
2888 struct anv_dynamic_state dynamic;
2889
2890 uint32_t primitive_topology;
2891
2892 struct {
2893 struct anv_buffer *index_buffer;
2894 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2895 uint32_t index_offset;
2896 } gen7;
2897 };
2898
2899 /** State tracking for compute pipeline
2900 *
2901 * This has anv_cmd_pipeline_state as a base struct to track things which get
2902 * bound to a compute pipeline. Along with general pipeline bind point state
2903 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2904 * state which is compute-specific.
2905 */
2906 struct anv_cmd_compute_state {
2907 struct anv_cmd_pipeline_state base;
2908
2909 struct anv_compute_pipeline *pipeline;
2910
2911 bool pipeline_dirty;
2912
2913 struct anv_address num_workgroups;
2914 };
2915
2916 /** State required while building cmd buffer */
2917 struct anv_cmd_state {
2918 /* PIPELINE_SELECT.PipelineSelection */
2919 uint32_t current_pipeline;
2920 const struct gen_l3_config * current_l3_config;
2921 uint32_t last_aux_map_state;
2922
2923 struct anv_cmd_graphics_state gfx;
2924 struct anv_cmd_compute_state compute;
2925
2926 enum anv_pipe_bits pending_pipe_bits;
2927 VkShaderStageFlags descriptors_dirty;
2928 VkShaderStageFlags push_constants_dirty;
2929
2930 struct anv_framebuffer * framebuffer;
2931 struct anv_render_pass * pass;
2932 struct anv_subpass * subpass;
2933 VkRect2D render_area;
2934 uint32_t restart_index;
2935 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2936 bool xfb_enabled;
2937 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
2938 struct anv_state binding_tables[MESA_SHADER_STAGES];
2939 struct anv_state samplers[MESA_SHADER_STAGES];
2940
2941 unsigned char sampler_sha1s[MESA_SHADER_STAGES][20];
2942 unsigned char surface_sha1s[MESA_SHADER_STAGES][20];
2943 unsigned char push_sha1s[MESA_SHADER_STAGES][20];
2944
2945 /**
2946 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2947 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2948 * and before invoking the secondary in ExecuteCommands.
2949 */
2950 bool pma_fix_enabled;
2951
2952 /**
2953 * Whether or not we know for certain that HiZ is enabled for the current
2954 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2955 * enabled or not, this will be false.
2956 */
2957 bool hiz_enabled;
2958
2959 bool conditional_render_enabled;
2960
2961 /**
2962 * Last rendering scale argument provided to
2963 * genX(cmd_buffer_emit_hashing_mode)().
2964 */
2965 unsigned current_hash_scale;
2966
2967 /**
2968 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2969 * valid only when recording a render pass instance.
2970 */
2971 struct anv_attachment_state * attachments;
2972
2973 /**
2974 * Surface states for color render targets. These are stored in a single
2975 * flat array. For depth-stencil attachments, the surface state is simply
2976 * left blank.
2977 */
2978 struct anv_state attachment_states;
2979
2980 /**
2981 * A null surface state of the right size to match the framebuffer. This
2982 * is one of the states in attachment_states.
2983 */
2984 struct anv_state null_surface_state;
2985 };
2986
2987 struct anv_cmd_pool {
2988 struct vk_object_base base;
2989 VkAllocationCallbacks alloc;
2990 struct list_head cmd_buffers;
2991 };
2992
2993 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2994
2995 enum anv_cmd_buffer_exec_mode {
2996 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2997 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2998 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2999 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
3000 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
3001 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN,
3002 };
3003
3004 struct anv_cmd_buffer {
3005 struct vk_object_base base;
3006
3007 struct anv_device * device;
3008
3009 struct anv_cmd_pool * pool;
3010 struct list_head pool_link;
3011
3012 struct anv_batch batch;
3013
3014 /* Fields required for the actual chain of anv_batch_bo's.
3015 *
3016 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
3017 */
3018 struct list_head batch_bos;
3019 enum anv_cmd_buffer_exec_mode exec_mode;
3020
3021 /* A vector of anv_batch_bo pointers for every batch or surface buffer
3022 * referenced by this command buffer
3023 *
3024 * initialized by anv_cmd_buffer_init_batch_bo_chain()
3025 */
3026 struct u_vector seen_bbos;
3027
3028 /* A vector of int32_t's for every block of binding tables.
3029 *
3030 * initialized by anv_cmd_buffer_init_batch_bo_chain()
3031 */
3032 struct u_vector bt_block_states;
3033 struct anv_state bt_next;
3034
3035 struct anv_reloc_list surface_relocs;
3036 /** Last seen surface state block pool center bo offset */
3037 uint32_t last_ss_pool_center;
3038
3039 /* Serial for tracking buffer completion */
3040 uint32_t serial;
3041
3042 /* Stream objects for storing temporary data */
3043 struct anv_state_stream surface_state_stream;
3044 struct anv_state_stream dynamic_state_stream;
3045
3046 VkCommandBufferUsageFlags usage_flags;
3047 VkCommandBufferLevel level;
3048
3049 struct anv_query_pool *perf_query_pool;
3050
3051 struct anv_cmd_state state;
3052
3053 struct anv_address return_addr;
3054
3055 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
3056 uint64_t intel_perf_marker;
3057 };
3058
3059 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3060 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3061 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3062 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
3063 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
3064 struct anv_cmd_buffer *secondary);
3065 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
3066 VkResult anv_cmd_buffer_execbuf(struct anv_queue *queue,
3067 struct anv_cmd_buffer *cmd_buffer,
3068 const VkSemaphore *in_semaphores,
3069 const uint64_t *in_wait_values,
3070 uint32_t num_in_semaphores,
3071 const VkSemaphore *out_semaphores,
3072 const uint64_t *out_signal_values,
3073 uint32_t num_out_semaphores,
3074 VkFence fence,
3075 int perf_query_pass);
3076
3077 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
3078
3079 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
3080 const void *data, uint32_t size, uint32_t alignment);
3081 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
3082 uint32_t *a, uint32_t *b,
3083 uint32_t dwords, uint32_t alignment);
3084
3085 struct anv_address
3086 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
3087 struct anv_state
3088 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
3089 uint32_t entries, uint32_t *state_offset);
3090 struct anv_state
3091 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
3092 struct anv_state
3093 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
3094 uint32_t size, uint32_t alignment);
3095
3096 VkResult
3097 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
3098
3099 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
3100 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
3101 bool depth_clamp_enable);
3102 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
3103
3104 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
3105 struct anv_render_pass *pass,
3106 struct anv_framebuffer *framebuffer,
3107 const VkClearValue *clear_values);
3108
3109 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
3110
3111 struct anv_state
3112 anv_cmd_buffer_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer);
3113 struct anv_state
3114 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
3115
3116 const struct anv_image_view *
3117 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
3118
3119 VkResult
3120 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
3121 uint32_t num_entries,
3122 uint32_t *state_offset,
3123 struct anv_state *bt_state);
3124
3125 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
3126
3127 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer);
3128
3129 enum anv_fence_type {
3130 ANV_FENCE_TYPE_NONE = 0,
3131 ANV_FENCE_TYPE_BO,
3132 ANV_FENCE_TYPE_WSI_BO,
3133 ANV_FENCE_TYPE_SYNCOBJ,
3134 ANV_FENCE_TYPE_WSI,
3135 };
3136
3137 enum anv_bo_fence_state {
3138 /** Indicates that this is a new (or newly reset fence) */
3139 ANV_BO_FENCE_STATE_RESET,
3140
3141 /** Indicates that this fence has been submitted to the GPU but is still
3142 * (as far as we know) in use by the GPU.
3143 */
3144 ANV_BO_FENCE_STATE_SUBMITTED,
3145
3146 ANV_BO_FENCE_STATE_SIGNALED,
3147 };
3148
3149 struct anv_fence_impl {
3150 enum anv_fence_type type;
3151
3152 union {
3153 /** Fence implementation for BO fences
3154 *
3155 * These fences use a BO and a set of CPU-tracked state flags. The BO
3156 * is added to the object list of the last execbuf call in a QueueSubmit
3157 * and is marked EXEC_WRITE. The state flags track when the BO has been
3158 * submitted to the kernel. We need to do this because Vulkan lets you
3159 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
3160 * will say it's idle in this case.
3161 */
3162 struct {
3163 struct anv_bo *bo;
3164 enum anv_bo_fence_state state;
3165 } bo;
3166
3167 /** DRM syncobj handle for syncobj-based fences */
3168 uint32_t syncobj;
3169
3170 /** WSI fence */
3171 struct wsi_fence *fence_wsi;
3172 };
3173 };
3174
3175 struct anv_fence {
3176 struct vk_object_base base;
3177
3178 /* Permanent fence state. Every fence has some form of permanent state
3179 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3180 * cross-process fences) or it could just be a dummy for use internally.
3181 */
3182 struct anv_fence_impl permanent;
3183
3184 /* Temporary fence state. A fence *may* have temporary state. That state
3185 * is added to the fence by an import operation and is reset back to
3186 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3187 * state cannot be signaled because the fence must already be signaled
3188 * before the temporary state can be exported from the fence in the other
3189 * process and imported here.
3190 */
3191 struct anv_fence_impl temporary;
3192 };
3193
3194 void anv_fence_reset_temporary(struct anv_device *device,
3195 struct anv_fence *fence);
3196
3197 struct anv_event {
3198 struct vk_object_base base;
3199 uint64_t semaphore;
3200 struct anv_state state;
3201 };
3202
3203 enum anv_semaphore_type {
3204 ANV_SEMAPHORE_TYPE_NONE = 0,
3205 ANV_SEMAPHORE_TYPE_DUMMY,
3206 ANV_SEMAPHORE_TYPE_BO,
3207 ANV_SEMAPHORE_TYPE_WSI_BO,
3208 ANV_SEMAPHORE_TYPE_SYNC_FILE,
3209 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
3210 ANV_SEMAPHORE_TYPE_TIMELINE,
3211 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ_TIMELINE,
3212 };
3213
3214 struct anv_timeline_point {
3215 struct list_head link;
3216
3217 uint64_t serial;
3218
3219 /* Number of waiter on this point, when > 0 the point should not be garbage
3220 * collected.
3221 */
3222 int waiting;
3223
3224 /* BO used for synchronization. */
3225 struct anv_bo *bo;
3226 };
3227
3228 struct anv_timeline {
3229 pthread_mutex_t mutex;
3230 pthread_cond_t cond;
3231
3232 uint64_t highest_past;
3233 uint64_t highest_pending;
3234
3235 struct list_head points;
3236 struct list_head free_points;
3237 };
3238
3239 struct anv_semaphore_impl {
3240 enum anv_semaphore_type type;
3241
3242 union {
3243 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3244 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3245 * object list on any execbuf2 calls for which this semaphore is used as
3246 * a wait or signal fence. When used as a signal fence or when type ==
3247 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3248 */
3249 struct anv_bo *bo;
3250
3251 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3252 * If the semaphore is in the unsignaled state due to either just being
3253 * created or because it has been used for a wait, fd will be -1.
3254 */
3255 int fd;
3256
3257 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3258 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3259 * import so we don't need to bother with a userspace cache.
3260 */
3261 uint32_t syncobj;
3262
3263 /* Non shareable timeline semaphore
3264 *
3265 * Used when kernel don't have support for timeline semaphores.
3266 */
3267 struct anv_timeline timeline;
3268 };
3269 };
3270
3271 struct anv_semaphore {
3272 struct vk_object_base base;
3273
3274 uint32_t refcount;
3275
3276 /* Permanent semaphore state. Every semaphore has some form of permanent
3277 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3278 * (for cross-process semaphores0 or it could just be a dummy for use
3279 * internally.
3280 */
3281 struct anv_semaphore_impl permanent;
3282
3283 /* Temporary semaphore state. A semaphore *may* have temporary state.
3284 * That state is added to the semaphore by an import operation and is reset
3285 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3286 * semaphore with temporary state cannot be signaled because the semaphore
3287 * must already be signaled before the temporary state can be exported from
3288 * the semaphore in the other process and imported here.
3289 */
3290 struct anv_semaphore_impl temporary;
3291 };
3292
3293 void anv_semaphore_reset_temporary(struct anv_device *device,
3294 struct anv_semaphore *semaphore);
3295
3296 struct anv_shader_module {
3297 struct vk_object_base base;
3298
3299 unsigned char sha1[20];
3300 uint32_t size;
3301 char data[0];
3302 };
3303
3304 static inline gl_shader_stage
3305 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
3306 {
3307 assert(__builtin_popcount(vk_stage) == 1);
3308 return ffs(vk_stage) - 1;
3309 }
3310
3311 static inline VkShaderStageFlagBits
3312 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
3313 {
3314 return (1 << mesa_stage);
3315 }
3316
3317 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3318
3319 #define anv_foreach_stage(stage, stage_bits) \
3320 for (gl_shader_stage stage, \
3321 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3322 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3323 __tmp &= ~(1 << (stage)))
3324
3325 struct anv_pipeline_bind_map {
3326 unsigned char surface_sha1[20];
3327 unsigned char sampler_sha1[20];
3328 unsigned char push_sha1[20];
3329
3330 uint32_t surface_count;
3331 uint32_t sampler_count;
3332
3333 struct anv_pipeline_binding * surface_to_descriptor;
3334 struct anv_pipeline_binding * sampler_to_descriptor;
3335
3336 struct anv_push_range push_ranges[4];
3337 };
3338
3339 struct anv_shader_bin_key {
3340 uint32_t size;
3341 uint8_t data[0];
3342 };
3343
3344 struct anv_shader_bin {
3345 uint32_t ref_cnt;
3346
3347 gl_shader_stage stage;
3348
3349 const struct anv_shader_bin_key *key;
3350
3351 struct anv_state kernel;
3352 uint32_t kernel_size;
3353
3354 struct anv_state constant_data;
3355 uint32_t constant_data_size;
3356
3357 const struct brw_stage_prog_data *prog_data;
3358 uint32_t prog_data_size;
3359
3360 struct brw_compile_stats stats[3];
3361 uint32_t num_stats;
3362
3363 struct nir_xfb_info *xfb_info;
3364
3365 struct anv_pipeline_bind_map bind_map;
3366 };
3367
3368 struct anv_shader_bin *
3369 anv_shader_bin_create(struct anv_device *device,
3370 gl_shader_stage stage,
3371 const void *key, uint32_t key_size,
3372 const void *kernel, uint32_t kernel_size,
3373 const void *constant_data, uint32_t constant_data_size,
3374 const struct brw_stage_prog_data *prog_data,
3375 uint32_t prog_data_size,
3376 const struct brw_compile_stats *stats, uint32_t num_stats,
3377 const struct nir_xfb_info *xfb_info,
3378 const struct anv_pipeline_bind_map *bind_map);
3379
3380 void
3381 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
3382
3383 static inline void
3384 anv_shader_bin_ref(struct anv_shader_bin *shader)
3385 {
3386 assert(shader && shader->ref_cnt >= 1);
3387 p_atomic_inc(&shader->ref_cnt);
3388 }
3389
3390 static inline void
3391 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
3392 {
3393 assert(shader && shader->ref_cnt >= 1);
3394 if (p_atomic_dec_zero(&shader->ref_cnt))
3395 anv_shader_bin_destroy(device, shader);
3396 }
3397
3398 struct anv_pipeline_executable {
3399 gl_shader_stage stage;
3400
3401 struct brw_compile_stats stats;
3402
3403 char *nir;
3404 char *disasm;
3405 };
3406
3407 enum anv_pipeline_type {
3408 ANV_PIPELINE_GRAPHICS,
3409 ANV_PIPELINE_COMPUTE,
3410 };
3411
3412 struct anv_pipeline {
3413 struct vk_object_base base;
3414
3415 struct anv_device * device;
3416
3417 struct anv_batch batch;
3418 struct anv_reloc_list batch_relocs;
3419
3420 void * mem_ctx;
3421
3422 enum anv_pipeline_type type;
3423 VkPipelineCreateFlags flags;
3424
3425 struct util_dynarray executables;
3426
3427 const struct gen_l3_config * l3_config;
3428 };
3429
3430 struct anv_graphics_pipeline {
3431 struct anv_pipeline base;
3432
3433 uint32_t batch_data[512];
3434
3435 anv_cmd_dirty_mask_t dynamic_state_mask;
3436 struct anv_dynamic_state dynamic_state;
3437
3438 uint32_t topology;
3439
3440 struct anv_subpass * subpass;
3441
3442 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
3443
3444 VkShaderStageFlags active_stages;
3445
3446 bool primitive_restart;
3447 bool writes_depth;
3448 bool depth_test_enable;
3449 bool writes_stencil;
3450 bool stencil_test_enable;
3451 bool depth_clamp_enable;
3452 bool depth_clip_enable;
3453 bool sample_shading_enable;
3454 bool kill_pixel;
3455 bool depth_bounds_test_enable;
3456
3457 /* When primitive replication is used, subpass->view_mask will describe what
3458 * views to replicate.
3459 */
3460 bool use_primitive_replication;
3461
3462 struct anv_state blend_state;
3463
3464 uint32_t vb_used;
3465 struct anv_pipeline_vertex_binding {
3466 uint32_t stride;
3467 bool instanced;
3468 uint32_t instance_divisor;
3469 } vb[MAX_VBS];
3470
3471 struct {
3472 uint32_t sf[7];
3473 uint32_t depth_stencil_state[3];
3474 uint32_t clip[4];
3475 } gen7;
3476
3477 struct {
3478 uint32_t sf[4];
3479 uint32_t raster[5];
3480 uint32_t wm_depth_stencil[3];
3481 } gen8;
3482
3483 struct {
3484 uint32_t wm_depth_stencil[4];
3485 } gen9;
3486 };
3487
3488 struct anv_compute_pipeline {
3489 struct anv_pipeline base;
3490
3491 struct anv_shader_bin * cs;
3492 uint32_t cs_right_mask;
3493 uint32_t batch_data[9];
3494 uint32_t interface_descriptor_data[8];
3495 };
3496
3497 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3498 static inline struct anv_##pipe_type##_pipeline * \
3499 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3500 { \
3501 assert(pipeline->type == pipe_enum); \
3502 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3503 }
3504
3505 ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS)
3506 ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE)
3507
3508 static inline bool
3509 anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
3510 gl_shader_stage stage)
3511 {
3512 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
3513 }
3514
3515 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3516 static inline const struct brw_##prefix##_prog_data * \
3517 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3518 { \
3519 if (anv_pipeline_has_stage(pipeline, stage)) { \
3520 return (const struct brw_##prefix##_prog_data *) \
3521 pipeline->shaders[stage]->prog_data; \
3522 } else { \
3523 return NULL; \
3524 } \
3525 }
3526
3527 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
3528 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
3529 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
3530 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
3531 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
3532
3533 static inline const struct brw_cs_prog_data *
3534 get_cs_prog_data(const struct anv_compute_pipeline *pipeline)
3535 {
3536 assert(pipeline->cs);
3537 return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
3538 }
3539
3540 static inline const struct brw_vue_prog_data *
3541 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
3542 {
3543 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
3544 return &get_gs_prog_data(pipeline)->base;
3545 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
3546 return &get_tes_prog_data(pipeline)->base;
3547 else
3548 return &get_vs_prog_data(pipeline)->base;
3549 }
3550
3551 VkResult
3552 anv_pipeline_init(struct anv_pipeline *pipeline,
3553 struct anv_device *device,
3554 enum anv_pipeline_type type,
3555 VkPipelineCreateFlags flags,
3556 const VkAllocationCallbacks *pAllocator);
3557
3558 void
3559 anv_pipeline_finish(struct anv_pipeline *pipeline,
3560 struct anv_device *device,
3561 const VkAllocationCallbacks *pAllocator);
3562
3563 VkResult
3564 anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline, struct anv_device *device,
3565 struct anv_pipeline_cache *cache,
3566 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3567 const VkAllocationCallbacks *alloc);
3568
3569 VkResult
3570 anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
3571 struct anv_pipeline_cache *cache,
3572 const VkComputePipelineCreateInfo *info,
3573 const struct anv_shader_module *module,
3574 const char *entrypoint,
3575 const VkSpecializationInfo *spec_info);
3576
3577 struct anv_cs_parameters {
3578 uint32_t group_size;
3579 uint32_t simd_size;
3580 uint32_t threads;
3581 };
3582
3583 struct anv_cs_parameters
3584 anv_cs_parameters(const struct anv_compute_pipeline *pipeline);
3585
3586 struct anv_format_plane {
3587 enum isl_format isl_format:16;
3588 struct isl_swizzle swizzle;
3589
3590 /* Whether this plane contains chroma channels */
3591 bool has_chroma;
3592
3593 /* For downscaling of YUV planes */
3594 uint8_t denominator_scales[2];
3595
3596 /* How to map sampled ycbcr planes to a single 4 component element. */
3597 struct isl_swizzle ycbcr_swizzle;
3598
3599 /* What aspect is associated to this plane */
3600 VkImageAspectFlags aspect;
3601 };
3602
3603
3604 struct anv_format {
3605 struct anv_format_plane planes[3];
3606 VkFormat vk_format;
3607 uint8_t n_planes;
3608 bool can_ycbcr;
3609 };
3610
3611 /**
3612 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3613 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3614 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3615 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3616 */
3617 static inline uint32_t
3618 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
3619 VkImageAspectFlags aspect_mask)
3620 {
3621 switch (aspect_mask) {
3622 case VK_IMAGE_ASPECT_COLOR_BIT:
3623 case VK_IMAGE_ASPECT_DEPTH_BIT:
3624 case VK_IMAGE_ASPECT_PLANE_0_BIT:
3625 return 0;
3626 case VK_IMAGE_ASPECT_STENCIL_BIT:
3627 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
3628 return 0;
3629 /* Fall-through */
3630 case VK_IMAGE_ASPECT_PLANE_1_BIT:
3631 return 1;
3632 case VK_IMAGE_ASPECT_PLANE_2_BIT:
3633 return 2;
3634 default:
3635 /* Purposefully assert with depth/stencil aspects. */
3636 unreachable("invalid image aspect");
3637 }
3638 }
3639
3640 static inline VkImageAspectFlags
3641 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
3642 uint32_t plane)
3643 {
3644 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
3645 if (util_bitcount(image_aspects) > 1)
3646 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
3647 return VK_IMAGE_ASPECT_COLOR_BIT;
3648 }
3649 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
3650 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
3651 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
3652 return VK_IMAGE_ASPECT_STENCIL_BIT;
3653 }
3654
3655 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3656 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3657
3658 const struct anv_format *
3659 anv_get_format(VkFormat format);
3660
3661 static inline uint32_t
3662 anv_get_format_planes(VkFormat vk_format)
3663 {
3664 const struct anv_format *format = anv_get_format(vk_format);
3665
3666 return format != NULL ? format->n_planes : 0;
3667 }
3668
3669 struct anv_format_plane
3670 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
3671 VkImageAspectFlagBits aspect, VkImageTiling tiling);
3672
3673 static inline enum isl_format
3674 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
3675 VkImageAspectFlags aspect, VkImageTiling tiling)
3676 {
3677 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
3678 }
3679
3680 bool anv_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
3681 VkImageCreateFlags create_flags,
3682 VkFormat vk_format,
3683 VkImageTiling vk_tiling,
3684 const VkImageFormatListCreateInfoKHR *fmt_list);
3685
3686 static inline struct isl_swizzle
3687 anv_swizzle_for_render(struct isl_swizzle swizzle)
3688 {
3689 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3690 * RGB as RGBA for texturing
3691 */
3692 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
3693 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
3694
3695 /* But it doesn't matter what we render to that channel */
3696 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
3697
3698 return swizzle;
3699 }
3700
3701 void
3702 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
3703
3704 /**
3705 * Subsurface of an anv_image.
3706 */
3707 struct anv_surface {
3708 /** Valid only if isl_surf::size_B > 0. */
3709 struct isl_surf isl;
3710
3711 /**
3712 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3713 */
3714 uint32_t offset;
3715 };
3716
3717 struct anv_image {
3718 struct vk_object_base base;
3719
3720 VkImageType type; /**< VkImageCreateInfo::imageType */
3721 /* The original VkFormat provided by the client. This may not match any
3722 * of the actual surface formats.
3723 */
3724 VkFormat vk_format;
3725 const struct anv_format *format;
3726
3727 VkImageAspectFlags aspects;
3728 VkExtent3D extent;
3729 uint32_t levels;
3730 uint32_t array_size;
3731 uint32_t samples; /**< VkImageCreateInfo::samples */
3732 uint32_t n_planes;
3733 VkImageUsageFlags usage; /**< VkImageCreateInfo::usage. */
3734 VkImageUsageFlags stencil_usage;
3735 VkImageCreateFlags create_flags; /* Flags used when creating image. */
3736 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
3737
3738 /** True if this is needs to be bound to an appropriately tiled BO.
3739 *
3740 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3741 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3742 * we require a dedicated allocation so that we can know to allocate a
3743 * tiled buffer.
3744 */
3745 bool needs_set_tiling;
3746
3747 /**
3748 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3749 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3750 */
3751 uint64_t drm_format_mod;
3752
3753 VkDeviceSize size;
3754 uint32_t alignment;
3755
3756 /* Whether the image is made of several underlying buffer objects rather a
3757 * single one with different offsets.
3758 */
3759 bool disjoint;
3760
3761 /* Image was created with external format. */
3762 bool external_format;
3763
3764 /**
3765 * Image subsurfaces
3766 *
3767 * For each foo, anv_image::planes[x].surface is valid if and only if
3768 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3769 * to figure the number associated with a given aspect.
3770 *
3771 * The hardware requires that the depth buffer and stencil buffer be
3772 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3773 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3774 * allocate the depth and stencil buffers as separate surfaces in the same
3775 * bo.
3776 *
3777 * Memory layout :
3778 *
3779 * -----------------------
3780 * | surface0 | /|\
3781 * ----------------------- |
3782 * | shadow surface0 | |
3783 * ----------------------- | Plane 0
3784 * | aux surface0 | |
3785 * ----------------------- |
3786 * | fast clear colors0 | \|/
3787 * -----------------------
3788 * | surface1 | /|\
3789 * ----------------------- |
3790 * | shadow surface1 | |
3791 * ----------------------- | Plane 1
3792 * | aux surface1 | |
3793 * ----------------------- |
3794 * | fast clear colors1 | \|/
3795 * -----------------------
3796 * | ... |
3797 * | |
3798 * -----------------------
3799 */
3800 struct {
3801 /**
3802 * Offset of the entire plane (whenever the image is disjoint this is
3803 * set to 0).
3804 */
3805 uint32_t offset;
3806
3807 VkDeviceSize size;
3808 uint32_t alignment;
3809
3810 struct anv_surface surface;
3811
3812 /**
3813 * A surface which shadows the main surface and may have different
3814 * tiling. This is used for sampling using a tiling that isn't supported
3815 * for other operations.
3816 */
3817 struct anv_surface shadow_surface;
3818
3819 /**
3820 * The base aux usage for this image. For color images, this can be
3821 * either CCS_E or CCS_D depending on whether or not we can reliably
3822 * leave CCS on all the time.
3823 */
3824 enum isl_aux_usage aux_usage;
3825
3826 struct anv_surface aux_surface;
3827
3828 /**
3829 * Offset of the fast clear state (used to compute the
3830 * fast_clear_state_offset of the following planes).
3831 */
3832 uint32_t fast_clear_state_offset;
3833
3834 /**
3835 * BO associated with this plane, set when bound.
3836 */
3837 struct anv_address address;
3838
3839 /**
3840 * When destroying the image, also free the bo.
3841 * */
3842 bool bo_is_owned;
3843 } planes[3];
3844 };
3845
3846 /* The ordering of this enum is important */
3847 enum anv_fast_clear_type {
3848 /** Image does not have/support any fast-clear blocks */
3849 ANV_FAST_CLEAR_NONE = 0,
3850 /** Image has/supports fast-clear but only to the default value */
3851 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
3852 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3853 ANV_FAST_CLEAR_ANY = 2,
3854 };
3855
3856 /* Returns the number of auxiliary buffer levels attached to an image. */
3857 static inline uint8_t
3858 anv_image_aux_levels(const struct anv_image * const image,
3859 VkImageAspectFlagBits aspect)
3860 {
3861 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3862 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
3863 return 0;
3864
3865 /* The Gen12 CCS aux surface is represented with only one level. */
3866 return image->planes[plane].aux_surface.isl.tiling == ISL_TILING_GEN12_CCS ?
3867 image->planes[plane].surface.isl.levels :
3868 image->planes[plane].aux_surface.isl.levels;
3869 }
3870
3871 /* Returns the number of auxiliary buffer layers attached to an image. */
3872 static inline uint32_t
3873 anv_image_aux_layers(const struct anv_image * const image,
3874 VkImageAspectFlagBits aspect,
3875 const uint8_t miplevel)
3876 {
3877 assert(image);
3878
3879 /* The miplevel must exist in the main buffer. */
3880 assert(miplevel < image->levels);
3881
3882 if (miplevel >= anv_image_aux_levels(image, aspect)) {
3883 /* There are no layers with auxiliary data because the miplevel has no
3884 * auxiliary data.
3885 */
3886 return 0;
3887 } else {
3888 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3889
3890 /* The Gen12 CCS aux surface is represented with only one layer. */
3891 const struct isl_extent4d *aux_logical_level0_px =
3892 image->planes[plane].aux_surface.isl.tiling == ISL_TILING_GEN12_CCS ?
3893 &image->planes[plane].surface.isl.logical_level0_px :
3894 &image->planes[plane].aux_surface.isl.logical_level0_px;
3895
3896 return MAX2(aux_logical_level0_px->array_len,
3897 aux_logical_level0_px->depth >> miplevel);
3898 }
3899 }
3900
3901 static inline struct anv_address
3902 anv_image_get_clear_color_addr(UNUSED const struct anv_device *device,
3903 const struct anv_image *image,
3904 VkImageAspectFlagBits aspect)
3905 {
3906 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
3907
3908 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3909 return anv_address_add(image->planes[plane].address,
3910 image->planes[plane].fast_clear_state_offset);
3911 }
3912
3913 static inline struct anv_address
3914 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
3915 const struct anv_image *image,
3916 VkImageAspectFlagBits aspect)
3917 {
3918 struct anv_address addr =
3919 anv_image_get_clear_color_addr(device, image, aspect);
3920
3921 const unsigned clear_color_state_size = device->info.gen >= 10 ?
3922 device->isl_dev.ss.clear_color_state_size :
3923 device->isl_dev.ss.clear_value_size;
3924 return anv_address_add(addr, clear_color_state_size);
3925 }
3926
3927 static inline struct anv_address
3928 anv_image_get_compression_state_addr(const struct anv_device *device,
3929 const struct anv_image *image,
3930 VkImageAspectFlagBits aspect,
3931 uint32_t level, uint32_t array_layer)
3932 {
3933 assert(level < anv_image_aux_levels(image, aspect));
3934 assert(array_layer < anv_image_aux_layers(image, aspect, level));
3935 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3936 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
3937
3938 struct anv_address addr =
3939 anv_image_get_fast_clear_type_addr(device, image, aspect);
3940 addr.offset += 4; /* Go past the fast clear type */
3941
3942 if (image->type == VK_IMAGE_TYPE_3D) {
3943 for (uint32_t l = 0; l < level; l++)
3944 addr.offset += anv_minify(image->extent.depth, l) * 4;
3945 } else {
3946 addr.offset += level * image->array_size * 4;
3947 }
3948 addr.offset += array_layer * 4;
3949
3950 assert(addr.offset <
3951 image->planes[plane].address.offset + image->planes[plane].size);
3952 return addr;
3953 }
3954
3955 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3956 static inline bool
3957 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
3958 const struct anv_image *image)
3959 {
3960 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
3961 return false;
3962
3963 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3964 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3965 * say:
3966 *
3967 * "If this field is set to AUX_HIZ, Number of Multisamples must
3968 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3969 */
3970 if (image->type == VK_IMAGE_TYPE_3D)
3971 return false;
3972
3973 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3974 * struct. There's documentation which suggests that this feature actually
3975 * reduces performance on BDW, but it has only been observed to help so
3976 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3977 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3978 */
3979 if (devinfo->gen != 8 && !devinfo->has_sample_with_hiz)
3980 return false;
3981
3982 return image->samples == 1;
3983 }
3984
3985 static inline bool
3986 anv_image_plane_uses_aux_map(const struct anv_device *device,
3987 const struct anv_image *image,
3988 uint32_t plane)
3989 {
3990 return device->info.has_aux_map &&
3991 isl_aux_usage_has_ccs(image->planes[plane].aux_usage);
3992 }
3993
3994 void
3995 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
3996 const struct anv_image *image,
3997 VkImageAspectFlagBits aspect,
3998 enum isl_aux_usage aux_usage,
3999 uint32_t level,
4000 uint32_t base_layer,
4001 uint32_t layer_count);
4002
4003 void
4004 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
4005 const struct anv_image *image,
4006 VkImageAspectFlagBits aspect,
4007 enum isl_aux_usage aux_usage,
4008 enum isl_format format, struct isl_swizzle swizzle,
4009 uint32_t level, uint32_t base_layer, uint32_t layer_count,
4010</