2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
76 struct anv_buffer_view
;
77 struct anv_image_view
;
80 struct gen_aux_map_context
;
81 struct gen_perf_config
;
82 struct gen_perf_counter_pass
;
83 struct gen_perf_query_result
;
85 #include <vulkan/vulkan.h>
86 #include <vulkan/vulkan_intel.h>
87 #include <vulkan/vk_icd.h>
89 #include "anv_android.h"
90 #include "anv_entrypoints.h"
91 #include "anv_extensions.h"
94 #include "dev/gen_debug.h"
95 #include "common/intel_log.h"
96 #include "wsi_common.h"
98 #define NSEC_PER_SEC 1000000000ull
100 /* anv Virtual Memory Layout
101 * =========================
103 * When the anv driver is determining the virtual graphics addresses of memory
104 * objects itself using the softpin mechanism, the following memory ranges
107 * Three special considerations to notice:
109 * (1) the dynamic state pool is located within the same 4 GiB as the low
110 * heap. This is to work around a VF cache issue described in a comment in
111 * anv_physical_device_init_heaps.
113 * (2) the binding table pool is located at lower addresses than the surface
114 * state pool, within a 4 GiB range. This allows surface state base addresses
115 * to cover both binding tables (16 bit offsets) and surface states (32 bit
118 * (3) the last 4 GiB of the address space is withheld from the high
119 * heap. Various hardware units will read past the end of an object for
120 * various reasons. This healthy margin prevents reads from wrapping around
123 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
124 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
125 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
126 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
127 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
128 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
129 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
130 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
131 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
132 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
133 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
134 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
135 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
137 #define LOW_HEAP_SIZE \
138 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
139 #define DYNAMIC_STATE_POOL_SIZE \
140 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
141 #define BINDING_TABLE_POOL_SIZE \
142 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
143 #define SURFACE_STATE_POOL_SIZE \
144 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
145 #define INSTRUCTION_STATE_POOL_SIZE \
146 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
147 #define CLIENT_VISIBLE_HEAP_SIZE \
148 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
150 /* Allowing different clear colors requires us to perform a depth resolve at
151 * the end of certain render passes. This is because while slow clears store
152 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
153 * See the PRMs for examples describing when additional resolves would be
154 * necessary. To enable fast clears without requiring extra resolves, we set
155 * the clear value to a globally-defined one. We could allow different values
156 * if the user doesn't expect coherent data during or after a render passes
157 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
158 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
159 * 1.0f seems to be the only value used. The only application that doesn't set
160 * this value does so through the usage of an seemingly uninitialized clear
163 #define ANV_HZ_FC_VAL 1.0f
166 #define MAX_XFB_BUFFERS 4
167 #define MAX_XFB_STREAMS 4
170 #define MAX_VIEWPORTS 16
171 #define MAX_SCISSORS 16
172 #define MAX_PUSH_CONSTANTS_SIZE 128
173 #define MAX_DYNAMIC_BUFFERS 16
174 #define MAX_IMAGES 64
175 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
176 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
177 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
178 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
179 * use 64 here to avoid cache issues. This could most likely bring it back to
180 * 32 if we had different virtual addresses for the different views on a given
183 #define ANV_UBO_ALIGNMENT 64
184 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
185 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
187 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
189 * "The surface state model is used when a Binding Table Index (specified
190 * in the message descriptor) of less than 240 is specified. In this model,
191 * the Binding Table Index is used to index into the binding table, and the
192 * binding table entry contains a pointer to the SURFACE_STATE."
194 * Binding table values above 240 are used for various things in the hardware
195 * such as stateless, stateless with incoherent cache, SLM, and bindless.
197 #define MAX_BINDING_TABLE_SIZE 240
199 /* The kernel relocation API has a limitation of a 32-bit delta value
200 * applied to the address before it is written which, in spite of it being
201 * unsigned, is treated as signed . Because of the way that this maps to
202 * the Vulkan API, we cannot handle an offset into a buffer that does not
203 * fit into a signed 32 bits. The only mechanism we have for dealing with
204 * this at the moment is to limit all VkDeviceMemory objects to a maximum
205 * of 2GB each. The Vulkan spec allows us to do this:
207 * "Some platforms may have a limit on the maximum size of a single
208 * allocation. For example, certain systems may fail to create
209 * allocations with a size greater than or equal to 4GB. Such a limit is
210 * implementation-dependent, and if such a failure occurs then the error
211 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
213 * We don't use vk_error here because it's not an error so much as an
214 * indication to the application that the allocation is too large.
216 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
218 #define ANV_SVGS_VB_INDEX MAX_VBS
219 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
221 /* We reserve this MI ALU register for the purpose of handling predication.
222 * Other code which uses the MI ALU should leave it alone.
224 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
226 /* We reserve this MI ALU register to pass around an offset computed from
227 * VkPerformanceQuerySubmitInfoKHR::counterPassIndex VK_KHR_performance_query.
228 * Other code which uses the MI ALU should leave it alone.
230 #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
232 /* For gen12 we set the streamout buffers using 4 separate commands
233 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
234 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
235 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
236 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
237 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
238 * 3DSTATE_SO_BUFFER_INDEX_0.
240 #define SO_BUFFER_INDEX_0_CMD 0x60
241 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
243 static inline uint32_t
244 align_down_npot_u32(uint32_t v
, uint32_t a
)
249 static inline uint32_t
250 align_down_u32(uint32_t v
, uint32_t a
)
252 assert(a
!= 0 && a
== (a
& -a
));
256 static inline uint32_t
257 align_u32(uint32_t v
, uint32_t a
)
259 assert(a
!= 0 && a
== (a
& -a
));
260 return align_down_u32(v
+ a
- 1, a
);
263 static inline uint64_t
264 align_down_u64(uint64_t v
, uint64_t a
)
266 assert(a
!= 0 && a
== (a
& -a
));
270 static inline uint64_t
271 align_u64(uint64_t v
, uint64_t a
)
273 return align_down_u64(v
+ a
- 1, a
);
276 static inline int32_t
277 align_i32(int32_t v
, int32_t a
)
279 assert(a
!= 0 && a
== (a
& -a
));
280 return (v
+ a
- 1) & ~(a
- 1);
283 /** Alignment must be a power of 2. */
285 anv_is_aligned(uintmax_t n
, uintmax_t a
)
287 assert(a
== (a
& -a
));
288 return (n
& (a
- 1)) == 0;
291 static inline uint32_t
292 anv_minify(uint32_t n
, uint32_t levels
)
294 if (unlikely(n
== 0))
297 return MAX2(n
>> levels
, 1);
301 anv_clamp_f(float f
, float min
, float max
)
314 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
316 if (*inout_mask
& clear_mask
) {
317 *inout_mask
&= ~clear_mask
;
324 static inline union isl_color_value
325 vk_to_isl_color(VkClearColorValue color
)
327 return (union isl_color_value
) {
337 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
339 uintptr_t mask
= (1ull << bits
) - 1;
341 return (void *) (ptr
& ~mask
);
344 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
346 uintptr_t value
= (uintptr_t) ptr
;
347 uintptr_t mask
= (1ull << bits
) - 1;
348 return value
| (mask
& flags
);
351 #define for_each_bit(b, dword) \
352 for (uint32_t __dword = (dword); \
353 (b) = __builtin_ffs(__dword) - 1, __dword; \
354 __dword &= ~(1 << (b)))
356 #define typed_memcpy(dest, src, count) ({ \
357 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
358 memcpy((dest), (src), (count) * sizeof(*(src))); \
361 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
362 * to be added here in order to utilize mapping in debug/error/perf macros.
364 #define REPORT_OBJECT_TYPE(o) \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
443 __builtin_choose_expr ( \
444 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
445 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
446 __builtin_choose_expr ( \
447 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
448 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
449 __builtin_choose_expr ( \
450 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
451 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
452 __builtin_choose_expr ( \
453 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
454 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
455 __builtin_choose_expr ( \
456 __builtin_types_compatible_p (__typeof (o), void*), \
457 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
458 /* The void expression results in a compile-time error \
459 when assigning the result to something. */ \
460 (void)0)))))))))))))))))))))))))))))))
462 /* Whenever we generate an error, pass it through this function. Useful for
463 * debugging, where we can break on it. Only call at error site, not when
464 * propagating errors. Might be useful to plug in a stack trace here.
467 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
468 VkDebugReportObjectTypeEXT type
, VkResult error
,
469 const char *file
, int line
, const char *format
,
472 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
473 VkDebugReportObjectTypeEXT type
, VkResult error
,
474 const char *file
, int line
, const char *format
, ...)
475 anv_printflike(7, 8);
478 #define vk_error(error) __vk_errorf(NULL, NULL,\
479 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
480 error, __FILE__, __LINE__, NULL)
481 #define vk_errorfi(instance, obj, error, format, ...)\
482 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
483 __FILE__, __LINE__, format, ## __VA_ARGS__)
484 #define vk_errorf(device, obj, error, format, ...)\
485 vk_errorfi(anv_device_instance_or_null(device),\
486 obj, error, format, ## __VA_ARGS__)
488 #define vk_error(error) error
489 #define vk_errorfi(instance, obj, error, format, ...) error
490 #define vk_errorf(device, obj, error, format, ...) error
494 * Warn on ignored extension structs.
496 * The Vulkan spec requires us to ignore unsupported or unknown structs in
497 * a pNext chain. In debug mode, emitting warnings for ignored structs may
498 * help us discover structs that we should not have ignored.
501 * From the Vulkan 1.0.38 spec:
503 * Any component of the implementation (the loader, any enabled layers,
504 * and drivers) must skip over, without processing (other than reading the
505 * sType and pNext members) any chained structures with sType values not
506 * defined by extensions supported by that component.
508 #define anv_debug_ignored_stype(sType) \
509 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
511 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
512 VkDebugReportObjectTypeEXT type
, const char *file
,
513 int line
, const char *format
, ...)
514 anv_printflike(6, 7);
515 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
516 void anv_loge_v(const char *format
, va_list va
);
519 * Print a FINISHME message, including its source location.
521 #define anv_finishme(format, ...) \
523 static bool reported = false; \
525 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
532 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
534 #define anv_perf_warn(instance, obj, format, ...) \
536 static bool reported = false; \
537 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
538 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
539 format, ##__VA_ARGS__); \
544 /* A non-fatal assert. Useful for debugging. */
546 #define anv_assert(x) ({ \
547 if (unlikely(!(x))) \
548 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
551 #define anv_assert(x)
554 /* A multi-pointer allocator
556 * When copying data structures from the user (such as a render pass), it's
557 * common to need to allocate data for a bunch of different things. Instead
558 * of doing several allocations and having to handle all of the error checking
559 * that entails, it can be easier to do a single allocation. This struct
560 * helps facilitate that. The intended usage looks like this:
563 * anv_multialloc_add(&ma, &main_ptr, 1);
564 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
565 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
567 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
568 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
570 struct anv_multialloc
{
578 #define ANV_MULTIALLOC_INIT \
579 ((struct anv_multialloc) { 0, })
581 #define ANV_MULTIALLOC(_name) \
582 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
584 __attribute__((always_inline
))
586 _anv_multialloc_add(struct anv_multialloc
*ma
,
587 void **ptr
, size_t size
, size_t align
)
589 size_t offset
= align_u64(ma
->size
, align
);
590 ma
->size
= offset
+ size
;
591 ma
->align
= MAX2(ma
->align
, align
);
593 /* Store the offset in the pointer. */
594 *ptr
= (void *)(uintptr_t)offset
;
596 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
597 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
600 #define anv_multialloc_add_size(_ma, _ptr, _size) \
601 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
603 #define anv_multialloc_add(_ma, _ptr, _count) \
604 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
606 __attribute__((always_inline
))
608 anv_multialloc_alloc(struct anv_multialloc
*ma
,
609 const VkAllocationCallbacks
*alloc
,
610 VkSystemAllocationScope scope
)
612 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
616 /* Fill out each of the pointers with their final value.
618 * for (uint32_t i = 0; i < ma->ptr_count; i++)
619 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
621 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
622 * constant, GCC is incapable of figuring this out and unrolling the loop
623 * so we have to give it a little help.
625 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
626 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
627 if ((_i) < ma->ptr_count) \
628 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
629 _ANV_MULTIALLOC_UPDATE_POINTER(0);
630 _ANV_MULTIALLOC_UPDATE_POINTER(1);
631 _ANV_MULTIALLOC_UPDATE_POINTER(2);
632 _ANV_MULTIALLOC_UPDATE_POINTER(3);
633 _ANV_MULTIALLOC_UPDATE_POINTER(4);
634 _ANV_MULTIALLOC_UPDATE_POINTER(5);
635 _ANV_MULTIALLOC_UPDATE_POINTER(6);
636 _ANV_MULTIALLOC_UPDATE_POINTER(7);
637 #undef _ANV_MULTIALLOC_UPDATE_POINTER
642 __attribute__((always_inline
))
644 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
645 const VkAllocationCallbacks
*parent_alloc
,
646 const VkAllocationCallbacks
*alloc
,
647 VkSystemAllocationScope scope
)
649 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
657 /* Index into the current validation list. This is used by the
658 * validation list building alrogithm to track which buffers are already
659 * in the validation list so that we can ensure uniqueness.
663 /* Index for use with util_sparse_array_free_list */
666 /* Last known offset. This value is provided by the kernel when we
667 * execbuf and is used as the presumed offset for the next bunch of
672 /** Size of the buffer not including implicit aux */
675 /* Map for internally mapped BOs.
677 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
681 /** Size of the implicit CCS range at the end of the buffer
683 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
684 * page of main surface data maps to a 256B chunk of CCS data and that
685 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
686 * addresses in the main surface to virtual memory addresses for CCS data.
688 * Because we can't change these maps around easily and because Vulkan
689 * allows two VkImages to be bound to overlapping memory regions (as long
690 * as the app is careful), it's not feasible to make this mapping part of
691 * the image. (On Gen11 and earlier, the mapping was provided via
692 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
693 * Instead, we attach the CCS data directly to the buffer object and setup
694 * the AUX table mapping at BO creation time.
696 * This field is for internal tracking use by the BO allocator only and
697 * should not be touched by other parts of the code. If something wants to
698 * know if a BO has implicit CCS data, it should instead look at the
699 * has_implicit_ccs boolean below.
701 * This data is not included in maps of this buffer.
705 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
708 /** True if this BO may be shared with other processes */
711 /** True if this BO is a wrapper
713 * When set to true, none of the fields in this BO are meaningful except
714 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
715 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
716 * is set in the physical device.
720 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
721 bool has_fixed_address
:1;
723 /** True if this BO wraps a host pointer */
724 bool from_host_ptr
:1;
726 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
727 bool has_client_visible_address
:1;
729 /** True if this BO has implicit CCS data attached to it */
730 bool has_implicit_ccs
:1;
733 static inline struct anv_bo
*
734 anv_bo_ref(struct anv_bo
*bo
)
736 p_atomic_inc(&bo
->refcount
);
740 static inline struct anv_bo
*
741 anv_bo_unwrap(struct anv_bo
*bo
)
743 while (bo
->is_wrapper
)
748 /* Represents a lock-free linked list of "free" things. This is used by
749 * both the block pool and the state pools. Unfortunately, in order to
750 * solve the ABA problem, we can't use a single uint32_t head.
752 union anv_free_list
{
756 /* A simple count that is incremented every time the head changes. */
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
762 uint64_t u64
__attribute__ ((aligned (8)));
765 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
767 struct anv_block_state
{
773 /* Make sure it's aligned to 64 bits. This will make atomic operations
774 * faster on 32 bit platforms.
776 uint64_t u64
__attribute__ ((aligned (8)));
780 #define anv_block_pool_foreach_bo(bo, pool) \
781 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
782 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
785 #define ANV_MAX_BLOCK_POOL_BOS 20
787 struct anv_block_pool
{
788 struct anv_device
*device
;
791 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
792 * around the actual BO so that we grow the pool after the wrapper BO has
793 * been put in a relocation list. This is only used in the non-softpin
796 struct anv_bo wrapper_bo
;
798 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
804 /* The address where the start of the pool is pinned. The various bos that
805 * are created as the pool grows will have addresses in the range
806 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
808 uint64_t start_address
;
810 /* The offset from the start of the bo to the "center" of the block
811 * pool. Pointers to allocated blocks are given by
812 * bo.map + center_bo_offset + offsets.
814 uint32_t center_bo_offset
;
816 /* Current memory map of the block pool. This pointer may or may not
817 * point to the actual beginning of the block pool memory. If
818 * anv_block_pool_alloc_back has ever been called, then this pointer
819 * will point to the "center" position of the buffer and all offsets
820 * (negative or positive) given out by the block pool alloc functions
821 * will be valid relative to this pointer.
823 * In particular, map == bo.map + center_offset
825 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
826 * since it will handle the softpin case as well, where this points to NULL.
832 * Array of mmaps and gem handles owned by the block pool, reclaimed when
833 * the block pool is destroyed.
835 struct u_vector mmap_cleanups
;
837 struct anv_block_state state
;
839 struct anv_block_state back_state
;
842 /* Block pools are backed by a fixed-size 1GB memfd */
843 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
845 /* The center of the block pool is also the middle of the memfd. This may
846 * change in the future if we decide differently for some reason.
848 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
850 static inline uint32_t
851 anv_block_pool_size(struct anv_block_pool
*pool
)
853 return pool
->state
.end
+ pool
->back_state
.end
;
863 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
865 struct anv_fixed_size_state_pool
{
866 union anv_free_list free_list
;
867 struct anv_block_state block
;
870 #define ANV_MIN_STATE_SIZE_LOG2 6
871 #define ANV_MAX_STATE_SIZE_LOG2 21
873 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
875 struct anv_free_entry
{
877 struct anv_state state
;
880 struct anv_state_table
{
881 struct anv_device
*device
;
883 struct anv_free_entry
*map
;
885 struct anv_block_state state
;
886 struct u_vector cleanups
;
889 struct anv_state_pool
{
890 struct anv_block_pool block_pool
;
892 /* Offset into the relevant state base address where the state pool starts
895 int32_t start_offset
;
897 struct anv_state_table table
;
899 /* The size of blocks which will be allocated from the block pool */
902 /** Free list for "back" allocations */
903 union anv_free_list back_alloc_free_list
;
905 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
908 struct anv_state_reserved_pool
{
909 struct anv_state_pool
*pool
;
910 union anv_free_list reserved_blocks
;
914 struct anv_state_stream
{
915 struct anv_state_pool
*state_pool
;
917 /* The size of blocks to allocate from the state pool */
920 /* Current block we're allocating from */
921 struct anv_state block
;
923 /* Offset into the current block at which to allocate the next state */
926 /* List of all blocks allocated from this pool */
927 struct util_dynarray all_blocks
;
930 /* The block_pool functions exported for testing only. The block pool should
931 * only be used via a state pool (see below).
933 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
934 struct anv_device
*device
,
935 uint64_t start_address
,
936 uint32_t initial_size
);
937 void anv_block_pool_finish(struct anv_block_pool
*pool
);
938 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
939 uint32_t block_size
, uint32_t *padding
);
940 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
941 uint32_t block_size
);
942 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
945 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
946 struct anv_device
*device
,
947 uint64_t base_address
,
948 int32_t start_offset
,
949 uint32_t block_size
);
950 void anv_state_pool_finish(struct anv_state_pool
*pool
);
951 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
952 uint32_t state_size
, uint32_t alignment
);
953 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
954 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
955 void anv_state_stream_init(struct anv_state_stream
*stream
,
956 struct anv_state_pool
*state_pool
,
957 uint32_t block_size
);
958 void anv_state_stream_finish(struct anv_state_stream
*stream
);
959 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
960 uint32_t size
, uint32_t alignment
);
962 void anv_state_reserved_pool_init(struct anv_state_reserved_pool
*pool
,
963 struct anv_state_pool
*parent
,
964 uint32_t count
, uint32_t size
,
966 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool
*pool
);
967 struct anv_state
anv_state_reserved_pool_alloc(struct anv_state_reserved_pool
*pool
);
968 void anv_state_reserved_pool_free(struct anv_state_reserved_pool
*pool
,
969 struct anv_state state
);
971 VkResult
anv_state_table_init(struct anv_state_table
*table
,
972 struct anv_device
*device
,
973 uint32_t initial_entries
);
974 void anv_state_table_finish(struct anv_state_table
*table
);
975 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
977 void anv_free_list_push(union anv_free_list
*list
,
978 struct anv_state_table
*table
,
979 uint32_t idx
, uint32_t count
);
980 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
981 struct anv_state_table
*table
);
984 static inline struct anv_state
*
985 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
987 return &table
->map
[idx
].state
;
990 * Implements a pool of re-usable BOs. The interface is identical to that
991 * of block_pool except that each block is its own BO.
994 struct anv_device
*device
;
996 struct util_sparse_array_free_list free_list
[16];
999 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
1000 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
1001 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
1002 struct anv_bo
**bo_out
);
1003 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
1005 struct anv_scratch_pool
{
1006 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
1007 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
1010 void anv_scratch_pool_init(struct anv_device
*device
,
1011 struct anv_scratch_pool
*pool
);
1012 void anv_scratch_pool_finish(struct anv_device
*device
,
1013 struct anv_scratch_pool
*pool
);
1014 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
1015 struct anv_scratch_pool
*pool
,
1016 gl_shader_stage stage
,
1017 unsigned per_thread_scratch
);
1019 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1020 struct anv_bo_cache
{
1021 struct util_sparse_array bo_map
;
1022 pthread_mutex_t mutex
;
1025 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
1026 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
1028 struct anv_memory_type
{
1029 /* Standard bits passed on to the client */
1030 VkMemoryPropertyFlags propertyFlags
;
1034 struct anv_memory_heap
{
1035 /* Standard bits passed on to the client */
1037 VkMemoryHeapFlags flags
;
1039 /** Driver-internal book-keeping.
1041 * Align it to 64 bits to make atomic operations faster on 32 bit platforms.
1043 VkDeviceSize used
__attribute__ ((aligned (8)));
1046 struct anv_physical_device
{
1047 struct vk_object_base base
;
1049 /* Link in anv_instance::physical_devices */
1050 struct list_head link
;
1052 struct anv_instance
* instance
;
1062 struct gen_device_info info
;
1063 /** Amount of "GPU memory" we want to advertise
1065 * Clearly, this value is bogus since Intel is a UMA architecture. On
1066 * gen7 platforms, we are limited by GTT size unless we want to implement
1067 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1068 * practically unlimited. However, we will never report more than 3/4 of
1069 * the total system ram to try and avoid running out of RAM.
1071 bool supports_48bit_addresses
;
1072 struct brw_compiler
* compiler
;
1073 struct isl_device isl_dev
;
1074 struct gen_perf_config
* perf
;
1075 int cmd_parser_version
;
1077 bool has_exec_async
;
1078 bool has_exec_capture
;
1079 bool has_exec_fence
;
1081 bool has_syncobj_wait
;
1082 bool has_syncobj_wait_available
;
1083 bool has_context_priority
;
1084 bool has_context_isolation
;
1085 bool has_thread_submit
;
1086 bool has_mem_available
;
1087 bool has_mmap_offset
;
1091 bool always_use_bindless
;
1092 bool use_call_secondary
;
1094 /** True if we can access buffers using A64 messages */
1095 bool has_a64_buffer_access
;
1096 /** True if we can use bindless access for images */
1097 bool has_bindless_images
;
1098 /** True if we can use bindless access for samplers */
1099 bool has_bindless_samplers
;
1100 /** True if we can use timeline semaphores through execbuf */
1101 bool has_exec_timeline
;
1103 /** True if we can read the GPU timestamp register
1105 * When running in a virtual context, the timestamp register is unreadable
1108 bool has_reg_timestamp
;
1110 /** True if this device has implicit AUX
1112 * If true, CCS is handled as an implicit attachment to the BO rather than
1113 * as an explicitly bound surface.
1115 bool has_implicit_ccs
;
1117 bool always_flush_cache
;
1119 struct anv_device_extension_table supported_extensions
;
1122 uint32_t subslice_total
;
1125 uint32_t type_count
;
1126 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1127 uint32_t heap_count
;
1128 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1131 uint8_t driver_build_sha1
[20];
1132 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1133 uint8_t driver_uuid
[VK_UUID_SIZE
];
1134 uint8_t device_uuid
[VK_UUID_SIZE
];
1136 struct disk_cache
* disk_cache
;
1138 struct wsi_device wsi_device
;
1143 struct anv_app_info
{
1144 const char* app_name
;
1145 uint32_t app_version
;
1146 const char* engine_name
;
1147 uint32_t engine_version
;
1148 uint32_t api_version
;
1151 struct anv_instance
{
1152 struct vk_object_base base
;
1154 VkAllocationCallbacks alloc
;
1156 struct anv_app_info app_info
;
1158 struct anv_instance_extension_table enabled_extensions
;
1159 struct anv_instance_dispatch_table dispatch
;
1160 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1161 struct anv_device_dispatch_table device_dispatch
;
1163 bool physical_devices_enumerated
;
1164 struct list_head physical_devices
;
1166 bool pipeline_cache_enabled
;
1168 struct vk_debug_report_instance debug_report_callbacks
;
1170 struct driOptionCache dri_options
;
1171 struct driOptionCache available_dri_options
;
1174 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1175 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1177 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1178 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1181 struct anv_queue_submit
{
1182 struct anv_cmd_buffer
* cmd_buffer
;
1184 uint32_t fence_count
;
1185 uint32_t fence_array_length
;
1186 struct drm_i915_gem_exec_fence
* fences
;
1187 uint64_t * fence_values
;
1189 uint32_t temporary_semaphore_count
;
1190 uint32_t temporary_semaphore_array_length
;
1191 struct anv_semaphore_impl
* temporary_semaphores
;
1193 /* Semaphores to be signaled with a SYNC_FD. */
1194 struct anv_semaphore
** sync_fd_semaphores
;
1195 uint32_t sync_fd_semaphore_count
;
1196 uint32_t sync_fd_semaphore_array_length
;
1198 /* Allocated only with non shareable timelines. */
1200 struct anv_timeline
** wait_timelines
;
1201 uint32_t * wait_timeline_syncobjs
;
1203 uint32_t wait_timeline_count
;
1204 uint32_t wait_timeline_array_length
;
1205 uint64_t * wait_timeline_values
;
1207 struct anv_timeline
** signal_timelines
;
1208 uint32_t signal_timeline_count
;
1209 uint32_t signal_timeline_array_length
;
1210 uint64_t * signal_timeline_values
;
1213 bool need_out_fence
;
1216 uint32_t fence_bo_count
;
1217 uint32_t fence_bo_array_length
;
1218 /* An array of struct anv_bo pointers with lower bit used as a flag to
1219 * signal we will wait on that BO (see anv_(un)pack_ptr).
1221 uintptr_t * fence_bos
;
1223 int perf_query_pass
;
1225 const VkAllocationCallbacks
* alloc
;
1226 VkSystemAllocationScope alloc_scope
;
1228 struct anv_bo
* simple_bo
;
1229 uint32_t simple_bo_size
;
1231 struct list_head link
;
1235 struct vk_object_base base
;
1237 struct anv_device
* device
;
1239 VkDeviceQueueCreateFlags flags
;
1241 /* Set once from the device api calls. */
1244 /* Only set once atomically by the queue */
1247 const char * error_file
;
1251 * This mutext protects the variables below.
1253 pthread_mutex_t mutex
;
1256 pthread_cond_t cond
;
1259 * A list of struct anv_queue_submit to be submitted to i915.
1261 struct list_head queued_submits
;
1263 /* Set to true to stop the submission thread */
1267 struct anv_pipeline_cache
{
1268 struct vk_object_base base
;
1269 struct anv_device
* device
;
1270 pthread_mutex_t mutex
;
1272 struct hash_table
* nir_cache
;
1274 struct hash_table
* cache
;
1279 struct nir_xfb_info
;
1280 struct anv_pipeline_bind_map
;
1282 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1283 struct anv_device
*device
,
1285 bool external_sync
);
1286 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1288 struct anv_shader_bin
*
1289 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1290 const void *key
, uint32_t key_size
);
1291 struct anv_shader_bin
*
1292 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1293 gl_shader_stage stage
,
1294 const void *key_data
, uint32_t key_size
,
1295 const void *kernel_data
, uint32_t kernel_size
,
1296 const struct brw_stage_prog_data
*prog_data
,
1297 uint32_t prog_data_size
,
1298 const struct brw_compile_stats
*stats
,
1300 const struct nir_xfb_info
*xfb_info
,
1301 const struct anv_pipeline_bind_map
*bind_map
);
1303 struct anv_shader_bin
*
1304 anv_device_search_for_kernel(struct anv_device
*device
,
1305 struct anv_pipeline_cache
*cache
,
1306 const void *key_data
, uint32_t key_size
,
1307 bool *user_cache_bit
);
1309 struct anv_shader_bin
*
1310 anv_device_upload_kernel(struct anv_device
*device
,
1311 struct anv_pipeline_cache
*cache
,
1312 gl_shader_stage stage
,
1313 const void *key_data
, uint32_t key_size
,
1314 const void *kernel_data
, uint32_t kernel_size
,
1315 const struct brw_stage_prog_data
*prog_data
,
1316 uint32_t prog_data_size
,
1317 const struct brw_compile_stats
*stats
,
1319 const struct nir_xfb_info
*xfb_info
,
1320 const struct anv_pipeline_bind_map
*bind_map
);
1323 struct nir_shader_compiler_options
;
1326 anv_device_search_for_nir(struct anv_device
*device
,
1327 struct anv_pipeline_cache
*cache
,
1328 const struct nir_shader_compiler_options
*nir_options
,
1329 unsigned char sha1_key
[20],
1333 anv_device_upload_nir(struct anv_device
*device
,
1334 struct anv_pipeline_cache
*cache
,
1335 const struct nir_shader
*nir
,
1336 unsigned char sha1_key
[20]);
1338 struct anv_address
{
1344 struct vk_device vk
;
1346 struct anv_physical_device
* physical
;
1348 struct gen_device_info info
;
1349 struct isl_device isl_dev
;
1352 bool can_chain_batches
;
1353 bool robust_buffer_access
;
1354 bool has_thread_submit
;
1355 struct anv_device_extension_table enabled_extensions
;
1356 struct anv_device_dispatch_table dispatch
;
1358 pthread_mutex_t vma_mutex
;
1359 struct util_vma_heap vma_lo
;
1360 struct util_vma_heap vma_cva
;
1361 struct util_vma_heap vma_hi
;
1363 /** List of all anv_device_memory objects */
1364 struct list_head memory_objects
;
1366 struct anv_bo_pool batch_bo_pool
;
1368 struct anv_bo_cache bo_cache
;
1370 struct anv_state_pool dynamic_state_pool
;
1371 struct anv_state_pool instruction_state_pool
;
1372 struct anv_state_pool binding_table_pool
;
1373 struct anv_state_pool surface_state_pool
;
1375 struct anv_state_reserved_pool custom_border_colors
;
1377 /** BO used for various workarounds
1379 * There are a number of workarounds on our hardware which require writing
1380 * data somewhere and it doesn't really matter where. For that, we use
1381 * this BO and just write to the first dword or so.
1383 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1384 * For that, we use the high bytes (>= 1024) of the workaround BO.
1386 struct anv_bo
* workaround_bo
;
1387 struct anv_address workaround_address
;
1389 struct anv_bo
* trivial_batch_bo
;
1390 struct anv_bo
* hiz_clear_bo
;
1391 struct anv_state null_surface_state
;
1393 struct anv_pipeline_cache default_pipeline_cache
;
1394 struct blorp_context blorp
;
1396 struct anv_state border_colors
;
1398 struct anv_state slice_hash
;
1400 struct anv_queue queue
;
1402 struct anv_scratch_pool scratch_pool
;
1404 pthread_mutex_t mutex
;
1405 pthread_cond_t queue_submit
;
1409 struct gen_batch_decode_ctx decoder_ctx
;
1411 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1412 * the cmd_buffer's list.
1414 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1416 int perf_fd
; /* -1 if no opened */
1417 uint64_t perf_metric
; /* 0 if unset */
1419 struct gen_aux_map_context
*aux_map_ctx
;
1421 struct gen_debug_block_frame
*debug_frame_desc
;
1424 static inline struct anv_instance
*
1425 anv_device_instance_or_null(const struct anv_device
*device
)
1427 return device
? device
->physical
->instance
: NULL
;
1430 static inline struct anv_state_pool
*
1431 anv_binding_table_pool(struct anv_device
*device
)
1433 if (device
->physical
->use_softpin
)
1434 return &device
->binding_table_pool
;
1436 return &device
->surface_state_pool
;
1439 static inline struct anv_state
1440 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1441 if (device
->physical
->use_softpin
)
1442 return anv_state_pool_alloc(&device
->binding_table_pool
,
1443 device
->binding_table_pool
.block_size
, 0);
1445 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1449 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1450 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1453 static inline uint32_t
1454 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1456 if (bo
->is_external
)
1457 return device
->isl_dev
.mocs
.external
;
1459 return device
->isl_dev
.mocs
.internal
;
1462 void anv_device_init_blorp(struct anv_device
*device
);
1463 void anv_device_finish_blorp(struct anv_device
*device
);
1465 void _anv_device_report_lost(struct anv_device
*device
);
1466 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1467 const char *file
, int line
,
1468 const char *msg
, ...)
1469 anv_printflike(4, 5);
1470 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1471 const char *file
, int line
,
1472 const char *msg
, ...)
1473 anv_printflike(4, 5);
1474 #define anv_device_set_lost(dev, ...) \
1475 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1476 #define anv_queue_set_lost(queue, ...) \
1477 (queue)->device->has_thread_submit ? \
1478 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__) : \
1479 _anv_device_set_lost(queue->device, __FILE__, __LINE__, __VA_ARGS__)
1482 anv_device_is_lost(struct anv_device
*device
)
1484 int lost
= p_atomic_read(&device
->_lost
);
1485 if (unlikely(lost
&& !device
->lost_reported
))
1486 _anv_device_report_lost(device
);
1490 VkResult
anv_device_query_status(struct anv_device
*device
);
1493 enum anv_bo_alloc_flags
{
1494 /** Specifies that the BO must have a 32-bit address
1496 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1498 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1500 /** Specifies that the BO may be shared externally */
1501 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1503 /** Specifies that the BO should be mapped */
1504 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1506 /** Specifies that the BO should be snooped so we get coherency */
1507 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1509 /** Specifies that the BO should be captured in error states */
1510 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1512 /** Specifies that the BO will have an address assigned by the caller
1514 * Such BOs do not exist in any VMA heap.
1516 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1518 /** Enables implicit synchronization on the BO
1520 * This is the opposite of EXEC_OBJECT_ASYNC.
1522 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1524 /** Enables implicit synchronization on the BO
1526 * This is equivalent to EXEC_OBJECT_WRITE.
1528 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1530 /** Has an address which is visible to the client */
1531 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1533 /** This buffer has implicit CCS data attached to it */
1534 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1537 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1538 enum anv_bo_alloc_flags alloc_flags
,
1539 uint64_t explicit_address
,
1540 struct anv_bo
**bo
);
1541 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1542 void *host_ptr
, uint32_t size
,
1543 enum anv_bo_alloc_flags alloc_flags
,
1544 uint64_t client_address
,
1545 struct anv_bo
**bo_out
);
1546 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1547 enum anv_bo_alloc_flags alloc_flags
,
1548 uint64_t client_address
,
1549 struct anv_bo
**bo
);
1550 VkResult
anv_device_export_bo(struct anv_device
*device
,
1551 struct anv_bo
*bo
, int *fd_out
);
1552 void anv_device_release_bo(struct anv_device
*device
,
1555 static inline struct anv_bo
*
1556 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1558 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1561 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1562 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1565 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1566 void anv_queue_finish(struct anv_queue
*queue
);
1568 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1569 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1570 struct anv_batch
*batch
);
1572 uint64_t anv_gettime_ns(void);
1573 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1575 void* anv_gem_mmap(struct anv_device
*device
,
1576 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1577 void anv_gem_munmap(struct anv_device
*device
, void *p
, uint64_t size
);
1578 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1579 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1580 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1581 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1582 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1583 int anv_gem_execbuffer(struct anv_device
*device
,
1584 struct drm_i915_gem_execbuffer2
*execbuf
);
1585 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1586 uint32_t stride
, uint32_t tiling
);
1587 int anv_gem_create_context(struct anv_device
*device
);
1588 bool anv_gem_has_context_priority(int fd
);
1589 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1590 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1592 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1594 int anv_gem_get_param(int fd
, uint32_t param
);
1595 uint64_t anv_gem_get_drm_cap(int fd
, uint32_t capability
);
1596 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1597 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1598 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1599 uint32_t *active
, uint32_t *pending
);
1600 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1601 int anv_gem_reg_read(int fd
, uint32_t offset
, uint64_t *result
);
1602 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1603 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1604 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1605 uint32_t read_domains
, uint32_t write_domain
);
1606 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1607 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1608 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1609 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1610 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1611 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1613 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1614 uint32_t handle
, int fd
);
1615 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1616 bool anv_gem_supports_syncobj_wait(int fd
);
1617 int anv_gem_syncobj_wait(struct anv_device
*device
,
1618 const uint32_t *handles
, uint32_t num_handles
,
1619 int64_t abs_timeout_ns
, bool wait_all
);
1620 int anv_gem_syncobj_timeline_wait(struct anv_device
*device
,
1621 const uint32_t *handles
, const uint64_t *points
,
1622 uint32_t num_items
, int64_t abs_timeout_ns
,
1623 bool wait_all
, bool wait_materialize
);
1624 int anv_gem_syncobj_timeline_signal(struct anv_device
*device
,
1625 const uint32_t *handles
, const uint64_t *points
,
1626 uint32_t num_items
);
1627 int anv_gem_syncobj_timeline_query(struct anv_device
*device
,
1628 const uint32_t *handles
, uint64_t *points
,
1629 uint32_t num_items
);
1631 uint64_t anv_vma_alloc(struct anv_device
*device
,
1632 uint64_t size
, uint64_t align
,
1633 enum anv_bo_alloc_flags alloc_flags
,
1634 uint64_t client_address
);
1635 void anv_vma_free(struct anv_device
*device
,
1636 uint64_t address
, uint64_t size
);
1638 struct anv_reloc_list
{
1639 uint32_t num_relocs
;
1640 uint32_t array_length
;
1641 struct drm_i915_gem_relocation_entry
* relocs
;
1642 struct anv_bo
** reloc_bos
;
1647 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1648 const VkAllocationCallbacks
*alloc
);
1649 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1650 const VkAllocationCallbacks
*alloc
);
1652 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1653 const VkAllocationCallbacks
*alloc
,
1654 uint32_t offset
, struct anv_bo
*target_bo
,
1655 uint32_t delta
, uint64_t *address_u64_out
);
1657 struct anv_batch_bo
{
1658 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1659 struct list_head link
;
1663 /* Bytes actually consumed in this batch BO */
1666 struct anv_reloc_list relocs
;
1670 const VkAllocationCallbacks
* alloc
;
1672 struct anv_address start_addr
;
1678 struct anv_reloc_list
* relocs
;
1680 /* This callback is called (with the associated user data) in the event
1681 * that the batch runs out of space.
1683 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1687 * Current error status of the command buffer. Used to track inconsistent
1688 * or incomplete command buffer states that are the consequence of run-time
1689 * errors such as out of memory scenarios. We want to track this in the
1690 * batch because the command buffer object is not visible to some parts
1696 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1697 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1698 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1699 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1700 struct anv_address
anv_batch_address(struct anv_batch
*batch
, void *batch_location
);
1703 anv_batch_set_storage(struct anv_batch
*batch
, struct anv_address addr
,
1704 void *map
, size_t size
)
1706 batch
->start_addr
= addr
;
1707 batch
->next
= batch
->start
= map
;
1708 batch
->end
= map
+ size
;
1711 static inline VkResult
1712 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1714 assert(error
!= VK_SUCCESS
);
1715 if (batch
->status
== VK_SUCCESS
)
1716 batch
->status
= error
;
1717 return batch
->status
;
1721 anv_batch_has_error(struct anv_batch
*batch
)
1723 return batch
->status
!= VK_SUCCESS
;
1726 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1729 anv_address_is_null(struct anv_address addr
)
1731 return addr
.bo
== NULL
&& addr
.offset
== 0;
1734 static inline uint64_t
1735 anv_address_physical(struct anv_address addr
)
1737 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1738 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1740 return gen_canonical_address(addr
.offset
);
1743 static inline struct anv_address
1744 anv_address_add(struct anv_address addr
, uint64_t offset
)
1746 addr
.offset
+= offset
;
1751 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1753 unsigned reloc_size
= 0;
1754 if (device
->info
.gen
>= 8) {
1755 reloc_size
= sizeof(uint64_t);
1756 *(uint64_t *)p
= gen_canonical_address(v
);
1758 reloc_size
= sizeof(uint32_t);
1762 if (flush
&& !device
->info
.has_llc
)
1763 gen_flush_range(p
, reloc_size
);
1766 static inline uint64_t
1767 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1768 const struct anv_address address
, uint32_t delta
)
1770 if (address
.bo
== NULL
) {
1771 return address
.offset
+ delta
;
1773 assert(batch
->start
<= location
&& location
< batch
->end
);
1775 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1779 #define __gen_address_type struct anv_address
1780 #define __gen_user_data struct anv_batch
1781 #define __gen_combine_address _anv_combine_address
1783 /* Wrapper macros needed to work around preprocessor argument issues. In
1784 * particular, arguments don't get pre-evaluated if they are concatenated.
1785 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1786 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1787 * We can work around this easily enough with these helpers.
1789 #define __anv_cmd_length(cmd) cmd ## _length
1790 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1791 #define __anv_cmd_header(cmd) cmd ## _header
1792 #define __anv_cmd_pack(cmd) cmd ## _pack
1793 #define __anv_reg_num(reg) reg ## _num
1795 #define anv_pack_struct(dst, struc, ...) do { \
1796 struct struc __template = { \
1799 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1800 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1803 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1804 void *__dst = anv_batch_emit_dwords(batch, n); \
1806 struct cmd __template = { \
1807 __anv_cmd_header(cmd), \
1808 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1811 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1816 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1820 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1821 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1824 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1825 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1826 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1829 #define anv_batch_emit(batch, cmd, name) \
1830 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1831 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1832 __builtin_expect(_dst != NULL, 1); \
1833 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1834 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1838 /* #define __gen_get_batch_dwords anv_batch_emit_dwords */
1839 /* #define __gen_get_batch_address anv_batch_address */
1840 /* #define __gen_address_value anv_address_physical */
1841 /* #define __gen_address_offset anv_address_add */
1843 struct anv_device_memory
{
1844 struct vk_object_base base
;
1846 struct list_head link
;
1849 struct anv_memory_type
* type
;
1850 VkDeviceSize map_size
;
1853 /* If set, we are holding reference to AHardwareBuffer
1854 * which we must release when memory is freed.
1856 struct AHardwareBuffer
* ahw
;
1858 /* If set, this memory comes from a host pointer. */
1863 * Header for Vertex URB Entry (VUE)
1865 struct anv_vue_header
{
1867 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1868 uint32_t ViewportIndex
;
1872 /** Struct representing a sampled image descriptor
1874 * This descriptor layout is used for sampled images, bare sampler, and
1875 * combined image/sampler descriptors.
1877 struct anv_sampled_image_descriptor
{
1878 /** Bindless image handle
1880 * This is expected to already be shifted such that the 20-bit
1881 * SURFACE_STATE table index is in the top 20 bits.
1885 /** Bindless sampler handle
1887 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1888 * to the dynamic state base address.
1893 struct anv_texture_swizzle_descriptor
{
1896 * See also nir_intrinsic_channel_select_intel
1900 /** Unused padding to ensure the struct is a multiple of 64 bits */
1904 /** Struct representing a storage image descriptor */
1905 struct anv_storage_image_descriptor
{
1906 /** Bindless image handles
1908 * These are expected to already be shifted such that the 20-bit
1909 * SURFACE_STATE table index is in the top 20 bits.
1911 uint32_t read_write
;
1912 uint32_t write_only
;
1915 /** Struct representing a address/range descriptor
1917 * The fields of this struct correspond directly to the data layout of
1918 * nir_address_format_64bit_bounded_global addresses. The last field is the
1919 * offset in the NIR address so it must be zero so that when you load the
1920 * descriptor you get a pointer to the start of the range.
1922 struct anv_address_range_descriptor
{
1928 enum anv_descriptor_data
{
1929 /** The descriptor contains a BTI reference to a surface state */
1930 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1931 /** The descriptor contains a BTI reference to a sampler state */
1932 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1933 /** The descriptor contains an actual buffer view */
1934 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1935 /** The descriptor contains auxiliary image layout data */
1936 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1937 /** The descriptor contains auxiliary image layout data */
1938 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1939 /** anv_address_range_descriptor with a buffer address and range */
1940 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1941 /** Bindless surface handle */
1942 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1943 /** Storage image handles */
1944 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1945 /** Storage image handles */
1946 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1949 struct anv_descriptor_set_binding_layout
{
1951 /* The type of the descriptors in this binding */
1952 VkDescriptorType type
;
1955 /* Flags provided when this binding was created */
1956 VkDescriptorBindingFlagsEXT flags
;
1958 /* Bitfield representing the type of data this descriptor contains */
1959 enum anv_descriptor_data data
;
1961 /* Maximum number of YCbCr texture/sampler planes */
1962 uint8_t max_plane_count
;
1964 /* Number of array elements in this binding (or size in bytes for inline
1967 uint16_t array_size
;
1969 /* Index into the flattend descriptor set */
1970 uint16_t descriptor_index
;
1972 /* Index into the dynamic state array for a dynamic buffer */
1973 int16_t dynamic_offset_index
;
1975 /* Index into the descriptor set buffer views */
1976 int16_t buffer_view_index
;
1978 /* Offset into the descriptor buffer where this descriptor lives */
1979 uint32_t descriptor_offset
;
1981 /* Immutable samplers (or NULL if no immutable samplers) */
1982 struct anv_sampler
**immutable_samplers
;
1985 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1987 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1988 VkDescriptorType type
);
1990 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1991 const struct anv_descriptor_set_binding_layout
*binding
,
1994 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1995 const struct anv_descriptor_set_binding_layout
*binding
,
1998 struct anv_descriptor_set_layout
{
1999 struct vk_object_base base
;
2001 /* Descriptor set layouts can be destroyed at almost any time */
2004 /* Number of bindings in this descriptor set */
2005 uint16_t binding_count
;
2007 /* Total size of the descriptor set with room for all array entries */
2010 /* Shader stages affected by this descriptor set */
2011 uint16_t shader_stages
;
2013 /* Number of buffer views in this descriptor set */
2014 uint16_t buffer_view_count
;
2016 /* Number of dynamic offsets used by this descriptor set */
2017 uint16_t dynamic_offset_count
;
2019 /* For each dynamic buffer, which VkShaderStageFlagBits stages are using
2022 VkShaderStageFlags dynamic_offset_stages
[MAX_DYNAMIC_BUFFERS
];
2024 /* Size of the descriptor buffer for this descriptor set */
2025 uint32_t descriptor_buffer_size
;
2027 /* Bindings in this descriptor set */
2028 struct anv_descriptor_set_binding_layout binding
[0];
2031 void anv_descriptor_set_layout_destroy(struct anv_device
*device
,
2032 struct anv_descriptor_set_layout
*layout
);
2035 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
2037 assert(layout
&& layout
->ref_cnt
>= 1);
2038 p_atomic_inc(&layout
->ref_cnt
);
2042 anv_descriptor_set_layout_unref(struct anv_device
*device
,
2043 struct anv_descriptor_set_layout
*layout
)
2045 assert(layout
&& layout
->ref_cnt
>= 1);
2046 if (p_atomic_dec_zero(&layout
->ref_cnt
))
2047 anv_descriptor_set_layout_destroy(device
, layout
);
2050 struct anv_descriptor
{
2051 VkDescriptorType type
;
2055 VkImageLayout layout
;
2056 struct anv_image_view
*image_view
;
2057 struct anv_sampler
*sampler
;
2061 struct anv_buffer
*buffer
;
2066 struct anv_buffer_view
*buffer_view
;
2070 struct anv_descriptor_set
{
2071 struct vk_object_base base
;
2073 struct anv_descriptor_pool
*pool
;
2074 struct anv_descriptor_set_layout
*layout
;
2076 /* Amount of space occupied in the the pool by this descriptor set. It can
2077 * be larger than the size of the descriptor set.
2081 /* State relative to anv_descriptor_pool::bo */
2082 struct anv_state desc_mem
;
2083 /* Surface state for the descriptor buffer */
2084 struct anv_state desc_surface_state
;
2086 uint32_t buffer_view_count
;
2087 struct anv_buffer_view
*buffer_views
;
2089 /* Link to descriptor pool's desc_sets list . */
2090 struct list_head pool_link
;
2092 struct anv_descriptor descriptors
[0];
2095 struct anv_buffer_view
{
2096 struct vk_object_base base
;
2098 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
2099 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2101 struct anv_address address
;
2103 struct anv_state surface_state
;
2104 struct anv_state storage_surface_state
;
2105 struct anv_state writeonly_storage_surface_state
;
2107 struct brw_image_param storage_image_param
;
2110 struct anv_push_descriptor_set
{
2111 struct anv_descriptor_set set
;
2113 /* Put this field right behind anv_descriptor_set so it fills up the
2114 * descriptors[0] field. */
2115 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
2117 /** True if the descriptor set buffer has been referenced by a draw or
2120 bool set_used_on_gpu
;
2122 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
2125 struct anv_descriptor_pool
{
2126 struct vk_object_base base
;
2133 struct util_vma_heap bo_heap
;
2135 struct anv_state_stream surface_state_stream
;
2136 void *surface_state_free_list
;
2138 struct list_head desc_sets
;
2143 enum anv_descriptor_template_entry_type
{
2144 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2145 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2146 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2149 struct anv_descriptor_template_entry
{
2150 /* The type of descriptor in this entry */
2151 VkDescriptorType type
;
2153 /* Binding in the descriptor set */
2156 /* Offset at which to write into the descriptor set binding */
2157 uint32_t array_element
;
2159 /* Number of elements to write into the descriptor set binding */
2160 uint32_t array_count
;
2162 /* Offset into the user provided data */
2165 /* Stride between elements into the user provided data */
2169 struct anv_descriptor_update_template
{
2170 struct vk_object_base base
;
2172 VkPipelineBindPoint bind_point
;
2174 /* The descriptor set this template corresponds to. This value is only
2175 * valid if the template was created with the templateType
2176 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2180 /* Number of entries in this template */
2181 uint32_t entry_count
;
2183 /* Entries of the template */
2184 struct anv_descriptor_template_entry entries
[0];
2188 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2191 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2192 struct anv_descriptor_set
*set
,
2193 const VkDescriptorImageInfo
* const info
,
2194 VkDescriptorType type
,
2199 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2200 struct anv_descriptor_set
*set
,
2201 VkDescriptorType type
,
2202 struct anv_buffer_view
*buffer_view
,
2207 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2208 struct anv_descriptor_set
*set
,
2209 struct anv_state_stream
*alloc_stream
,
2210 VkDescriptorType type
,
2211 struct anv_buffer
*buffer
,
2214 VkDeviceSize offset
,
2215 VkDeviceSize range
);
2217 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2218 struct anv_descriptor_set
*set
,
2225 anv_descriptor_set_write_template(struct anv_device
*device
,
2226 struct anv_descriptor_set
*set
,
2227 struct anv_state_stream
*alloc_stream
,
2228 const struct anv_descriptor_update_template
*template,
2232 anv_descriptor_set_create(struct anv_device
*device
,
2233 struct anv_descriptor_pool
*pool
,
2234 struct anv_descriptor_set_layout
*layout
,
2235 struct anv_descriptor_set
**out_set
);
2238 anv_descriptor_set_destroy(struct anv_device
*device
,
2239 struct anv_descriptor_pool
*pool
,
2240 struct anv_descriptor_set
*set
);
2242 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2243 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2244 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2245 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2246 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2247 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2249 struct anv_pipeline_binding
{
2250 /** Index in the descriptor set
2252 * This is a flattened index; the descriptor set layout is already taken
2257 /** The descriptor set this surface corresponds to.
2259 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2260 * binding is not a normal descriptor set but something else.
2265 /** Plane in the binding index for images */
2268 /** Input attachment index (relative to the subpass) */
2269 uint8_t input_attachment_index
;
2271 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2272 uint8_t dynamic_offset_index
;
2275 /** For a storage image, whether it is write-only */
2278 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2279 * assuming POD zero-initialization.
2284 struct anv_push_range
{
2285 /** Index in the descriptor set */
2288 /** Descriptor set index */
2291 /** Dynamic offset index (for dynamic UBOs) */
2292 uint8_t dynamic_offset_index
;
2294 /** Start offset in units of 32B */
2297 /** Range in units of 32B */
2301 struct anv_pipeline_layout
{
2302 struct vk_object_base base
;
2305 struct anv_descriptor_set_layout
*layout
;
2306 uint32_t dynamic_offset_start
;
2311 unsigned char sha1
[20];
2315 struct vk_object_base base
;
2317 struct anv_device
* device
;
2320 VkBufferUsageFlags usage
;
2322 /* Set when bound */
2323 struct anv_address address
;
2326 static inline uint64_t
2327 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2329 assert(offset
<= buffer
->size
);
2330 if (range
== VK_WHOLE_SIZE
) {
2331 return buffer
->size
- offset
;
2333 assert(range
+ offset
>= range
);
2334 assert(range
+ offset
<= buffer
->size
);
2339 enum anv_cmd_dirty_bits
{
2340 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2341 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2342 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2343 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2344 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2345 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2346 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2347 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2348 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2349 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2350 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2351 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2352 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2353 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2354 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE
= 1 << 14, /* VK_DYNAMIC_STATE_CULL_MODE_EXT */
2355 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE
= 1 << 15, /* VK_DYNAMIC_STATE_FRONT_FACE_EXT */
2356 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
= 1 << 16, /* VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT */
2357 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
= 1 << 17, /* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT */
2358 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
= 1 << 18, /* VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT */
2359 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
= 1 << 19, /* VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT */
2360 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
= 1 << 20, /* VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT */
2361 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
= 1 << 21, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT */
2362 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
= 1 << 22, /* VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT */
2363 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP
= 1 << 23, /* VK_DYNAMIC_STATE_STENCIL_OP_EXT */
2365 typedef uint32_t anv_cmd_dirty_mask_t
;
2367 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2368 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2369 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2370 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2371 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2372 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2373 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2374 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2375 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2376 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2377 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE | \
2378 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE | \
2379 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE | \
2380 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | \
2381 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE | \
2382 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | \
2383 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE | \
2384 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | \
2385 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE | \
2386 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE | \
2387 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2389 static inline enum anv_cmd_dirty_bits
2390 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2393 case VK_DYNAMIC_STATE_VIEWPORT
:
2394 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
2395 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2396 case VK_DYNAMIC_STATE_SCISSOR
:
2397 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
2398 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2399 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2400 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2401 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2402 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2403 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2404 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2405 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2406 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2407 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2408 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2409 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2410 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2411 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2412 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2413 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2414 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2415 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
2416 return ANV_CMD_DIRTY_DYNAMIC_CULL_MODE
;
2417 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
2418 return ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE
;
2419 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
2420 return ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
;
2421 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
2422 return ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
2423 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
2424 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
;
2425 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
2426 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
;
2427 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
2428 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
;
2429 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
2430 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
2431 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
2432 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
;
2433 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
2434 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP
;
2436 assert(!"Unsupported dynamic state");
2442 enum anv_pipe_bits
{
2443 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2444 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2445 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2446 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2447 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2448 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2449 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2450 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2451 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2452 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2453 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2454 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2455 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2457 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2458 * a flush has happened but not a CS stall. The next time we do any sort
2459 * of invalidation we need to insert a CS stall at that time. Otherwise,
2460 * we would have to CS stall on every flush which could be bad.
2462 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2464 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2465 * target operations related to transfer commands with VkBuffer as
2466 * destination are ongoing. Some operations like copies on the command
2467 * streamer might need to be aware of this to trigger the appropriate stall
2468 * before they can proceed with the copy.
2470 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2472 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2473 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2474 * done by writing the AUX-TT register.
2476 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2478 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2479 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2480 * implement a workaround for Gen9.
2482 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2485 #define ANV_PIPE_FLUSH_BITS ( \
2486 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2487 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2488 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2489 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2491 #define ANV_PIPE_STALL_BITS ( \
2492 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2493 ANV_PIPE_DEPTH_STALL_BIT | \
2494 ANV_PIPE_CS_STALL_BIT)
2496 #define ANV_PIPE_INVALIDATE_BITS ( \
2497 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2498 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2499 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2500 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2501 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2502 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2503 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2505 static inline enum anv_pipe_bits
2506 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2508 enum anv_pipe_bits pipe_bits
= 0;
2511 for_each_bit(b
, flags
) {
2512 switch ((VkAccessFlagBits
)(1 << b
)) {
2513 case VK_ACCESS_SHADER_WRITE_BIT
:
2514 /* We're transitioning a buffer that was previously used as write
2515 * destination through the data port. To make its content available
2516 * to future operations, flush the data cache.
2518 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2520 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2521 /* We're transitioning a buffer that was previously used as render
2522 * target. To make its content available to future operations, flush
2523 * the render target cache.
2525 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2527 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2528 /* We're transitioning a buffer that was previously used as depth
2529 * buffer. To make its content available to future operations, flush
2532 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2534 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2535 /* We're transitioning a buffer that was previously used as a
2536 * transfer write destination. Generic write operations include color
2537 * & depth operations as well as buffer operations like :
2538 * - vkCmdClearColorImage()
2539 * - vkCmdClearDepthStencilImage()
2540 * - vkCmdBlitImage()
2541 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2543 * Most of these operations are implemented using Blorp which writes
2544 * through the render target, so flush that cache to make it visible
2545 * to future operations. And for depth related operations we also
2546 * need to flush the depth cache.
2548 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2549 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2551 case VK_ACCESS_MEMORY_WRITE_BIT
:
2552 /* We're transitioning a buffer for generic write operations. Flush
2555 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2558 break; /* Nothing to do */
2565 static inline enum anv_pipe_bits
2566 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2568 enum anv_pipe_bits pipe_bits
= 0;
2571 for_each_bit(b
, flags
) {
2572 switch ((VkAccessFlagBits
)(1 << b
)) {
2573 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2574 /* Indirect draw commands take a buffer as input that we're going to
2575 * read from the command streamer to load some of the HW registers
2576 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2577 * command streamer stall so that all the cache flushes have
2578 * completed before the command streamer loads from memory.
2580 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2581 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2582 * through a vertex buffer, so invalidate that cache.
2584 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2585 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2586 * UBO from the buffer, so we need to invalidate constant cache.
2588 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2590 case VK_ACCESS_INDEX_READ_BIT
:
2591 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2592 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2593 * commands, so we invalidate the VF cache to make sure there is no
2594 * stale data when we start rendering.
2596 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2598 case VK_ACCESS_UNIFORM_READ_BIT
:
2599 /* We transitioning a buffer to be used as uniform data. Because
2600 * uniform is accessed through the data port & sampler, we need to
2601 * invalidate the texture cache (sampler) & constant cache (data
2602 * port) to avoid stale data.
2604 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2605 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2607 case VK_ACCESS_SHADER_READ_BIT
:
2608 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2609 case VK_ACCESS_TRANSFER_READ_BIT
:
2610 /* Transitioning a buffer to be read through the sampler, so
2611 * invalidate the texture cache, we don't want any stale data.
2613 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2615 case VK_ACCESS_MEMORY_READ_BIT
:
2616 /* Transitioning a buffer for generic read, invalidate all the
2619 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2621 case VK_ACCESS_MEMORY_WRITE_BIT
:
2622 /* Generic write, make sure all previously written things land in
2625 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2627 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2628 /* Transitioning a buffer for conditional rendering. We'll load the
2629 * content of this buffer into HW registers using the command
2630 * streamer, so we need to stall the command streamer to make sure
2631 * any in-flight flush operations have completed.
2633 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2636 break; /* Nothing to do */
2643 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2644 VK_IMAGE_ASPECT_COLOR_BIT | \
2645 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2646 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2647 VK_IMAGE_ASPECT_PLANE_2_BIT)
2648 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2649 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2650 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2651 VK_IMAGE_ASPECT_PLANE_2_BIT)
2653 struct anv_vertex_binding
{
2654 struct anv_buffer
* buffer
;
2655 VkDeviceSize offset
;
2656 VkDeviceSize stride
;
2660 struct anv_xfb_binding
{
2661 struct anv_buffer
* buffer
;
2662 VkDeviceSize offset
;
2666 struct anv_push_constants
{
2667 /** Push constant data provided by the client through vkPushConstants */
2668 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2670 /** Dynamic offsets for dynamic UBOs and SSBOs */
2671 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2673 /* Robust access pushed registers. */
2674 uint64_t push_reg_mask
[MESA_SHADER_STAGES
];
2676 /** Pad out to a multiple of 32 bytes */
2680 /** Base workgroup ID
2682 * Used for vkCmdDispatchBase.
2684 uint32_t base_work_group_id
[3];
2688 * This is never set by software but is implicitly filled out when
2689 * uploading the push constants for compute shaders.
2691 uint32_t subgroup_id
;
2695 struct anv_dynamic_state
{
2698 VkViewport viewports
[MAX_VIEWPORTS
];
2703 VkRect2D scissors
[MAX_SCISSORS
];
2714 float blend_constants
[4];
2724 } stencil_compare_mask
;
2729 } stencil_write_mask
;
2734 } stencil_reference
;
2738 VkStencilOp fail_op
;
2739 VkStencilOp pass_op
;
2740 VkStencilOp depth_fail_op
;
2741 VkCompareOp compare_op
;
2744 VkStencilOp fail_op
;
2745 VkStencilOp pass_op
;
2746 VkStencilOp depth_fail_op
;
2747 VkCompareOp compare_op
;
2756 VkCullModeFlags cull_mode
;
2757 VkFrontFace front_face
;
2758 VkPrimitiveTopology primitive_topology
;
2759 bool depth_test_enable
;
2760 bool depth_write_enable
;
2761 VkCompareOp depth_compare_op
;
2762 bool depth_bounds_test_enable
;
2763 bool stencil_test_enable
;
2764 bool dyn_vbo_stride
;
2768 extern const struct anv_dynamic_state default_dynamic_state
;
2770 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2771 const struct anv_dynamic_state
*src
,
2772 uint32_t copy_mask
);
2774 struct anv_surface_state
{
2775 struct anv_state state
;
2776 /** Address of the surface referred to by this state
2778 * This address is relative to the start of the BO.
2780 struct anv_address address
;
2781 /* Address of the aux surface, if any
2783 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2785 * With the exception of gen8, the bottom 12 bits of this address' offset
2786 * include extra aux information.
2788 struct anv_address aux_address
;
2789 /* Address of the clear color, if any
2791 * This address is relative to the start of the BO.
2793 struct anv_address clear_address
;
2797 * Attachment state when recording a renderpass instance.
2799 * The clear value is valid only if there exists a pending clear.
2801 struct anv_attachment_state
{
2802 enum isl_aux_usage aux_usage
;
2803 struct anv_surface_state color
;
2804 struct anv_surface_state input
;
2806 VkImageLayout current_layout
;
2807 VkImageLayout current_stencil_layout
;
2808 VkImageAspectFlags pending_clear_aspects
;
2809 VkImageAspectFlags pending_load_aspects
;
2811 VkClearValue clear_value
;
2813 /* When multiview is active, attachments with a renderpass clear
2814 * operation have their respective layers cleared on the first
2815 * subpass that uses them, and only in that subpass. We keep track
2816 * of this using a bitfield to indicate which layers of an attachment
2817 * have not been cleared yet when multiview is active.
2819 uint32_t pending_clear_views
;
2820 struct anv_image_view
* image_view
;
2823 /** State tracking for vertex buffer flushes
2825 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2826 * addresses. If you happen to have two vertex buffers which get placed
2827 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2828 * collisions. In order to solve this problem, we track vertex address ranges
2829 * which are live in the cache and invalidate the cache if one ever exceeds 32
2832 struct anv_vb_cache_range
{
2833 /* Virtual address at which the live vertex buffer cache range starts for
2834 * this vertex buffer index.
2838 /* Virtual address of the byte after where vertex buffer cache range ends.
2839 * This is exclusive such that end - start is the size of the range.
2844 /** State tracking for particular pipeline bind point
2846 * This struct is the base struct for anv_cmd_graphics_state and
2847 * anv_cmd_compute_state. These are used to track state which is bound to a
2848 * particular type of pipeline. Generic state that applies per-stage such as
2849 * binding table offsets and push constants is tracked generically with a
2850 * per-stage array in anv_cmd_state.
2852 struct anv_cmd_pipeline_state
{
2853 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2854 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2856 struct anv_push_constants push_constants
;
2858 /* Push constant state allocated when flushing push constants. */
2859 struct anv_state push_constants_state
;
2862 /** State tracking for graphics pipeline
2864 * This has anv_cmd_pipeline_state as a base struct to track things which get
2865 * bound to a graphics pipeline. Along with general pipeline bind point state
2866 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2867 * state which is graphics-specific.
2869 struct anv_cmd_graphics_state
{
2870 struct anv_cmd_pipeline_state base
;
2872 struct anv_graphics_pipeline
*pipeline
;
2874 anv_cmd_dirty_mask_t dirty
;
2877 struct anv_vb_cache_range ib_bound_range
;
2878 struct anv_vb_cache_range ib_dirty_range
;
2879 struct anv_vb_cache_range vb_bound_ranges
[33];
2880 struct anv_vb_cache_range vb_dirty_ranges
[33];
2882 VkShaderStageFlags push_constant_stages
;
2884 struct anv_dynamic_state dynamic
;
2886 uint32_t primitive_topology
;
2889 struct anv_buffer
*index_buffer
;
2890 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2891 uint32_t index_offset
;
2895 /** State tracking for compute pipeline
2897 * This has anv_cmd_pipeline_state as a base struct to track things which get
2898 * bound to a compute pipeline. Along with general pipeline bind point state
2899 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2900 * state which is compute-specific.
2902 struct anv_cmd_compute_state
{
2903 struct anv_cmd_pipeline_state base
;
2905 struct anv_compute_pipeline
*pipeline
;
2907 bool pipeline_dirty
;
2909 struct anv_address num_workgroups
;
2912 /** State required while building cmd buffer */
2913 struct anv_cmd_state
{
2914 /* PIPELINE_SELECT.PipelineSelection */
2915 uint32_t current_pipeline
;
2916 const struct gen_l3_config
* current_l3_config
;
2917 uint32_t last_aux_map_state
;
2919 struct anv_cmd_graphics_state gfx
;
2920 struct anv_cmd_compute_state compute
;
2922 enum anv_pipe_bits pending_pipe_bits
;
2923 VkShaderStageFlags descriptors_dirty
;
2924 VkShaderStageFlags push_constants_dirty
;
2926 struct anv_framebuffer
* framebuffer
;
2927 struct anv_render_pass
* pass
;
2928 struct anv_subpass
* subpass
;
2929 VkRect2D render_area
;
2930 uint32_t restart_index
;
2931 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2933 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2934 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2935 struct anv_state samplers
[MESA_SHADER_STAGES
];
2937 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2938 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2939 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2942 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2943 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2944 * and before invoking the secondary in ExecuteCommands.
2946 bool pma_fix_enabled
;
2949 * Whether or not we know for certain that HiZ is enabled for the current
2950 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2951 * enabled or not, this will be false.
2955 bool conditional_render_enabled
;
2958 * Last rendering scale argument provided to
2959 * genX(cmd_buffer_emit_hashing_mode)().
2961 unsigned current_hash_scale
;
2964 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2965 * valid only when recording a render pass instance.
2967 struct anv_attachment_state
* attachments
;
2970 * Surface states for color render targets. These are stored in a single
2971 * flat array. For depth-stencil attachments, the surface state is simply
2974 struct anv_state attachment_states
;
2977 * A null surface state of the right size to match the framebuffer. This
2978 * is one of the states in attachment_states.
2980 struct anv_state null_surface_state
;
2983 struct anv_cmd_pool
{
2984 struct vk_object_base base
;
2985 VkAllocationCallbacks alloc
;
2986 struct list_head cmd_buffers
;
2989 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2991 enum anv_cmd_buffer_exec_mode
{
2992 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2993 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2994 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2995 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2996 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2997 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN
,
3000 struct anv_cmd_buffer
{
3001 struct vk_object_base base
;
3003 struct anv_device
* device
;
3005 struct anv_cmd_pool
* pool
;
3006 struct list_head pool_link
;
3008 struct anv_batch batch
;
3010 /* Fields required for the actual chain of anv_batch_bo's.
3012 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
3014 struct list_head batch_bos
;
3015 enum anv_cmd_buffer_exec_mode exec_mode
;
3017 /* A vector of anv_batch_bo pointers for every batch or surface buffer
3018 * referenced by this command buffer
3020 * initialized by anv_cmd_buffer_init_batch_bo_chain()
3022 struct u_vector seen_bbos
;
3024 /* A vector of int32_t's for every block of binding tables.
3026 * initialized by anv_cmd_buffer_init_batch_bo_chain()
3028 struct u_vector bt_block_states
;
3029 struct anv_state bt_next
;
3031 struct anv_reloc_list surface_relocs
;
3032 /** Last seen surface state block pool center bo offset */
3033 uint32_t last_ss_pool_center
;
3035 /* Serial for tracking buffer completion */
3038 /* Stream objects for storing temporary data */
3039 struct anv_state_stream surface_state_stream
;
3040 struct anv_state_stream dynamic_state_stream
;
3042 VkCommandBufferUsageFlags usage_flags
;
3043 VkCommandBufferLevel level
;
3045 struct anv_query_pool
*perf_query_pool
;
3047 struct anv_cmd_state state
;
3049 struct anv_address return_addr
;
3051 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
3052 uint64_t intel_perf_marker
;
3055 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
3056 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
3057 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
3058 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
3059 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
3060 struct anv_cmd_buffer
*secondary
);
3061 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
3062 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
3063 struct anv_cmd_buffer
*cmd_buffer
,
3064 const VkSemaphore
*in_semaphores
,
3065 const uint64_t *in_wait_values
,
3066 uint32_t num_in_semaphores
,
3067 const VkSemaphore
*out_semaphores
,
3068 const uint64_t *out_signal_values
,
3069 uint32_t num_out_semaphores
,
3071 int perf_query_pass
);
3073 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
3075 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
3076 const void *data
, uint32_t size
, uint32_t alignment
);
3077 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
3078 uint32_t *a
, uint32_t *b
,
3079 uint32_t dwords
, uint32_t alignment
);
3082 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
3084 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
3085 uint32_t entries
, uint32_t *state_offset
);
3087 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
3089 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
3090 uint32_t size
, uint32_t alignment
);
3093 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
3095 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
3096 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
3097 bool depth_clamp_enable
);
3098 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
3100 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
3101 struct anv_render_pass
*pass
,
3102 struct anv_framebuffer
*framebuffer
,
3103 const VkClearValue
*clear_values
);
3105 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
3108 anv_cmd_buffer_gfx_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
3110 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
3112 const struct anv_image_view
*
3113 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
3116 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
3117 uint32_t num_entries
,
3118 uint32_t *state_offset
,
3119 struct anv_state
*bt_state
);
3121 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
3123 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
3125 enum anv_fence_type
{
3126 ANV_FENCE_TYPE_NONE
= 0,
3128 ANV_FENCE_TYPE_WSI_BO
,
3129 ANV_FENCE_TYPE_SYNCOBJ
,
3133 enum anv_bo_fence_state
{
3134 /** Indicates that this is a new (or newly reset fence) */
3135 ANV_BO_FENCE_STATE_RESET
,
3137 /** Indicates that this fence has been submitted to the GPU but is still
3138 * (as far as we know) in use by the GPU.
3140 ANV_BO_FENCE_STATE_SUBMITTED
,
3142 ANV_BO_FENCE_STATE_SIGNALED
,
3145 struct anv_fence_impl
{
3146 enum anv_fence_type type
;
3149 /** Fence implementation for BO fences
3151 * These fences use a BO and a set of CPU-tracked state flags. The BO
3152 * is added to the object list of the last execbuf call in a QueueSubmit
3153 * and is marked EXEC_WRITE. The state flags track when the BO has been
3154 * submitted to the kernel. We need to do this because Vulkan lets you
3155 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
3156 * will say it's idle in this case.
3160 enum anv_bo_fence_state state
;
3163 /** DRM syncobj handle for syncobj-based fences */
3167 struct wsi_fence
*fence_wsi
;
3172 struct vk_object_base base
;
3174 /* Permanent fence state. Every fence has some form of permanent state
3175 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3176 * cross-process fences) or it could just be a dummy for use internally.
3178 struct anv_fence_impl permanent
;
3180 /* Temporary fence state. A fence *may* have temporary state. That state
3181 * is added to the fence by an import operation and is reset back to
3182 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3183 * state cannot be signaled because the fence must already be signaled
3184 * before the temporary state can be exported from the fence in the other
3185 * process and imported here.
3187 struct anv_fence_impl temporary
;
3190 void anv_fence_reset_temporary(struct anv_device
*device
,
3191 struct anv_fence
*fence
);
3194 struct vk_object_base base
;
3196 struct anv_state state
;
3199 enum anv_semaphore_type
{
3200 ANV_SEMAPHORE_TYPE_NONE
= 0,
3201 ANV_SEMAPHORE_TYPE_DUMMY
,
3202 ANV_SEMAPHORE_TYPE_BO
,
3203 ANV_SEMAPHORE_TYPE_WSI_BO
,
3204 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
3205 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
3206 ANV_SEMAPHORE_TYPE_TIMELINE
,
3207 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ_TIMELINE
,
3210 struct anv_timeline_point
{
3211 struct list_head link
;
3215 /* Number of waiter on this point, when > 0 the point should not be garbage
3220 /* BO used for synchronization. */
3224 struct anv_timeline
{
3225 pthread_mutex_t mutex
;
3226 pthread_cond_t cond
;
3228 uint64_t highest_past
;
3229 uint64_t highest_pending
;
3231 struct list_head points
;
3232 struct list_head free_points
;
3235 struct anv_semaphore_impl
{
3236 enum anv_semaphore_type type
;
3239 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3240 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3241 * object list on any execbuf2 calls for which this semaphore is used as
3242 * a wait or signal fence. When used as a signal fence or when type ==
3243 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3247 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3248 * If the semaphore is in the unsignaled state due to either just being
3249 * created or because it has been used for a wait, fd will be -1.
3253 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3254 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3255 * import so we don't need to bother with a userspace cache.
3259 /* Non shareable timeline semaphore
3261 * Used when kernel don't have support for timeline semaphores.
3263 struct anv_timeline timeline
;
3267 struct anv_semaphore
{
3268 struct vk_object_base base
;
3272 /* Permanent semaphore state. Every semaphore has some form of permanent
3273 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3274 * (for cross-process semaphores0 or it could just be a dummy for use
3277 struct anv_semaphore_impl permanent
;
3279 /* Temporary semaphore state. A semaphore *may* have temporary state.
3280 * That state is added to the semaphore by an import operation and is reset
3281 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3282 * semaphore with temporary state cannot be signaled because the semaphore
3283 * must already be signaled before the temporary state can be exported from
3284 * the semaphore in the other process and imported here.
3286 struct anv_semaphore_impl temporary
;
3289 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3290 struct anv_semaphore
*semaphore
);
3292 struct anv_shader_module
{
3293 struct vk_object_base base
;
3295 unsigned char sha1
[20];
3300 static inline gl_shader_stage
3301 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3303 assert(__builtin_popcount(vk_stage
) == 1);
3304 return ffs(vk_stage
) - 1;
3307 static inline VkShaderStageFlagBits
3308 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3310 return (1 << mesa_stage
);
3313 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3315 #define anv_foreach_stage(stage, stage_bits) \
3316 for (gl_shader_stage stage, \
3317 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3318 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3319 __tmp &= ~(1 << (stage)))
3321 enum anv_shader_reloc
{
3322 ANV_SHADER_RELOC_CONST_DATA_ADDR_LOW
,
3323 ANV_SHADER_RELOC_CONST_DATA_ADDR_HIGH
,
3326 struct anv_pipeline_bind_map
{
3327 unsigned char surface_sha1
[20];
3328 unsigned char sampler_sha1
[20];
3329 unsigned char push_sha1
[20];
3331 uint32_t surface_count
;
3332 uint32_t sampler_count
;
3334 struct anv_pipeline_binding
* surface_to_descriptor
;
3335 struct anv_pipeline_binding
* sampler_to_descriptor
;
3337 struct anv_push_range push_ranges
[4];
3340 struct anv_shader_bin_key
{
3345 struct anv_shader_bin
{
3348 gl_shader_stage stage
;
3350 const struct anv_shader_bin_key
*key
;
3352 struct anv_state kernel
;
3353 uint32_t kernel_size
;
3355 const struct brw_stage_prog_data
*prog_data
;
3356 uint32_t prog_data_size
;
3358 struct brw_compile_stats stats
[3];
3361 struct nir_xfb_info
*xfb_info
;
3363 struct anv_pipeline_bind_map bind_map
;
3366 struct anv_shader_bin
*
3367 anv_shader_bin_create(struct anv_device
*device
,
3368 gl_shader_stage stage
,
3369 const void *key
, uint32_t key_size
,
3370 const void *kernel
, uint32_t kernel_size
,
3371 const struct brw_stage_prog_data
*prog_data
,
3372 uint32_t prog_data_size
,
3373 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3374 const struct nir_xfb_info
*xfb_info
,
3375 const struct anv_pipeline_bind_map
*bind_map
);
3378 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3381 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3383 assert(shader
&& shader
->ref_cnt
>= 1);
3384 p_atomic_inc(&shader
->ref_cnt
);
3388 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3390 assert(shader
&& shader
->ref_cnt
>= 1);
3391 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3392 anv_shader_bin_destroy(device
, shader
);
3395 struct anv_pipeline_executable
{
3396 gl_shader_stage stage
;
3398 struct brw_compile_stats stats
;
3404 enum anv_pipeline_type
{
3405 ANV_PIPELINE_GRAPHICS
,
3406 ANV_PIPELINE_COMPUTE
,
3409 struct anv_pipeline
{
3410 struct vk_object_base base
;
3412 struct anv_device
* device
;
3414 struct anv_batch batch
;
3415 struct anv_reloc_list batch_relocs
;
3419 enum anv_pipeline_type type
;
3420 VkPipelineCreateFlags flags
;
3422 struct util_dynarray executables
;
3424 const struct gen_l3_config
* l3_config
;
3427 struct anv_graphics_pipeline
{
3428 struct anv_pipeline base
;
3430 uint32_t batch_data
[512];
3432 anv_cmd_dirty_mask_t dynamic_state_mask
;
3433 struct anv_dynamic_state dynamic_state
;
3437 struct anv_subpass
* subpass
;
3439 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3441 VkShaderStageFlags active_stages
;
3443 bool primitive_restart
;
3445 bool depth_test_enable
;
3446 bool writes_stencil
;
3447 bool stencil_test_enable
;
3448 bool depth_clamp_enable
;
3449 bool depth_clip_enable
;
3450 bool sample_shading_enable
;
3452 bool depth_bounds_test_enable
;
3454 /* When primitive replication is used, subpass->view_mask will describe what
3455 * views to replicate.
3457 bool use_primitive_replication
;
3459 struct anv_state blend_state
;
3462 struct anv_pipeline_vertex_binding
{
3465 uint32_t instance_divisor
;
3470 uint32_t depth_stencil_state
[3];
3477 uint32_t wm_depth_stencil
[3];
3481 uint32_t wm_depth_stencil
[4];
3485 struct anv_compute_pipeline
{
3486 struct anv_pipeline base
;
3488 struct anv_shader_bin
* cs
;
3489 uint32_t cs_right_mask
;
3490 uint32_t batch_data
[9];
3491 uint32_t interface_descriptor_data
[8];
3494 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3495 static inline struct anv_##pipe_type##_pipeline * \
3496 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3498 assert(pipeline->type == pipe_enum); \
3499 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3502 ANV_DECL_PIPELINE_DOWNCAST(graphics
, ANV_PIPELINE_GRAPHICS
)
3503 ANV_DECL_PIPELINE_DOWNCAST(compute
, ANV_PIPELINE_COMPUTE
)
3506 anv_pipeline_has_stage(const struct anv_graphics_pipeline
*pipeline
,
3507 gl_shader_stage stage
)
3509 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3512 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3513 static inline const struct brw_##prefix##_prog_data * \
3514 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3516 if (anv_pipeline_has_stage(pipeline, stage)) { \
3517 return (const struct brw_##prefix##_prog_data *) \
3518 pipeline->shaders[stage]->prog_data; \
3524 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3525 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3526 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3527 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3528 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3530 static inline const struct brw_cs_prog_data
*
3531 get_cs_prog_data(const struct anv_compute_pipeline
*pipeline
)
3533 assert(pipeline
->cs
);
3534 return (const struct brw_cs_prog_data
*) pipeline
->cs
->prog_data
;
3537 static inline const struct brw_vue_prog_data
*
3538 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline
*pipeline
)
3540 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3541 return &get_gs_prog_data(pipeline
)->base
;
3542 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3543 return &get_tes_prog_data(pipeline
)->base
;
3545 return &get_vs_prog_data(pipeline
)->base
;
3549 anv_pipeline_init(struct anv_pipeline
*pipeline
,
3550 struct anv_device
*device
,
3551 enum anv_pipeline_type type
,
3552 VkPipelineCreateFlags flags
,
3553 const VkAllocationCallbacks
*pAllocator
);
3556 anv_pipeline_finish(struct anv_pipeline
*pipeline
,
3557 struct anv_device
*device
,
3558 const VkAllocationCallbacks
*pAllocator
);
3561 anv_graphics_pipeline_init(struct anv_graphics_pipeline
*pipeline
, struct anv_device
*device
,
3562 struct anv_pipeline_cache
*cache
,
3563 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3564 const VkAllocationCallbacks
*alloc
);
3567 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
3568 struct anv_pipeline_cache
*cache
,
3569 const VkComputePipelineCreateInfo
*info
,
3570 const struct anv_shader_module
*module
,
3571 const char *entrypoint
,
3572 const VkSpecializationInfo
*spec_info
);
3574 struct anv_cs_parameters
{
3575 uint32_t group_size
;
3580 struct anv_cs_parameters
3581 anv_cs_parameters(const struct anv_compute_pipeline
*pipeline
);
3583 struct anv_format_plane
{
3584 enum isl_format isl_format
:16;
3585 struct isl_swizzle swizzle
;
3587 /* Whether this plane contains chroma channels */
3590 /* For downscaling of YUV planes */
3591 uint8_t denominator_scales
[2];
3593 /* How to map sampled ycbcr planes to a single 4 component element. */
3594 struct isl_swizzle ycbcr_swizzle
;
3596 /* What aspect is associated to this plane */
3597 VkImageAspectFlags aspect
;
3602 struct anv_format_plane planes
[3];
3609 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3610 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3611 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3612 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3614 static inline uint32_t
3615 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3616 VkImageAspectFlags aspect_mask
)
3618 switch (aspect_mask
) {
3619 case VK_IMAGE_ASPECT_COLOR_BIT
:
3620 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3621 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3623 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3624 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3627 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3629 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3632 /* Purposefully assert with depth/stencil aspects. */
3633 unreachable("invalid image aspect");
3637 static inline VkImageAspectFlags
3638 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3641 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3642 if (util_bitcount(image_aspects
) > 1)
3643 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3644 return VK_IMAGE_ASPECT_COLOR_BIT
;
3646 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3647 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3648 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3649 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3652 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3653 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3655 const struct anv_format
*
3656 anv_get_format(VkFormat format
);
3658 static inline uint32_t
3659 anv_get_format_planes(VkFormat vk_format
)
3661 const struct anv_format
*format
= anv_get_format(vk_format
);
3663 return format
!= NULL
? format
->n_planes
: 0;
3666 struct anv_format_plane
3667 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3668 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3670 static inline enum isl_format
3671 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3672 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3674 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3677 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3678 VkImageCreateFlags create_flags
,
3680 VkImageTiling vk_tiling
,
3681 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3683 static inline struct isl_swizzle
3684 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3686 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3687 * RGB as RGBA for texturing
3689 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3690 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3692 /* But it doesn't matter what we render to that channel */
3693 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3699 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3702 * Subsurface of an anv_image.
3704 struct anv_surface
{
3705 /** Valid only if isl_surf::size_B > 0. */
3706 struct isl_surf isl
;
3709 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3715 struct vk_object_base base
;
3717 VkImageType type
; /**< VkImageCreateInfo::imageType */
3718 /* The original VkFormat provided by the client. This may not match any
3719 * of the actual surface formats.
3722 const struct anv_format
*format
;
3724 VkImageAspectFlags aspects
;
3727 uint32_t array_size
;
3728 uint32_t samples
; /**< VkImageCreateInfo::samples */
3730 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3731 VkImageUsageFlags stencil_usage
;
3732 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3733 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3735 /** True if this is needs to be bound to an appropriately tiled BO.
3737 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3738 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3739 * we require a dedicated allocation so that we can know to allocate a
3742 bool needs_set_tiling
;
3745 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3746 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3748 uint64_t drm_format_mod
;
3753 /* Whether the image is made of several underlying buffer objects rather a
3754 * single one with different offsets.
3758 /* Image was created with external format. */
3759 bool external_format
;
3764 * For each foo, anv_image::planes[x].surface is valid if and only if
3765 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3766 * to figure the number associated with a given aspect.
3768 * The hardware requires that the depth buffer and stencil buffer be
3769 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3770 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3771 * allocate the depth and stencil buffers as separate surfaces in the same
3776 * -----------------------
3778 * ----------------------- |
3779 * | shadow surface0 | |
3780 * ----------------------- | Plane 0
3781 * | aux surface0 | |
3782 * ----------------------- |
3783 * | fast clear colors0 | \|/
3784 * -----------------------
3786 * ----------------------- |
3787 * | shadow surface1 | |
3788 * ----------------------- | Plane 1
3789 * | aux surface1 | |
3790 * ----------------------- |
3791 * | fast clear colors1 | \|/
3792 * -----------------------
3795 * -----------------------
3799 * Offset of the entire plane (whenever the image is disjoint this is
3807 struct anv_surface surface
;
3810 * A surface which shadows the main surface and may have different
3811 * tiling. This is used for sampling using a tiling that isn't supported
3812 * for other operations.
3814 struct anv_surface shadow_surface
;
3817 * The base aux usage for this image. For color images, this can be
3818 * either CCS_E or CCS_D depending on whether or not we can reliably
3819 * leave CCS on all the time.
3821 enum isl_aux_usage aux_usage
;
3823 struct anv_surface aux_surface
;
3826 * Offset of the fast clear state (used to compute the
3827 * fast_clear_state_offset of the following planes).
3829 uint32_t fast_clear_state_offset
;
3832 * BO associated with this plane, set when bound.
3834 struct anv_address address
;
3837 * When destroying the image, also free the bo.
3843 /* The ordering of this enum is important */
3844 enum anv_fast_clear_type
{
3845 /** Image does not have/support any fast-clear blocks */
3846 ANV_FAST_CLEAR_NONE
= 0,
3847 /** Image has/supports fast-clear but only to the default value */
3848 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3849 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3850 ANV_FAST_CLEAR_ANY
= 2,
3853 /* Returns the number of auxiliary buffer levels attached to an image. */
3854 static inline uint8_t
3855 anv_image_aux_levels(const struct anv_image
* const image
,
3856 VkImageAspectFlagBits aspect
)
3858 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3859 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3862 /* The Gen12 CCS aux surface is represented with only one level. */
3863 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3864 image
->planes
[plane
].surface
.isl
.levels
:
3865 image
->planes
[plane
].aux_surface
.isl
.levels
;
3868 /* Returns the number of auxiliary buffer layers attached to an image. */
3869 static inline uint32_t
3870 anv_image_aux_layers(const struct anv_image
* const image
,
3871 VkImageAspectFlagBits aspect
,
3872 const uint8_t miplevel
)
3876 /* The miplevel must exist in the main buffer. */
3877 assert(miplevel
< image
->levels
);
3879 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3880 /* There are no layers with auxiliary data because the miplevel has no
3885 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3887 /* The Gen12 CCS aux surface is represented with only one layer. */
3888 const struct isl_extent4d
*aux_logical_level0_px
=
3889 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3890 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3891 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3893 return MAX2(aux_logical_level0_px
->array_len
,
3894 aux_logical_level0_px
->depth
>> miplevel
);
3898 static inline struct anv_address
3899 anv_image_get_clear_color_addr(UNUSED
const struct anv_device
*device
,
3900 const struct anv_image
*image
,
3901 VkImageAspectFlagBits aspect
)
3903 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3905 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3906 return anv_address_add(image
->planes
[plane
].address
,
3907 image
->planes
[plane
].fast_clear_state_offset
);
3910 static inline struct anv_address
3911 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3912 const struct anv_image
*image
,
3913 VkImageAspectFlagBits aspect
)
3915 struct anv_address addr
=
3916 anv_image_get_clear_color_addr(device
, image
, aspect
);
3918 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3919 device
->isl_dev
.ss
.clear_color_state_size
:
3920 device
->isl_dev
.ss
.clear_value_size
;
3921 return anv_address_add(addr
, clear_color_state_size
);
3924 static inline struct anv_address
3925 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3926 const struct anv_image
*image
,
3927 VkImageAspectFlagBits aspect
,
3928 uint32_t level
, uint32_t array_layer
)
3930 assert(level
< anv_image_aux_levels(image
, aspect
));
3931 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3932 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3933 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3935 struct anv_address addr
=
3936 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3937 addr
.offset
+= 4; /* Go past the fast clear type */
3939 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3940 for (uint32_t l
= 0; l
< level
; l
++)
3941 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3943 addr
.offset
+= level
* image
->array_size
* 4;
3945 addr
.offset
+= array_layer
* 4;
3947 assert(addr
.offset
<
3948 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3952 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3954 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3955 const struct anv_image
*image
)
3957 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3960 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3961 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3964 * "If this field is set to AUX_HIZ, Number of Multisamples must
3965 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3967 if (image
->type
== VK_IMAGE_TYPE_3D
)
3970 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3971 * struct. There's documentation which suggests that this feature actually
3972 * reduces performance on BDW, but it has only been observed to help so
3973 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3974 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3976 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3979 return image
->samples
== 1;
3983 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3984 const struct anv_image
*image
,
3987 return device
->info
.has_aux_map
&&
3988 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3992 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3993 const struct anv_image
*image
,
3994 VkImageAspectFlagBits aspect
,
3995 enum isl_aux_usage aux_usage
,
3997 uint32_t base_layer
,
3998 uint32_t layer_count
);
4001 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
4002 const struct anv_image
*image
,
4003 VkImageAspectFlagBits aspect
,
4004 enum isl_aux_usage aux_usage
,
4005 enum isl_format format
, struct isl_swizzle swizzle
,
4006 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
4007 VkRect2D area
, union isl_color_value clear_color
);
4009 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
4010 const struct anv_image
*image
,
4011 VkImageAspectFlags aspects
,
4012 enum isl_aux_usage depth_aux_usage
,
4014 uint32_t base_layer
, uint32_t layer_count
,
4016 float depth_value
, uint8_t stencil_value
);
4018 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
4019 const struct anv_image
*src_image
,
4020 enum isl_aux_usage src_aux_usage
,
4021 uint32_t src_level
, uint32_t src_base_layer
,
4022 const struct anv_image
*dst_image
,
4023 enum isl_aux_usage dst_aux_usage
,
4024 uint32_t dst_level
, uint32_t dst_base_layer
,
4025 VkImageAspectFlagBits aspect
,
4026 uint32_t src_x
, uint32_t src_y
,
4027 uint32_t dst_x
, uint32_t dst_y
,
4028 uint32_t width
, uint32_t height
,
4029 uint32_t layer_count
,
4030 enum blorp_filter filter
);
4032 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
4033 const struct anv_image
*image
,
4034 VkImageAspectFlagBits aspect
, uint32_t level
,
4035 uint32_t base_layer
, uint32_t layer_count
,
4036 enum isl_aux_op hiz_op
);
4038 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
4039 const struct anv_image
*image
,
4040 VkImageAspectFlags aspects
,
4042 uint32_t base_layer
, uint32_t layer_count
,
4043 VkRect2D area
, uint8_t stencil_value
);
4045 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
4046 const struct anv_image
*image
,
4047 enum isl_format format
, struct isl_swizzle swizzle
,
4048 VkImageAspectFlagBits aspect
,
4049 uint32_t base_layer
, uint32_t layer_count
,
4050 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
4053 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
4054 const struct anv_image
*image
,
4055 enum isl_format format
, struct isl_swizzle swizzle
,
4056 VkImageAspectFlagBits aspect
, uint32_t level
,
4057 uint32_t base_layer
, uint32_t layer_count
,
4058 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
4062 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
4063 const struct anv_image
*image
,
4064 VkImageAspectFlagBits aspect
,
4065 uint32_t base_level
, uint32_t level_count
,
4066 uint32_t base_layer
, uint32_t layer_count
);
4069 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
4070 const struct anv_image
*image
,
4071 const VkImageAspectFlagBits aspect
,
4072 const VkImageLayout layout
);
4075 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
4076 const struct anv_image
*image
,
4077 const VkImageAspectFlagBits aspect
,
4078 const VkImageUsageFlagBits usage
,
4079 const VkImageLayout layout
);
4081 enum anv_fast_clear_type
4082 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
4083 const struct anv_image
* const image
,
4084 const VkImageAspectFlagBits aspect
,
4085 const VkImageLayout layout
);
4087 /* This is defined as a macro so that it works for both
4088 * VkImageSubresourceRange and VkImageSubresourceLayers
4090 #define anv_get_layerCount(_image, _range) \
4091 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
4092 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
4094 static inline uint32_t
4095 anv_get_levelCount(const struct anv_image
*image
,
4096 const VkImageSubresourceRange
*range
)
4098 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
4099 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
4102 static inline VkImageAspectFlags
4103 anv_image_expand_aspects(const struct anv_image
*image
,
4104 VkImageAspectFlags aspects
)
4106 /* If the underlying image has color plane aspects and
4107 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
4108 * the underlying image. */
4109 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
4110 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
4111 return image
->aspects
;
4117 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
4118 VkImageAspectFlags aspects2
)
4120 if (aspects1
== aspects2
)
4123 /* Only 1 color aspects are compatibles. */
4124 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
4125 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
4126 util_bitcount(aspects1
) == util_bitcount(aspects2
))
4132 struct anv_image_view
{
4133 struct vk_object_base base
;
4135 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
4137 VkImageAspectFlags aspect_mask
;
4139 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
4143 uint32_t image_plane
;
4145 struct isl_view isl
;
4148 * RENDER_SURFACE_STATE when using image as a sampler surface with an
4149 * image layout of SHADER_READ_ONLY_OPTIMAL or
4150 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
4152 struct anv_surface_state optimal_sampler_surface_state
;
4155 * RENDER_SURFACE_STATE when using image as a sampler surface with an
4156 * image layout of GENERAL.
4158 struct anv_surface_state general_sampler_surface_state
;
4161 * RENDER_SURFACE_STATE when using image as a storage image. Separate
4162 * states for write-only and readable, using the real format for
4163 * write-only and the lowered format for readable.
4165 struct anv_surface_state storage_surface_state
;
4166 struct anv_surface_state writeonly_storage_surface_state
;
4168 struct brw_image_param storage_image_param
;
4172 enum anv_image_view_state_flags
{
4173 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
4174 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
4177 void anv_image_fill_surface_state(struct anv_device
*device
,
4178 const struct anv_image
*image
,
4179 VkImageAspectFlagBits aspect
,
4180 const struct isl_view
*view
,
4181 isl_surf_usage_flags_t view_usage
,
4182 enum isl_aux_usage aux_usage
,
4183 const union isl_color_value
*clear_color
,
4184 enum anv_image_view_state_flags flags
,
4185 struct anv_surface_state
*state_inout
,
4186 struct brw_image_param
*image_param_out
);
4188 struct anv_image_create_info
{
4189 const VkImageCreateInfo
*vk_info
;
4191 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
4192 isl_tiling_flags_t isl_tiling_flags
;
4194 /** These flags will be added to any derived from VkImageCreateInfo. */
4195 isl_surf_usage_flags_t isl_extra_usage_flags
;
4198 bool external_format
;
4201 VkResult
anv_image_create(VkDevice _device
,
4202 const struct anv_image_create_info
*info
,
4203 const VkAllocationCallbacks
* alloc
,
4207 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
4209 static inline VkExtent3D
4210 anv_sanitize_image_extent(const VkImageType imageType
,
4211 const VkExtent3D imageExtent
)
4213 switch (imageType
) {
4214 case VK_IMAGE_TYPE_1D
:
4215 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
4216 case VK_IMAGE_TYPE_2D
:
4217 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
4218 case VK_IMAGE_TYPE_3D
:
4221 unreachable("invalid image type");
4225 static inline VkOffset3D
4226 anv_sanitize_image_offset(const VkImageType imageType
,
4227 const VkOffset3D imageOffset
)
4229 switch (imageType
) {
4230 case VK_IMAGE_TYPE_1D
:
4231 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
4232 case VK_IMAGE_TYPE_2D
:
4233 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
4234 case VK_IMAGE_TYPE_3D
:
4237 unreachable("invalid image type");
4241 VkFormatFeatureFlags
4242 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
4244 const struct anv_format
*anv_format
,
4245 VkImageTiling vk_tiling
);
4247 void anv_fill_buffer_surface_state(struct anv_device
*device
,
4248 struct anv_state state
,
4249 enum isl_format format
,
4250 struct anv_address address
,
4251 uint32_t range
, uint32_t stride
);
4254 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
4255 const struct anv_attachment_state
*att_state
,
4256 const struct anv_image_view
*iview
)
4258 const struct isl_format_layout
*view_fmtl
=
4259 isl_format_get_layout(iview
->planes
[0].isl
.format
);
4261 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
4262 if (view_fmtl->channels.c.bits) \
4263 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
4265 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
4266 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
4267 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
4268 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
4270 #undef COPY_CLEAR_COLOR_CHANNEL
4274 /* Haswell border color is a bit of a disaster. Float and unorm formats use a
4275 * straightforward 32-bit float color in the first 64 bytes. Instead of using
4276 * a nice float/integer union like Gen8+, Haswell specifies the integer border
4277 * color as a separate entry /after/ the float color. The layout of this entry
4278 * also depends on the format's bpp (with extra hacks for RG32), and overlaps.
4280 * Since we don't know the format/bpp, we can't make any of the border colors
4281 * containing '1' work for all formats, as it would be in the wrong place for
4282 * some of them. We opt to make 32-bit integers work as this seems like the
4283 * most common option. Fortunately, transparent black works regardless, as
4284 * all zeroes is the same in every bit-size.
4286 struct hsw_border_color
{
4290 uint32_t _pad1
[108];
4293 struct gen8_border_color
{
4298 /* Pad out to 64 bytes */
4302 struct anv_ycbcr_conversion
{
4303 struct vk_object_base base
;
4305 const struct anv_format
* format
;
4306 VkSamplerYcbcrModelConversion ycbcr_model
;
4307 VkSamplerYcbcrRange ycbcr_range
;
4308 VkComponentSwizzle mapping
[4];
4309 VkChromaLocation chroma_offsets
[2];
4310 VkFilter chroma_filter
;
4311 bool chroma_reconstruction
;
4314 struct anv_sampler
{
4315 struct vk_object_base base
;
4317 uint32_t state
[3][4];
4319 struct anv_ycbcr_conversion
*conversion
;
4321 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
4322 * and with a 32-byte stride for use as bindless samplers.
4324 struct anv_state bindless_state
;
4326 struct anv_state custom_border_color
;
4329 struct anv_framebuffer
{
4330 struct vk_object_base base
;
4336 uint32_t attachment_count
;
4337 struct anv_image_view
* attachments
[0];
4340 struct anv_subpass_attachment
{
4341 VkImageUsageFlagBits usage
;
4342 uint32_t attachment
;
4343 VkImageLayout layout
;
4345 /* Used only with attachment containing stencil data. */
4346 VkImageLayout stencil_layout
;
4349 struct anv_subpass
{
4350 uint32_t attachment_count
;
4353 * A pointer to all attachment references used in this subpass.
4354 * Only valid if ::attachment_count > 0.
4356 struct anv_subpass_attachment
* attachments
;
4357 uint32_t input_count
;
4358 struct anv_subpass_attachment
* input_attachments
;
4359 uint32_t color_count
;
4360 struct anv_subpass_attachment
* color_attachments
;
4361 struct anv_subpass_attachment
* resolve_attachments
;
4363 struct anv_subpass_attachment
* depth_stencil_attachment
;
4364 struct anv_subpass_attachment
* ds_resolve_attachment
;
4365 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4366 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4370 /** Subpass has a depth/stencil self-dependency */
4371 bool has_ds_self_dep
;
4373 /** Subpass has at least one color resolve attachment */
4374 bool has_color_resolve
;
4377 static inline unsigned
4378 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4380 return MAX2(1, util_bitcount(subpass
->view_mask
));
4383 struct anv_render_pass_attachment
{
4384 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4385 * its members individually.
4389 VkImageUsageFlags usage
;
4390 VkAttachmentLoadOp load_op
;
4391 VkAttachmentStoreOp store_op
;
4392 VkAttachmentLoadOp stencil_load_op
;
4393 VkImageLayout initial_layout
;
4394 VkImageLayout final_layout
;
4395 VkImageLayout first_subpass_layout
;
4397 VkImageLayout stencil_initial_layout
;
4398 VkImageLayout stencil_final_layout
;
4400 /* The subpass id in which the attachment will be used last. */
4401 uint32_t last_subpass_idx
;
4404 struct anv_render_pass
{
4405 struct vk_object_base base
;
4407 uint32_t attachment_count
;
4408 uint32_t subpass_count
;
4409 /* An array of subpass_count+1 flushes, one per subpass boundary */
4410 enum anv_pipe_bits
* subpass_flushes
;
4411 struct anv_render_pass_attachment
* attachments
;
4412 struct anv_subpass subpasses
[0];
4415 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4417 #define OA_SNAPSHOT_SIZE (256)
4418 #define ANV_KHR_PERF_QUERY_SIZE (ALIGN(sizeof(uint64_t), 64) + 2 * OA_SNAPSHOT_SIZE)
4420 struct anv_query_pool
{
4421 struct vk_object_base base
;
4424 VkQueryPipelineStatisticFlags pipeline_statistics
;
4425 /** Stride between slots, in bytes */
4427 /** Number of slots in this query pool */
4431 /* Perf queries : */
4432 struct anv_bo reset_bo
;
4433 uint32_t n_counters
;
4434 struct gen_perf_counter_pass
*counter_pass
;
4436 struct gen_perf_query_info
**pass_query
;
4439 static inline uint32_t khr_perf_query_preamble_offset(struct anv_query_pool
*pool
,
4442 return pass
* ANV_KHR_PERF_QUERY_SIZE
+ 8;
4445 int anv_get_instance_entrypoint_index(const char *name
);
4446 int anv_get_device_entrypoint_index(const char *name
);
4447 int anv_get_physical_device_entrypoint_index(const char *name
);
4449 const char *anv_get_instance_entry_name(int index
);
4450 const char *anv_get_physical_device_entry_name(int index
);
4451 const char *anv_get_device_entry_name(int index
);
4454 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4455 const struct anv_instance_extension_table
*instance
);
4457 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4458 const struct anv_instance_extension_table
*instance
);
4460 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4461 const struct anv_instance_extension_table
*instance
,
4462 const struct anv_device_extension_table
*device
);
4464 void *anv_resolve_device_entrypoint(const struct gen_device_info
*devinfo
,
4466 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4469 void anv_dump_image_to_ppm(struct anv_device
*device
,
4470 struct anv_image
*image
, unsigned miplevel
,
4471 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4472 const char *filename
);
4474 enum anv_dump_action
{
4475 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4481 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4485 void anv_dump_finish(void);
4487 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4489 static inline uint32_t
4490 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4492 /* This function must be called from within a subpass. */
4493 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4495 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4497 /* The id of this subpass shouldn't exceed the number of subpasses in this
4498 * render pass minus 1.
4500 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4504 struct anv_performance_configuration_intel
{
4505 struct vk_object_base base
;
4507 struct gen_perf_registers
*register_config
;
4512 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4513 void anv_device_perf_init(struct anv_device
*device
);
4514 void anv_perf_write_pass_results(struct gen_perf_config
*perf
,
4515 struct anv_query_pool
*pool
, uint32_t pass
,
4516 const struct gen_perf_query_result
*accumulated_results
,
4517 union VkPerformanceCounterResultKHR
*results
);
4519 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4520 VK_FROM_HANDLE(__anv_type, __name, __handle)
4522 VK_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, base
, VkCommandBuffer
,
4523 VK_OBJECT_TYPE_COMMAND_BUFFER
)
4524 VK_DEFINE_HANDLE_CASTS(anv_device
, vk
.base
, VkDevice
, VK_OBJECT_TYPE_DEVICE
)
4525 VK_DEFINE_HANDLE_CASTS(anv_instance
, base
, VkInstance
, VK_OBJECT_TYPE_INSTANCE
)
4526 VK_DEFINE_HANDLE_CASTS(anv_physical_device
, base
, VkPhysicalDevice
,
4527 VK_OBJECT_TYPE_PHYSICAL_DEVICE
)
4528 VK_DEFINE_HANDLE_CASTS(anv_queue
, base
, VkQueue
, VK_OBJECT_TYPE_QUEUE
)
4530 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, base
, VkCommandPool
,
4531 VK_OBJECT_TYPE_COMMAND_POOL
)
4532 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, base
, VkBuffer
,
4533 VK_OBJECT_TYPE_BUFFER
)
4534 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, base
, VkBufferView
,
4535 VK_OBJECT_TYPE_BUFFER_VIEW
)
4536 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, base
, VkDescriptorPool
,
4537 VK_OBJECT_TYPE_DESCRIPTOR_POOL
)
4538 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, base
, VkDescriptorSet
,
4539 VK_OBJECT_TYPE_DESCRIPTOR_SET
)
4540 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, base
,
4541 VkDescriptorSetLayout
,
4542 VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT
)
4543 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, base
,
4544 VkDescriptorUpdateTemplate
,
4545 VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE
)
4546 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, base
, VkDeviceMemory
,
4547 VK_OBJECT_TYPE_DEVICE_MEMORY
)
4548 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, base
, VkFence
, VK_OBJECT_TYPE_FENCE
)
4549 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, base
, VkEvent
, VK_OBJECT_TYPE_EVENT
)
4550 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, base
, VkFramebuffer
,
4551 VK_OBJECT_TYPE_FRAMEBUFFER
)
4552 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, base
, VkImage
, VK_OBJECT_TYPE_IMAGE
)
4553 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, base
, VkImageView
,
4554 VK_OBJECT_TYPE_IMAGE_VIEW
);
4555 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, base
, VkPipelineCache
,
4556 VK_OBJECT_TYPE_PIPELINE_CACHE
)
4557 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, base
, VkPipeline
,
4558 VK_OBJECT_TYPE_PIPELINE
)
4559 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, base
, VkPipelineLayout
,
4560 VK_OBJECT_TYPE_PIPELINE_LAYOUT
)
4561 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, base
, VkQueryPool
,
4562 VK_OBJECT_TYPE_QUERY_POOL
)
4563 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, base
, VkRenderPass
,
4564 VK_OBJECT_TYPE_RENDER_PASS
)
4565 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, base
, VkSampler
,
4566 VK_OBJECT_TYPE_SAMPLER
)
4567 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, base
, VkSemaphore
,
4568 VK_OBJECT_TYPE_SEMAPHORE
)
4569 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, base
, VkShaderModule
,
4570 VK_OBJECT_TYPE_SHADER_MODULE
)
4571 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, base
,
4572 VkSamplerYcbcrConversion
,
4573 VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION
)
4574 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_performance_configuration_intel
, base
,
4575 VkPerformanceConfigurationINTEL
,
4576 VK_OBJECT_TYPE_PERFORMANCE_CONFIGURATION_INTEL
)
4578 /* Gen-specific function declarations */
4580 # include "anv_genX.h"
4582 # define genX(x) gen7_##x
4583 # include "anv_genX.h"
4585 # define genX(x) gen75_##x
4586 # include "anv_genX.h"
4588 # define genX(x) gen8_##x
4589 # include "anv_genX.h"
4591 # define genX(x) gen9_##x
4592 # include "anv_genX.h"
4594 # define genX(x) gen10_##x
4595 # include "anv_genX.h"
4597 # define genX(x) gen11_##x
4598 # include "anv_genX.h"
4600 # define genX(x) gen12_##x
4601 # include "anv_genX.h"
4605 #endif /* ANV_PRIVATE_H */