54b1c730791bbd3eb6ed25a86ed61b9c8f4dd181
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include "drm-uapi/i915_drm.h"
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #ifndef NDEBUG
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
41 #endif
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
61 #include "util/vma.h"
62 #include "util/xmlconfig.h"
63 #include "vk_alloc.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 struct anv_batch;
75 struct anv_buffer;
76 struct anv_buffer_view;
77 struct anv_image_view;
78 struct anv_instance;
79
80 struct gen_aux_map_context;
81 struct gen_perf_config;
82 struct gen_perf_counter_pass;
83 struct gen_perf_query_result;
84
85 #include <vulkan/vulkan.h>
86 #include <vulkan/vulkan_intel.h>
87 #include <vulkan/vk_icd.h>
88
89 #include "anv_android.h"
90 #include "anv_entrypoints.h"
91 #include "anv_extensions.h"
92 #include "isl/isl.h"
93
94 #include "dev/gen_debug.h"
95 #include "common/intel_log.h"
96 #include "wsi_common.h"
97
98 #define NSEC_PER_SEC 1000000000ull
99
100 /* anv Virtual Memory Layout
101 * =========================
102 *
103 * When the anv driver is determining the virtual graphics addresses of memory
104 * objects itself using the softpin mechanism, the following memory ranges
105 * will be used.
106 *
107 * Three special considerations to notice:
108 *
109 * (1) the dynamic state pool is located within the same 4 GiB as the low
110 * heap. This is to work around a VF cache issue described in a comment in
111 * anv_physical_device_init_heaps.
112 *
113 * (2) the binding table pool is located at lower addresses than the surface
114 * state pool, within a 4 GiB range. This allows surface state base addresses
115 * to cover both binding tables (16 bit offsets) and surface states (32 bit
116 * offsets).
117 *
118 * (3) the last 4 GiB of the address space is withheld from the high
119 * heap. Various hardware units will read past the end of an object for
120 * various reasons. This healthy margin prevents reads from wrapping around
121 * 48-bit addresses.
122 */
123 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
124 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
125 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
126 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
127 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
128 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
129 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
130 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
131 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
132 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
133 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
134 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
135 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
136
137 #define LOW_HEAP_SIZE \
138 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
139 #define DYNAMIC_STATE_POOL_SIZE \
140 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
141 #define BINDING_TABLE_POOL_SIZE \
142 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
143 #define SURFACE_STATE_POOL_SIZE \
144 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
145 #define INSTRUCTION_STATE_POOL_SIZE \
146 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
147 #define CLIENT_VISIBLE_HEAP_SIZE \
148 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
149
150 /* Allowing different clear colors requires us to perform a depth resolve at
151 * the end of certain render passes. This is because while slow clears store
152 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
153 * See the PRMs for examples describing when additional resolves would be
154 * necessary. To enable fast clears without requiring extra resolves, we set
155 * the clear value to a globally-defined one. We could allow different values
156 * if the user doesn't expect coherent data during or after a render passes
157 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
158 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
159 * 1.0f seems to be the only value used. The only application that doesn't set
160 * this value does so through the usage of an seemingly uninitialized clear
161 * value.
162 */
163 #define ANV_HZ_FC_VAL 1.0f
164
165 #define MAX_VBS 28
166 #define MAX_XFB_BUFFERS 4
167 #define MAX_XFB_STREAMS 4
168 #define MAX_SETS 8
169 #define MAX_RTS 8
170 #define MAX_VIEWPORTS 16
171 #define MAX_SCISSORS 16
172 #define MAX_PUSH_CONSTANTS_SIZE 128
173 #define MAX_DYNAMIC_BUFFERS 16
174 #define MAX_IMAGES 64
175 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
176 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
177 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
178 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
179 * use 64 here to avoid cache issues. This could most likely bring it back to
180 * 32 if we had different virtual addresses for the different views on a given
181 * GEM object.
182 */
183 #define ANV_UBO_ALIGNMENT 64
184 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
185 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
186
187 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
188 *
189 * "The surface state model is used when a Binding Table Index (specified
190 * in the message descriptor) of less than 240 is specified. In this model,
191 * the Binding Table Index is used to index into the binding table, and the
192 * binding table entry contains a pointer to the SURFACE_STATE."
193 *
194 * Binding table values above 240 are used for various things in the hardware
195 * such as stateless, stateless with incoherent cache, SLM, and bindless.
196 */
197 #define MAX_BINDING_TABLE_SIZE 240
198
199 /* The kernel relocation API has a limitation of a 32-bit delta value
200 * applied to the address before it is written which, in spite of it being
201 * unsigned, is treated as signed . Because of the way that this maps to
202 * the Vulkan API, we cannot handle an offset into a buffer that does not
203 * fit into a signed 32 bits. The only mechanism we have for dealing with
204 * this at the moment is to limit all VkDeviceMemory objects to a maximum
205 * of 2GB each. The Vulkan spec allows us to do this:
206 *
207 * "Some platforms may have a limit on the maximum size of a single
208 * allocation. For example, certain systems may fail to create
209 * allocations with a size greater than or equal to 4GB. Such a limit is
210 * implementation-dependent, and if such a failure occurs then the error
211 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
212 *
213 * We don't use vk_error here because it's not an error so much as an
214 * indication to the application that the allocation is too large.
215 */
216 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
217
218 #define ANV_SVGS_VB_INDEX MAX_VBS
219 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
220
221 /* We reserve this MI ALU register for the purpose of handling predication.
222 * Other code which uses the MI ALU should leave it alone.
223 */
224 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
225
226 /* We reserve this MI ALU register to pass around an offset computed from
227 * VkPerformanceQuerySubmitInfoKHR::counterPassIndex VK_KHR_performance_query.
228 * Other code which uses the MI ALU should leave it alone.
229 */
230 #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
231
232 /* For gen12 we set the streamout buffers using 4 separate commands
233 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
234 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
235 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
236 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
237 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
238 * 3DSTATE_SO_BUFFER_INDEX_0.
239 */
240 #define SO_BUFFER_INDEX_0_CMD 0x60
241 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
242
243 static inline uint32_t
244 align_down_npot_u32(uint32_t v, uint32_t a)
245 {
246 return v - (v % a);
247 }
248
249 static inline uint32_t
250 align_down_u32(uint32_t v, uint32_t a)
251 {
252 assert(a != 0 && a == (a & -a));
253 return v & ~(a - 1);
254 }
255
256 static inline uint32_t
257 align_u32(uint32_t v, uint32_t a)
258 {
259 assert(a != 0 && a == (a & -a));
260 return align_down_u32(v + a - 1, a);
261 }
262
263 static inline uint64_t
264 align_down_u64(uint64_t v, uint64_t a)
265 {
266 assert(a != 0 && a == (a & -a));
267 return v & ~(a - 1);
268 }
269
270 static inline uint64_t
271 align_u64(uint64_t v, uint64_t a)
272 {
273 return align_down_u64(v + a - 1, a);
274 }
275
276 static inline int32_t
277 align_i32(int32_t v, int32_t a)
278 {
279 assert(a != 0 && a == (a & -a));
280 return (v + a - 1) & ~(a - 1);
281 }
282
283 /** Alignment must be a power of 2. */
284 static inline bool
285 anv_is_aligned(uintmax_t n, uintmax_t a)
286 {
287 assert(a == (a & -a));
288 return (n & (a - 1)) == 0;
289 }
290
291 static inline uint32_t
292 anv_minify(uint32_t n, uint32_t levels)
293 {
294 if (unlikely(n == 0))
295 return 0;
296 else
297 return MAX2(n >> levels, 1);
298 }
299
300 static inline float
301 anv_clamp_f(float f, float min, float max)
302 {
303 assert(min < max);
304
305 if (f > max)
306 return max;
307 else if (f < min)
308 return min;
309 else
310 return f;
311 }
312
313 static inline bool
314 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
315 {
316 if (*inout_mask & clear_mask) {
317 *inout_mask &= ~clear_mask;
318 return true;
319 } else {
320 return false;
321 }
322 }
323
324 static inline union isl_color_value
325 vk_to_isl_color(VkClearColorValue color)
326 {
327 return (union isl_color_value) {
328 .u32 = {
329 color.uint32[0],
330 color.uint32[1],
331 color.uint32[2],
332 color.uint32[3],
333 },
334 };
335 }
336
337 static inline void *anv_unpack_ptr(uintptr_t ptr, int bits, int *flags)
338 {
339 uintptr_t mask = (1ull << bits) - 1;
340 *flags = ptr & mask;
341 return (void *) (ptr & ~mask);
342 }
343
344 static inline uintptr_t anv_pack_ptr(void *ptr, int bits, int flags)
345 {
346 uintptr_t value = (uintptr_t) ptr;
347 uintptr_t mask = (1ull << bits) - 1;
348 return value | (mask & flags);
349 }
350
351 #define for_each_bit(b, dword) \
352 for (uint32_t __dword = (dword); \
353 (b) = __builtin_ffs(__dword) - 1, __dword; \
354 __dword &= ~(1 << (b)))
355
356 #define typed_memcpy(dest, src, count) ({ \
357 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
358 memcpy((dest), (src), (count) * sizeof(*(src))); \
359 })
360
361 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
362 * to be added here in order to utilize mapping in debug/error/perf macros.
363 */
364 #define REPORT_OBJECT_TYPE(o) \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
443 __builtin_choose_expr ( \
444 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
445 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
446 __builtin_choose_expr ( \
447 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
448 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
449 __builtin_choose_expr ( \
450 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
451 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
452 __builtin_choose_expr ( \
453 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
454 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
455 __builtin_choose_expr ( \
456 __builtin_types_compatible_p (__typeof (o), void*), \
457 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
458 /* The void expression results in a compile-time error \
459 when assigning the result to something. */ \
460 (void)0)))))))))))))))))))))))))))))))
461
462 /* Whenever we generate an error, pass it through this function. Useful for
463 * debugging, where we can break on it. Only call at error site, not when
464 * propagating errors. Might be useful to plug in a stack trace here.
465 */
466
467 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
468 VkDebugReportObjectTypeEXT type, VkResult error,
469 const char *file, int line, const char *format,
470 va_list args);
471
472 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
473 VkDebugReportObjectTypeEXT type, VkResult error,
474 const char *file, int line, const char *format, ...)
475 anv_printflike(7, 8);
476
477 #ifdef DEBUG
478 #define vk_error(error) __vk_errorf(NULL, NULL,\
479 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
480 error, __FILE__, __LINE__, NULL)
481 #define vk_errorfi(instance, obj, error, format, ...)\
482 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
483 __FILE__, __LINE__, format, ## __VA_ARGS__)
484 #define vk_errorf(device, obj, error, format, ...)\
485 vk_errorfi(anv_device_instance_or_null(device),\
486 obj, error, format, ## __VA_ARGS__)
487 #else
488 #define vk_error(error) error
489 #define vk_errorfi(instance, obj, error, format, ...) error
490 #define vk_errorf(device, obj, error, format, ...) error
491 #endif
492
493 /**
494 * Warn on ignored extension structs.
495 *
496 * The Vulkan spec requires us to ignore unsupported or unknown structs in
497 * a pNext chain. In debug mode, emitting warnings for ignored structs may
498 * help us discover structs that we should not have ignored.
499 *
500 *
501 * From the Vulkan 1.0.38 spec:
502 *
503 * Any component of the implementation (the loader, any enabled layers,
504 * and drivers) must skip over, without processing (other than reading the
505 * sType and pNext members) any chained structures with sType values not
506 * defined by extensions supported by that component.
507 */
508 #define anv_debug_ignored_stype(sType) \
509 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
510
511 void __anv_perf_warn(struct anv_device *device, const void *object,
512 VkDebugReportObjectTypeEXT type, const char *file,
513 int line, const char *format, ...)
514 anv_printflike(6, 7);
515 void anv_loge(const char *format, ...) anv_printflike(1, 2);
516 void anv_loge_v(const char *format, va_list va);
517
518 /**
519 * Print a FINISHME message, including its source location.
520 */
521 #define anv_finishme(format, ...) \
522 do { \
523 static bool reported = false; \
524 if (!reported) { \
525 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
526 ##__VA_ARGS__); \
527 reported = true; \
528 } \
529 } while (0)
530
531 /**
532 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
533 */
534 #define anv_perf_warn(instance, obj, format, ...) \
535 do { \
536 static bool reported = false; \
537 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
538 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
539 format, ##__VA_ARGS__); \
540 reported = true; \
541 } \
542 } while (0)
543
544 /* A non-fatal assert. Useful for debugging. */
545 #ifdef DEBUG
546 #define anv_assert(x) ({ \
547 if (unlikely(!(x))) \
548 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
549 })
550 #else
551 #define anv_assert(x)
552 #endif
553
554 /* A multi-pointer allocator
555 *
556 * When copying data structures from the user (such as a render pass), it's
557 * common to need to allocate data for a bunch of different things. Instead
558 * of doing several allocations and having to handle all of the error checking
559 * that entails, it can be easier to do a single allocation. This struct
560 * helps facilitate that. The intended usage looks like this:
561 *
562 * ANV_MULTIALLOC(ma)
563 * anv_multialloc_add(&ma, &main_ptr, 1);
564 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
565 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
566 *
567 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
568 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
569 */
570 struct anv_multialloc {
571 size_t size;
572 size_t align;
573
574 uint32_t ptr_count;
575 void **ptrs[8];
576 };
577
578 #define ANV_MULTIALLOC_INIT \
579 ((struct anv_multialloc) { 0, })
580
581 #define ANV_MULTIALLOC(_name) \
582 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
583
584 __attribute__((always_inline))
585 static inline void
586 _anv_multialloc_add(struct anv_multialloc *ma,
587 void **ptr, size_t size, size_t align)
588 {
589 size_t offset = align_u64(ma->size, align);
590 ma->size = offset + size;
591 ma->align = MAX2(ma->align, align);
592
593 /* Store the offset in the pointer. */
594 *ptr = (void *)(uintptr_t)offset;
595
596 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
597 ma->ptrs[ma->ptr_count++] = ptr;
598 }
599
600 #define anv_multialloc_add_size(_ma, _ptr, _size) \
601 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
602
603 #define anv_multialloc_add(_ma, _ptr, _count) \
604 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
605
606 __attribute__((always_inline))
607 static inline void *
608 anv_multialloc_alloc(struct anv_multialloc *ma,
609 const VkAllocationCallbacks *alloc,
610 VkSystemAllocationScope scope)
611 {
612 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
613 if (!ptr)
614 return NULL;
615
616 /* Fill out each of the pointers with their final value.
617 *
618 * for (uint32_t i = 0; i < ma->ptr_count; i++)
619 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
620 *
621 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
622 * constant, GCC is incapable of figuring this out and unrolling the loop
623 * so we have to give it a little help.
624 */
625 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
626 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
627 if ((_i) < ma->ptr_count) \
628 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
629 _ANV_MULTIALLOC_UPDATE_POINTER(0);
630 _ANV_MULTIALLOC_UPDATE_POINTER(1);
631 _ANV_MULTIALLOC_UPDATE_POINTER(2);
632 _ANV_MULTIALLOC_UPDATE_POINTER(3);
633 _ANV_MULTIALLOC_UPDATE_POINTER(4);
634 _ANV_MULTIALLOC_UPDATE_POINTER(5);
635 _ANV_MULTIALLOC_UPDATE_POINTER(6);
636 _ANV_MULTIALLOC_UPDATE_POINTER(7);
637 #undef _ANV_MULTIALLOC_UPDATE_POINTER
638
639 return ptr;
640 }
641
642 __attribute__((always_inline))
643 static inline void *
644 anv_multialloc_alloc2(struct anv_multialloc *ma,
645 const VkAllocationCallbacks *parent_alloc,
646 const VkAllocationCallbacks *alloc,
647 VkSystemAllocationScope scope)
648 {
649 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
650 }
651
652 struct anv_bo {
653 uint32_t gem_handle;
654
655 uint32_t refcount;
656
657 /* Index into the current validation list. This is used by the
658 * validation list building alrogithm to track which buffers are already
659 * in the validation list so that we can ensure uniqueness.
660 */
661 uint32_t index;
662
663 /* Index for use with util_sparse_array_free_list */
664 uint32_t free_index;
665
666 /* Last known offset. This value is provided by the kernel when we
667 * execbuf and is used as the presumed offset for the next bunch of
668 * relocations.
669 */
670 uint64_t offset;
671
672 /** Size of the buffer not including implicit aux */
673 uint64_t size;
674
675 /* Map for internally mapped BOs.
676 *
677 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
678 */
679 void *map;
680
681 /** Size of the implicit CCS range at the end of the buffer
682 *
683 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
684 * page of main surface data maps to a 256B chunk of CCS data and that
685 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
686 * addresses in the main surface to virtual memory addresses for CCS data.
687 *
688 * Because we can't change these maps around easily and because Vulkan
689 * allows two VkImages to be bound to overlapping memory regions (as long
690 * as the app is careful), it's not feasible to make this mapping part of
691 * the image. (On Gen11 and earlier, the mapping was provided via
692 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
693 * Instead, we attach the CCS data directly to the buffer object and setup
694 * the AUX table mapping at BO creation time.
695 *
696 * This field is for internal tracking use by the BO allocator only and
697 * should not be touched by other parts of the code. If something wants to
698 * know if a BO has implicit CCS data, it should instead look at the
699 * has_implicit_ccs boolean below.
700 *
701 * This data is not included in maps of this buffer.
702 */
703 uint32_t _ccs_size;
704
705 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
706 uint32_t flags;
707
708 /** True if this BO may be shared with other processes */
709 bool is_external:1;
710
711 /** True if this BO is a wrapper
712 *
713 * When set to true, none of the fields in this BO are meaningful except
714 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
715 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
716 * is set in the physical device.
717 */
718 bool is_wrapper:1;
719
720 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
721 bool has_fixed_address:1;
722
723 /** True if this BO wraps a host pointer */
724 bool from_host_ptr:1;
725
726 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
727 bool has_client_visible_address:1;
728
729 /** True if this BO has implicit CCS data attached to it */
730 bool has_implicit_ccs:1;
731 };
732
733 static inline struct anv_bo *
734 anv_bo_ref(struct anv_bo *bo)
735 {
736 p_atomic_inc(&bo->refcount);
737 return bo;
738 }
739
740 static inline struct anv_bo *
741 anv_bo_unwrap(struct anv_bo *bo)
742 {
743 while (bo->is_wrapper)
744 bo = bo->map;
745 return bo;
746 }
747
748 /* Represents a lock-free linked list of "free" things. This is used by
749 * both the block pool and the state pools. Unfortunately, in order to
750 * solve the ABA problem, we can't use a single uint32_t head.
751 */
752 union anv_free_list {
753 struct {
754 uint32_t offset;
755
756 /* A simple count that is incremented every time the head changes. */
757 uint32_t count;
758 };
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
761 */
762 uint64_t u64 __attribute__ ((aligned (8)));
763 };
764
765 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
766
767 struct anv_block_state {
768 union {
769 struct {
770 uint32_t next;
771 uint32_t end;
772 };
773 /* Make sure it's aligned to 64 bits. This will make atomic operations
774 * faster on 32 bit platforms.
775 */
776 uint64_t u64 __attribute__ ((aligned (8)));
777 };
778 };
779
780 #define anv_block_pool_foreach_bo(bo, pool) \
781 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
782 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
783 _pp_bo++)
784
785 #define ANV_MAX_BLOCK_POOL_BOS 20
786
787 struct anv_block_pool {
788 struct anv_device *device;
789 bool use_softpin;
790
791 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
792 * around the actual BO so that we grow the pool after the wrapper BO has
793 * been put in a relocation list. This is only used in the non-softpin
794 * case.
795 */
796 struct anv_bo wrapper_bo;
797
798 struct anv_bo *bos[ANV_MAX_BLOCK_POOL_BOS];
799 struct anv_bo *bo;
800 uint32_t nbos;
801
802 uint64_t size;
803
804 /* The address where the start of the pool is pinned. The various bos that
805 * are created as the pool grows will have addresses in the range
806 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
807 */
808 uint64_t start_address;
809
810 /* The offset from the start of the bo to the "center" of the block
811 * pool. Pointers to allocated blocks are given by
812 * bo.map + center_bo_offset + offsets.
813 */
814 uint32_t center_bo_offset;
815
816 /* Current memory map of the block pool. This pointer may or may not
817 * point to the actual beginning of the block pool memory. If
818 * anv_block_pool_alloc_back has ever been called, then this pointer
819 * will point to the "center" position of the buffer and all offsets
820 * (negative or positive) given out by the block pool alloc functions
821 * will be valid relative to this pointer.
822 *
823 * In particular, map == bo.map + center_offset
824 *
825 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
826 * since it will handle the softpin case as well, where this points to NULL.
827 */
828 void *map;
829 int fd;
830
831 /**
832 * Array of mmaps and gem handles owned by the block pool, reclaimed when
833 * the block pool is destroyed.
834 */
835 struct u_vector mmap_cleanups;
836
837 struct anv_block_state state;
838
839 struct anv_block_state back_state;
840 };
841
842 /* Block pools are backed by a fixed-size 1GB memfd */
843 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
844
845 /* The center of the block pool is also the middle of the memfd. This may
846 * change in the future if we decide differently for some reason.
847 */
848 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
849
850 static inline uint32_t
851 anv_block_pool_size(struct anv_block_pool *pool)
852 {
853 return pool->state.end + pool->back_state.end;
854 }
855
856 struct anv_state {
857 int32_t offset;
858 uint32_t alloc_size;
859 void *map;
860 uint32_t idx;
861 };
862
863 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
864
865 struct anv_fixed_size_state_pool {
866 union anv_free_list free_list;
867 struct anv_block_state block;
868 };
869
870 #define ANV_MIN_STATE_SIZE_LOG2 6
871 #define ANV_MAX_STATE_SIZE_LOG2 21
872
873 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
874
875 struct anv_free_entry {
876 uint32_t next;
877 struct anv_state state;
878 };
879
880 struct anv_state_table {
881 struct anv_device *device;
882 int fd;
883 struct anv_free_entry *map;
884 uint32_t size;
885 struct anv_block_state state;
886 struct u_vector cleanups;
887 };
888
889 struct anv_state_pool {
890 struct anv_block_pool block_pool;
891
892 /* Offset into the relevant state base address where the state pool starts
893 * allocating memory.
894 */
895 int32_t start_offset;
896
897 struct anv_state_table table;
898
899 /* The size of blocks which will be allocated from the block pool */
900 uint32_t block_size;
901
902 /** Free list for "back" allocations */
903 union anv_free_list back_alloc_free_list;
904
905 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
906 };
907
908 struct anv_state_reserved_pool {
909 struct anv_state_pool *pool;
910 union anv_free_list reserved_blocks;
911 uint32_t count;
912 };
913
914 struct anv_state_stream {
915 struct anv_state_pool *state_pool;
916
917 /* The size of blocks to allocate from the state pool */
918 uint32_t block_size;
919
920 /* Current block we're allocating from */
921 struct anv_state block;
922
923 /* Offset into the current block at which to allocate the next state */
924 uint32_t next;
925
926 /* List of all blocks allocated from this pool */
927 struct util_dynarray all_blocks;
928 };
929
930 /* The block_pool functions exported for testing only. The block pool should
931 * only be used via a state pool (see below).
932 */
933 VkResult anv_block_pool_init(struct anv_block_pool *pool,
934 struct anv_device *device,
935 uint64_t start_address,
936 uint32_t initial_size);
937 void anv_block_pool_finish(struct anv_block_pool *pool);
938 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
939 uint32_t block_size, uint32_t *padding);
940 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
941 uint32_t block_size);
942 void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset, uint32_t
943 size);
944
945 VkResult anv_state_pool_init(struct anv_state_pool *pool,
946 struct anv_device *device,
947 uint64_t base_address,
948 int32_t start_offset,
949 uint32_t block_size);
950 void anv_state_pool_finish(struct anv_state_pool *pool);
951 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
952 uint32_t state_size, uint32_t alignment);
953 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
954 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
955 void anv_state_stream_init(struct anv_state_stream *stream,
956 struct anv_state_pool *state_pool,
957 uint32_t block_size);
958 void anv_state_stream_finish(struct anv_state_stream *stream);
959 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
960 uint32_t size, uint32_t alignment);
961
962 void anv_state_reserved_pool_init(struct anv_state_reserved_pool *pool,
963 struct anv_state_pool *parent,
964 uint32_t count, uint32_t size,
965 uint32_t alignment);
966 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool *pool);
967 struct anv_state anv_state_reserved_pool_alloc(struct anv_state_reserved_pool *pool);
968 void anv_state_reserved_pool_free(struct anv_state_reserved_pool *pool,
969 struct anv_state state);
970
971 VkResult anv_state_table_init(struct anv_state_table *table,
972 struct anv_device *device,
973 uint32_t initial_entries);
974 void anv_state_table_finish(struct anv_state_table *table);
975 VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx,
976 uint32_t count);
977 void anv_free_list_push(union anv_free_list *list,
978 struct anv_state_table *table,
979 uint32_t idx, uint32_t count);
980 struct anv_state* anv_free_list_pop(union anv_free_list *list,
981 struct anv_state_table *table);
982
983
984 static inline struct anv_state *
985 anv_state_table_get(struct anv_state_table *table, uint32_t idx)
986 {
987 return &table->map[idx].state;
988 }
989 /**
990 * Implements a pool of re-usable BOs. The interface is identical to that
991 * of block_pool except that each block is its own BO.
992 */
993 struct anv_bo_pool {
994 struct anv_device *device;
995
996 struct util_sparse_array_free_list free_list[16];
997 };
998
999 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
1000 void anv_bo_pool_finish(struct anv_bo_pool *pool);
1001 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, uint32_t size,
1002 struct anv_bo **bo_out);
1003 void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
1004
1005 struct anv_scratch_pool {
1006 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
1007 struct anv_bo *bos[16][MESA_SHADER_STAGES];
1008 };
1009
1010 void anv_scratch_pool_init(struct anv_device *device,
1011 struct anv_scratch_pool *pool);
1012 void anv_scratch_pool_finish(struct anv_device *device,
1013 struct anv_scratch_pool *pool);
1014 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
1015 struct anv_scratch_pool *pool,
1016 gl_shader_stage stage,
1017 unsigned per_thread_scratch);
1018
1019 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1020 struct anv_bo_cache {
1021 struct util_sparse_array bo_map;
1022 pthread_mutex_t mutex;
1023 };
1024
1025 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
1026 void anv_bo_cache_finish(struct anv_bo_cache *cache);
1027
1028 struct anv_memory_type {
1029 /* Standard bits passed on to the client */
1030 VkMemoryPropertyFlags propertyFlags;
1031 uint32_t heapIndex;
1032 };
1033
1034 struct anv_memory_heap {
1035 /* Standard bits passed on to the client */
1036 VkDeviceSize size;
1037 VkMemoryHeapFlags flags;
1038
1039 /** Driver-internal book-keeping.
1040 *
1041 * Align it to 64 bits to make atomic operations faster on 32 bit platforms.
1042 */
1043 VkDeviceSize used __attribute__ ((aligned (8)));
1044 };
1045
1046 struct anv_physical_device {
1047 struct vk_object_base base;
1048
1049 /* Link in anv_instance::physical_devices */
1050 struct list_head link;
1051
1052 struct anv_instance * instance;
1053 bool no_hw;
1054 char path[20];
1055 const char * name;
1056 struct {
1057 uint16_t domain;
1058 uint8_t bus;
1059 uint8_t device;
1060 uint8_t function;
1061 } pci_info;
1062 struct gen_device_info info;
1063 /** Amount of "GPU memory" we want to advertise
1064 *
1065 * Clearly, this value is bogus since Intel is a UMA architecture. On
1066 * gen7 platforms, we are limited by GTT size unless we want to implement
1067 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1068 * practically unlimited. However, we will never report more than 3/4 of
1069 * the total system ram to try and avoid running out of RAM.
1070 */
1071 bool supports_48bit_addresses;
1072 struct brw_compiler * compiler;
1073 struct isl_device isl_dev;
1074 struct gen_perf_config * perf;
1075 int cmd_parser_version;
1076 bool has_softpin;
1077 bool has_exec_async;
1078 bool has_exec_capture;
1079 bool has_exec_fence;
1080 bool has_syncobj;
1081 bool has_syncobj_wait;
1082 bool has_syncobj_wait_available;
1083 bool has_context_priority;
1084 bool has_context_isolation;
1085 bool has_mem_available;
1086 bool has_mmap_offset;
1087 uint64_t gtt_size;
1088
1089 bool use_softpin;
1090 bool always_use_bindless;
1091 bool use_call_secondary;
1092
1093 /** True if we can access buffers using A64 messages */
1094 bool has_a64_buffer_access;
1095 /** True if we can use bindless access for images */
1096 bool has_bindless_images;
1097 /** True if we can use bindless access for samplers */
1098 bool has_bindless_samplers;
1099 /** True if we can use timeline semaphores through execbuf */
1100 bool has_exec_timeline;
1101
1102 /** True if we can read the GPU timestamp register
1103 *
1104 * When running in a virtual context, the timestamp register is unreadable
1105 * on Gen12+.
1106 */
1107 bool has_reg_timestamp;
1108
1109 /** True if this device has implicit AUX
1110 *
1111 * If true, CCS is handled as an implicit attachment to the BO rather than
1112 * as an explicitly bound surface.
1113 */
1114 bool has_implicit_ccs;
1115
1116 bool always_flush_cache;
1117
1118 struct anv_device_extension_table supported_extensions;
1119
1120 uint32_t eu_total;
1121 uint32_t subslice_total;
1122
1123 struct {
1124 uint32_t type_count;
1125 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
1126 uint32_t heap_count;
1127 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
1128 } memory;
1129
1130 uint8_t driver_build_sha1[20];
1131 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
1132 uint8_t driver_uuid[VK_UUID_SIZE];
1133 uint8_t device_uuid[VK_UUID_SIZE];
1134
1135 struct disk_cache * disk_cache;
1136
1137 struct wsi_device wsi_device;
1138 int local_fd;
1139 int master_fd;
1140 };
1141
1142 struct anv_app_info {
1143 const char* app_name;
1144 uint32_t app_version;
1145 const char* engine_name;
1146 uint32_t engine_version;
1147 uint32_t api_version;
1148 };
1149
1150 struct anv_instance {
1151 struct vk_object_base base;
1152
1153 VkAllocationCallbacks alloc;
1154
1155 struct anv_app_info app_info;
1156
1157 struct anv_instance_extension_table enabled_extensions;
1158 struct anv_instance_dispatch_table dispatch;
1159 struct anv_physical_device_dispatch_table physical_device_dispatch;
1160 struct anv_device_dispatch_table device_dispatch;
1161
1162 bool physical_devices_enumerated;
1163 struct list_head physical_devices;
1164
1165 bool pipeline_cache_enabled;
1166
1167 struct vk_debug_report_instance debug_report_callbacks;
1168
1169 struct driOptionCache dri_options;
1170 struct driOptionCache available_dri_options;
1171 };
1172
1173 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
1174 void anv_finish_wsi(struct anv_physical_device *physical_device);
1175
1176 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
1177 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
1178 const char *name);
1179
1180 struct anv_queue_submit {
1181 struct anv_cmd_buffer * cmd_buffer;
1182
1183 uint32_t fence_count;
1184 uint32_t fence_array_length;
1185 struct drm_i915_gem_exec_fence * fences;
1186
1187 uint32_t temporary_semaphore_count;
1188 uint32_t temporary_semaphore_array_length;
1189 struct anv_semaphore_impl * temporary_semaphores;
1190
1191 /* Semaphores to be signaled with a SYNC_FD. */
1192 struct anv_semaphore ** sync_fd_semaphores;
1193 uint32_t sync_fd_semaphore_count;
1194 uint32_t sync_fd_semaphore_array_length;
1195
1196 /* Allocated only with non shareable timelines. */
1197 struct anv_timeline ** wait_timelines;
1198 uint32_t wait_timeline_count;
1199 uint32_t wait_timeline_array_length;
1200 uint64_t * wait_timeline_values;
1201
1202 struct anv_timeline ** signal_timelines;
1203 uint32_t signal_timeline_count;
1204 uint32_t signal_timeline_array_length;
1205 uint64_t * signal_timeline_values;
1206
1207 int in_fence;
1208 bool need_out_fence;
1209 int out_fence;
1210
1211 uint32_t fence_bo_count;
1212 uint32_t fence_bo_array_length;
1213 /* An array of struct anv_bo pointers with lower bit used as a flag to
1214 * signal we will wait on that BO (see anv_(un)pack_ptr).
1215 */
1216 uintptr_t * fence_bos;
1217
1218 int perf_query_pass;
1219
1220 const VkAllocationCallbacks * alloc;
1221 VkSystemAllocationScope alloc_scope;
1222
1223 struct anv_bo * simple_bo;
1224 uint32_t simple_bo_size;
1225
1226 struct list_head link;
1227 };
1228
1229 struct anv_queue {
1230 struct vk_object_base base;
1231
1232 struct anv_device * device;
1233
1234 /*
1235 * A list of struct anv_queue_submit to be submitted to i915.
1236 */
1237 struct list_head queued_submits;
1238
1239 VkDeviceQueueCreateFlags flags;
1240 };
1241
1242 struct anv_pipeline_cache {
1243 struct vk_object_base base;
1244 struct anv_device * device;
1245 pthread_mutex_t mutex;
1246
1247 struct hash_table * nir_cache;
1248
1249 struct hash_table * cache;
1250
1251 bool external_sync;
1252 };
1253
1254 struct nir_xfb_info;
1255 struct anv_pipeline_bind_map;
1256
1257 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
1258 struct anv_device *device,
1259 bool cache_enabled,
1260 bool external_sync);
1261 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
1262
1263 struct anv_shader_bin *
1264 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
1265 const void *key, uint32_t key_size);
1266 struct anv_shader_bin *
1267 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
1268 gl_shader_stage stage,
1269 const void *key_data, uint32_t key_size,
1270 const void *kernel_data, uint32_t kernel_size,
1271 const void *constant_data,
1272 uint32_t constant_data_size,
1273 const struct brw_stage_prog_data *prog_data,
1274 uint32_t prog_data_size,
1275 const struct brw_compile_stats *stats,
1276 uint32_t num_stats,
1277 const struct nir_xfb_info *xfb_info,
1278 const struct anv_pipeline_bind_map *bind_map);
1279
1280 struct anv_shader_bin *
1281 anv_device_search_for_kernel(struct anv_device *device,
1282 struct anv_pipeline_cache *cache,
1283 const void *key_data, uint32_t key_size,
1284 bool *user_cache_bit);
1285
1286 struct anv_shader_bin *
1287 anv_device_upload_kernel(struct anv_device *device,
1288 struct anv_pipeline_cache *cache,
1289 gl_shader_stage stage,
1290 const void *key_data, uint32_t key_size,
1291 const void *kernel_data, uint32_t kernel_size,
1292 const void *constant_data,
1293 uint32_t constant_data_size,
1294 const struct brw_stage_prog_data *prog_data,
1295 uint32_t prog_data_size,
1296 const struct brw_compile_stats *stats,
1297 uint32_t num_stats,
1298 const struct nir_xfb_info *xfb_info,
1299 const struct anv_pipeline_bind_map *bind_map);
1300
1301 struct nir_shader;
1302 struct nir_shader_compiler_options;
1303
1304 struct nir_shader *
1305 anv_device_search_for_nir(struct anv_device *device,
1306 struct anv_pipeline_cache *cache,
1307 const struct nir_shader_compiler_options *nir_options,
1308 unsigned char sha1_key[20],
1309 void *mem_ctx);
1310
1311 void
1312 anv_device_upload_nir(struct anv_device *device,
1313 struct anv_pipeline_cache *cache,
1314 const struct nir_shader *nir,
1315 unsigned char sha1_key[20]);
1316
1317 struct anv_address {
1318 struct anv_bo *bo;
1319 uint32_t offset;
1320 };
1321
1322 struct anv_device {
1323 struct vk_device vk;
1324
1325 struct anv_physical_device * physical;
1326 bool no_hw;
1327 struct gen_device_info info;
1328 struct isl_device isl_dev;
1329 int context_id;
1330 int fd;
1331 bool can_chain_batches;
1332 bool robust_buffer_access;
1333 struct anv_device_extension_table enabled_extensions;
1334 struct anv_device_dispatch_table dispatch;
1335
1336 pthread_mutex_t vma_mutex;
1337 struct util_vma_heap vma_lo;
1338 struct util_vma_heap vma_cva;
1339 struct util_vma_heap vma_hi;
1340
1341 /** List of all anv_device_memory objects */
1342 struct list_head memory_objects;
1343
1344 struct anv_bo_pool batch_bo_pool;
1345
1346 struct anv_bo_cache bo_cache;
1347
1348 struct anv_state_pool dynamic_state_pool;
1349 struct anv_state_pool instruction_state_pool;
1350 struct anv_state_pool binding_table_pool;
1351 struct anv_state_pool surface_state_pool;
1352
1353 struct anv_state_reserved_pool custom_border_colors;
1354
1355 /** BO used for various workarounds
1356 *
1357 * There are a number of workarounds on our hardware which require writing
1358 * data somewhere and it doesn't really matter where. For that, we use
1359 * this BO and just write to the first dword or so.
1360 *
1361 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1362 * For that, we use the high bytes (>= 1024) of the workaround BO.
1363 */
1364 struct anv_bo * workaround_bo;
1365 struct anv_address workaround_address;
1366
1367 struct anv_bo * trivial_batch_bo;
1368 struct anv_bo * hiz_clear_bo;
1369 struct anv_state null_surface_state;
1370
1371 struct anv_pipeline_cache default_pipeline_cache;
1372 struct blorp_context blorp;
1373
1374 struct anv_state border_colors;
1375
1376 struct anv_state slice_hash;
1377
1378 struct anv_queue queue;
1379
1380 struct anv_scratch_pool scratch_pool;
1381
1382 pthread_mutex_t mutex;
1383 pthread_cond_t queue_submit;
1384 int _lost;
1385
1386 struct gen_batch_decode_ctx decoder_ctx;
1387 /*
1388 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1389 * the cmd_buffer's list.
1390 */
1391 struct anv_cmd_buffer *cmd_buffer_being_decoded;
1392
1393 int perf_fd; /* -1 if no opened */
1394 uint64_t perf_metric; /* 0 if unset */
1395
1396 struct gen_aux_map_context *aux_map_ctx;
1397
1398 struct gen_debug_block_frame *debug_frame_desc;
1399 };
1400
1401 static inline struct anv_instance *
1402 anv_device_instance_or_null(const struct anv_device *device)
1403 {
1404 return device ? device->physical->instance : NULL;
1405 }
1406
1407 static inline struct anv_state_pool *
1408 anv_binding_table_pool(struct anv_device *device)
1409 {
1410 if (device->physical->use_softpin)
1411 return &device->binding_table_pool;
1412 else
1413 return &device->surface_state_pool;
1414 }
1415
1416 static inline struct anv_state
1417 anv_binding_table_pool_alloc(struct anv_device *device) {
1418 if (device->physical->use_softpin)
1419 return anv_state_pool_alloc(&device->binding_table_pool,
1420 device->binding_table_pool.block_size, 0);
1421 else
1422 return anv_state_pool_alloc_back(&device->surface_state_pool);
1423 }
1424
1425 static inline void
1426 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1427 anv_state_pool_free(anv_binding_table_pool(device), state);
1428 }
1429
1430 static inline uint32_t
1431 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1432 {
1433 if (bo->is_external)
1434 return device->isl_dev.mocs.external;
1435 else
1436 return device->isl_dev.mocs.internal;
1437 }
1438
1439 void anv_device_init_blorp(struct anv_device *device);
1440 void anv_device_finish_blorp(struct anv_device *device);
1441
1442 void _anv_device_set_all_queue_lost(struct anv_device *device);
1443 VkResult _anv_device_set_lost(struct anv_device *device,
1444 const char *file, int line,
1445 const char *msg, ...)
1446 anv_printflike(4, 5);
1447 VkResult _anv_queue_set_lost(struct anv_queue *queue,
1448 const char *file, int line,
1449 const char *msg, ...)
1450 anv_printflike(4, 5);
1451 #define anv_device_set_lost(dev, ...) \
1452 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1453 #define anv_queue_set_lost(queue, ...) \
1454 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1455
1456 static inline bool
1457 anv_device_is_lost(struct anv_device *device)
1458 {
1459 return unlikely(p_atomic_read(&device->_lost));
1460 }
1461
1462 VkResult anv_device_query_status(struct anv_device *device);
1463
1464
1465 enum anv_bo_alloc_flags {
1466 /** Specifies that the BO must have a 32-bit address
1467 *
1468 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1469 */
1470 ANV_BO_ALLOC_32BIT_ADDRESS = (1 << 0),
1471
1472 /** Specifies that the BO may be shared externally */
1473 ANV_BO_ALLOC_EXTERNAL = (1 << 1),
1474
1475 /** Specifies that the BO should be mapped */
1476 ANV_BO_ALLOC_MAPPED = (1 << 2),
1477
1478 /** Specifies that the BO should be snooped so we get coherency */
1479 ANV_BO_ALLOC_SNOOPED = (1 << 3),
1480
1481 /** Specifies that the BO should be captured in error states */
1482 ANV_BO_ALLOC_CAPTURE = (1 << 4),
1483
1484 /** Specifies that the BO will have an address assigned by the caller
1485 *
1486 * Such BOs do not exist in any VMA heap.
1487 */
1488 ANV_BO_ALLOC_FIXED_ADDRESS = (1 << 5),
1489
1490 /** Enables implicit synchronization on the BO
1491 *
1492 * This is the opposite of EXEC_OBJECT_ASYNC.
1493 */
1494 ANV_BO_ALLOC_IMPLICIT_SYNC = (1 << 6),
1495
1496 /** Enables implicit synchronization on the BO
1497 *
1498 * This is equivalent to EXEC_OBJECT_WRITE.
1499 */
1500 ANV_BO_ALLOC_IMPLICIT_WRITE = (1 << 7),
1501
1502 /** Has an address which is visible to the client */
1503 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS = (1 << 8),
1504
1505 /** This buffer has implicit CCS data attached to it */
1506 ANV_BO_ALLOC_IMPLICIT_CCS = (1 << 9),
1507 };
1508
1509 VkResult anv_device_alloc_bo(struct anv_device *device, uint64_t size,
1510 enum anv_bo_alloc_flags alloc_flags,
1511 uint64_t explicit_address,
1512 struct anv_bo **bo);
1513 VkResult anv_device_import_bo_from_host_ptr(struct anv_device *device,
1514 void *host_ptr, uint32_t size,
1515 enum anv_bo_alloc_flags alloc_flags,
1516 uint64_t client_address,
1517 struct anv_bo **bo_out);
1518 VkResult anv_device_import_bo(struct anv_device *device, int fd,
1519 enum anv_bo_alloc_flags alloc_flags,
1520 uint64_t client_address,
1521 struct anv_bo **bo);
1522 VkResult anv_device_export_bo(struct anv_device *device,
1523 struct anv_bo *bo, int *fd_out);
1524 void anv_device_release_bo(struct anv_device *device,
1525 struct anv_bo *bo);
1526
1527 static inline struct anv_bo *
1528 anv_device_lookup_bo(struct anv_device *device, uint32_t gem_handle)
1529 {
1530 return util_sparse_array_get(&device->bo_cache.bo_map, gem_handle);
1531 }
1532
1533 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1534 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1535 int64_t timeout);
1536
1537 VkResult anv_queue_init(struct anv_device *device, struct anv_queue *queue);
1538 void anv_queue_finish(struct anv_queue *queue);
1539
1540 VkResult anv_queue_execbuf_locked(struct anv_queue *queue, struct anv_queue_submit *submit);
1541 VkResult anv_queue_submit_simple_batch(struct anv_queue *queue,
1542 struct anv_batch *batch);
1543
1544 uint64_t anv_gettime_ns(void);
1545 uint64_t anv_get_absolute_timeout(uint64_t timeout);
1546
1547 void* anv_gem_mmap(struct anv_device *device,
1548 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1549 void anv_gem_munmap(struct anv_device *device, void *p, uint64_t size);
1550 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1551 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1552 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1553 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1554 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1555 int anv_gem_execbuffer(struct anv_device *device,
1556 struct drm_i915_gem_execbuffer2 *execbuf);
1557 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1558 uint32_t stride, uint32_t tiling);
1559 int anv_gem_create_context(struct anv_device *device);
1560 bool anv_gem_has_context_priority(int fd);
1561 int anv_gem_destroy_context(struct anv_device *device, int context);
1562 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1563 uint64_t value);
1564 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1565 uint64_t *value);
1566 int anv_gem_get_param(int fd, uint32_t param);
1567 uint64_t anv_gem_get_drm_cap(int fd, uint32_t capability);
1568 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1569 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1570 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1571 uint32_t *active, uint32_t *pending);
1572 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1573 int anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result);
1574 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1575 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1576 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1577 uint32_t read_domains, uint32_t write_domain);
1578 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1579 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1580 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1581 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1582 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1583 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1584 uint32_t handle);
1585 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1586 uint32_t handle, int fd);
1587 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1588 bool anv_gem_supports_syncobj_wait(int fd);
1589 int anv_gem_syncobj_wait(struct anv_device *device,
1590 const uint32_t *handles, uint32_t num_handles,
1591 int64_t abs_timeout_ns, bool wait_all);
1592 int anv_gem_syncobj_timeline_wait(struct anv_device *device,
1593 const uint32_t *handles, const uint64_t *points,
1594 uint32_t num_items, int64_t abs_timeout_ns,
1595 bool wait_all, bool wait_materialize);
1596 int anv_gem_syncobj_timeline_signal(struct anv_device *device,
1597 const uint32_t *handles, const uint64_t *points,
1598 uint32_t num_items);
1599 int anv_gem_syncobj_timeline_query(struct anv_device *device,
1600 const uint32_t *handles, uint64_t *points,
1601 uint32_t num_items);
1602
1603 uint64_t anv_vma_alloc(struct anv_device *device,
1604 uint64_t size, uint64_t align,
1605 enum anv_bo_alloc_flags alloc_flags,
1606 uint64_t client_address);
1607 void anv_vma_free(struct anv_device *device,
1608 uint64_t address, uint64_t size);
1609
1610 struct anv_reloc_list {
1611 uint32_t num_relocs;
1612 uint32_t array_length;
1613 struct drm_i915_gem_relocation_entry * relocs;
1614 struct anv_bo ** reloc_bos;
1615 uint32_t dep_words;
1616 BITSET_WORD * deps;
1617 };
1618
1619 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1620 const VkAllocationCallbacks *alloc);
1621 void anv_reloc_list_finish(struct anv_reloc_list *list,
1622 const VkAllocationCallbacks *alloc);
1623
1624 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1625 const VkAllocationCallbacks *alloc,
1626 uint32_t offset, struct anv_bo *target_bo,
1627 uint32_t delta, uint64_t *address_u64_out);
1628
1629 struct anv_batch_bo {
1630 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1631 struct list_head link;
1632
1633 struct anv_bo * bo;
1634
1635 /* Bytes actually consumed in this batch BO */
1636 uint32_t length;
1637
1638 struct anv_reloc_list relocs;
1639 };
1640
1641 struct anv_batch {
1642 const VkAllocationCallbacks * alloc;
1643
1644 struct anv_address start_addr;
1645
1646 void * start;
1647 void * end;
1648 void * next;
1649
1650 struct anv_reloc_list * relocs;
1651
1652 /* This callback is called (with the associated user data) in the event
1653 * that the batch runs out of space.
1654 */
1655 VkResult (*extend_cb)(struct anv_batch *, void *);
1656 void * user_data;
1657
1658 /**
1659 * Current error status of the command buffer. Used to track inconsistent
1660 * or incomplete command buffer states that are the consequence of run-time
1661 * errors such as out of memory scenarios. We want to track this in the
1662 * batch because the command buffer object is not visible to some parts
1663 * of the driver.
1664 */
1665 VkResult status;
1666 };
1667
1668 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1669 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1670 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1671 void *location, struct anv_bo *bo, uint32_t offset);
1672 struct anv_address anv_batch_address(struct anv_batch *batch, void *batch_location);
1673
1674 static inline void
1675 anv_batch_set_storage(struct anv_batch *batch, struct anv_address addr,
1676 void *map, size_t size)
1677 {
1678 batch->start_addr = addr;
1679 batch->next = batch->start = map;
1680 batch->end = map + size;
1681 }
1682
1683 static inline VkResult
1684 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1685 {
1686 assert(error != VK_SUCCESS);
1687 if (batch->status == VK_SUCCESS)
1688 batch->status = error;
1689 return batch->status;
1690 }
1691
1692 static inline bool
1693 anv_batch_has_error(struct anv_batch *batch)
1694 {
1695 return batch->status != VK_SUCCESS;
1696 }
1697
1698 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1699
1700 static inline bool
1701 anv_address_is_null(struct anv_address addr)
1702 {
1703 return addr.bo == NULL && addr.offset == 0;
1704 }
1705
1706 static inline uint64_t
1707 anv_address_physical(struct anv_address addr)
1708 {
1709 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1710 return gen_canonical_address(addr.bo->offset + addr.offset);
1711 else
1712 return gen_canonical_address(addr.offset);
1713 }
1714
1715 static inline struct anv_address
1716 anv_address_add(struct anv_address addr, uint64_t offset)
1717 {
1718 addr.offset += offset;
1719 return addr;
1720 }
1721
1722 static inline void
1723 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1724 {
1725 unsigned reloc_size = 0;
1726 if (device->info.gen >= 8) {
1727 reloc_size = sizeof(uint64_t);
1728 *(uint64_t *)p = gen_canonical_address(v);
1729 } else {
1730 reloc_size = sizeof(uint32_t);
1731 *(uint32_t *)p = v;
1732 }
1733
1734 if (flush && !device->info.has_llc)
1735 gen_flush_range(p, reloc_size);
1736 }
1737
1738 static inline uint64_t
1739 _anv_combine_address(struct anv_batch *batch, void *location,
1740 const struct anv_address address, uint32_t delta)
1741 {
1742 if (address.bo == NULL) {
1743 return address.offset + delta;
1744 } else {
1745 assert(batch->start <= location && location < batch->end);
1746
1747 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1748 }
1749 }
1750
1751 #define __gen_address_type struct anv_address
1752 #define __gen_user_data struct anv_batch
1753 #define __gen_combine_address _anv_combine_address
1754
1755 /* Wrapper macros needed to work around preprocessor argument issues. In
1756 * particular, arguments don't get pre-evaluated if they are concatenated.
1757 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1758 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1759 * We can work around this easily enough with these helpers.
1760 */
1761 #define __anv_cmd_length(cmd) cmd ## _length
1762 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1763 #define __anv_cmd_header(cmd) cmd ## _header
1764 #define __anv_cmd_pack(cmd) cmd ## _pack
1765 #define __anv_reg_num(reg) reg ## _num
1766
1767 #define anv_pack_struct(dst, struc, ...) do { \
1768 struct struc __template = { \
1769 __VA_ARGS__ \
1770 }; \
1771 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1772 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1773 } while (0)
1774
1775 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1776 void *__dst = anv_batch_emit_dwords(batch, n); \
1777 if (__dst) { \
1778 struct cmd __template = { \
1779 __anv_cmd_header(cmd), \
1780 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1781 __VA_ARGS__ \
1782 }; \
1783 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1784 } \
1785 __dst; \
1786 })
1787
1788 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1789 do { \
1790 uint32_t *dw; \
1791 \
1792 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1793 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1794 if (!dw) \
1795 break; \
1796 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1797 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1798 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1799 } while (0)
1800
1801 #define anv_batch_emit(batch, cmd, name) \
1802 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1803 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1804 __builtin_expect(_dst != NULL, 1); \
1805 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1806 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1807 _dst = NULL; \
1808 }))
1809
1810 /* #define __gen_get_batch_dwords anv_batch_emit_dwords */
1811 /* #define __gen_get_batch_address anv_batch_address */
1812 /* #define __gen_address_value anv_address_physical */
1813 /* #define __gen_address_offset anv_address_add */
1814
1815 struct anv_device_memory {
1816 struct vk_object_base base;
1817
1818 struct list_head link;
1819
1820 struct anv_bo * bo;
1821 struct anv_memory_type * type;
1822 VkDeviceSize map_size;
1823 void * map;
1824
1825 /* If set, we are holding reference to AHardwareBuffer
1826 * which we must release when memory is freed.
1827 */
1828 struct AHardwareBuffer * ahw;
1829
1830 /* If set, this memory comes from a host pointer. */
1831 void * host_ptr;
1832 };
1833
1834 /**
1835 * Header for Vertex URB Entry (VUE)
1836 */
1837 struct anv_vue_header {
1838 uint32_t Reserved;
1839 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1840 uint32_t ViewportIndex;
1841 float PointWidth;
1842 };
1843
1844 /** Struct representing a sampled image descriptor
1845 *
1846 * This descriptor layout is used for sampled images, bare sampler, and
1847 * combined image/sampler descriptors.
1848 */
1849 struct anv_sampled_image_descriptor {
1850 /** Bindless image handle
1851 *
1852 * This is expected to already be shifted such that the 20-bit
1853 * SURFACE_STATE table index is in the top 20 bits.
1854 */
1855 uint32_t image;
1856
1857 /** Bindless sampler handle
1858 *
1859 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1860 * to the dynamic state base address.
1861 */
1862 uint32_t sampler;
1863 };
1864
1865 struct anv_texture_swizzle_descriptor {
1866 /** Texture swizzle
1867 *
1868 * See also nir_intrinsic_channel_select_intel
1869 */
1870 uint8_t swizzle[4];
1871
1872 /** Unused padding to ensure the struct is a multiple of 64 bits */
1873 uint32_t _pad;
1874 };
1875
1876 /** Struct representing a storage image descriptor */
1877 struct anv_storage_image_descriptor {
1878 /** Bindless image handles
1879 *
1880 * These are expected to already be shifted such that the 20-bit
1881 * SURFACE_STATE table index is in the top 20 bits.
1882 */
1883 uint32_t read_write;
1884 uint32_t write_only;
1885 };
1886
1887 /** Struct representing a address/range descriptor
1888 *
1889 * The fields of this struct correspond directly to the data layout of
1890 * nir_address_format_64bit_bounded_global addresses. The last field is the
1891 * offset in the NIR address so it must be zero so that when you load the
1892 * descriptor you get a pointer to the start of the range.
1893 */
1894 struct anv_address_range_descriptor {
1895 uint64_t address;
1896 uint32_t range;
1897 uint32_t zero;
1898 };
1899
1900 enum anv_descriptor_data {
1901 /** The descriptor contains a BTI reference to a surface state */
1902 ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0),
1903 /** The descriptor contains a BTI reference to a sampler state */
1904 ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1),
1905 /** The descriptor contains an actual buffer view */
1906 ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2),
1907 /** The descriptor contains auxiliary image layout data */
1908 ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3),
1909 /** The descriptor contains auxiliary image layout data */
1910 ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4),
1911 /** anv_address_range_descriptor with a buffer address and range */
1912 ANV_DESCRIPTOR_ADDRESS_RANGE = (1 << 5),
1913 /** Bindless surface handle */
1914 ANV_DESCRIPTOR_SAMPLED_IMAGE = (1 << 6),
1915 /** Storage image handles */
1916 ANV_DESCRIPTOR_STORAGE_IMAGE = (1 << 7),
1917 /** Storage image handles */
1918 ANV_DESCRIPTOR_TEXTURE_SWIZZLE = (1 << 8),
1919 };
1920
1921 struct anv_descriptor_set_binding_layout {
1922 #ifndef NDEBUG
1923 /* The type of the descriptors in this binding */
1924 VkDescriptorType type;
1925 #endif
1926
1927 /* Flags provided when this binding was created */
1928 VkDescriptorBindingFlagsEXT flags;
1929
1930 /* Bitfield representing the type of data this descriptor contains */
1931 enum anv_descriptor_data data;
1932
1933 /* Maximum number of YCbCr texture/sampler planes */
1934 uint8_t max_plane_count;
1935
1936 /* Number of array elements in this binding (or size in bytes for inline
1937 * uniform data)
1938 */
1939 uint16_t array_size;
1940
1941 /* Index into the flattend descriptor set */
1942 uint16_t descriptor_index;
1943
1944 /* Index into the dynamic state array for a dynamic buffer */
1945 int16_t dynamic_offset_index;
1946
1947 /* Index into the descriptor set buffer views */
1948 int16_t buffer_view_index;
1949
1950 /* Offset into the descriptor buffer where this descriptor lives */
1951 uint32_t descriptor_offset;
1952
1953 /* Immutable samplers (or NULL if no immutable samplers) */
1954 struct anv_sampler **immutable_samplers;
1955 };
1956
1957 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout);
1958
1959 unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice,
1960 VkDescriptorType type);
1961
1962 bool anv_descriptor_supports_bindless(const struct anv_physical_device *pdevice,
1963 const struct anv_descriptor_set_binding_layout *binding,
1964 bool sampler);
1965
1966 bool anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice,
1967 const struct anv_descriptor_set_binding_layout *binding,
1968 bool sampler);
1969
1970 struct anv_descriptor_set_layout {
1971 struct vk_object_base base;
1972
1973 /* Descriptor set layouts can be destroyed at almost any time */
1974 uint32_t ref_cnt;
1975
1976 /* Number of bindings in this descriptor set */
1977 uint16_t binding_count;
1978
1979 /* Total size of the descriptor set with room for all array entries */
1980 uint16_t size;
1981
1982 /* Shader stages affected by this descriptor set */
1983 uint16_t shader_stages;
1984
1985 /* Number of buffer views in this descriptor set */
1986 uint16_t buffer_view_count;
1987
1988 /* Number of dynamic offsets used by this descriptor set */
1989 uint16_t dynamic_offset_count;
1990
1991 /* For each dynamic buffer, which VkShaderStageFlagBits stages are using
1992 * this buffer
1993 */
1994 VkShaderStageFlags dynamic_offset_stages[MAX_DYNAMIC_BUFFERS];
1995
1996 /* Size of the descriptor buffer for this descriptor set */
1997 uint32_t descriptor_buffer_size;
1998
1999 /* Bindings in this descriptor set */
2000 struct anv_descriptor_set_binding_layout binding[0];
2001 };
2002
2003 void anv_descriptor_set_layout_destroy(struct anv_device *device,
2004 struct anv_descriptor_set_layout *layout);
2005
2006 static inline void
2007 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
2008 {
2009 assert(layout && layout->ref_cnt >= 1);
2010 p_atomic_inc(&layout->ref_cnt);
2011 }
2012
2013 static inline void
2014 anv_descriptor_set_layout_unref(struct anv_device *device,
2015 struct anv_descriptor_set_layout *layout)
2016 {
2017 assert(layout && layout->ref_cnt >= 1);
2018 if (p_atomic_dec_zero(&layout->ref_cnt))
2019 anv_descriptor_set_layout_destroy(device, layout);
2020 }
2021
2022 struct anv_descriptor {
2023 VkDescriptorType type;
2024
2025 union {
2026 struct {
2027 VkImageLayout layout;
2028 struct anv_image_view *image_view;
2029 struct anv_sampler *sampler;
2030 };
2031
2032 struct {
2033 struct anv_buffer *buffer;
2034 uint64_t offset;
2035 uint64_t range;
2036 };
2037
2038 struct anv_buffer_view *buffer_view;
2039 };
2040 };
2041
2042 struct anv_descriptor_set {
2043 struct vk_object_base base;
2044
2045 struct anv_descriptor_pool *pool;
2046 struct anv_descriptor_set_layout *layout;
2047
2048 /* Amount of space occupied in the the pool by this descriptor set. It can
2049 * be larger than the size of the descriptor set.
2050 */
2051 uint32_t size;
2052
2053 /* State relative to anv_descriptor_pool::bo */
2054 struct anv_state desc_mem;
2055 /* Surface state for the descriptor buffer */
2056 struct anv_state desc_surface_state;
2057
2058 uint32_t buffer_view_count;
2059 struct anv_buffer_view *buffer_views;
2060
2061 /* Link to descriptor pool's desc_sets list . */
2062 struct list_head pool_link;
2063
2064 struct anv_descriptor descriptors[0];
2065 };
2066
2067 struct anv_buffer_view {
2068 struct vk_object_base base;
2069
2070 enum isl_format format; /**< VkBufferViewCreateInfo::format */
2071 uint64_t range; /**< VkBufferViewCreateInfo::range */
2072
2073 struct anv_address address;
2074
2075 struct anv_state surface_state;
2076 struct anv_state storage_surface_state;
2077 struct anv_state writeonly_storage_surface_state;
2078
2079 struct brw_image_param storage_image_param;
2080 };
2081
2082 struct anv_push_descriptor_set {
2083 struct anv_descriptor_set set;
2084
2085 /* Put this field right behind anv_descriptor_set so it fills up the
2086 * descriptors[0] field. */
2087 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
2088
2089 /** True if the descriptor set buffer has been referenced by a draw or
2090 * dispatch command.
2091 */
2092 bool set_used_on_gpu;
2093
2094 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
2095 };
2096
2097 struct anv_descriptor_pool {
2098 struct vk_object_base base;
2099
2100 uint32_t size;
2101 uint32_t next;
2102 uint32_t free_list;
2103
2104 struct anv_bo *bo;
2105 struct util_vma_heap bo_heap;
2106
2107 struct anv_state_stream surface_state_stream;
2108 void *surface_state_free_list;
2109
2110 struct list_head desc_sets;
2111
2112 char data[0];
2113 };
2114
2115 enum anv_descriptor_template_entry_type {
2116 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
2117 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
2118 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2119 };
2120
2121 struct anv_descriptor_template_entry {
2122 /* The type of descriptor in this entry */
2123 VkDescriptorType type;
2124
2125 /* Binding in the descriptor set */
2126 uint32_t binding;
2127
2128 /* Offset at which to write into the descriptor set binding */
2129 uint32_t array_element;
2130
2131 /* Number of elements to write into the descriptor set binding */
2132 uint32_t array_count;
2133
2134 /* Offset into the user provided data */
2135 size_t offset;
2136
2137 /* Stride between elements into the user provided data */
2138 size_t stride;
2139 };
2140
2141 struct anv_descriptor_update_template {
2142 struct vk_object_base base;
2143
2144 VkPipelineBindPoint bind_point;
2145
2146 /* The descriptor set this template corresponds to. This value is only
2147 * valid if the template was created with the templateType
2148 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2149 */
2150 uint8_t set;
2151
2152 /* Number of entries in this template */
2153 uint32_t entry_count;
2154
2155 /* Entries of the template */
2156 struct anv_descriptor_template_entry entries[0];
2157 };
2158
2159 size_t
2160 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
2161
2162 void
2163 anv_descriptor_set_write_image_view(struct anv_device *device,
2164 struct anv_descriptor_set *set,
2165 const VkDescriptorImageInfo * const info,
2166 VkDescriptorType type,
2167 uint32_t binding,
2168 uint32_t element);
2169
2170 void
2171 anv_descriptor_set_write_buffer_view(struct anv_device *device,
2172 struct anv_descriptor_set *set,
2173 VkDescriptorType type,
2174 struct anv_buffer_view *buffer_view,
2175 uint32_t binding,
2176 uint32_t element);
2177
2178 void
2179 anv_descriptor_set_write_buffer(struct anv_device *device,
2180 struct anv_descriptor_set *set,
2181 struct anv_state_stream *alloc_stream,
2182 VkDescriptorType type,
2183 struct anv_buffer *buffer,
2184 uint32_t binding,
2185 uint32_t element,
2186 VkDeviceSize offset,
2187 VkDeviceSize range);
2188 void
2189 anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
2190 struct anv_descriptor_set *set,
2191 uint32_t binding,
2192 const void *data,
2193 size_t offset,
2194 size_t size);
2195
2196 void
2197 anv_descriptor_set_write_template(struct anv_device *device,
2198 struct anv_descriptor_set *set,
2199 struct anv_state_stream *alloc_stream,
2200 const struct anv_descriptor_update_template *template,
2201 const void *data);
2202
2203 VkResult
2204 anv_descriptor_set_create(struct anv_device *device,
2205 struct anv_descriptor_pool *pool,
2206 struct anv_descriptor_set_layout *layout,
2207 struct anv_descriptor_set **out_set);
2208
2209 void
2210 anv_descriptor_set_destroy(struct anv_device *device,
2211 struct anv_descriptor_pool *pool,
2212 struct anv_descriptor_set *set);
2213
2214 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2215 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2216 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2217 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2218 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2219 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2220
2221 struct anv_pipeline_binding {
2222 /** Index in the descriptor set
2223 *
2224 * This is a flattened index; the descriptor set layout is already taken
2225 * into account.
2226 */
2227 uint32_t index;
2228
2229 /** The descriptor set this surface corresponds to.
2230 *
2231 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2232 * binding is not a normal descriptor set but something else.
2233 */
2234 uint8_t set;
2235
2236 union {
2237 /** Plane in the binding index for images */
2238 uint8_t plane;
2239
2240 /** Input attachment index (relative to the subpass) */
2241 uint8_t input_attachment_index;
2242
2243 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2244 uint8_t dynamic_offset_index;
2245 };
2246
2247 /** For a storage image, whether it is write-only */
2248 uint8_t write_only;
2249
2250 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2251 * assuming POD zero-initialization.
2252 */
2253 uint8_t pad;
2254 };
2255
2256 struct anv_push_range {
2257 /** Index in the descriptor set */
2258 uint32_t index;
2259
2260 /** Descriptor set index */
2261 uint8_t set;
2262
2263 /** Dynamic offset index (for dynamic UBOs) */
2264 uint8_t dynamic_offset_index;
2265
2266 /** Start offset in units of 32B */
2267 uint8_t start;
2268
2269 /** Range in units of 32B */
2270 uint8_t length;
2271 };
2272
2273 struct anv_pipeline_layout {
2274 struct vk_object_base base;
2275
2276 struct {
2277 struct anv_descriptor_set_layout *layout;
2278 uint32_t dynamic_offset_start;
2279 } set[MAX_SETS];
2280
2281 uint32_t num_sets;
2282
2283 unsigned char sha1[20];
2284 };
2285
2286 struct anv_buffer {
2287 struct vk_object_base base;
2288
2289 struct anv_device * device;
2290 VkDeviceSize size;
2291
2292 VkBufferUsageFlags usage;
2293
2294 /* Set when bound */
2295 struct anv_address address;
2296 };
2297
2298 static inline uint64_t
2299 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
2300 {
2301 assert(offset <= buffer->size);
2302 if (range == VK_WHOLE_SIZE) {
2303 return buffer->size - offset;
2304 } else {
2305 assert(range + offset >= range);
2306 assert(range + offset <= buffer->size);
2307 return range;
2308 }
2309 }
2310
2311 enum anv_cmd_dirty_bits {
2312 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2313 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2314 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2315 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2316 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2317 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2318 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2319 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2320 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2321 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
2322 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
2323 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
2324 ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
2325 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2326 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 14, /* VK_DYNAMIC_STATE_CULL_MODE_EXT */
2327 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 15, /* VK_DYNAMIC_STATE_FRONT_FACE_EXT */
2328 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 16, /* VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT */
2329 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 17, /* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT */
2330 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 18, /* VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT */
2331 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 19, /* VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT */
2332 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 20, /* VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT */
2333 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 21, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT */
2334 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 22, /* VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT */
2335 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 23, /* VK_DYNAMIC_STATE_STENCIL_OP_EXT */
2336 };
2337 typedef uint32_t anv_cmd_dirty_mask_t;
2338
2339 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2340 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2341 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2342 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2343 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2344 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2345 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2346 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2347 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2348 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2349 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE | \
2350 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE | \
2351 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE | \
2352 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | \
2353 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE | \
2354 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | \
2355 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE | \
2356 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | \
2357 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE | \
2358 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE | \
2359 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2360
2361 static inline enum anv_cmd_dirty_bits
2362 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
2363 {
2364 switch (vk_state) {
2365 case VK_DYNAMIC_STATE_VIEWPORT:
2366 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
2367 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2368 case VK_DYNAMIC_STATE_SCISSOR:
2369 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
2370 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
2371 case VK_DYNAMIC_STATE_LINE_WIDTH:
2372 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2373 case VK_DYNAMIC_STATE_DEPTH_BIAS:
2374 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2375 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
2376 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2377 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
2378 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2379 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
2380 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2381 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
2382 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2383 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2384 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2385 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
2386 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
2387 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
2388 return ANV_CMD_DIRTY_DYNAMIC_CULL_MODE;
2389 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
2390 return ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
2391 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
2392 return ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
2393 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
2394 return ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
2395 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
2396 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
2397 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
2398 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
2399 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
2400 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
2401 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
2402 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
2403 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
2404 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
2405 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
2406 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
2407 default:
2408 assert(!"Unsupported dynamic state");
2409 return 0;
2410 }
2411 }
2412
2413
2414 enum anv_pipe_bits {
2415 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
2416 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
2417 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
2418 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
2419 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
2420 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
2421 ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
2422 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
2423 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
2424 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
2425 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
2426 ANV_PIPE_CS_STALL_BIT = (1 << 20),
2427 ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
2428
2429 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2430 * a flush has happened but not a CS stall. The next time we do any sort
2431 * of invalidation we need to insert a CS stall at that time. Otherwise,
2432 * we would have to CS stall on every flush which could be bad.
2433 */
2434 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT = (1 << 22),
2435
2436 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2437 * target operations related to transfer commands with VkBuffer as
2438 * destination are ongoing. Some operations like copies on the command
2439 * streamer might need to be aware of this to trigger the appropriate stall
2440 * before they can proceed with the copy.
2441 */
2442 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 23),
2443
2444 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2445 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2446 * done by writing the AUX-TT register.
2447 */
2448 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 24),
2449
2450 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2451 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2452 * implement a workaround for Gen9.
2453 */
2454 ANV_PIPE_POST_SYNC_BIT = (1 << 25),
2455 };
2456
2457 #define ANV_PIPE_FLUSH_BITS ( \
2458 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2459 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2460 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2461 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2462
2463 #define ANV_PIPE_STALL_BITS ( \
2464 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2465 ANV_PIPE_DEPTH_STALL_BIT | \
2466 ANV_PIPE_CS_STALL_BIT)
2467
2468 #define ANV_PIPE_INVALIDATE_BITS ( \
2469 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2470 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2471 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2472 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2473 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2474 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2475 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2476
2477 static inline enum anv_pipe_bits
2478 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
2479 {
2480 enum anv_pipe_bits pipe_bits = 0;
2481
2482 unsigned b;
2483 for_each_bit(b, flags) {
2484 switch ((VkAccessFlagBits)(1 << b)) {
2485 case VK_ACCESS_SHADER_WRITE_BIT:
2486 /* We're transitioning a buffer that was previously used as write
2487 * destination through the data port. To make its content available
2488 * to future operations, flush the data cache.
2489 */
2490 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2491 break;
2492 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2493 /* We're transitioning a buffer that was previously used as render
2494 * target. To make its content available to future operations, flush
2495 * the render target cache.
2496 */
2497 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2498 break;
2499 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2500 /* We're transitioning a buffer that was previously used as depth
2501 * buffer. To make its content available to future operations, flush
2502 * the depth cache.
2503 */
2504 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2505 break;
2506 case VK_ACCESS_TRANSFER_WRITE_BIT:
2507 /* We're transitioning a buffer that was previously used as a
2508 * transfer write destination. Generic write operations include color
2509 * & depth operations as well as buffer operations like :
2510 * - vkCmdClearColorImage()
2511 * - vkCmdClearDepthStencilImage()
2512 * - vkCmdBlitImage()
2513 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2514 *
2515 * Most of these operations are implemented using Blorp which writes
2516 * through the render target, so flush that cache to make it visible
2517 * to future operations. And for depth related operations we also
2518 * need to flush the depth cache.
2519 */
2520 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2521 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2522 break;
2523 case VK_ACCESS_MEMORY_WRITE_BIT:
2524 /* We're transitioning a buffer for generic write operations. Flush
2525 * all the caches.
2526 */
2527 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2528 break;
2529 default:
2530 break; /* Nothing to do */
2531 }
2532 }
2533
2534 return pipe_bits;
2535 }
2536
2537 static inline enum anv_pipe_bits
2538 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
2539 {
2540 enum anv_pipe_bits pipe_bits = 0;
2541
2542 unsigned b;
2543 for_each_bit(b, flags) {
2544 switch ((VkAccessFlagBits)(1 << b)) {
2545 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2546 /* Indirect draw commands take a buffer as input that we're going to
2547 * read from the command streamer to load some of the HW registers
2548 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2549 * command streamer stall so that all the cache flushes have
2550 * completed before the command streamer loads from memory.
2551 */
2552 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2553 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2554 * through a vertex buffer, so invalidate that cache.
2555 */
2556 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2557 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2558 * UBO from the buffer, so we need to invalidate constant cache.
2559 */
2560 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2561 break;
2562 case VK_ACCESS_INDEX_READ_BIT:
2563 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2564 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2565 * commands, so we invalidate the VF cache to make sure there is no
2566 * stale data when we start rendering.
2567 */
2568 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2569 break;
2570 case VK_ACCESS_UNIFORM_READ_BIT:
2571 /* We transitioning a buffer to be used as uniform data. Because
2572 * uniform is accessed through the data port & sampler, we need to
2573 * invalidate the texture cache (sampler) & constant cache (data
2574 * port) to avoid stale data.
2575 */
2576 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2577 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2578 break;
2579 case VK_ACCESS_SHADER_READ_BIT:
2580 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2581 case VK_ACCESS_TRANSFER_READ_BIT:
2582 /* Transitioning a buffer to be read through the sampler, so
2583 * invalidate the texture cache, we don't want any stale data.
2584 */
2585 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2586 break;
2587 case VK_ACCESS_MEMORY_READ_BIT:
2588 /* Transitioning a buffer for generic read, invalidate all the
2589 * caches.
2590 */
2591 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
2592 break;
2593 case VK_ACCESS_MEMORY_WRITE_BIT:
2594 /* Generic write, make sure all previously written things land in
2595 * memory.
2596 */
2597 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2598 break;
2599 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
2600 /* Transitioning a buffer for conditional rendering. We'll load the
2601 * content of this buffer into HW registers using the command
2602 * streamer, so we need to stall the command streamer to make sure
2603 * any in-flight flush operations have completed.
2604 */
2605 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2606 break;
2607 default:
2608 break; /* Nothing to do */
2609 }
2610 }
2611
2612 return pipe_bits;
2613 }
2614
2615 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2616 VK_IMAGE_ASPECT_COLOR_BIT | \
2617 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2618 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2619 VK_IMAGE_ASPECT_PLANE_2_BIT)
2620 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2621 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2622 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2623 VK_IMAGE_ASPECT_PLANE_2_BIT)
2624
2625 struct anv_vertex_binding {
2626 struct anv_buffer * buffer;
2627 VkDeviceSize offset;
2628 VkDeviceSize stride;
2629 VkDeviceSize size;
2630 };
2631
2632 struct anv_xfb_binding {
2633 struct anv_buffer * buffer;
2634 VkDeviceSize offset;
2635 VkDeviceSize size;
2636 };
2637
2638 struct anv_push_constants {
2639 /** Push constant data provided by the client through vkPushConstants */
2640 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
2641
2642 /** Dynamic offsets for dynamic UBOs and SSBOs */
2643 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2644
2645 /* Robust access pushed registers. */
2646 uint64_t push_reg_mask[MESA_SHADER_STAGES];
2647
2648 /** Pad out to a multiple of 32 bytes */
2649 uint32_t pad[2];
2650
2651 struct {
2652 /** Base workgroup ID
2653 *
2654 * Used for vkCmdDispatchBase.
2655 */
2656 uint32_t base_work_group_id[3];
2657
2658 /** Subgroup ID
2659 *
2660 * This is never set by software but is implicitly filled out when
2661 * uploading the push constants for compute shaders.
2662 */
2663 uint32_t subgroup_id;
2664 } cs;
2665 };
2666
2667 struct anv_dynamic_state {
2668 struct {
2669 uint32_t count;
2670 VkViewport viewports[MAX_VIEWPORTS];
2671 } viewport;
2672
2673 struct {
2674 uint32_t count;
2675 VkRect2D scissors[MAX_SCISSORS];
2676 } scissor;
2677
2678 float line_width;
2679
2680 struct {
2681 float bias;
2682 float clamp;
2683 float slope;
2684 } depth_bias;
2685
2686 float blend_constants[4];
2687
2688 struct {
2689 float min;
2690 float max;
2691 } depth_bounds;
2692
2693 struct {
2694 uint32_t front;
2695 uint32_t back;
2696 } stencil_compare_mask;
2697
2698 struct {
2699 uint32_t front;
2700 uint32_t back;
2701 } stencil_write_mask;
2702
2703 struct {
2704 uint32_t front;
2705 uint32_t back;
2706 } stencil_reference;
2707
2708 struct {
2709 struct {
2710 VkStencilOp fail_op;
2711 VkStencilOp pass_op;
2712 VkStencilOp depth_fail_op;
2713 VkCompareOp compare_op;
2714 } front;
2715 struct {
2716 VkStencilOp fail_op;
2717 VkStencilOp pass_op;
2718 VkStencilOp depth_fail_op;
2719 VkCompareOp compare_op;
2720 } back;
2721 } stencil_op;
2722
2723 struct {
2724 uint32_t factor;
2725 uint16_t pattern;
2726 } line_stipple;
2727
2728 VkCullModeFlags cull_mode;
2729 VkFrontFace front_face;
2730 VkPrimitiveTopology primitive_topology;
2731 bool depth_test_enable;
2732 bool depth_write_enable;
2733 VkCompareOp depth_compare_op;
2734 bool depth_bounds_test_enable;
2735 bool stencil_test_enable;
2736 bool dyn_vbo_stride;
2737 bool dyn_vbo_size;
2738 };
2739
2740 extern const struct anv_dynamic_state default_dynamic_state;
2741
2742 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state *dest,
2743 const struct anv_dynamic_state *src,
2744 uint32_t copy_mask);
2745
2746 struct anv_surface_state {
2747 struct anv_state state;
2748 /** Address of the surface referred to by this state
2749 *
2750 * This address is relative to the start of the BO.
2751 */
2752 struct anv_address address;
2753 /* Address of the aux surface, if any
2754 *
2755 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2756 *
2757 * With the exception of gen8, the bottom 12 bits of this address' offset
2758 * include extra aux information.
2759 */
2760 struct anv_address aux_address;
2761 /* Address of the clear color, if any
2762 *
2763 * This address is relative to the start of the BO.
2764 */
2765 struct anv_address clear_address;
2766 };
2767
2768 /**
2769 * Attachment state when recording a renderpass instance.
2770 *
2771 * The clear value is valid only if there exists a pending clear.
2772 */
2773 struct anv_attachment_state {
2774 enum isl_aux_usage aux_usage;
2775 struct anv_surface_state color;
2776 struct anv_surface_state input;
2777
2778 VkImageLayout current_layout;
2779 VkImageLayout current_stencil_layout;
2780 VkImageAspectFlags pending_clear_aspects;
2781 VkImageAspectFlags pending_load_aspects;
2782 bool fast_clear;
2783 VkClearValue clear_value;
2784
2785 /* When multiview is active, attachments with a renderpass clear
2786 * operation have their respective layers cleared on the first
2787 * subpass that uses them, and only in that subpass. We keep track
2788 * of this using a bitfield to indicate which layers of an attachment
2789 * have not been cleared yet when multiview is active.
2790 */
2791 uint32_t pending_clear_views;
2792 struct anv_image_view * image_view;
2793 };
2794
2795 /** State tracking for vertex buffer flushes
2796 *
2797 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2798 * addresses. If you happen to have two vertex buffers which get placed
2799 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2800 * collisions. In order to solve this problem, we track vertex address ranges
2801 * which are live in the cache and invalidate the cache if one ever exceeds 32
2802 * bits.
2803 */
2804 struct anv_vb_cache_range {
2805 /* Virtual address at which the live vertex buffer cache range starts for
2806 * this vertex buffer index.
2807 */
2808 uint64_t start;
2809
2810 /* Virtual address of the byte after where vertex buffer cache range ends.
2811 * This is exclusive such that end - start is the size of the range.
2812 */
2813 uint64_t end;
2814 };
2815
2816 /** State tracking for particular pipeline bind point
2817 *
2818 * This struct is the base struct for anv_cmd_graphics_state and
2819 * anv_cmd_compute_state. These are used to track state which is bound to a
2820 * particular type of pipeline. Generic state that applies per-stage such as
2821 * binding table offsets and push constants is tracked generically with a
2822 * per-stage array in anv_cmd_state.
2823 */
2824 struct anv_cmd_pipeline_state {
2825 struct anv_descriptor_set *descriptors[MAX_SETS];
2826 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2827
2828 struct anv_push_constants push_constants;
2829
2830 /* Push constant state allocated when flushing push constants. */
2831 struct anv_state push_constants_state;
2832 };
2833
2834 /** State tracking for graphics pipeline
2835 *
2836 * This has anv_cmd_pipeline_state as a base struct to track things which get
2837 * bound to a graphics pipeline. Along with general pipeline bind point state
2838 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2839 * state which is graphics-specific.
2840 */
2841 struct anv_cmd_graphics_state {
2842 struct anv_cmd_pipeline_state base;
2843
2844 struct anv_graphics_pipeline *pipeline;
2845
2846 anv_cmd_dirty_mask_t dirty;
2847 uint32_t vb_dirty;
2848
2849 struct anv_vb_cache_range ib_bound_range;
2850 struct anv_vb_cache_range ib_dirty_range;
2851 struct anv_vb_cache_range vb_bound_ranges[33];
2852 struct anv_vb_cache_range vb_dirty_ranges[33];
2853
2854 VkShaderStageFlags push_constant_stages;
2855
2856 struct anv_dynamic_state dynamic;
2857
2858 uint32_t primitive_topology;
2859
2860 struct {
2861 struct anv_buffer *index_buffer;
2862 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2863 uint32_t index_offset;
2864 } gen7;
2865 };
2866
2867 /** State tracking for compute pipeline
2868 *
2869 * This has anv_cmd_pipeline_state as a base struct to track things which get
2870 * bound to a compute pipeline. Along with general pipeline bind point state
2871 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2872 * state which is compute-specific.
2873 */
2874 struct anv_cmd_compute_state {
2875 struct anv_cmd_pipeline_state base;
2876
2877 struct anv_compute_pipeline *pipeline;
2878
2879 bool pipeline_dirty;
2880
2881 struct anv_address num_workgroups;
2882 };
2883
2884 /** State required while building cmd buffer */
2885 struct anv_cmd_state {
2886 /* PIPELINE_SELECT.PipelineSelection */
2887 uint32_t current_pipeline;
2888 const struct gen_l3_config * current_l3_config;
2889 uint32_t last_aux_map_state;
2890
2891 struct anv_cmd_graphics_state gfx;
2892 struct anv_cmd_compute_state compute;
2893
2894 enum anv_pipe_bits pending_pipe_bits;
2895 VkShaderStageFlags descriptors_dirty;
2896 VkShaderStageFlags push_constants_dirty;
2897
2898 struct anv_framebuffer * framebuffer;
2899 struct anv_render_pass * pass;
2900 struct anv_subpass * subpass;
2901 VkRect2D render_area;
2902 uint32_t restart_index;
2903 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2904 bool xfb_enabled;
2905 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
2906 struct anv_state binding_tables[MESA_SHADER_STAGES];
2907 struct anv_state samplers[MESA_SHADER_STAGES];
2908
2909 unsigned char sampler_sha1s[MESA_SHADER_STAGES][20];
2910 unsigned char surface_sha1s[MESA_SHADER_STAGES][20];
2911 unsigned char push_sha1s[MESA_SHADER_STAGES][20];
2912
2913 /**
2914 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2915 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2916 * and before invoking the secondary in ExecuteCommands.
2917 */
2918 bool pma_fix_enabled;
2919
2920 /**
2921 * Whether or not we know for certain that HiZ is enabled for the current
2922 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2923 * enabled or not, this will be false.
2924 */
2925 bool hiz_enabled;
2926
2927 bool conditional_render_enabled;
2928
2929 /**
2930 * Last rendering scale argument provided to
2931 * genX(cmd_buffer_emit_hashing_mode)().
2932 */
2933 unsigned current_hash_scale;
2934
2935 /**
2936 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2937 * valid only when recording a render pass instance.
2938 */
2939 struct anv_attachment_state * attachments;
2940
2941 /**
2942 * Surface states for color render targets. These are stored in a single
2943 * flat array. For depth-stencil attachments, the surface state is simply
2944 * left blank.
2945 */
2946 struct anv_state attachment_states;
2947
2948 /**
2949 * A null surface state of the right size to match the framebuffer. This
2950 * is one of the states in attachment_states.
2951 */
2952 struct anv_state null_surface_state;
2953 };
2954
2955 struct anv_cmd_pool {
2956 struct vk_object_base base;
2957 VkAllocationCallbacks alloc;
2958 struct list_head cmd_buffers;
2959 };
2960
2961 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2962
2963 enum anv_cmd_buffer_exec_mode {
2964 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2965 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2966 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2967 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2968 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2969 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN,
2970 };
2971
2972 struct anv_cmd_buffer {
2973 struct vk_object_base base;
2974
2975 struct anv_device * device;
2976
2977 struct anv_cmd_pool * pool;
2978 struct list_head pool_link;
2979
2980 struct anv_batch batch;
2981
2982 /* Fields required for the actual chain of anv_batch_bo's.
2983 *
2984 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2985 */
2986 struct list_head batch_bos;
2987 enum anv_cmd_buffer_exec_mode exec_mode;
2988
2989 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2990 * referenced by this command buffer
2991 *
2992 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2993 */
2994 struct u_vector seen_bbos;
2995
2996 /* A vector of int32_t's for every block of binding tables.
2997 *
2998 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2999 */
3000 struct u_vector bt_block_states;
3001 struct anv_state bt_next;
3002
3003 struct anv_reloc_list surface_relocs;
3004 /** Last seen surface state block pool center bo offset */
3005 uint32_t last_ss_pool_center;
3006
3007 /* Serial for tracking buffer completion */
3008 uint32_t serial;
3009
3010 /* Stream objects for storing temporary data */
3011 struct anv_state_stream surface_state_stream;
3012 struct anv_state_stream dynamic_state_stream;
3013
3014 VkCommandBufferUsageFlags usage_flags;
3015 VkCommandBufferLevel level;
3016
3017 struct anv_query_pool *perf_query_pool;
3018
3019 struct anv_cmd_state state;
3020
3021 struct anv_address return_addr;
3022
3023 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
3024 uint64_t intel_perf_marker;
3025 };
3026
3027 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3028 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3029 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3030 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
3031 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
3032 struct anv_cmd_buffer *secondary);
3033 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
3034 VkResult anv_cmd_buffer_execbuf(struct anv_queue *queue,
3035 struct anv_cmd_buffer *cmd_buffer,
3036 const VkSemaphore *in_semaphores,
3037 const uint64_t *in_wait_values,
3038 uint32_t num_in_semaphores,
3039 const VkSemaphore *out_semaphores,
3040 const uint64_t *out_signal_values,
3041 uint32_t num_out_semaphores,
3042 VkFence fence,
3043 int perf_query_pass);
3044
3045 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
3046
3047 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
3048 const void *data, uint32_t size, uint32_t alignment);
3049 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
3050 uint32_t *a, uint32_t *b,
3051 uint32_t dwords, uint32_t alignment);
3052
3053 struct anv_address
3054 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
3055 struct anv_state
3056 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
3057 uint32_t entries, uint32_t *state_offset);
3058 struct anv_state
3059 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
3060 struct anv_state
3061 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
3062 uint32_t size, uint32_t alignment);
3063
3064 VkResult
3065 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
3066
3067 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
3068 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
3069 bool depth_clamp_enable);
3070 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
3071
3072 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
3073 struct anv_render_pass *pass,
3074 struct anv_framebuffer *framebuffer,
3075 const VkClearValue *clear_values);
3076
3077 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
3078
3079 struct anv_state
3080 anv_cmd_buffer_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer);
3081 struct anv_state
3082 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
3083
3084 const struct anv_image_view *
3085 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
3086
3087 VkResult
3088 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
3089 uint32_t num_entries,
3090 uint32_t *state_offset,
3091 struct anv_state *bt_state);
3092
3093 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
3094
3095 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer);
3096
3097 enum anv_fence_type {
3098 ANV_FENCE_TYPE_NONE = 0,
3099 ANV_FENCE_TYPE_BO,
3100 ANV_FENCE_TYPE_WSI_BO,
3101 ANV_FENCE_TYPE_SYNCOBJ,
3102 ANV_FENCE_TYPE_WSI,
3103 };
3104
3105 enum anv_bo_fence_state {
3106 /** Indicates that this is a new (or newly reset fence) */
3107 ANV_BO_FENCE_STATE_RESET,
3108
3109 /** Indicates that this fence has been submitted to the GPU but is still
3110 * (as far as we know) in use by the GPU.
3111 */
3112 ANV_BO_FENCE_STATE_SUBMITTED,
3113
3114 ANV_BO_FENCE_STATE_SIGNALED,
3115 };
3116
3117 struct anv_fence_impl {
3118 enum anv_fence_type type;
3119
3120 union {
3121 /** Fence implementation for BO fences
3122 *
3123 * These fences use a BO and a set of CPU-tracked state flags. The BO
3124 * is added to the object list of the last execbuf call in a QueueSubmit
3125 * and is marked EXEC_WRITE. The state flags track when the BO has been
3126 * submitted to the kernel. We need to do this because Vulkan lets you
3127 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
3128 * will say it's idle in this case.
3129 */
3130 struct {
3131 struct anv_bo *bo;
3132 enum anv_bo_fence_state state;
3133 } bo;
3134
3135 /** DRM syncobj handle for syncobj-based fences */
3136 uint32_t syncobj;
3137
3138 /** WSI fence */
3139 struct wsi_fence *fence_wsi;
3140 };
3141 };
3142
3143 struct anv_fence {
3144 struct vk_object_base base;
3145
3146 /* Permanent fence state. Every fence has some form of permanent state
3147 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3148 * cross-process fences) or it could just be a dummy for use internally.
3149 */
3150 struct anv_fence_impl permanent;
3151
3152 /* Temporary fence state. A fence *may* have temporary state. That state
3153 * is added to the fence by an import operation and is reset back to
3154 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3155 * state cannot be signaled because the fence must already be signaled
3156 * before the temporary state can be exported from the fence in the other
3157 * process and imported here.
3158 */
3159 struct anv_fence_impl temporary;
3160 };
3161
3162 void anv_fence_reset_temporary(struct anv_device *device,
3163 struct anv_fence *fence);
3164
3165 struct anv_event {
3166 struct vk_object_base base;
3167 uint64_t semaphore;
3168 struct anv_state state;
3169 };
3170
3171 enum anv_semaphore_type {
3172 ANV_SEMAPHORE_TYPE_NONE = 0,
3173 ANV_SEMAPHORE_TYPE_DUMMY,
3174 ANV_SEMAPHORE_TYPE_BO,
3175 ANV_SEMAPHORE_TYPE_WSI_BO,
3176 ANV_SEMAPHORE_TYPE_SYNC_FILE,
3177 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
3178 ANV_SEMAPHORE_TYPE_TIMELINE,
3179 };
3180
3181 struct anv_timeline_point {
3182 struct list_head link;
3183
3184 uint64_t serial;
3185
3186 /* Number of waiter on this point, when > 0 the point should not be garbage
3187 * collected.
3188 */
3189 int waiting;
3190
3191 /* BO used for synchronization. */
3192 struct anv_bo *bo;
3193 };
3194
3195 struct anv_timeline {
3196 pthread_mutex_t mutex;
3197 pthread_cond_t cond;
3198
3199 uint64_t highest_past;
3200 uint64_t highest_pending;
3201
3202 struct list_head points;
3203 struct list_head free_points;
3204 };
3205
3206 struct anv_semaphore_impl {
3207 enum anv_semaphore_type type;
3208
3209 union {
3210 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3211 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3212 * object list on any execbuf2 calls for which this semaphore is used as
3213 * a wait or signal fence. When used as a signal fence or when type ==
3214 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3215 */
3216 struct anv_bo *bo;
3217
3218 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3219 * If the semaphore is in the unsignaled state due to either just being
3220 * created or because it has been used for a wait, fd will be -1.
3221 */
3222 int fd;
3223
3224 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3225 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3226 * import so we don't need to bother with a userspace cache.
3227 */
3228 uint32_t syncobj;
3229
3230 /* Non shareable timeline semaphore
3231 *
3232 * Used when kernel don't have support for timeline semaphores.
3233 */
3234 struct anv_timeline timeline;
3235 };
3236 };
3237
3238 struct anv_semaphore {
3239 struct vk_object_base base;
3240
3241 uint32_t refcount;
3242
3243 /* Permanent semaphore state. Every semaphore has some form of permanent
3244 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3245 * (for cross-process semaphores0 or it could just be a dummy for use
3246 * internally.
3247 */
3248 struct anv_semaphore_impl permanent;
3249
3250 /* Temporary semaphore state. A semaphore *may* have temporary state.
3251 * That state is added to the semaphore by an import operation and is reset
3252 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3253 * semaphore with temporary state cannot be signaled because the semaphore
3254 * must already be signaled before the temporary state can be exported from
3255 * the semaphore in the other process and imported here.
3256 */
3257 struct anv_semaphore_impl temporary;
3258 };
3259
3260 void anv_semaphore_reset_temporary(struct anv_device *device,
3261 struct anv_semaphore *semaphore);
3262
3263 struct anv_shader_module {
3264 struct vk_object_base base;
3265
3266 unsigned char sha1[20];
3267 uint32_t size;
3268 char data[0];
3269 };
3270
3271 static inline gl_shader_stage
3272 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
3273 {
3274 assert(__builtin_popcount(vk_stage) == 1);
3275 return ffs(vk_stage) - 1;
3276 }
3277
3278 static inline VkShaderStageFlagBits
3279 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
3280 {
3281 return (1 << mesa_stage);
3282 }
3283
3284 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3285
3286 #define anv_foreach_stage(stage, stage_bits) \
3287 for (gl_shader_stage stage, \
3288 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3289 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3290 __tmp &= ~(1 << (stage)))
3291
3292 struct anv_pipeline_bind_map {
3293 unsigned char surface_sha1[20];
3294 unsigned char sampler_sha1[20];
3295 unsigned char push_sha1[20];
3296
3297 uint32_t surface_count;
3298 uint32_t sampler_count;
3299
3300 struct anv_pipeline_binding * surface_to_descriptor;
3301 struct anv_pipeline_binding * sampler_to_descriptor;
3302
3303 struct anv_push_range push_ranges[4];
3304 };
3305
3306 struct anv_shader_bin_key {
3307 uint32_t size;
3308 uint8_t data[0];
3309 };
3310
3311 struct anv_shader_bin {
3312 uint32_t ref_cnt;
3313
3314 gl_shader_stage stage;
3315
3316 const struct anv_shader_bin_key *key;
3317
3318 struct anv_state kernel;
3319 uint32_t kernel_size;
3320
3321 struct anv_state constant_data;
3322 uint32_t constant_data_size;
3323
3324 const struct brw_stage_prog_data *prog_data;
3325 uint32_t prog_data_size;
3326
3327 struct brw_compile_stats stats[3];
3328 uint32_t num_stats;
3329
3330 struct nir_xfb_info *xfb_info;
3331
3332 struct anv_pipeline_bind_map bind_map;
3333 };
3334
3335 struct anv_shader_bin *
3336 anv_shader_bin_create(struct anv_device *device,
3337 gl_shader_stage stage,
3338 const void *key, uint32_t key_size,
3339 const void *kernel, uint32_t kernel_size,
3340 const void *constant_data, uint32_t constant_data_size,
3341 const struct brw_stage_prog_data *prog_data,
3342 uint32_t prog_data_size,
3343 const struct brw_compile_stats *stats, uint32_t num_stats,
3344 const struct nir_xfb_info *xfb_info,
3345 const struct anv_pipeline_bind_map *bind_map);
3346
3347 void
3348 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
3349
3350 static inline void
3351 anv_shader_bin_ref(struct anv_shader_bin *shader)
3352 {
3353 assert(shader && shader->ref_cnt >= 1);
3354 p_atomic_inc(&shader->ref_cnt);
3355 }
3356
3357 static inline void
3358 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
3359 {
3360 assert(shader && shader->ref_cnt >= 1);
3361 if (p_atomic_dec_zero(&shader->ref_cnt))
3362 anv_shader_bin_destroy(device, shader);
3363 }
3364
3365 struct anv_pipeline_executable {
3366 gl_shader_stage stage;
3367
3368 struct brw_compile_stats stats;
3369
3370 char *nir;
3371 char *disasm;
3372 };
3373
3374 enum anv_pipeline_type {
3375 ANV_PIPELINE_GRAPHICS,
3376 ANV_PIPELINE_COMPUTE,
3377 };
3378
3379 struct anv_pipeline {
3380 struct vk_object_base base;
3381
3382 struct anv_device * device;
3383
3384 struct anv_batch batch;
3385 struct anv_reloc_list batch_relocs;
3386
3387 void * mem_ctx;
3388
3389 enum anv_pipeline_type type;
3390 VkPipelineCreateFlags flags;
3391
3392 struct util_dynarray executables;
3393
3394 const struct gen_l3_config * l3_config;
3395 };
3396
3397 struct anv_graphics_pipeline {
3398 struct anv_pipeline base;
3399
3400 uint32_t batch_data[512];
3401
3402 anv_cmd_dirty_mask_t dynamic_state_mask;
3403 struct anv_dynamic_state dynamic_state;
3404
3405 uint32_t topology;
3406
3407 struct anv_subpass * subpass;
3408
3409 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
3410
3411 VkShaderStageFlags active_stages;
3412
3413 bool primitive_restart;
3414 bool writes_depth;
3415 bool depth_test_enable;
3416 bool writes_stencil;
3417 bool stencil_test_enable;
3418 bool depth_clamp_enable;
3419 bool depth_clip_enable;
3420 bool sample_shading_enable;
3421 bool kill_pixel;
3422 bool depth_bounds_test_enable;
3423
3424 /* When primitive replication is used, subpass->view_mask will describe what
3425 * views to replicate.
3426 */
3427 bool use_primitive_replication;
3428
3429 struct anv_state blend_state;
3430
3431 uint32_t vb_used;
3432 struct anv_pipeline_vertex_binding {
3433 uint32_t stride;
3434 bool instanced;
3435