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intel: Split gen_device_info out into libintel_dev
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_clflush.h"
45 #include "dev/gen_device_info.h"
46 #include "blorp/blorp.h"
47 #include "compiler/brw_compiler.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/u_atomic.h"
51 #include "util/u_vector.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 /* Pre-declarations needed for WSI entrypoints */
56 struct wl_surface;
57 struct wl_display;
58 typedef struct xcb_connection_t xcb_connection_t;
59 typedef uint32_t xcb_visualid_t;
60 typedef uint32_t xcb_window_t;
61
62 struct anv_buffer;
63 struct anv_buffer_view;
64 struct anv_image_view;
65 struct anv_instance;
66
67 struct gen_l3_config;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72 #include <vulkan/vk_android_native_buffer.h>
73
74 #include "anv_entrypoints.h"
75 #include "anv_extensions.h"
76 #include "isl/isl.h"
77
78 #include "common/gen_debug.h"
79 #include "common/intel_log.h"
80 #include "wsi_common.h"
81
82 /* Allowing different clear colors requires us to perform a depth resolve at
83 * the end of certain render passes. This is because while slow clears store
84 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
85 * See the PRMs for examples describing when additional resolves would be
86 * necessary. To enable fast clears without requiring extra resolves, we set
87 * the clear value to a globally-defined one. We could allow different values
88 * if the user doesn't expect coherent data during or after a render passes
89 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
90 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
91 * 1.0f seems to be the only value used. The only application that doesn't set
92 * this value does so through the usage of an seemingly uninitialized clear
93 * value.
94 */
95 #define ANV_HZ_FC_VAL 1.0f
96
97 #define MAX_VBS 28
98 #define MAX_SETS 8
99 #define MAX_RTS 8
100 #define MAX_VIEWPORTS 16
101 #define MAX_SCISSORS 16
102 #define MAX_PUSH_CONSTANTS_SIZE 128
103 #define MAX_DYNAMIC_BUFFERS 16
104 #define MAX_IMAGES 8
105 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
106
107 #define ANV_SVGS_VB_INDEX MAX_VBS
108 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
109
110 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_down_npot_u32(uint32_t v, uint32_t a)
114 {
115 return v - (v % a);
116 }
117
118 static inline uint32_t
119 align_u32(uint32_t v, uint32_t a)
120 {
121 assert(a != 0 && a == (a & -a));
122 return (v + a - 1) & ~(a - 1);
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 anv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 anv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155
156 static inline float
157 anv_clamp_f(float f, float min, float max)
158 {
159 assert(min < max);
160
161 if (f > max)
162 return max;
163 else if (f < min)
164 return min;
165 else
166 return f;
167 }
168
169 static inline bool
170 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
171 {
172 if (*inout_mask & clear_mask) {
173 *inout_mask &= ~clear_mask;
174 return true;
175 } else {
176 return false;
177 }
178 }
179
180 static inline union isl_color_value
181 vk_to_isl_color(VkClearColorValue color)
182 {
183 return (union isl_color_value) {
184 .u32 = {
185 color.uint32[0],
186 color.uint32[1],
187 color.uint32[2],
188 color.uint32[3],
189 },
190 };
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
204 * to be added here in order to utilize mapping in debug/error/perf macros.
205 */
206 #define REPORT_OBJECT_TYPE(o) \
207 __builtin_choose_expr ( \
208 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
209 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
210 __builtin_choose_expr ( \
211 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
212 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
213 __builtin_choose_expr ( \
214 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
215 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
216 __builtin_choose_expr ( \
217 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
218 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
219 __builtin_choose_expr ( \
220 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
221 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
222 __builtin_choose_expr ( \
223 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
224 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
225 __builtin_choose_expr ( \
226 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
227 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
228 __builtin_choose_expr ( \
229 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
230 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
231 __builtin_choose_expr ( \
232 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
233 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
234 __builtin_choose_expr ( \
235 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
236 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
237 __builtin_choose_expr ( \
238 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
239 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
240 __builtin_choose_expr ( \
241 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
242 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
243 __builtin_choose_expr ( \
244 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
245 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
246 __builtin_choose_expr ( \
247 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
248 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
249 __builtin_choose_expr ( \
250 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
251 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
252 __builtin_choose_expr ( \
253 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
254 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
255 __builtin_choose_expr ( \
256 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
257 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
258 __builtin_choose_expr ( \
259 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
260 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
261 __builtin_choose_expr ( \
262 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
263 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
264 __builtin_choose_expr ( \
265 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
266 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
267 __builtin_choose_expr ( \
268 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
269 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
270 __builtin_choose_expr ( \
271 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
272 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
273 __builtin_choose_expr ( \
274 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
275 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
276 __builtin_choose_expr ( \
277 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
278 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
279 __builtin_choose_expr ( \
280 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
281 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
282 __builtin_choose_expr ( \
283 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
284 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
285 __builtin_choose_expr ( \
286 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
287 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
288 __builtin_choose_expr ( \
289 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
290 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
291 __builtin_choose_expr ( \
292 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
293 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
294 __builtin_choose_expr ( \
295 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
296 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
297 __builtin_choose_expr ( \
298 __builtin_types_compatible_p (__typeof (o), void*), \
299 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
300 /* The void expression results in a compile-time error \
301 when assigning the result to something. */ \
302 (void)0)))))))))))))))))))))))))))))))
303
304 /* Whenever we generate an error, pass it through this function. Useful for
305 * debugging, where we can break on it. Only call at error site, not when
306 * propagating errors. Might be useful to plug in a stack trace here.
307 */
308
309 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
310 VkDebugReportObjectTypeEXT type, VkResult error,
311 const char *file, int line, const char *format, ...);
312
313 #ifdef DEBUG
314 #define vk_error(error) __vk_errorf(NULL, NULL,\
315 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
316 error, __FILE__, __LINE__, NULL)
317 #define vk_errorf(instance, obj, error, format, ...)\
318 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
319 __FILE__, __LINE__, format, ## __VA_ARGS__)
320 #else
321 #define vk_error(error) error
322 #define vk_errorf(instance, obj, error, format, ...) error
323 #endif
324
325 /**
326 * Warn on ignored extension structs.
327 *
328 * The Vulkan spec requires us to ignore unsupported or unknown structs in
329 * a pNext chain. In debug mode, emitting warnings for ignored structs may
330 * help us discover structs that we should not have ignored.
331 *
332 *
333 * From the Vulkan 1.0.38 spec:
334 *
335 * Any component of the implementation (the loader, any enabled layers,
336 * and drivers) must skip over, without processing (other than reading the
337 * sType and pNext members) any chained structures with sType values not
338 * defined by extensions supported by that component.
339 */
340 #define anv_debug_ignored_stype(sType) \
341 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
342
343 void __anv_perf_warn(struct anv_instance *instance, const void *object,
344 VkDebugReportObjectTypeEXT type, const char *file,
345 int line, const char *format, ...)
346 anv_printflike(6, 7);
347 void anv_loge(const char *format, ...) anv_printflike(1, 2);
348 void anv_loge_v(const char *format, va_list va);
349
350 /**
351 * Print a FINISHME message, including its source location.
352 */
353 #define anv_finishme(format, ...) \
354 do { \
355 static bool reported = false; \
356 if (!reported) { \
357 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
358 ##__VA_ARGS__); \
359 reported = true; \
360 } \
361 } while (0)
362
363 /**
364 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
365 */
366 #define anv_perf_warn(instance, obj, format, ...) \
367 do { \
368 static bool reported = false; \
369 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
370 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
371 format, ##__VA_ARGS__); \
372 reported = true; \
373 } \
374 } while (0)
375
376 /* A non-fatal assert. Useful for debugging. */
377 #ifdef DEBUG
378 #define anv_assert(x) ({ \
379 if (unlikely(!(x))) \
380 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
381 })
382 #else
383 #define anv_assert(x)
384 #endif
385
386 /* A multi-pointer allocator
387 *
388 * When copying data structures from the user (such as a render pass), it's
389 * common to need to allocate data for a bunch of different things. Instead
390 * of doing several allocations and having to handle all of the error checking
391 * that entails, it can be easier to do a single allocation. This struct
392 * helps facilitate that. The intended usage looks like this:
393 *
394 * ANV_MULTIALLOC(ma)
395 * anv_multialloc_add(&ma, &main_ptr, 1);
396 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
397 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
398 *
399 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
400 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
401 */
402 struct anv_multialloc {
403 size_t size;
404 size_t align;
405
406 uint32_t ptr_count;
407 void **ptrs[8];
408 };
409
410 #define ANV_MULTIALLOC_INIT \
411 ((struct anv_multialloc) { 0, })
412
413 #define ANV_MULTIALLOC(_name) \
414 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
415
416 __attribute__((always_inline))
417 static inline void
418 _anv_multialloc_add(struct anv_multialloc *ma,
419 void **ptr, size_t size, size_t align)
420 {
421 size_t offset = align_u64(ma->size, align);
422 ma->size = offset + size;
423 ma->align = MAX2(ma->align, align);
424
425 /* Store the offset in the pointer. */
426 *ptr = (void *)(uintptr_t)offset;
427
428 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
429 ma->ptrs[ma->ptr_count++] = ptr;
430 }
431
432 #define anv_multialloc_add_size(_ma, _ptr, _size) \
433 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
434
435 #define anv_multialloc_add(_ma, _ptr, _count) \
436 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
437
438 __attribute__((always_inline))
439 static inline void *
440 anv_multialloc_alloc(struct anv_multialloc *ma,
441 const VkAllocationCallbacks *alloc,
442 VkSystemAllocationScope scope)
443 {
444 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
445 if (!ptr)
446 return NULL;
447
448 /* Fill out each of the pointers with their final value.
449 *
450 * for (uint32_t i = 0; i < ma->ptr_count; i++)
451 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
452 *
453 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
454 * constant, GCC is incapable of figuring this out and unrolling the loop
455 * so we have to give it a little help.
456 */
457 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
458 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
459 if ((_i) < ma->ptr_count) \
460 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
461 _ANV_MULTIALLOC_UPDATE_POINTER(0);
462 _ANV_MULTIALLOC_UPDATE_POINTER(1);
463 _ANV_MULTIALLOC_UPDATE_POINTER(2);
464 _ANV_MULTIALLOC_UPDATE_POINTER(3);
465 _ANV_MULTIALLOC_UPDATE_POINTER(4);
466 _ANV_MULTIALLOC_UPDATE_POINTER(5);
467 _ANV_MULTIALLOC_UPDATE_POINTER(6);
468 _ANV_MULTIALLOC_UPDATE_POINTER(7);
469 #undef _ANV_MULTIALLOC_UPDATE_POINTER
470
471 return ptr;
472 }
473
474 __attribute__((always_inline))
475 static inline void *
476 anv_multialloc_alloc2(struct anv_multialloc *ma,
477 const VkAllocationCallbacks *parent_alloc,
478 const VkAllocationCallbacks *alloc,
479 VkSystemAllocationScope scope)
480 {
481 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
482 }
483
484 struct anv_bo {
485 uint32_t gem_handle;
486
487 /* Index into the current validation list. This is used by the
488 * validation list building alrogithm to track which buffers are already
489 * in the validation list so that we can ensure uniqueness.
490 */
491 uint32_t index;
492
493 /* Last known offset. This value is provided by the kernel when we
494 * execbuf and is used as the presumed offset for the next bunch of
495 * relocations.
496 */
497 uint64_t offset;
498
499 uint64_t size;
500 void *map;
501
502 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
503 uint32_t flags;
504 };
505
506 static inline void
507 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
508 {
509 bo->gem_handle = gem_handle;
510 bo->index = 0;
511 bo->offset = -1;
512 bo->size = size;
513 bo->map = NULL;
514 bo->flags = 0;
515 }
516
517 /* Represents a lock-free linked list of "free" things. This is used by
518 * both the block pool and the state pools. Unfortunately, in order to
519 * solve the ABA problem, we can't use a single uint32_t head.
520 */
521 union anv_free_list {
522 struct {
523 int32_t offset;
524
525 /* A simple count that is incremented every time the head changes. */
526 uint32_t count;
527 };
528 uint64_t u64;
529 };
530
531 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
532
533 struct anv_block_state {
534 union {
535 struct {
536 uint32_t next;
537 uint32_t end;
538 };
539 uint64_t u64;
540 };
541 };
542
543 struct anv_block_pool {
544 struct anv_device *device;
545
546 uint64_t bo_flags;
547
548 struct anv_bo bo;
549
550 /* The offset from the start of the bo to the "center" of the block
551 * pool. Pointers to allocated blocks are given by
552 * bo.map + center_bo_offset + offsets.
553 */
554 uint32_t center_bo_offset;
555
556 /* Current memory map of the block pool. This pointer may or may not
557 * point to the actual beginning of the block pool memory. If
558 * anv_block_pool_alloc_back has ever been called, then this pointer
559 * will point to the "center" position of the buffer and all offsets
560 * (negative or positive) given out by the block pool alloc functions
561 * will be valid relative to this pointer.
562 *
563 * In particular, map == bo.map + center_offset
564 */
565 void *map;
566 int fd;
567
568 /**
569 * Array of mmaps and gem handles owned by the block pool, reclaimed when
570 * the block pool is destroyed.
571 */
572 struct u_vector mmap_cleanups;
573
574 struct anv_block_state state;
575
576 struct anv_block_state back_state;
577 };
578
579 /* Block pools are backed by a fixed-size 1GB memfd */
580 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
581
582 /* The center of the block pool is also the middle of the memfd. This may
583 * change in the future if we decide differently for some reason.
584 */
585 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
586
587 static inline uint32_t
588 anv_block_pool_size(struct anv_block_pool *pool)
589 {
590 return pool->state.end + pool->back_state.end;
591 }
592
593 struct anv_state {
594 int32_t offset;
595 uint32_t alloc_size;
596 void *map;
597 };
598
599 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
600
601 struct anv_fixed_size_state_pool {
602 union anv_free_list free_list;
603 struct anv_block_state block;
604 };
605
606 #define ANV_MIN_STATE_SIZE_LOG2 6
607 #define ANV_MAX_STATE_SIZE_LOG2 20
608
609 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
610
611 struct anv_state_pool {
612 struct anv_block_pool block_pool;
613
614 /* The size of blocks which will be allocated from the block pool */
615 uint32_t block_size;
616
617 /** Free list for "back" allocations */
618 union anv_free_list back_alloc_free_list;
619
620 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
621 };
622
623 struct anv_state_stream_block;
624
625 struct anv_state_stream {
626 struct anv_state_pool *state_pool;
627
628 /* The size of blocks to allocate from the state pool */
629 uint32_t block_size;
630
631 /* Current block we're allocating from */
632 struct anv_state block;
633
634 /* Offset into the current block at which to allocate the next state */
635 uint32_t next;
636
637 /* List of all blocks allocated from this pool */
638 struct anv_state_stream_block *block_list;
639 };
640
641 /* The block_pool functions exported for testing only. The block pool should
642 * only be used via a state pool (see below).
643 */
644 VkResult anv_block_pool_init(struct anv_block_pool *pool,
645 struct anv_device *device,
646 uint32_t initial_size,
647 uint64_t bo_flags);
648 void anv_block_pool_finish(struct anv_block_pool *pool);
649 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
650 uint32_t block_size);
651 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
652 uint32_t block_size);
653
654 VkResult anv_state_pool_init(struct anv_state_pool *pool,
655 struct anv_device *device,
656 uint32_t block_size,
657 uint64_t bo_flags);
658 void anv_state_pool_finish(struct anv_state_pool *pool);
659 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
660 uint32_t state_size, uint32_t alignment);
661 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
662 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
663 void anv_state_stream_init(struct anv_state_stream *stream,
664 struct anv_state_pool *state_pool,
665 uint32_t block_size);
666 void anv_state_stream_finish(struct anv_state_stream *stream);
667 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
668 uint32_t size, uint32_t alignment);
669
670 /**
671 * Implements a pool of re-usable BOs. The interface is identical to that
672 * of block_pool except that each block is its own BO.
673 */
674 struct anv_bo_pool {
675 struct anv_device *device;
676
677 uint64_t bo_flags;
678
679 void *free_list[16];
680 };
681
682 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device,
683 uint64_t bo_flags);
684 void anv_bo_pool_finish(struct anv_bo_pool *pool);
685 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
686 uint32_t size);
687 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
688
689 struct anv_scratch_bo {
690 bool exists;
691 struct anv_bo bo;
692 };
693
694 struct anv_scratch_pool {
695 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
696 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
697 };
698
699 void anv_scratch_pool_init(struct anv_device *device,
700 struct anv_scratch_pool *pool);
701 void anv_scratch_pool_finish(struct anv_device *device,
702 struct anv_scratch_pool *pool);
703 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
704 struct anv_scratch_pool *pool,
705 gl_shader_stage stage,
706 unsigned per_thread_scratch);
707
708 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
709 struct anv_bo_cache {
710 struct hash_table *bo_map;
711 pthread_mutex_t mutex;
712 };
713
714 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
715 void anv_bo_cache_finish(struct anv_bo_cache *cache);
716 VkResult anv_bo_cache_alloc(struct anv_device *device,
717 struct anv_bo_cache *cache,
718 uint64_t size, struct anv_bo **bo);
719 VkResult anv_bo_cache_import(struct anv_device *device,
720 struct anv_bo_cache *cache,
721 int fd, struct anv_bo **bo);
722 VkResult anv_bo_cache_export(struct anv_device *device,
723 struct anv_bo_cache *cache,
724 struct anv_bo *bo_in, int *fd_out);
725 void anv_bo_cache_release(struct anv_device *device,
726 struct anv_bo_cache *cache,
727 struct anv_bo *bo);
728
729 struct anv_memory_type {
730 /* Standard bits passed on to the client */
731 VkMemoryPropertyFlags propertyFlags;
732 uint32_t heapIndex;
733
734 /* Driver-internal book-keeping */
735 VkBufferUsageFlags valid_buffer_usage;
736 };
737
738 struct anv_memory_heap {
739 /* Standard bits passed on to the client */
740 VkDeviceSize size;
741 VkMemoryHeapFlags flags;
742
743 /* Driver-internal book-keeping */
744 bool supports_48bit_addresses;
745 };
746
747 struct anv_physical_device {
748 VK_LOADER_DATA _loader_data;
749
750 struct anv_instance * instance;
751 uint32_t chipset_id;
752 bool no_hw;
753 char path[20];
754 const char * name;
755 struct gen_device_info info;
756 /** Amount of "GPU memory" we want to advertise
757 *
758 * Clearly, this value is bogus since Intel is a UMA architecture. On
759 * gen7 platforms, we are limited by GTT size unless we want to implement
760 * fine-grained tracking and GTT splitting. On Broadwell and above we are
761 * practically unlimited. However, we will never report more than 3/4 of
762 * the total system ram to try and avoid running out of RAM.
763 */
764 bool supports_48bit_addresses;
765 struct brw_compiler * compiler;
766 struct isl_device isl_dev;
767 int cmd_parser_version;
768 bool has_exec_async;
769 bool has_exec_capture;
770 bool has_exec_fence;
771 bool has_syncobj;
772 bool has_syncobj_wait;
773 bool has_context_priority;
774
775 struct anv_device_extension_table supported_extensions;
776
777 uint32_t eu_total;
778 uint32_t subslice_total;
779
780 struct {
781 uint32_t type_count;
782 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
783 uint32_t heap_count;
784 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
785 } memory;
786
787 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
788 uint8_t driver_uuid[VK_UUID_SIZE];
789 uint8_t device_uuid[VK_UUID_SIZE];
790
791 struct wsi_device wsi_device;
792 int local_fd;
793 };
794
795 struct anv_instance {
796 VK_LOADER_DATA _loader_data;
797
798 VkAllocationCallbacks alloc;
799
800 uint32_t apiVersion;
801 struct anv_instance_extension_table enabled_extensions;
802 struct anv_dispatch_table dispatch;
803
804 int physicalDeviceCount;
805 struct anv_physical_device physicalDevice;
806
807 struct vk_debug_report_instance debug_report_callbacks;
808 };
809
810 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
811 void anv_finish_wsi(struct anv_physical_device *physical_device);
812
813 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
814 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
815 const char *name);
816
817 struct anv_queue {
818 VK_LOADER_DATA _loader_data;
819
820 struct anv_device * device;
821
822 struct anv_state_pool * pool;
823 };
824
825 struct anv_pipeline_cache {
826 struct anv_device * device;
827 pthread_mutex_t mutex;
828
829 struct hash_table * cache;
830 };
831
832 struct anv_pipeline_bind_map;
833
834 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
835 struct anv_device *device,
836 bool cache_enabled);
837 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
838
839 struct anv_shader_bin *
840 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
841 const void *key, uint32_t key_size);
842 struct anv_shader_bin *
843 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
844 const void *key_data, uint32_t key_size,
845 const void *kernel_data, uint32_t kernel_size,
846 const struct brw_stage_prog_data *prog_data,
847 uint32_t prog_data_size,
848 const struct anv_pipeline_bind_map *bind_map);
849
850 struct anv_device {
851 VK_LOADER_DATA _loader_data;
852
853 VkAllocationCallbacks alloc;
854
855 struct anv_instance * instance;
856 uint32_t chipset_id;
857 bool no_hw;
858 struct gen_device_info info;
859 struct isl_device isl_dev;
860 int context_id;
861 int fd;
862 bool can_chain_batches;
863 bool robust_buffer_access;
864 struct anv_device_extension_table enabled_extensions;
865 struct anv_dispatch_table dispatch;
866
867 struct anv_bo_pool batch_bo_pool;
868
869 struct anv_bo_cache bo_cache;
870
871 struct anv_state_pool dynamic_state_pool;
872 struct anv_state_pool instruction_state_pool;
873 struct anv_state_pool surface_state_pool;
874
875 struct anv_bo workaround_bo;
876 struct anv_bo trivial_batch_bo;
877
878 struct anv_pipeline_cache blorp_shader_cache;
879 struct blorp_context blorp;
880
881 struct anv_state border_colors;
882
883 struct anv_queue queue;
884
885 struct anv_scratch_pool scratch_pool;
886
887 uint32_t default_mocs;
888
889 pthread_mutex_t mutex;
890 pthread_cond_t queue_submit;
891 bool lost;
892 };
893
894 static void inline
895 anv_state_flush(struct anv_device *device, struct anv_state state)
896 {
897 if (device->info.has_llc)
898 return;
899
900 gen_flush_range(state.map, state.alloc_size);
901 }
902
903 void anv_device_init_blorp(struct anv_device *device);
904 void anv_device_finish_blorp(struct anv_device *device);
905
906 VkResult anv_device_execbuf(struct anv_device *device,
907 struct drm_i915_gem_execbuffer2 *execbuf,
908 struct anv_bo **execbuf_bos);
909 VkResult anv_device_query_status(struct anv_device *device);
910 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
911 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
912 int64_t timeout);
913
914 void* anv_gem_mmap(struct anv_device *device,
915 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
916 void anv_gem_munmap(void *p, uint64_t size);
917 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
918 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
919 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
920 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
921 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
922 int anv_gem_execbuffer(struct anv_device *device,
923 struct drm_i915_gem_execbuffer2 *execbuf);
924 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
925 uint32_t stride, uint32_t tiling);
926 int anv_gem_create_context(struct anv_device *device);
927 bool anv_gem_has_context_priority(int fd);
928 int anv_gem_destroy_context(struct anv_device *device, int context);
929 int anv_gem_set_context_param(int fd, int context, uint32_t param,
930 uint64_t value);
931 int anv_gem_get_context_param(int fd, int context, uint32_t param,
932 uint64_t *value);
933 int anv_gem_get_param(int fd, uint32_t param);
934 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
935 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
936 int anv_gem_get_aperture(int fd, uint64_t *size);
937 bool anv_gem_supports_48b_addresses(int fd);
938 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
939 uint32_t *active, uint32_t *pending);
940 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
941 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
942 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
943 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
944 uint32_t read_domains, uint32_t write_domain);
945 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
946 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
947 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
948 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
949 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
950 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
951 uint32_t handle);
952 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
953 uint32_t handle, int fd);
954 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
955 bool anv_gem_supports_syncobj_wait(int fd);
956 int anv_gem_syncobj_wait(struct anv_device *device,
957 uint32_t *handles, uint32_t num_handles,
958 int64_t abs_timeout_ns, bool wait_all);
959
960 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
961
962 struct anv_reloc_list {
963 uint32_t num_relocs;
964 uint32_t array_length;
965 struct drm_i915_gem_relocation_entry * relocs;
966 struct anv_bo ** reloc_bos;
967 };
968
969 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
970 const VkAllocationCallbacks *alloc);
971 void anv_reloc_list_finish(struct anv_reloc_list *list,
972 const VkAllocationCallbacks *alloc);
973
974 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
975 const VkAllocationCallbacks *alloc,
976 uint32_t offset, struct anv_bo *target_bo,
977 uint32_t delta);
978
979 struct anv_batch_bo {
980 /* Link in the anv_cmd_buffer.owned_batch_bos list */
981 struct list_head link;
982
983 struct anv_bo bo;
984
985 /* Bytes actually consumed in this batch BO */
986 uint32_t length;
987
988 struct anv_reloc_list relocs;
989 };
990
991 struct anv_batch {
992 const VkAllocationCallbacks * alloc;
993
994 void * start;
995 void * end;
996 void * next;
997
998 struct anv_reloc_list * relocs;
999
1000 /* This callback is called (with the associated user data) in the event
1001 * that the batch runs out of space.
1002 */
1003 VkResult (*extend_cb)(struct anv_batch *, void *);
1004 void * user_data;
1005
1006 /**
1007 * Current error status of the command buffer. Used to track inconsistent
1008 * or incomplete command buffer states that are the consequence of run-time
1009 * errors such as out of memory scenarios. We want to track this in the
1010 * batch because the command buffer object is not visible to some parts
1011 * of the driver.
1012 */
1013 VkResult status;
1014 };
1015
1016 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1017 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1018 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1019 void *location, struct anv_bo *bo, uint32_t offset);
1020 VkResult anv_device_submit_simple_batch(struct anv_device *device,
1021 struct anv_batch *batch);
1022
1023 static inline VkResult
1024 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1025 {
1026 assert(error != VK_SUCCESS);
1027 if (batch->status == VK_SUCCESS)
1028 batch->status = error;
1029 return batch->status;
1030 }
1031
1032 static inline bool
1033 anv_batch_has_error(struct anv_batch *batch)
1034 {
1035 return batch->status != VK_SUCCESS;
1036 }
1037
1038 struct anv_address {
1039 struct anv_bo *bo;
1040 uint32_t offset;
1041 };
1042
1043 static inline uint64_t
1044 _anv_combine_address(struct anv_batch *batch, void *location,
1045 const struct anv_address address, uint32_t delta)
1046 {
1047 if (address.bo == NULL) {
1048 return address.offset + delta;
1049 } else {
1050 assert(batch->start <= location && location < batch->end);
1051
1052 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1053 }
1054 }
1055
1056 #define __gen_address_type struct anv_address
1057 #define __gen_user_data struct anv_batch
1058 #define __gen_combine_address _anv_combine_address
1059
1060 /* Wrapper macros needed to work around preprocessor argument issues. In
1061 * particular, arguments don't get pre-evaluated if they are concatenated.
1062 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1063 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1064 * We can work around this easily enough with these helpers.
1065 */
1066 #define __anv_cmd_length(cmd) cmd ## _length
1067 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1068 #define __anv_cmd_header(cmd) cmd ## _header
1069 #define __anv_cmd_pack(cmd) cmd ## _pack
1070 #define __anv_reg_num(reg) reg ## _num
1071
1072 #define anv_pack_struct(dst, struc, ...) do { \
1073 struct struc __template = { \
1074 __VA_ARGS__ \
1075 }; \
1076 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1077 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1078 } while (0)
1079
1080 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1081 void *__dst = anv_batch_emit_dwords(batch, n); \
1082 if (__dst) { \
1083 struct cmd __template = { \
1084 __anv_cmd_header(cmd), \
1085 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1086 __VA_ARGS__ \
1087 }; \
1088 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1089 } \
1090 __dst; \
1091 })
1092
1093 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1094 do { \
1095 uint32_t *dw; \
1096 \
1097 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1098 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1099 if (!dw) \
1100 break; \
1101 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1102 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1103 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1104 } while (0)
1105
1106 #define anv_batch_emit(batch, cmd, name) \
1107 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1108 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1109 __builtin_expect(_dst != NULL, 1); \
1110 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1111 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1112 _dst = NULL; \
1113 }))
1114
1115 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
1116 .GraphicsDataTypeGFDT = 0, \
1117 .LLCCacheabilityControlLLCCC = 0, \
1118 .L3CacheabilityControlL3CC = 1, \
1119 }
1120
1121 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
1122 .LLCeLLCCacheabilityControlLLCCC = 0, \
1123 .L3CacheabilityControlL3CC = 1, \
1124 }
1125
1126 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
1127 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
1128 .TargetCache = L3DefertoPATforLLCeLLCselection, \
1129 .AgeforQUADLRU = 0 \
1130 }
1131
1132 /* Skylake: MOCS is now an index into an array of 62 different caching
1133 * configurations programmed by the kernel.
1134 */
1135
1136 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
1137 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1138 .IndextoMOCSTables = 2 \
1139 }
1140
1141 #define GEN9_MOCS_PTE { \
1142 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1143 .IndextoMOCSTables = 1 \
1144 }
1145
1146 /* Cannonlake MOCS defines are duplicates of Skylake MOCS defines. */
1147 #define GEN10_MOCS (struct GEN10_MEMORY_OBJECT_CONTROL_STATE) { \
1148 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1149 .IndextoMOCSTables = 2 \
1150 }
1151
1152 #define GEN10_MOCS_PTE { \
1153 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1154 .IndextoMOCSTables = 1 \
1155 }
1156
1157 /* Ice Lake MOCS defines are duplicates of Skylake MOCS defines. */
1158 #define GEN11_MOCS (struct GEN11_MEMORY_OBJECT_CONTROL_STATE) { \
1159 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1160 .IndextoMOCSTables = 2 \
1161 }
1162
1163 #define GEN11_MOCS_PTE { \
1164 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
1165 .IndextoMOCSTables = 1 \
1166 }
1167
1168 struct anv_device_memory {
1169 struct anv_bo * bo;
1170 struct anv_memory_type * type;
1171 VkDeviceSize map_size;
1172 void * map;
1173 };
1174
1175 /**
1176 * Header for Vertex URB Entry (VUE)
1177 */
1178 struct anv_vue_header {
1179 uint32_t Reserved;
1180 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1181 uint32_t ViewportIndex;
1182 float PointWidth;
1183 };
1184
1185 struct anv_descriptor_set_binding_layout {
1186 #ifndef NDEBUG
1187 /* The type of the descriptors in this binding */
1188 VkDescriptorType type;
1189 #endif
1190
1191 /* Number of array elements in this binding */
1192 uint16_t array_size;
1193
1194 /* Index into the flattend descriptor set */
1195 uint16_t descriptor_index;
1196
1197 /* Index into the dynamic state array for a dynamic buffer */
1198 int16_t dynamic_offset_index;
1199
1200 /* Index into the descriptor set buffer views */
1201 int16_t buffer_index;
1202
1203 struct {
1204 /* Index into the binding table for the associated surface */
1205 int16_t surface_index;
1206
1207 /* Index into the sampler table for the associated sampler */
1208 int16_t sampler_index;
1209
1210 /* Index into the image table for the associated image */
1211 int16_t image_index;
1212 } stage[MESA_SHADER_STAGES];
1213
1214 /* Immutable samplers (or NULL if no immutable samplers) */
1215 struct anv_sampler **immutable_samplers;
1216 };
1217
1218 struct anv_descriptor_set_layout {
1219 /* Descriptor set layouts can be destroyed at almost any time */
1220 uint32_t ref_cnt;
1221
1222 /* Number of bindings in this descriptor set */
1223 uint16_t binding_count;
1224
1225 /* Total size of the descriptor set with room for all array entries */
1226 uint16_t size;
1227
1228 /* Shader stages affected by this descriptor set */
1229 uint16_t shader_stages;
1230
1231 /* Number of buffers in this descriptor set */
1232 uint16_t buffer_count;
1233
1234 /* Number of dynamic offsets used by this descriptor set */
1235 uint16_t dynamic_offset_count;
1236
1237 /* Bindings in this descriptor set */
1238 struct anv_descriptor_set_binding_layout binding[0];
1239 };
1240
1241 static inline void
1242 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1243 {
1244 assert(layout && layout->ref_cnt >= 1);
1245 p_atomic_inc(&layout->ref_cnt);
1246 }
1247
1248 static inline void
1249 anv_descriptor_set_layout_unref(struct anv_device *device,
1250 struct anv_descriptor_set_layout *layout)
1251 {
1252 assert(layout && layout->ref_cnt >= 1);
1253 if (p_atomic_dec_zero(&layout->ref_cnt))
1254 vk_free(&device->alloc, layout);
1255 }
1256
1257 struct anv_descriptor {
1258 VkDescriptorType type;
1259
1260 union {
1261 struct {
1262 VkImageLayout layout;
1263 struct anv_image_view *image_view;
1264 struct anv_sampler *sampler;
1265 };
1266
1267 struct {
1268 struct anv_buffer *buffer;
1269 uint64_t offset;
1270 uint64_t range;
1271 };
1272
1273 struct anv_buffer_view *buffer_view;
1274 };
1275 };
1276
1277 struct anv_descriptor_set {
1278 struct anv_descriptor_set_layout *layout;
1279 uint32_t size;
1280 uint32_t buffer_count;
1281 struct anv_buffer_view *buffer_views;
1282 struct anv_descriptor descriptors[0];
1283 };
1284
1285 struct anv_buffer_view {
1286 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1287 struct anv_bo *bo;
1288 uint32_t offset; /**< Offset into bo. */
1289 uint64_t range; /**< VkBufferViewCreateInfo::range */
1290
1291 struct anv_state surface_state;
1292 struct anv_state storage_surface_state;
1293 struct anv_state writeonly_storage_surface_state;
1294
1295 struct brw_image_param storage_image_param;
1296 };
1297
1298 struct anv_push_descriptor_set {
1299 struct anv_descriptor_set set;
1300
1301 /* Put this field right behind anv_descriptor_set so it fills up the
1302 * descriptors[0] field. */
1303 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
1304 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
1305 };
1306
1307 struct anv_descriptor_pool {
1308 uint32_t size;
1309 uint32_t next;
1310 uint32_t free_list;
1311
1312 struct anv_state_stream surface_state_stream;
1313 void *surface_state_free_list;
1314
1315 char data[0];
1316 };
1317
1318 enum anv_descriptor_template_entry_type {
1319 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
1320 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
1321 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
1322 };
1323
1324 struct anv_descriptor_template_entry {
1325 /* The type of descriptor in this entry */
1326 VkDescriptorType type;
1327
1328 /* Binding in the descriptor set */
1329 uint32_t binding;
1330
1331 /* Offset at which to write into the descriptor set binding */
1332 uint32_t array_element;
1333
1334 /* Number of elements to write into the descriptor set binding */
1335 uint32_t array_count;
1336
1337 /* Offset into the user provided data */
1338 size_t offset;
1339
1340 /* Stride between elements into the user provided data */
1341 size_t stride;
1342 };
1343
1344 struct anv_descriptor_update_template {
1345 VkPipelineBindPoint bind_point;
1346
1347 /* The descriptor set this template corresponds to. This value is only
1348 * valid if the template was created with the templateType
1349 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET_KHR.
1350 */
1351 uint8_t set;
1352
1353 /* Number of entries in this template */
1354 uint32_t entry_count;
1355
1356 /* Entries of the template */
1357 struct anv_descriptor_template_entry entries[0];
1358 };
1359
1360 size_t
1361 anv_descriptor_set_binding_layout_get_hw_size(const struct anv_descriptor_set_binding_layout *binding);
1362
1363 size_t
1364 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
1365
1366 void
1367 anv_descriptor_set_write_image_view(struct anv_descriptor_set *set,
1368 const struct gen_device_info * const devinfo,
1369 const VkDescriptorImageInfo * const info,
1370 VkDescriptorType type,
1371 uint32_t binding,
1372 uint32_t element);
1373
1374 void
1375 anv_descriptor_set_write_buffer_view(struct anv_descriptor_set *set,
1376 VkDescriptorType type,
1377 struct anv_buffer_view *buffer_view,
1378 uint32_t binding,
1379 uint32_t element);
1380
1381 void
1382 anv_descriptor_set_write_buffer(struct anv_descriptor_set *set,
1383 struct anv_device *device,
1384 struct anv_state_stream *alloc_stream,
1385 VkDescriptorType type,
1386 struct anv_buffer *buffer,
1387 uint32_t binding,
1388 uint32_t element,
1389 VkDeviceSize offset,
1390 VkDeviceSize range);
1391
1392 void
1393 anv_descriptor_set_write_template(struct anv_descriptor_set *set,
1394 struct anv_device *device,
1395 struct anv_state_stream *alloc_stream,
1396 const struct anv_descriptor_update_template *template,
1397 const void *data);
1398
1399 VkResult
1400 anv_descriptor_set_create(struct anv_device *device,
1401 struct anv_descriptor_pool *pool,
1402 struct anv_descriptor_set_layout *layout,
1403 struct anv_descriptor_set **out_set);
1404
1405 void
1406 anv_descriptor_set_destroy(struct anv_device *device,
1407 struct anv_descriptor_pool *pool,
1408 struct anv_descriptor_set *set);
1409
1410 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
1411
1412 struct anv_pipeline_binding {
1413 /* The descriptor set this surface corresponds to. The special value of
1414 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
1415 * to a color attachment and not a regular descriptor.
1416 */
1417 uint8_t set;
1418
1419 /* Binding in the descriptor set */
1420 uint32_t binding;
1421
1422 /* Index in the binding */
1423 uint32_t index;
1424
1425 /* Plane in the binding index */
1426 uint8_t plane;
1427
1428 /* Input attachment index (relative to the subpass) */
1429 uint8_t input_attachment_index;
1430
1431 /* For a storage image, whether it is write-only */
1432 bool write_only;
1433 };
1434
1435 struct anv_pipeline_layout {
1436 struct {
1437 struct anv_descriptor_set_layout *layout;
1438 uint32_t dynamic_offset_start;
1439 } set[MAX_SETS];
1440
1441 uint32_t num_sets;
1442
1443 struct {
1444 bool has_dynamic_offsets;
1445 } stage[MESA_SHADER_STAGES];
1446
1447 unsigned char sha1[20];
1448 };
1449
1450 struct anv_buffer {
1451 struct anv_device * device;
1452 VkDeviceSize size;
1453
1454 VkBufferUsageFlags usage;
1455
1456 /* Set when bound */
1457 struct anv_bo * bo;
1458 VkDeviceSize offset;
1459 };
1460
1461 static inline uint64_t
1462 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
1463 {
1464 assert(offset <= buffer->size);
1465 if (range == VK_WHOLE_SIZE) {
1466 return buffer->size - offset;
1467 } else {
1468 assert(range <= buffer->size);
1469 return range;
1470 }
1471 }
1472
1473 enum anv_cmd_dirty_bits {
1474 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
1475 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
1476 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
1477 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
1478 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
1479 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
1480 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
1481 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
1482 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
1483 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
1484 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
1485 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1486 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1487 };
1488 typedef uint32_t anv_cmd_dirty_mask_t;
1489
1490 enum anv_pipe_bits {
1491 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1492 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1493 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1494 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1495 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1496 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1497 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1498 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1499 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1500 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1501 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1502
1503 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1504 * a flush has happened but not a CS stall. The next time we do any sort
1505 * of invalidation we need to insert a CS stall at that time. Otherwise,
1506 * we would have to CS stall on every flush which could be bad.
1507 */
1508 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1509 };
1510
1511 #define ANV_PIPE_FLUSH_BITS ( \
1512 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1513 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1514 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1515
1516 #define ANV_PIPE_STALL_BITS ( \
1517 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1518 ANV_PIPE_DEPTH_STALL_BIT | \
1519 ANV_PIPE_CS_STALL_BIT)
1520
1521 #define ANV_PIPE_INVALIDATE_BITS ( \
1522 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1523 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1524 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1525 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1526 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1527 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1528
1529 static inline enum anv_pipe_bits
1530 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
1531 {
1532 enum anv_pipe_bits pipe_bits = 0;
1533
1534 unsigned b;
1535 for_each_bit(b, flags) {
1536 switch ((VkAccessFlagBits)(1 << b)) {
1537 case VK_ACCESS_SHADER_WRITE_BIT:
1538 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
1539 break;
1540 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1541 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1542 break;
1543 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1544 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1545 break;
1546 case VK_ACCESS_TRANSFER_WRITE_BIT:
1547 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1548 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1549 break;
1550 default:
1551 break; /* Nothing to do */
1552 }
1553 }
1554
1555 return pipe_bits;
1556 }
1557
1558 static inline enum anv_pipe_bits
1559 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
1560 {
1561 enum anv_pipe_bits pipe_bits = 0;
1562
1563 unsigned b;
1564 for_each_bit(b, flags) {
1565 switch ((VkAccessFlagBits)(1 << b)) {
1566 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1567 case VK_ACCESS_INDEX_READ_BIT:
1568 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1569 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
1570 break;
1571 case VK_ACCESS_UNIFORM_READ_BIT:
1572 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
1573 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1574 break;
1575 case VK_ACCESS_SHADER_READ_BIT:
1576 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1577 case VK_ACCESS_TRANSFER_READ_BIT:
1578 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
1579 break;
1580 default:
1581 break; /* Nothing to do */
1582 }
1583 }
1584
1585 return pipe_bits;
1586 }
1587
1588 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
1589 VK_IMAGE_ASPECT_COLOR_BIT | \
1590 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1591 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1592 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1593 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
1594 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | \
1595 VK_IMAGE_ASPECT_PLANE_1_BIT_KHR | \
1596 VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
1597
1598 struct anv_vertex_binding {
1599 struct anv_buffer * buffer;
1600 VkDeviceSize offset;
1601 };
1602
1603 #define ANV_PARAM_PUSH(offset) ((1 << 16) | (uint32_t)(offset))
1604 #define ANV_PARAM_PUSH_OFFSET(param) ((param) & 0xffff)
1605
1606 struct anv_push_constants {
1607 /* Current allocated size of this push constants data structure.
1608 * Because a decent chunk of it may not be used (images on SKL, for
1609 * instance), we won't actually allocate the entire structure up-front.
1610 */
1611 uint32_t size;
1612
1613 /* Push constant data provided by the client through vkPushConstants */
1614 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1615
1616 /* Image data for image_load_store on pre-SKL */
1617 struct brw_image_param images[MAX_IMAGES];
1618 };
1619
1620 struct anv_dynamic_state {
1621 struct {
1622 uint32_t count;
1623 VkViewport viewports[MAX_VIEWPORTS];
1624 } viewport;
1625
1626 struct {
1627 uint32_t count;
1628 VkRect2D scissors[MAX_SCISSORS];
1629 } scissor;
1630
1631 float line_width;
1632
1633 struct {
1634 float bias;
1635 float clamp;
1636 float slope;
1637 } depth_bias;
1638
1639 float blend_constants[4];
1640
1641 struct {
1642 float min;
1643 float max;
1644 } depth_bounds;
1645
1646 struct {
1647 uint32_t front;
1648 uint32_t back;
1649 } stencil_compare_mask;
1650
1651 struct {
1652 uint32_t front;
1653 uint32_t back;
1654 } stencil_write_mask;
1655
1656 struct {
1657 uint32_t front;
1658 uint32_t back;
1659 } stencil_reference;
1660 };
1661
1662 extern const struct anv_dynamic_state default_dynamic_state;
1663
1664 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1665 const struct anv_dynamic_state *src,
1666 uint32_t copy_mask);
1667
1668 struct anv_surface_state {
1669 struct anv_state state;
1670 /** Address of the surface referred to by this state
1671 *
1672 * This address is relative to the start of the BO.
1673 */
1674 uint64_t address;
1675 /* Address of the aux surface, if any
1676 *
1677 * This field is 0 if and only if no aux surface exists.
1678 *
1679 * This address is relative to the start of the BO. On gen7, the bottom 12
1680 * bits of this address include extra aux information.
1681 */
1682 uint64_t aux_address;
1683 };
1684
1685 /**
1686 * Attachment state when recording a renderpass instance.
1687 *
1688 * The clear value is valid only if there exists a pending clear.
1689 */
1690 struct anv_attachment_state {
1691 enum isl_aux_usage aux_usage;
1692 enum isl_aux_usage input_aux_usage;
1693 struct anv_surface_state color;
1694 struct anv_surface_state input;
1695
1696 VkImageLayout current_layout;
1697 VkImageAspectFlags pending_clear_aspects;
1698 VkImageAspectFlags pending_load_aspects;
1699 bool fast_clear;
1700 VkClearValue clear_value;
1701 bool clear_color_is_zero_one;
1702 bool clear_color_is_zero;
1703 };
1704
1705 /** State tracking for particular pipeline bind point
1706 *
1707 * This struct is the base struct for anv_cmd_graphics_state and
1708 * anv_cmd_compute_state. These are used to track state which is bound to a
1709 * particular type of pipeline. Generic state that applies per-stage such as
1710 * binding table offsets and push constants is tracked generically with a
1711 * per-stage array in anv_cmd_state.
1712 */
1713 struct anv_cmd_pipeline_state {
1714 struct anv_pipeline *pipeline;
1715 struct anv_pipeline_layout *layout;
1716
1717 struct anv_descriptor_set *descriptors[MAX_SETS];
1718 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
1719
1720 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
1721 };
1722
1723 /** State tracking for graphics pipeline
1724 *
1725 * This has anv_cmd_pipeline_state as a base struct to track things which get
1726 * bound to a graphics pipeline. Along with general pipeline bind point state
1727 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1728 * state which is graphics-specific.
1729 */
1730 struct anv_cmd_graphics_state {
1731 struct anv_cmd_pipeline_state base;
1732
1733 anv_cmd_dirty_mask_t dirty;
1734 uint32_t vb_dirty;
1735
1736 struct anv_dynamic_state dynamic;
1737
1738 struct {
1739 struct anv_buffer *index_buffer;
1740 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1741 uint32_t index_offset;
1742 } gen7;
1743 };
1744
1745 /** State tracking for compute pipeline
1746 *
1747 * This has anv_cmd_pipeline_state as a base struct to track things which get
1748 * bound to a compute pipeline. Along with general pipeline bind point state
1749 * which is in the anv_cmd_pipeline_state base struct, it also contains other
1750 * state which is compute-specific.
1751 */
1752 struct anv_cmd_compute_state {
1753 struct anv_cmd_pipeline_state base;
1754
1755 bool pipeline_dirty;
1756
1757 struct anv_address num_workgroups;
1758 };
1759
1760 /** State required while building cmd buffer */
1761 struct anv_cmd_state {
1762 /* PIPELINE_SELECT.PipelineSelection */
1763 uint32_t current_pipeline;
1764 const struct gen_l3_config * current_l3_config;
1765
1766 struct anv_cmd_graphics_state gfx;
1767 struct anv_cmd_compute_state compute;
1768
1769 enum anv_pipe_bits pending_pipe_bits;
1770 VkShaderStageFlags descriptors_dirty;
1771 VkShaderStageFlags push_constants_dirty;
1772
1773 struct anv_framebuffer * framebuffer;
1774 struct anv_render_pass * pass;
1775 struct anv_subpass * subpass;
1776 VkRect2D render_area;
1777 uint32_t restart_index;
1778 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1779 VkShaderStageFlags push_constant_stages;
1780 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1781 struct anv_state binding_tables[MESA_SHADER_STAGES];
1782 struct anv_state samplers[MESA_SHADER_STAGES];
1783
1784 /**
1785 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1786 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1787 * and before invoking the secondary in ExecuteCommands.
1788 */
1789 bool pma_fix_enabled;
1790
1791 /**
1792 * Whether or not we know for certain that HiZ is enabled for the current
1793 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1794 * enabled or not, this will be false.
1795 */
1796 bool hiz_enabled;
1797
1798 /**
1799 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1800 * valid only when recording a render pass instance.
1801 */
1802 struct anv_attachment_state * attachments;
1803
1804 /**
1805 * Surface states for color render targets. These are stored in a single
1806 * flat array. For depth-stencil attachments, the surface state is simply
1807 * left blank.
1808 */
1809 struct anv_state render_pass_states;
1810
1811 /**
1812 * A null surface state of the right size to match the framebuffer. This
1813 * is one of the states in render_pass_states.
1814 */
1815 struct anv_state null_surface_state;
1816 };
1817
1818 struct anv_cmd_pool {
1819 VkAllocationCallbacks alloc;
1820 struct list_head cmd_buffers;
1821 };
1822
1823 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1824
1825 enum anv_cmd_buffer_exec_mode {
1826 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1827 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1828 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1829 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1830 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1831 };
1832
1833 struct anv_cmd_buffer {
1834 VK_LOADER_DATA _loader_data;
1835
1836 struct anv_device * device;
1837
1838 struct anv_cmd_pool * pool;
1839 struct list_head pool_link;
1840
1841 struct anv_batch batch;
1842
1843 /* Fields required for the actual chain of anv_batch_bo's.
1844 *
1845 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1846 */
1847 struct list_head batch_bos;
1848 enum anv_cmd_buffer_exec_mode exec_mode;
1849
1850 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1851 * referenced by this command buffer
1852 *
1853 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1854 */
1855 struct u_vector seen_bbos;
1856
1857 /* A vector of int32_t's for every block of binding tables.
1858 *
1859 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1860 */
1861 struct u_vector bt_block_states;
1862 uint32_t bt_next;
1863
1864 struct anv_reloc_list surface_relocs;
1865 /** Last seen surface state block pool center bo offset */
1866 uint32_t last_ss_pool_center;
1867
1868 /* Serial for tracking buffer completion */
1869 uint32_t serial;
1870
1871 /* Stream objects for storing temporary data */
1872 struct anv_state_stream surface_state_stream;
1873 struct anv_state_stream dynamic_state_stream;
1874
1875 VkCommandBufferUsageFlags usage_flags;
1876 VkCommandBufferLevel level;
1877
1878 struct anv_cmd_state state;
1879 };
1880
1881 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1882 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1883 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1884 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1885 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1886 struct anv_cmd_buffer *secondary);
1887 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1888 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1889 struct anv_cmd_buffer *cmd_buffer,
1890 const VkSemaphore *in_semaphores,
1891 uint32_t num_in_semaphores,
1892 const VkSemaphore *out_semaphores,
1893 uint32_t num_out_semaphores,
1894 VkFence fence);
1895
1896 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1897
1898 VkResult
1899 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1900 gl_shader_stage stage, uint32_t size);
1901 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1902 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1903 (offsetof(struct anv_push_constants, field) + \
1904 sizeof(cmd_buffer->state.push_constants[0]->field)))
1905
1906 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1907 const void *data, uint32_t size, uint32_t alignment);
1908 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1909 uint32_t *a, uint32_t *b,
1910 uint32_t dwords, uint32_t alignment);
1911
1912 struct anv_address
1913 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1914 struct anv_state
1915 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1916 uint32_t entries, uint32_t *state_offset);
1917 struct anv_state
1918 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1919 struct anv_state
1920 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1921 uint32_t size, uint32_t alignment);
1922
1923 VkResult
1924 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1925
1926 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1927 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1928 bool depth_clamp_enable);
1929 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1930
1931 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1932 struct anv_render_pass *pass,
1933 struct anv_framebuffer *framebuffer,
1934 const VkClearValue *clear_values);
1935
1936 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1937
1938 struct anv_state
1939 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1940 gl_shader_stage stage);
1941 struct anv_state
1942 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1943
1944 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1945
1946 const struct anv_image_view *
1947 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1948
1949 VkResult
1950 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1951 uint32_t num_entries,
1952 uint32_t *state_offset,
1953 struct anv_state *bt_state);
1954
1955 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1956
1957 enum anv_fence_type {
1958 ANV_FENCE_TYPE_NONE = 0,
1959 ANV_FENCE_TYPE_BO,
1960 ANV_FENCE_TYPE_SYNCOBJ,
1961 };
1962
1963 enum anv_bo_fence_state {
1964 /** Indicates that this is a new (or newly reset fence) */
1965 ANV_BO_FENCE_STATE_RESET,
1966
1967 /** Indicates that this fence has been submitted to the GPU but is still
1968 * (as far as we know) in use by the GPU.
1969 */
1970 ANV_BO_FENCE_STATE_SUBMITTED,
1971
1972 ANV_BO_FENCE_STATE_SIGNALED,
1973 };
1974
1975 struct anv_fence_impl {
1976 enum anv_fence_type type;
1977
1978 union {
1979 /** Fence implementation for BO fences
1980 *
1981 * These fences use a BO and a set of CPU-tracked state flags. The BO
1982 * is added to the object list of the last execbuf call in a QueueSubmit
1983 * and is marked EXEC_WRITE. The state flags track when the BO has been
1984 * submitted to the kernel. We need to do this because Vulkan lets you
1985 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
1986 * will say it's idle in this case.
1987 */
1988 struct {
1989 struct anv_bo bo;
1990 enum anv_bo_fence_state state;
1991 } bo;
1992
1993 /** DRM syncobj handle for syncobj-based fences */
1994 uint32_t syncobj;
1995 };
1996 };
1997
1998 struct anv_fence {
1999 /* Permanent fence state. Every fence has some form of permanent state
2000 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2001 * cross-process fences) or it could just be a dummy for use internally.
2002 */
2003 struct anv_fence_impl permanent;
2004
2005 /* Temporary fence state. A fence *may* have temporary state. That state
2006 * is added to the fence by an import operation and is reset back to
2007 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2008 * state cannot be signaled because the fence must already be signaled
2009 * before the temporary state can be exported from the fence in the other
2010 * process and imported here.
2011 */
2012 struct anv_fence_impl temporary;
2013 };
2014
2015 struct anv_event {
2016 uint64_t semaphore;
2017 struct anv_state state;
2018 };
2019
2020 enum anv_semaphore_type {
2021 ANV_SEMAPHORE_TYPE_NONE = 0,
2022 ANV_SEMAPHORE_TYPE_DUMMY,
2023 ANV_SEMAPHORE_TYPE_BO,
2024 ANV_SEMAPHORE_TYPE_SYNC_FILE,
2025 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
2026 };
2027
2028 struct anv_semaphore_impl {
2029 enum anv_semaphore_type type;
2030
2031 union {
2032 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO.
2033 * This BO will be added to the object list on any execbuf2 calls for
2034 * which this semaphore is used as a wait or signal fence. When used as
2035 * a signal fence, the EXEC_OBJECT_WRITE flag will be set.
2036 */
2037 struct anv_bo *bo;
2038
2039 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
2040 * If the semaphore is in the unsignaled state due to either just being
2041 * created or because it has been used for a wait, fd will be -1.
2042 */
2043 int fd;
2044
2045 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
2046 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
2047 * import so we don't need to bother with a userspace cache.
2048 */
2049 uint32_t syncobj;
2050 };
2051 };
2052
2053 struct anv_semaphore {
2054 /* Permanent semaphore state. Every semaphore has some form of permanent
2055 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
2056 * (for cross-process semaphores0 or it could just be a dummy for use
2057 * internally.
2058 */
2059 struct anv_semaphore_impl permanent;
2060
2061 /* Temporary semaphore state. A semaphore *may* have temporary state.
2062 * That state is added to the semaphore by an import operation and is reset
2063 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
2064 * semaphore with temporary state cannot be signaled because the semaphore
2065 * must already be signaled before the temporary state can be exported from
2066 * the semaphore in the other process and imported here.
2067 */
2068 struct anv_semaphore_impl temporary;
2069 };
2070
2071 void anv_semaphore_reset_temporary(struct anv_device *device,
2072 struct anv_semaphore *semaphore);
2073
2074 struct anv_shader_module {
2075 unsigned char sha1[20];
2076 uint32_t size;
2077 char data[0];
2078 };
2079
2080 static inline gl_shader_stage
2081 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
2082 {
2083 assert(__builtin_popcount(vk_stage) == 1);
2084 return ffs(vk_stage) - 1;
2085 }
2086
2087 static inline VkShaderStageFlagBits
2088 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
2089 {
2090 return (1 << mesa_stage);
2091 }
2092
2093 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
2094
2095 #define anv_foreach_stage(stage, stage_bits) \
2096 for (gl_shader_stage stage, \
2097 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
2098 stage = __builtin_ffs(__tmp) - 1, __tmp; \
2099 __tmp &= ~(1 << (stage)))
2100
2101 struct anv_pipeline_bind_map {
2102 uint32_t surface_count;
2103 uint32_t sampler_count;
2104 uint32_t image_count;
2105
2106 struct anv_pipeline_binding * surface_to_descriptor;
2107 struct anv_pipeline_binding * sampler_to_descriptor;
2108 };
2109
2110 struct anv_shader_bin_key {
2111 uint32_t size;
2112 uint8_t data[0];
2113 };
2114
2115 struct anv_shader_bin {
2116 uint32_t ref_cnt;
2117
2118 const struct anv_shader_bin_key *key;
2119
2120 struct anv_state kernel;
2121 uint32_t kernel_size;
2122
2123 const struct brw_stage_prog_data *prog_data;
2124 uint32_t prog_data_size;
2125
2126 struct anv_pipeline_bind_map bind_map;
2127 };
2128
2129 struct anv_shader_bin *
2130 anv_shader_bin_create(struct anv_device *device,
2131 const void *key, uint32_t key_size,
2132 const void *kernel, uint32_t kernel_size,
2133 const struct brw_stage_prog_data *prog_data,
2134 uint32_t prog_data_size, const void *prog_data_param,
2135 const struct anv_pipeline_bind_map *bind_map);
2136
2137 void
2138 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
2139
2140 static inline void
2141 anv_shader_bin_ref(struct anv_shader_bin *shader)
2142 {
2143 assert(shader && shader->ref_cnt >= 1);
2144 p_atomic_inc(&shader->ref_cnt);
2145 }
2146
2147 static inline void
2148 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
2149 {
2150 assert(shader && shader->ref_cnt >= 1);
2151 if (p_atomic_dec_zero(&shader->ref_cnt))
2152 anv_shader_bin_destroy(device, shader);
2153 }
2154
2155 struct anv_pipeline {
2156 struct anv_device * device;
2157 struct anv_batch batch;
2158 uint32_t batch_data[512];
2159 struct anv_reloc_list batch_relocs;
2160 uint32_t dynamic_state_mask;
2161 struct anv_dynamic_state dynamic_state;
2162
2163 struct anv_subpass * subpass;
2164
2165 bool needs_data_cache;
2166
2167 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
2168
2169 struct {
2170 const struct gen_l3_config * l3_config;
2171 uint32_t total_size;
2172 } urb;
2173
2174 VkShaderStageFlags active_stages;
2175 struct anv_state blend_state;
2176
2177 uint32_t vb_used;
2178 uint32_t binding_stride[MAX_VBS];
2179 bool instancing_enable[MAX_VBS];
2180 bool primitive_restart;
2181 uint32_t topology;
2182
2183 uint32_t cs_right_mask;
2184
2185 bool writes_depth;
2186 bool depth_test_enable;
2187 bool writes_stencil;
2188 bool stencil_test_enable;
2189 bool depth_clamp_enable;
2190 bool sample_shading_enable;
2191 bool kill_pixel;
2192
2193 struct {
2194 uint32_t sf[7];
2195 uint32_t depth_stencil_state[3];
2196 } gen7;
2197
2198 struct {
2199 uint32_t sf[4];
2200 uint32_t raster[5];
2201 uint32_t wm_depth_stencil[3];
2202 } gen8;
2203
2204 struct {
2205 uint32_t wm_depth_stencil[4];
2206 } gen9;
2207
2208 uint32_t interface_descriptor_data[8];
2209 };
2210
2211 static inline bool
2212 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
2213 gl_shader_stage stage)
2214 {
2215 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
2216 }
2217
2218 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
2219 static inline const struct brw_##prefix##_prog_data * \
2220 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
2221 { \
2222 if (anv_pipeline_has_stage(pipeline, stage)) { \
2223 return (const struct brw_##prefix##_prog_data *) \
2224 pipeline->shaders[stage]->prog_data; \
2225 } else { \
2226 return NULL; \
2227 } \
2228 }
2229
2230 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
2231 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
2232 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
2233 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
2234 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
2235 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
2236
2237 static inline const struct brw_vue_prog_data *
2238 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
2239 {
2240 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
2241 return &get_gs_prog_data(pipeline)->base;
2242 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
2243 return &get_tes_prog_data(pipeline)->base;
2244 else
2245 return &get_vs_prog_data(pipeline)->base;
2246 }
2247
2248 VkResult
2249 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
2250 struct anv_pipeline_cache *cache,
2251 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2252 const VkAllocationCallbacks *alloc);
2253
2254 VkResult
2255 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
2256 struct anv_pipeline_cache *cache,
2257 const VkComputePipelineCreateInfo *info,
2258 struct anv_shader_module *module,
2259 const char *entrypoint,
2260 const VkSpecializationInfo *spec_info);
2261
2262 struct anv_format_plane {
2263 enum isl_format isl_format:16;
2264 struct isl_swizzle swizzle;
2265
2266 /* Whether this plane contains chroma channels */
2267 bool has_chroma;
2268
2269 /* For downscaling of YUV planes */
2270 uint8_t denominator_scales[2];
2271
2272 /* How to map sampled ycbcr planes to a single 4 component element. */
2273 struct isl_swizzle ycbcr_swizzle;
2274 };
2275
2276
2277 struct anv_format {
2278 struct anv_format_plane planes[3];
2279 uint8_t n_planes;
2280 bool can_ycbcr;
2281 };
2282
2283 static inline uint32_t
2284 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
2285 VkImageAspectFlags aspect_mask)
2286 {
2287 switch (aspect_mask) {
2288 case VK_IMAGE_ASPECT_COLOR_BIT:
2289 case VK_IMAGE_ASPECT_DEPTH_BIT:
2290 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
2291 return 0;
2292 case VK_IMAGE_ASPECT_STENCIL_BIT:
2293 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
2294 return 0;
2295 /* Fall-through */
2296 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
2297 return 1;
2298 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
2299 return 2;
2300 default:
2301 /* Purposefully assert with depth/stencil aspects. */
2302 unreachable("invalid image aspect");
2303 }
2304 }
2305
2306 static inline uint32_t
2307 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
2308 {
2309 uint32_t planes = 0;
2310
2311 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
2312 VK_IMAGE_ASPECT_DEPTH_BIT |
2313 VK_IMAGE_ASPECT_STENCIL_BIT |
2314 VK_IMAGE_ASPECT_PLANE_0_BIT_KHR))
2315 planes++;
2316 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT_KHR)
2317 planes++;
2318 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT_KHR)
2319 planes++;
2320
2321 return planes;
2322 }
2323
2324 static inline VkImageAspectFlags
2325 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
2326 uint32_t plane)
2327 {
2328 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
2329 if (_mesa_bitcount(image_aspects) > 1)
2330 return VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << plane;
2331 return VK_IMAGE_ASPECT_COLOR_BIT;
2332 }
2333 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
2334 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
2335 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2336 return VK_IMAGE_ASPECT_STENCIL_BIT;
2337 }
2338
2339 #define anv_foreach_image_aspect_bit(b, image, aspects) \
2340 for_each_bit(b, anv_image_expand_aspects(image, aspects))
2341
2342 const struct anv_format *
2343 anv_get_format(VkFormat format);
2344
2345 static inline uint32_t
2346 anv_get_format_planes(VkFormat vk_format)
2347 {
2348 const struct anv_format *format = anv_get_format(vk_format);
2349
2350 return format != NULL ? format->n_planes : 0;
2351 }
2352
2353 struct anv_format_plane
2354 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
2355 VkImageAspectFlagBits aspect, VkImageTiling tiling);
2356
2357 static inline enum isl_format
2358 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
2359 VkImageAspectFlags aspect, VkImageTiling tiling)
2360 {
2361 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
2362 }
2363
2364 static inline struct isl_swizzle
2365 anv_swizzle_for_render(struct isl_swizzle swizzle)
2366 {
2367 /* Sometimes the swizzle will have alpha map to one. We do this to fake
2368 * RGB as RGBA for texturing
2369 */
2370 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
2371 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
2372
2373 /* But it doesn't matter what we render to that channel */
2374 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
2375
2376 return swizzle;
2377 }
2378
2379 void
2380 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
2381
2382 /**
2383 * Subsurface of an anv_image.
2384 */
2385 struct anv_surface {
2386 /** Valid only if isl_surf::size > 0. */
2387 struct isl_surf isl;
2388
2389 /**
2390 * Offset from VkImage's base address, as bound by vkBindImageMemory().
2391 */
2392 uint32_t offset;
2393 };
2394
2395 struct anv_image {
2396 VkImageType type;
2397 /* The original VkFormat provided by the client. This may not match any
2398 * of the actual surface formats.
2399 */
2400 VkFormat vk_format;
2401 const struct anv_format *format;
2402
2403 VkImageAspectFlags aspects;
2404 VkExtent3D extent;
2405 uint32_t levels;
2406 uint32_t array_size;
2407 uint32_t samples; /**< VkImageCreateInfo::samples */
2408 uint32_t n_planes;
2409 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
2410 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
2411
2412 /** True if this is needs to be bound to an appropriately tiled BO.
2413 *
2414 * When not using modifiers, consumers such as X11, Wayland, and KMS need
2415 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
2416 * we require a dedicated allocation so that we can know to allocate a
2417 * tiled buffer.
2418 */
2419 bool needs_set_tiling;
2420
2421 /**
2422 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
2423 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
2424 */
2425 uint64_t drm_format_mod;
2426
2427 VkDeviceSize size;
2428 uint32_t alignment;
2429
2430 /* Whether the image is made of several underlying buffer objects rather a
2431 * single one with different offsets.
2432 */
2433 bool disjoint;
2434
2435 /**
2436 * Image subsurfaces
2437 *
2438 * For each foo, anv_image::planes[x].surface is valid if and only if
2439 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
2440 * to figure the number associated with a given aspect.
2441 *
2442 * The hardware requires that the depth buffer and stencil buffer be
2443 * separate surfaces. From Vulkan's perspective, though, depth and stencil
2444 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
2445 * allocate the depth and stencil buffers as separate surfaces in the same
2446 * bo.
2447 *
2448 * Memory layout :
2449 *
2450 * -----------------------
2451 * | surface0 | /|\
2452 * ----------------------- |
2453 * | shadow surface0 | |
2454 * ----------------------- | Plane 0
2455 * | aux surface0 | |
2456 * ----------------------- |
2457 * | fast clear colors0 | \|/
2458 * -----------------------
2459 * | surface1 | /|\
2460 * ----------------------- |
2461 * | shadow surface1 | |
2462 * ----------------------- | Plane 1
2463 * | aux surface1 | |
2464 * ----------------------- |
2465 * | fast clear colors1 | \|/
2466 * -----------------------
2467 * | ... |
2468 * | |
2469 * -----------------------
2470 */
2471 struct {
2472 /**
2473 * Offset of the entire plane (whenever the image is disjoint this is
2474 * set to 0).
2475 */
2476 uint32_t offset;
2477
2478 VkDeviceSize size;
2479 uint32_t alignment;
2480
2481 struct anv_surface surface;
2482
2483 /**
2484 * A surface which shadows the main surface and may have different
2485 * tiling. This is used for sampling using a tiling that isn't supported
2486 * for other operations.
2487 */
2488 struct anv_surface shadow_surface;
2489
2490 /**
2491 * For color images, this is the aux usage for this image when not used
2492 * as a color attachment.
2493 *
2494 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the
2495 * image has a HiZ buffer.
2496 */
2497 enum isl_aux_usage aux_usage;
2498
2499 struct anv_surface aux_surface;
2500
2501 /**
2502 * Offset of the fast clear state (used to compute the
2503 * fast_clear_state_offset of the following planes).
2504 */
2505 uint32_t fast_clear_state_offset;
2506
2507 /**
2508 * BO associated with this plane, set when bound.
2509 */
2510 struct anv_bo *bo;
2511 VkDeviceSize bo_offset;
2512
2513 /**
2514 * When destroying the image, also free the bo.
2515 * */
2516 bool bo_is_owned;
2517 } planes[3];
2518 };
2519
2520 /* The ordering of this enum is important */
2521 enum anv_fast_clear_type {
2522 /** Image does not have/support any fast-clear blocks */
2523 ANV_FAST_CLEAR_NONE = 0,
2524 /** Image has/supports fast-clear but only to the default value */
2525 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
2526 /** Image has/supports fast-clear with an arbitrary fast-clear value */
2527 ANV_FAST_CLEAR_ANY = 2,
2528 };
2529
2530 /* Returns the number of auxiliary buffer levels attached to an image. */
2531 static inline uint8_t
2532 anv_image_aux_levels(const struct anv_image * const image,
2533 VkImageAspectFlagBits aspect)
2534 {
2535 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2536 return image->planes[plane].aux_surface.isl.size > 0 ?
2537 image->planes[plane].aux_surface.isl.levels : 0;
2538 }
2539
2540 /* Returns the number of auxiliary buffer layers attached to an image. */
2541 static inline uint32_t
2542 anv_image_aux_layers(const struct anv_image * const image,
2543 VkImageAspectFlagBits aspect,
2544 const uint8_t miplevel)
2545 {
2546 assert(image);
2547
2548 /* The miplevel must exist in the main buffer. */
2549 assert(miplevel < image->levels);
2550
2551 if (miplevel >= anv_image_aux_levels(image, aspect)) {
2552 /* There are no layers with auxiliary data because the miplevel has no
2553 * auxiliary data.
2554 */
2555 return 0;
2556 } else {
2557 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2558 return MAX2(image->planes[plane].aux_surface.isl.logical_level0_px.array_len,
2559 image->planes[plane].aux_surface.isl.logical_level0_px.depth >> miplevel);
2560 }
2561 }
2562
2563 static inline struct anv_address
2564 anv_image_get_clear_color_addr(const struct anv_device *device,
2565 const struct anv_image *image,
2566 VkImageAspectFlagBits aspect)
2567 {
2568 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
2569
2570 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2571 return (struct anv_address) {
2572 .bo = image->planes[plane].bo,
2573 .offset = image->planes[plane].bo_offset +
2574 image->planes[plane].fast_clear_state_offset,
2575 };
2576 }
2577
2578 static inline struct anv_address
2579 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
2580 const struct anv_image *image,
2581 VkImageAspectFlagBits aspect)
2582 {
2583 struct anv_address addr =
2584 anv_image_get_clear_color_addr(device, image, aspect);
2585 addr.offset += device->isl_dev.ss.clear_value_size;
2586 return addr;
2587 }
2588
2589 static inline struct anv_address
2590 anv_image_get_compression_state_addr(const struct anv_device *device,
2591 const struct anv_image *image,
2592 VkImageAspectFlagBits aspect,
2593 uint32_t level, uint32_t array_layer)
2594 {
2595 assert(level < anv_image_aux_levels(image, aspect));
2596 assert(array_layer < anv_image_aux_layers(image, aspect, level));
2597 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
2598 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
2599
2600 struct anv_address addr =
2601 anv_image_get_fast_clear_type_addr(device, image, aspect);
2602 addr.offset += 4; /* Go past the fast clear type */
2603
2604 if (image->type == VK_IMAGE_TYPE_3D) {
2605 for (uint32_t l = 0; l < level; l++)
2606 addr.offset += anv_minify(image->extent.depth, l) * 4;
2607 } else {
2608 addr.offset += level * image->array_size * 4;
2609 }
2610 addr.offset += array_layer * 4;
2611
2612 return addr;
2613 }
2614
2615 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
2616 static inline bool
2617 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
2618 const struct anv_image *image)
2619 {
2620 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
2621 return false;
2622
2623 if (devinfo->gen < 8)
2624 return false;
2625
2626 return image->samples == 1;
2627 }
2628
2629 void
2630 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
2631 const struct anv_image *image,
2632 VkImageAspectFlagBits aspect,
2633 enum isl_aux_usage aux_usage,
2634 uint32_t level,
2635 uint32_t base_layer,
2636 uint32_t layer_count);
2637
2638 void
2639 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
2640 const struct anv_image *image,
2641 VkImageAspectFlagBits aspect,
2642 enum isl_aux_usage aux_usage,
2643 enum isl_format format, struct isl_swizzle swizzle,
2644 uint32_t level, uint32_t base_layer, uint32_t layer_count,
2645 VkRect2D area, union isl_color_value clear_color);
2646 void
2647 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
2648 const struct anv_image *image,
2649 VkImageAspectFlags aspects,
2650 enum isl_aux_usage depth_aux_usage,
2651 uint32_t level,
2652 uint32_t base_layer, uint32_t layer_count,
2653 VkRect2D area,
2654 float depth_value, uint8_t stencil_value);
2655 void
2656 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
2657 const struct anv_image *image,
2658 VkImageAspectFlagBits aspect, uint32_t level,
2659 uint32_t base_layer, uint32_t layer_count,
2660 enum isl_aux_op hiz_op);
2661 void
2662 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
2663 const struct anv_image *image,
2664 VkImageAspectFlags aspects,
2665 uint32_t level,
2666 uint32_t base_layer, uint32_t layer_count,
2667 VkRect2D area, uint8_t stencil_value);
2668 void
2669 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
2670 const struct anv_image *image,
2671 VkImageAspectFlagBits aspect,
2672 uint32_t base_layer, uint32_t layer_count,
2673 enum isl_aux_op mcs_op, bool predicate);
2674 void
2675 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
2676 const struct anv_image *image,
2677 VkImageAspectFlagBits aspect, uint32_t level,
2678 uint32_t base_layer, uint32_t layer_count,
2679 enum isl_aux_op ccs_op, bool predicate);
2680
2681 void
2682 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
2683 const struct anv_image *image,
2684 uint32_t base_level, uint32_t level_count,
2685 uint32_t base_layer, uint32_t layer_count);
2686
2687 enum isl_aux_usage
2688 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
2689 const struct anv_image *image,
2690 const VkImageAspectFlagBits aspect,
2691 const VkImageLayout layout);
2692
2693 enum anv_fast_clear_type
2694 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
2695 const struct anv_image * const image,
2696 const VkImageAspectFlagBits aspect,
2697 const VkImageLayout layout);
2698
2699 /* This is defined as a macro so that it works for both
2700 * VkImageSubresourceRange and VkImageSubresourceLayers
2701 */
2702 #define anv_get_layerCount(_image, _range) \
2703 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
2704 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
2705
2706 static inline uint32_t
2707 anv_get_levelCount(const struct anv_image *image,
2708 const VkImageSubresourceRange *range)
2709 {
2710 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2711 image->levels - range->baseMipLevel : range->levelCount;
2712 }
2713
2714 static inline VkImageAspectFlags
2715 anv_image_expand_aspects(const struct anv_image *image,
2716 VkImageAspectFlags aspects)
2717 {
2718 /* If the underlying image has color plane aspects and
2719 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
2720 * the underlying image. */
2721 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
2722 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
2723 return image->aspects;
2724
2725 return aspects;
2726 }
2727
2728 static inline bool
2729 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
2730 VkImageAspectFlags aspects2)
2731 {
2732 if (aspects1 == aspects2)
2733 return true;
2734
2735 /* Only 1 color aspects are compatibles. */
2736 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2737 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
2738 _mesa_bitcount(aspects1) == _mesa_bitcount(aspects2))
2739 return true;
2740
2741 return false;
2742 }
2743
2744 struct anv_image_view {
2745 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
2746
2747 VkImageAspectFlags aspect_mask;
2748 VkFormat vk_format;
2749 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2750
2751 unsigned n_planes;
2752 struct {
2753 uint32_t image_plane;
2754
2755 struct isl_view isl;
2756
2757 /**
2758 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2759 * image layout of SHADER_READ_ONLY_OPTIMAL or
2760 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
2761 */
2762 struct anv_surface_state optimal_sampler_surface_state;
2763
2764 /**
2765 * RENDER_SURFACE_STATE when using image as a sampler surface with an
2766 * image layout of GENERAL.
2767 */
2768 struct anv_surface_state general_sampler_surface_state;
2769
2770 /**
2771 * RENDER_SURFACE_STATE when using image as a storage image. Separate
2772 * states for write-only and readable, using the real format for
2773 * write-only and the lowered format for readable.
2774 */
2775 struct anv_surface_state storage_surface_state;
2776 struct anv_surface_state writeonly_storage_surface_state;
2777
2778 struct brw_image_param storage_image_param;
2779 } planes[3];
2780 };
2781
2782 enum anv_image_view_state_flags {
2783 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
2784 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
2785 };
2786
2787 void anv_image_fill_surface_state(struct anv_device *device,
2788 const struct anv_image *image,
2789 VkImageAspectFlagBits aspect,
2790 const struct isl_view *view,
2791 isl_surf_usage_flags_t view_usage,
2792 enum isl_aux_usage aux_usage,
2793 const union isl_color_value *clear_color,
2794 enum anv_image_view_state_flags flags,
2795 struct anv_surface_state *state_inout,
2796 struct brw_image_param *image_param_out);
2797
2798 struct anv_image_create_info {
2799 const VkImageCreateInfo *vk_info;
2800
2801 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
2802 isl_tiling_flags_t isl_tiling_flags;
2803
2804 /** These flags will be added to any derived from VkImageCreateInfo. */
2805 isl_surf_usage_flags_t isl_extra_usage_flags;
2806
2807 uint32_t stride;
2808 };
2809
2810 VkResult anv_image_create(VkDevice _device,
2811 const struct anv_image_create_info *info,
2812 const VkAllocationCallbacks* alloc,
2813 VkImage *pImage);
2814
2815 #ifdef ANDROID
2816 VkResult anv_image_from_gralloc(VkDevice device_h,
2817 const VkImageCreateInfo *base_info,
2818 const VkNativeBufferANDROID *gralloc_info,
2819 const VkAllocationCallbacks *alloc,
2820 VkImage *pImage);
2821 #endif
2822
2823 const struct anv_surface *
2824 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
2825 VkImageAspectFlags aspect_mask);
2826
2827 enum isl_format
2828 anv_isl_format_for_descriptor_type(VkDescriptorType type);
2829
2830 static inline struct VkExtent3D
2831 anv_sanitize_image_extent(const VkImageType imageType,
2832 const struct VkExtent3D imageExtent)
2833 {
2834 switch (imageType) {
2835 case VK_IMAGE_TYPE_1D:
2836 return (VkExtent3D) { imageExtent.width, 1, 1 };
2837 case VK_IMAGE_TYPE_2D:
2838 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2839 case VK_IMAGE_TYPE_3D:
2840 return imageExtent;
2841 default:
2842 unreachable("invalid image type");
2843 }
2844 }
2845
2846 static inline struct VkOffset3D
2847 anv_sanitize_image_offset(const VkImageType imageType,
2848 const struct VkOffset3D imageOffset)
2849 {
2850 switch (imageType) {
2851 case VK_IMAGE_TYPE_1D:
2852 return (VkOffset3D) { imageOffset.x, 0, 0 };
2853 case VK_IMAGE_TYPE_2D:
2854 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2855 case VK_IMAGE_TYPE_3D:
2856 return imageOffset;
2857 default:
2858 unreachable("invalid image type");
2859 }
2860 }
2861
2862
2863 void anv_fill_buffer_surface_state(struct anv_device *device,
2864 struct anv_state state,
2865 enum isl_format format,
2866 uint32_t offset, uint32_t range,
2867 uint32_t stride);
2868
2869
2870 struct anv_ycbcr_conversion {
2871 const struct anv_format * format;
2872 VkSamplerYcbcrModelConversionKHR ycbcr_model;
2873 VkSamplerYcbcrRangeKHR ycbcr_range;
2874 VkComponentSwizzle mapping[4];
2875 VkChromaLocationKHR chroma_offsets[2];
2876 VkFilter chroma_filter;
2877 bool chroma_reconstruction;
2878 };
2879
2880 struct anv_sampler {
2881 uint32_t state[3][4];
2882 uint32_t n_planes;
2883 struct anv_ycbcr_conversion *conversion;
2884 };
2885
2886 struct anv_framebuffer {
2887 uint32_t width;
2888 uint32_t height;
2889 uint32_t layers;
2890
2891 uint32_t attachment_count;
2892 struct anv_image_view * attachments[0];
2893 };
2894
2895 struct anv_subpass_attachment {
2896 VkImageUsageFlagBits usage;
2897 uint32_t attachment;
2898 VkImageLayout layout;
2899 };
2900
2901 struct anv_subpass {
2902 uint32_t attachment_count;
2903
2904 /**
2905 * A pointer to all attachment references used in this subpass.
2906 * Only valid if ::attachment_count > 0.
2907 */
2908 struct anv_subpass_attachment * attachments;
2909 uint32_t input_count;
2910 struct anv_subpass_attachment * input_attachments;
2911 uint32_t color_count;
2912 struct anv_subpass_attachment * color_attachments;
2913 struct anv_subpass_attachment * resolve_attachments;
2914
2915 struct anv_subpass_attachment depth_stencil_attachment;
2916
2917 uint32_t view_mask;
2918
2919 /** Subpass has a depth/stencil self-dependency */
2920 bool has_ds_self_dep;
2921
2922 /** Subpass has at least one resolve attachment */
2923 bool has_resolve;
2924 };
2925
2926 static inline unsigned
2927 anv_subpass_view_count(const struct anv_subpass *subpass)
2928 {
2929 return MAX2(1, _mesa_bitcount(subpass->view_mask));
2930 }
2931
2932 struct anv_render_pass_attachment {
2933 /* TODO: Consider using VkAttachmentDescription instead of storing each of
2934 * its members individually.
2935 */
2936 VkFormat format;
2937 uint32_t samples;
2938 VkImageUsageFlags usage;
2939 VkAttachmentLoadOp load_op;
2940 VkAttachmentStoreOp store_op;
2941 VkAttachmentLoadOp stencil_load_op;
2942 VkImageLayout initial_layout;
2943 VkImageLayout final_layout;
2944 VkImageLayout first_subpass_layout;
2945
2946 /* The subpass id in which the attachment will be used last. */
2947 uint32_t last_subpass_idx;
2948 };
2949
2950 struct anv_render_pass {
2951 uint32_t attachment_count;
2952 uint32_t subpass_count;
2953 /* An array of subpass_count+1 flushes, one per subpass boundary */
2954 enum anv_pipe_bits * subpass_flushes;
2955 struct anv_render_pass_attachment * attachments;
2956 struct anv_subpass subpasses[0];
2957 };
2958
2959 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
2960
2961 struct anv_query_pool {
2962 VkQueryType type;
2963 VkQueryPipelineStatisticFlags pipeline_statistics;
2964 /** Stride between slots, in bytes */
2965 uint32_t stride;
2966 /** Number of slots in this query pool */
2967 uint32_t slots;
2968 struct anv_bo bo;
2969 };
2970
2971 int anv_get_entrypoint_index(const char *name);
2972
2973 bool
2974 anv_entrypoint_is_enabled(int index, uint32_t core_version,
2975 const struct anv_instance_extension_table *instance,
2976 const struct anv_device_extension_table *device);
2977
2978 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
2979 const char *name);
2980
2981 void anv_dump_image_to_ppm(struct anv_device *device,
2982 struct anv_image *image, unsigned miplevel,
2983 unsigned array_layer, VkImageAspectFlagBits aspect,
2984 const char *filename);
2985
2986 enum anv_dump_action {
2987 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
2988 };
2989
2990 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
2991 void anv_dump_finish(void);
2992
2993 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
2994 struct anv_framebuffer *fb);
2995
2996 static inline uint32_t
2997 anv_get_subpass_id(const struct anv_cmd_state * const cmd_state)
2998 {
2999 /* This function must be called from within a subpass. */
3000 assert(cmd_state->pass && cmd_state->subpass);
3001
3002 const uint32_t subpass_id = cmd_state->subpass - cmd_state->pass->subpasses;
3003
3004 /* The id of this subpass shouldn't exceed the number of subpasses in this
3005 * render pass minus 1.
3006 */
3007 assert(subpass_id < cmd_state->pass->subpass_count);
3008 return subpass_id;
3009 }
3010
3011 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
3012 \
3013 static inline struct __anv_type * \
3014 __anv_type ## _from_handle(__VkType _handle) \
3015 { \
3016 return (struct __anv_type *) _handle; \
3017 } \
3018 \
3019 static inline __VkType \
3020 __anv_type ## _to_handle(struct __anv_type *_obj) \
3021 { \
3022 return (__VkType) _obj; \
3023 }
3024
3025 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
3026 \
3027 static inline struct __anv_type * \
3028 __anv_type ## _from_handle(__VkType _handle) \
3029 { \
3030 return (struct __anv_type *)(uintptr_t) _handle; \
3031 } \
3032 \
3033 static inline __VkType \
3034 __anv_type ## _to_handle(struct __anv_type *_obj) \
3035 { \
3036 return (__VkType)(uintptr_t) _obj; \
3037 }
3038
3039 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
3040 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
3041
3042 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
3043 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
3044 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
3045 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
3046 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
3047
3048 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
3049 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
3050 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
3051 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
3052 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
3053 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
3054 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
3055 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
3056 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
3057 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
3058 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
3059 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
3060 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
3061 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
3062 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
3063 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
3064 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
3065 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
3066 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
3067 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore, VkSemaphore)
3068 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
3069 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback, VkDebugReportCallbackEXT)
3070 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion, VkSamplerYcbcrConversionKHR)
3071
3072 /* Gen-specific function declarations */
3073 #ifdef genX
3074 # include "anv_genX.h"
3075 #else
3076 # define genX(x) gen7_##x
3077 # include "anv_genX.h"
3078 # undef genX
3079 # define genX(x) gen75_##x
3080 # include "anv_genX.h"
3081 # undef genX
3082 # define genX(x) gen8_##x
3083 # include "anv_genX.h"
3084 # undef genX
3085 # define genX(x) gen9_##x
3086 # include "anv_genX.h"
3087 # undef genX
3088 # define genX(x) gen10_##x
3089 # include "anv_genX.h"
3090 # undef genX
3091 # define genX(x) gen11_##x
3092 # include "anv_genX.h"
3093 # undef genX
3094 #endif
3095
3096 #endif /* ANV_PRIVATE_H */