2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
76 struct anv_buffer_view
;
77 struct anv_image_view
;
80 struct gen_aux_map_context
;
81 struct gen_perf_config
;
82 struct gen_perf_counter_pass
;
83 struct gen_perf_query_result
;
85 #include <vulkan/vulkan.h>
86 #include <vulkan/vulkan_intel.h>
87 #include <vulkan/vk_icd.h>
89 #include "anv_android.h"
90 #include "anv_entrypoints.h"
91 #include "anv_extensions.h"
94 #include "dev/gen_debug.h"
95 #include "common/intel_log.h"
96 #include "wsi_common.h"
98 #define NSEC_PER_SEC 1000000000ull
100 /* anv Virtual Memory Layout
101 * =========================
103 * When the anv driver is determining the virtual graphics addresses of memory
104 * objects itself using the softpin mechanism, the following memory ranges
107 * Three special considerations to notice:
109 * (1) the dynamic state pool is located within the same 4 GiB as the low
110 * heap. This is to work around a VF cache issue described in a comment in
111 * anv_physical_device_init_heaps.
113 * (2) the binding table pool is located at lower addresses than the surface
114 * state pool, within a 4 GiB range. This allows surface state base addresses
115 * to cover both binding tables (16 bit offsets) and surface states (32 bit
118 * (3) the last 4 GiB of the address space is withheld from the high
119 * heap. Various hardware units will read past the end of an object for
120 * various reasons. This healthy margin prevents reads from wrapping around
123 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
124 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
125 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
126 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
127 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
128 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
129 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
130 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
131 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
132 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
133 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
134 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
135 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
137 #define LOW_HEAP_SIZE \
138 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
139 #define DYNAMIC_STATE_POOL_SIZE \
140 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
141 #define BINDING_TABLE_POOL_SIZE \
142 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
143 #define SURFACE_STATE_POOL_SIZE \
144 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
145 #define INSTRUCTION_STATE_POOL_SIZE \
146 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
147 #define CLIENT_VISIBLE_HEAP_SIZE \
148 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
150 /* Allowing different clear colors requires us to perform a depth resolve at
151 * the end of certain render passes. This is because while slow clears store
152 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
153 * See the PRMs for examples describing when additional resolves would be
154 * necessary. To enable fast clears without requiring extra resolves, we set
155 * the clear value to a globally-defined one. We could allow different values
156 * if the user doesn't expect coherent data during or after a render passes
157 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
158 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
159 * 1.0f seems to be the only value used. The only application that doesn't set
160 * this value does so through the usage of an seemingly uninitialized clear
163 #define ANV_HZ_FC_VAL 1.0f
166 #define MAX_XFB_BUFFERS 4
167 #define MAX_XFB_STREAMS 4
170 #define MAX_VIEWPORTS 16
171 #define MAX_SCISSORS 16
172 #define MAX_PUSH_CONSTANTS_SIZE 128
173 #define MAX_DYNAMIC_BUFFERS 16
174 #define MAX_IMAGES 64
175 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
176 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
177 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
178 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
179 * use 64 here to avoid cache issues. This could most likely bring it back to
180 * 32 if we had different virtual addresses for the different views on a given
183 #define ANV_UBO_ALIGNMENT 64
184 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
185 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
187 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
189 * "The surface state model is used when a Binding Table Index (specified
190 * in the message descriptor) of less than 240 is specified. In this model,
191 * the Binding Table Index is used to index into the binding table, and the
192 * binding table entry contains a pointer to the SURFACE_STATE."
194 * Binding table values above 240 are used for various things in the hardware
195 * such as stateless, stateless with incoherent cache, SLM, and bindless.
197 #define MAX_BINDING_TABLE_SIZE 240
199 /* The kernel relocation API has a limitation of a 32-bit delta value
200 * applied to the address before it is written which, in spite of it being
201 * unsigned, is treated as signed . Because of the way that this maps to
202 * the Vulkan API, we cannot handle an offset into a buffer that does not
203 * fit into a signed 32 bits. The only mechanism we have for dealing with
204 * this at the moment is to limit all VkDeviceMemory objects to a maximum
205 * of 2GB each. The Vulkan spec allows us to do this:
207 * "Some platforms may have a limit on the maximum size of a single
208 * allocation. For example, certain systems may fail to create
209 * allocations with a size greater than or equal to 4GB. Such a limit is
210 * implementation-dependent, and if such a failure occurs then the error
211 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
213 * We don't use vk_error here because it's not an error so much as an
214 * indication to the application that the allocation is too large.
216 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
218 #define ANV_SVGS_VB_INDEX MAX_VBS
219 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
221 /* We reserve this MI ALU register for the purpose of handling predication.
222 * Other code which uses the MI ALU should leave it alone.
224 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
226 /* We reserve this MI ALU register to pass around an offset computed from
227 * VkPerformanceQuerySubmitInfoKHR::counterPassIndex VK_KHR_performance_query.
228 * Other code which uses the MI ALU should leave it alone.
230 #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
232 /* For gen12 we set the streamout buffers using 4 separate commands
233 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
234 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
235 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
236 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
237 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
238 * 3DSTATE_SO_BUFFER_INDEX_0.
240 #define SO_BUFFER_INDEX_0_CMD 0x60
241 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
243 static inline uint32_t
244 align_down_npot_u32(uint32_t v
, uint32_t a
)
249 static inline uint32_t
250 align_down_u32(uint32_t v
, uint32_t a
)
252 assert(a
!= 0 && a
== (a
& -a
));
256 static inline uint32_t
257 align_u32(uint32_t v
, uint32_t a
)
259 assert(a
!= 0 && a
== (a
& -a
));
260 return align_down_u32(v
+ a
- 1, a
);
263 static inline uint64_t
264 align_down_u64(uint64_t v
, uint64_t a
)
266 assert(a
!= 0 && a
== (a
& -a
));
270 static inline uint64_t
271 align_u64(uint64_t v
, uint64_t a
)
273 return align_down_u64(v
+ a
- 1, a
);
276 static inline int32_t
277 align_i32(int32_t v
, int32_t a
)
279 assert(a
!= 0 && a
== (a
& -a
));
280 return (v
+ a
- 1) & ~(a
- 1);
283 /** Alignment must be a power of 2. */
285 anv_is_aligned(uintmax_t n
, uintmax_t a
)
287 assert(a
== (a
& -a
));
288 return (n
& (a
- 1)) == 0;
291 static inline uint32_t
292 anv_minify(uint32_t n
, uint32_t levels
)
294 if (unlikely(n
== 0))
297 return MAX2(n
>> levels
, 1);
301 anv_clamp_f(float f
, float min
, float max
)
314 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
316 if (*inout_mask
& clear_mask
) {
317 *inout_mask
&= ~clear_mask
;
324 static inline union isl_color_value
325 vk_to_isl_color(VkClearColorValue color
)
327 return (union isl_color_value
) {
337 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
339 uintptr_t mask
= (1ull << bits
) - 1;
341 return (void *) (ptr
& ~mask
);
344 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
346 uintptr_t value
= (uintptr_t) ptr
;
347 uintptr_t mask
= (1ull << bits
) - 1;
348 return value
| (mask
& flags
);
351 #define for_each_bit(b, dword) \
352 for (uint32_t __dword = (dword); \
353 (b) = __builtin_ffs(__dword) - 1, __dword; \
354 __dword &= ~(1 << (b)))
356 #define typed_memcpy(dest, src, count) ({ \
357 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
358 memcpy((dest), (src), (count) * sizeof(*(src))); \
361 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
362 * to be added here in order to utilize mapping in debug/error/perf macros.
364 #define REPORT_OBJECT_TYPE(o) \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
443 __builtin_choose_expr ( \
444 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
445 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
446 __builtin_choose_expr ( \
447 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
448 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
449 __builtin_choose_expr ( \
450 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
451 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
452 __builtin_choose_expr ( \
453 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
454 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
455 __builtin_choose_expr ( \
456 __builtin_types_compatible_p (__typeof (o), void*), \
457 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
458 /* The void expression results in a compile-time error \
459 when assigning the result to something. */ \
460 (void)0)))))))))))))))))))))))))))))))
462 /* Whenever we generate an error, pass it through this function. Useful for
463 * debugging, where we can break on it. Only call at error site, not when
464 * propagating errors. Might be useful to plug in a stack trace here.
467 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
468 VkDebugReportObjectTypeEXT type
, VkResult error
,
469 const char *file
, int line
, const char *format
,
472 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
473 VkDebugReportObjectTypeEXT type
, VkResult error
,
474 const char *file
, int line
, const char *format
, ...)
475 anv_printflike(7, 8);
478 #define vk_error(error) __vk_errorf(NULL, NULL,\
479 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
480 error, __FILE__, __LINE__, NULL)
481 #define vk_errorfi(instance, obj, error, format, ...)\
482 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
483 __FILE__, __LINE__, format, ## __VA_ARGS__)
484 #define vk_errorf(device, obj, error, format, ...)\
485 vk_errorfi(anv_device_instance_or_null(device),\
486 obj, error, format, ## __VA_ARGS__)
488 #define vk_error(error) error
489 #define vk_errorfi(instance, obj, error, format, ...) error
490 #define vk_errorf(device, obj, error, format, ...) error
494 * Warn on ignored extension structs.
496 * The Vulkan spec requires us to ignore unsupported or unknown structs in
497 * a pNext chain. In debug mode, emitting warnings for ignored structs may
498 * help us discover structs that we should not have ignored.
501 * From the Vulkan 1.0.38 spec:
503 * Any component of the implementation (the loader, any enabled layers,
504 * and drivers) must skip over, without processing (other than reading the
505 * sType and pNext members) any chained structures with sType values not
506 * defined by extensions supported by that component.
508 #define anv_debug_ignored_stype(sType) \
509 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
511 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
512 VkDebugReportObjectTypeEXT type
, const char *file
,
513 int line
, const char *format
, ...)
514 anv_printflike(6, 7);
515 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
516 void anv_loge_v(const char *format
, va_list va
);
519 * Print a FINISHME message, including its source location.
521 #define anv_finishme(format, ...) \
523 static bool reported = false; \
525 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
532 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
534 #define anv_perf_warn(instance, obj, format, ...) \
536 static bool reported = false; \
537 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
538 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
539 format, ##__VA_ARGS__); \
544 /* A non-fatal assert. Useful for debugging. */
546 #define anv_assert(x) ({ \
547 if (unlikely(!(x))) \
548 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
551 #define anv_assert(x)
554 /* A multi-pointer allocator
556 * When copying data structures from the user (such as a render pass), it's
557 * common to need to allocate data for a bunch of different things. Instead
558 * of doing several allocations and having to handle all of the error checking
559 * that entails, it can be easier to do a single allocation. This struct
560 * helps facilitate that. The intended usage looks like this:
563 * anv_multialloc_add(&ma, &main_ptr, 1);
564 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
565 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
567 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
568 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
570 struct anv_multialloc
{
578 #define ANV_MULTIALLOC_INIT \
579 ((struct anv_multialloc) { 0, })
581 #define ANV_MULTIALLOC(_name) \
582 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
584 __attribute__((always_inline
))
586 _anv_multialloc_add(struct anv_multialloc
*ma
,
587 void **ptr
, size_t size
, size_t align
)
589 size_t offset
= align_u64(ma
->size
, align
);
590 ma
->size
= offset
+ size
;
591 ma
->align
= MAX2(ma
->align
, align
);
593 /* Store the offset in the pointer. */
594 *ptr
= (void *)(uintptr_t)offset
;
596 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
597 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
600 #define anv_multialloc_add_size(_ma, _ptr, _size) \
601 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
603 #define anv_multialloc_add(_ma, _ptr, _count) \
604 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
606 __attribute__((always_inline
))
608 anv_multialloc_alloc(struct anv_multialloc
*ma
,
609 const VkAllocationCallbacks
*alloc
,
610 VkSystemAllocationScope scope
)
612 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
616 /* Fill out each of the pointers with their final value.
618 * for (uint32_t i = 0; i < ma->ptr_count; i++)
619 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
621 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
622 * constant, GCC is incapable of figuring this out and unrolling the loop
623 * so we have to give it a little help.
625 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
626 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
627 if ((_i) < ma->ptr_count) \
628 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
629 _ANV_MULTIALLOC_UPDATE_POINTER(0);
630 _ANV_MULTIALLOC_UPDATE_POINTER(1);
631 _ANV_MULTIALLOC_UPDATE_POINTER(2);
632 _ANV_MULTIALLOC_UPDATE_POINTER(3);
633 _ANV_MULTIALLOC_UPDATE_POINTER(4);
634 _ANV_MULTIALLOC_UPDATE_POINTER(5);
635 _ANV_MULTIALLOC_UPDATE_POINTER(6);
636 _ANV_MULTIALLOC_UPDATE_POINTER(7);
637 #undef _ANV_MULTIALLOC_UPDATE_POINTER
642 __attribute__((always_inline
))
644 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
645 const VkAllocationCallbacks
*parent_alloc
,
646 const VkAllocationCallbacks
*alloc
,
647 VkSystemAllocationScope scope
)
649 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
657 /* Index into the current validation list. This is used by the
658 * validation list building alrogithm to track which buffers are already
659 * in the validation list so that we can ensure uniqueness.
663 /* Index for use with util_sparse_array_free_list */
666 /* Last known offset. This value is provided by the kernel when we
667 * execbuf and is used as the presumed offset for the next bunch of
672 /** Size of the buffer not including implicit aux */
675 /* Map for internally mapped BOs.
677 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
681 /** Size of the implicit CCS range at the end of the buffer
683 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
684 * page of main surface data maps to a 256B chunk of CCS data and that
685 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
686 * addresses in the main surface to virtual memory addresses for CCS data.
688 * Because we can't change these maps around easily and because Vulkan
689 * allows two VkImages to be bound to overlapping memory regions (as long
690 * as the app is careful), it's not feasible to make this mapping part of
691 * the image. (On Gen11 and earlier, the mapping was provided via
692 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
693 * Instead, we attach the CCS data directly to the buffer object and setup
694 * the AUX table mapping at BO creation time.
696 * This field is for internal tracking use by the BO allocator only and
697 * should not be touched by other parts of the code. If something wants to
698 * know if a BO has implicit CCS data, it should instead look at the
699 * has_implicit_ccs boolean below.
701 * This data is not included in maps of this buffer.
705 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
708 /** True if this BO may be shared with other processes */
711 /** True if this BO is a wrapper
713 * When set to true, none of the fields in this BO are meaningful except
714 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
715 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
716 * is set in the physical device.
720 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
721 bool has_fixed_address
:1;
723 /** True if this BO wraps a host pointer */
724 bool from_host_ptr
:1;
726 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
727 bool has_client_visible_address
:1;
729 /** True if this BO has implicit CCS data attached to it */
730 bool has_implicit_ccs
:1;
733 static inline struct anv_bo
*
734 anv_bo_ref(struct anv_bo
*bo
)
736 p_atomic_inc(&bo
->refcount
);
740 static inline struct anv_bo
*
741 anv_bo_unwrap(struct anv_bo
*bo
)
743 while (bo
->is_wrapper
)
748 /* Represents a lock-free linked list of "free" things. This is used by
749 * both the block pool and the state pools. Unfortunately, in order to
750 * solve the ABA problem, we can't use a single uint32_t head.
752 union anv_free_list
{
756 /* A simple count that is incremented every time the head changes. */
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
762 uint64_t u64
__attribute__ ((aligned (8)));
765 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
767 struct anv_block_state
{
773 /* Make sure it's aligned to 64 bits. This will make atomic operations
774 * faster on 32 bit platforms.
776 uint64_t u64
__attribute__ ((aligned (8)));
780 #define anv_block_pool_foreach_bo(bo, pool) \
781 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
782 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
785 #define ANV_MAX_BLOCK_POOL_BOS 20
787 struct anv_block_pool
{
788 struct anv_device
*device
;
791 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
792 * around the actual BO so that we grow the pool after the wrapper BO has
793 * been put in a relocation list. This is only used in the non-softpin
796 struct anv_bo wrapper_bo
;
798 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
804 /* The address where the start of the pool is pinned. The various bos that
805 * are created as the pool grows will have addresses in the range
806 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
808 uint64_t start_address
;
810 /* The offset from the start of the bo to the "center" of the block
811 * pool. Pointers to allocated blocks are given by
812 * bo.map + center_bo_offset + offsets.
814 uint32_t center_bo_offset
;
816 /* Current memory map of the block pool. This pointer may or may not
817 * point to the actual beginning of the block pool memory. If
818 * anv_block_pool_alloc_back has ever been called, then this pointer
819 * will point to the "center" position of the buffer and all offsets
820 * (negative or positive) given out by the block pool alloc functions
821 * will be valid relative to this pointer.
823 * In particular, map == bo.map + center_offset
825 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
826 * since it will handle the softpin case as well, where this points to NULL.
832 * Array of mmaps and gem handles owned by the block pool, reclaimed when
833 * the block pool is destroyed.
835 struct u_vector mmap_cleanups
;
837 struct anv_block_state state
;
839 struct anv_block_state back_state
;
842 /* Block pools are backed by a fixed-size 1GB memfd */
843 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
845 /* The center of the block pool is also the middle of the memfd. This may
846 * change in the future if we decide differently for some reason.
848 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
850 static inline uint32_t
851 anv_block_pool_size(struct anv_block_pool
*pool
)
853 return pool
->state
.end
+ pool
->back_state
.end
;
863 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
865 struct anv_fixed_size_state_pool
{
866 union anv_free_list free_list
;
867 struct anv_block_state block
;
870 #define ANV_MIN_STATE_SIZE_LOG2 6
871 #define ANV_MAX_STATE_SIZE_LOG2 21
873 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
875 struct anv_free_entry
{
877 struct anv_state state
;
880 struct anv_state_table
{
881 struct anv_device
*device
;
883 struct anv_free_entry
*map
;
885 struct anv_block_state state
;
886 struct u_vector cleanups
;
889 struct anv_state_pool
{
890 struct anv_block_pool block_pool
;
892 /* Offset into the relevant state base address where the state pool starts
895 int32_t start_offset
;
897 struct anv_state_table table
;
899 /* The size of blocks which will be allocated from the block pool */
902 /** Free list for "back" allocations */
903 union anv_free_list back_alloc_free_list
;
905 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
908 struct anv_state_reserved_pool
{
909 struct anv_state_pool
*pool
;
910 union anv_free_list reserved_blocks
;
914 struct anv_state_stream
{
915 struct anv_state_pool
*state_pool
;
917 /* The size of blocks to allocate from the state pool */
920 /* Current block we're allocating from */
921 struct anv_state block
;
923 /* Offset into the current block at which to allocate the next state */
926 /* List of all blocks allocated from this pool */
927 struct util_dynarray all_blocks
;
930 /* The block_pool functions exported for testing only. The block pool should
931 * only be used via a state pool (see below).
933 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
934 struct anv_device
*device
,
935 uint64_t start_address
,
936 uint32_t initial_size
);
937 void anv_block_pool_finish(struct anv_block_pool
*pool
);
938 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
939 uint32_t block_size
, uint32_t *padding
);
940 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
941 uint32_t block_size
);
942 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
945 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
946 struct anv_device
*device
,
947 uint64_t base_address
,
948 int32_t start_offset
,
949 uint32_t block_size
);
950 void anv_state_pool_finish(struct anv_state_pool
*pool
);
951 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
952 uint32_t state_size
, uint32_t alignment
);
953 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
954 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
955 void anv_state_stream_init(struct anv_state_stream
*stream
,
956 struct anv_state_pool
*state_pool
,
957 uint32_t block_size
);
958 void anv_state_stream_finish(struct anv_state_stream
*stream
);
959 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
960 uint32_t size
, uint32_t alignment
);
962 void anv_state_reserved_pool_init(struct anv_state_reserved_pool
*pool
,
963 struct anv_state_pool
*parent
,
964 uint32_t count
, uint32_t size
,
966 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool
*pool
);
967 struct anv_state
anv_state_reserved_pool_alloc(struct anv_state_reserved_pool
*pool
);
968 void anv_state_reserved_pool_free(struct anv_state_reserved_pool
*pool
,
969 struct anv_state state
);
971 VkResult
anv_state_table_init(struct anv_state_table
*table
,
972 struct anv_device
*device
,
973 uint32_t initial_entries
);
974 void anv_state_table_finish(struct anv_state_table
*table
);
975 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
977 void anv_free_list_push(union anv_free_list
*list
,
978 struct anv_state_table
*table
,
979 uint32_t idx
, uint32_t count
);
980 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
981 struct anv_state_table
*table
);
984 static inline struct anv_state
*
985 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
987 return &table
->map
[idx
].state
;
990 * Implements a pool of re-usable BOs. The interface is identical to that
991 * of block_pool except that each block is its own BO.
994 struct anv_device
*device
;
996 struct util_sparse_array_free_list free_list
[16];
999 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
1000 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
1001 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
1002 struct anv_bo
**bo_out
);
1003 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
1005 struct anv_scratch_pool
{
1006 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
1007 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
1010 void anv_scratch_pool_init(struct anv_device
*device
,
1011 struct anv_scratch_pool
*pool
);
1012 void anv_scratch_pool_finish(struct anv_device
*device
,
1013 struct anv_scratch_pool
*pool
);
1014 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
1015 struct anv_scratch_pool
*pool
,
1016 gl_shader_stage stage
,
1017 unsigned per_thread_scratch
);
1019 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1020 struct anv_bo_cache
{
1021 struct util_sparse_array bo_map
;
1022 pthread_mutex_t mutex
;
1025 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
1026 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
1028 struct anv_memory_type
{
1029 /* Standard bits passed on to the client */
1030 VkMemoryPropertyFlags propertyFlags
;
1034 struct anv_memory_heap
{
1035 /* Standard bits passed on to the client */
1037 VkMemoryHeapFlags flags
;
1039 /** Driver-internal book-keeping.
1041 * Align it to 64 bits to make atomic operations faster on 32 bit platforms.
1043 VkDeviceSize used
__attribute__ ((aligned (8)));
1046 struct anv_physical_device
{
1047 struct vk_object_base base
;
1049 /* Link in anv_instance::physical_devices */
1050 struct list_head link
;
1052 struct anv_instance
* instance
;
1062 struct gen_device_info info
;
1063 /** Amount of "GPU memory" we want to advertise
1065 * Clearly, this value is bogus since Intel is a UMA architecture. On
1066 * gen7 platforms, we are limited by GTT size unless we want to implement
1067 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1068 * practically unlimited. However, we will never report more than 3/4 of
1069 * the total system ram to try and avoid running out of RAM.
1071 bool supports_48bit_addresses
;
1072 struct brw_compiler
* compiler
;
1073 struct isl_device isl_dev
;
1074 struct gen_perf_config
* perf
;
1075 int cmd_parser_version
;
1077 bool has_exec_async
;
1078 bool has_exec_capture
;
1079 bool has_exec_fence
;
1081 bool has_syncobj_wait
;
1082 bool has_context_priority
;
1083 bool has_context_isolation
;
1084 bool has_mem_available
;
1085 bool has_mmap_offset
;
1089 bool always_use_bindless
;
1090 bool use_call_secondary
;
1092 /** True if we can access buffers using A64 messages */
1093 bool has_a64_buffer_access
;
1094 /** True if we can use bindless access for images */
1095 bool has_bindless_images
;
1096 /** True if we can use bindless access for samplers */
1097 bool has_bindless_samplers
;
1099 /** True if we can read the GPU timestamp register
1101 * When running in a virtual context, the timestamp register is unreadable
1104 bool has_reg_timestamp
;
1106 /** True if this device has implicit AUX
1108 * If true, CCS is handled as an implicit attachment to the BO rather than
1109 * as an explicitly bound surface.
1111 bool has_implicit_ccs
;
1113 bool always_flush_cache
;
1115 struct anv_device_extension_table supported_extensions
;
1118 uint32_t subslice_total
;
1121 uint32_t type_count
;
1122 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1123 uint32_t heap_count
;
1124 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1127 uint8_t driver_build_sha1
[20];
1128 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1129 uint8_t driver_uuid
[VK_UUID_SIZE
];
1130 uint8_t device_uuid
[VK_UUID_SIZE
];
1132 struct disk_cache
* disk_cache
;
1134 struct wsi_device wsi_device
;
1139 struct anv_app_info
{
1140 const char* app_name
;
1141 uint32_t app_version
;
1142 const char* engine_name
;
1143 uint32_t engine_version
;
1144 uint32_t api_version
;
1147 struct anv_instance
{
1148 struct vk_object_base base
;
1150 VkAllocationCallbacks alloc
;
1152 struct anv_app_info app_info
;
1154 struct anv_instance_extension_table enabled_extensions
;
1155 struct anv_instance_dispatch_table dispatch
;
1156 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1157 struct anv_device_dispatch_table device_dispatch
;
1159 bool physical_devices_enumerated
;
1160 struct list_head physical_devices
;
1162 bool pipeline_cache_enabled
;
1164 struct vk_debug_report_instance debug_report_callbacks
;
1166 struct driOptionCache dri_options
;
1167 struct driOptionCache available_dri_options
;
1170 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1171 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1173 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1174 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1177 struct anv_queue_submit
{
1178 struct anv_cmd_buffer
* cmd_buffer
;
1180 uint32_t fence_count
;
1181 uint32_t fence_array_length
;
1182 struct drm_i915_gem_exec_fence
* fences
;
1184 uint32_t temporary_semaphore_count
;
1185 uint32_t temporary_semaphore_array_length
;
1186 struct anv_semaphore_impl
* temporary_semaphores
;
1188 /* Semaphores to be signaled with a SYNC_FD. */
1189 struct anv_semaphore
** sync_fd_semaphores
;
1190 uint32_t sync_fd_semaphore_count
;
1191 uint32_t sync_fd_semaphore_array_length
;
1193 /* Allocated only with non shareable timelines. */
1194 struct anv_timeline
** wait_timelines
;
1195 uint32_t wait_timeline_count
;
1196 uint32_t wait_timeline_array_length
;
1197 uint64_t * wait_timeline_values
;
1199 struct anv_timeline
** signal_timelines
;
1200 uint32_t signal_timeline_count
;
1201 uint32_t signal_timeline_array_length
;
1202 uint64_t * signal_timeline_values
;
1205 bool need_out_fence
;
1208 uint32_t fence_bo_count
;
1209 uint32_t fence_bo_array_length
;
1210 /* An array of struct anv_bo pointers with lower bit used as a flag to
1211 * signal we will wait on that BO (see anv_(un)pack_ptr).
1213 uintptr_t * fence_bos
;
1215 int perf_query_pass
;
1217 const VkAllocationCallbacks
* alloc
;
1218 VkSystemAllocationScope alloc_scope
;
1220 struct anv_bo
* simple_bo
;
1221 uint32_t simple_bo_size
;
1223 struct list_head link
;
1227 struct vk_object_base base
;
1229 struct anv_device
* device
;
1232 * A list of struct anv_queue_submit to be submitted to i915.
1234 struct list_head queued_submits
;
1236 VkDeviceQueueCreateFlags flags
;
1239 struct anv_pipeline_cache
{
1240 struct vk_object_base base
;
1241 struct anv_device
* device
;
1242 pthread_mutex_t mutex
;
1244 struct hash_table
* nir_cache
;
1246 struct hash_table
* cache
;
1251 struct nir_xfb_info
;
1252 struct anv_pipeline_bind_map
;
1254 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1255 struct anv_device
*device
,
1257 bool external_sync
);
1258 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1260 struct anv_shader_bin
*
1261 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1262 const void *key
, uint32_t key_size
);
1263 struct anv_shader_bin
*
1264 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1265 gl_shader_stage stage
,
1266 const void *key_data
, uint32_t key_size
,
1267 const void *kernel_data
, uint32_t kernel_size
,
1268 const void *constant_data
,
1269 uint32_t constant_data_size
,
1270 const struct brw_stage_prog_data
*prog_data
,
1271 uint32_t prog_data_size
,
1272 const struct brw_compile_stats
*stats
,
1274 const struct nir_xfb_info
*xfb_info
,
1275 const struct anv_pipeline_bind_map
*bind_map
);
1277 struct anv_shader_bin
*
1278 anv_device_search_for_kernel(struct anv_device
*device
,
1279 struct anv_pipeline_cache
*cache
,
1280 const void *key_data
, uint32_t key_size
,
1281 bool *user_cache_bit
);
1283 struct anv_shader_bin
*
1284 anv_device_upload_kernel(struct anv_device
*device
,
1285 struct anv_pipeline_cache
*cache
,
1286 gl_shader_stage stage
,
1287 const void *key_data
, uint32_t key_size
,
1288 const void *kernel_data
, uint32_t kernel_size
,
1289 const void *constant_data
,
1290 uint32_t constant_data_size
,
1291 const struct brw_stage_prog_data
*prog_data
,
1292 uint32_t prog_data_size
,
1293 const struct brw_compile_stats
*stats
,
1295 const struct nir_xfb_info
*xfb_info
,
1296 const struct anv_pipeline_bind_map
*bind_map
);
1299 struct nir_shader_compiler_options
;
1302 anv_device_search_for_nir(struct anv_device
*device
,
1303 struct anv_pipeline_cache
*cache
,
1304 const struct nir_shader_compiler_options
*nir_options
,
1305 unsigned char sha1_key
[20],
1309 anv_device_upload_nir(struct anv_device
*device
,
1310 struct anv_pipeline_cache
*cache
,
1311 const struct nir_shader
*nir
,
1312 unsigned char sha1_key
[20]);
1314 struct anv_address
{
1320 struct vk_device vk
;
1322 struct anv_physical_device
* physical
;
1324 struct gen_device_info info
;
1325 struct isl_device isl_dev
;
1328 bool can_chain_batches
;
1329 bool robust_buffer_access
;
1330 struct anv_device_extension_table enabled_extensions
;
1331 struct anv_device_dispatch_table dispatch
;
1333 pthread_mutex_t vma_mutex
;
1334 struct util_vma_heap vma_lo
;
1335 struct util_vma_heap vma_cva
;
1336 struct util_vma_heap vma_hi
;
1338 /** List of all anv_device_memory objects */
1339 struct list_head memory_objects
;
1341 struct anv_bo_pool batch_bo_pool
;
1343 struct anv_bo_cache bo_cache
;
1345 struct anv_state_pool dynamic_state_pool
;
1346 struct anv_state_pool instruction_state_pool
;
1347 struct anv_state_pool binding_table_pool
;
1348 struct anv_state_pool surface_state_pool
;
1350 struct anv_state_reserved_pool custom_border_colors
;
1352 /** BO used for various workarounds
1354 * There are a number of workarounds on our hardware which require writing
1355 * data somewhere and it doesn't really matter where. For that, we use
1356 * this BO and just write to the first dword or so.
1358 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1359 * For that, we use the high bytes (>= 1024) of the workaround BO.
1361 struct anv_bo
* workaround_bo
;
1362 struct anv_address workaround_address
;
1364 struct anv_bo
* trivial_batch_bo
;
1365 struct anv_bo
* hiz_clear_bo
;
1366 struct anv_state null_surface_state
;
1368 struct anv_pipeline_cache default_pipeline_cache
;
1369 struct blorp_context blorp
;
1371 struct anv_state border_colors
;
1373 struct anv_state slice_hash
;
1375 struct anv_queue queue
;
1377 struct anv_scratch_pool scratch_pool
;
1379 pthread_mutex_t mutex
;
1380 pthread_cond_t queue_submit
;
1383 struct gen_batch_decode_ctx decoder_ctx
;
1385 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1386 * the cmd_buffer's list.
1388 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1390 int perf_fd
; /* -1 if no opened */
1391 uint64_t perf_metric
; /* 0 if unset */
1393 struct gen_aux_map_context
*aux_map_ctx
;
1395 struct gen_debug_block_frame
*debug_frame_desc
;
1398 static inline struct anv_instance
*
1399 anv_device_instance_or_null(const struct anv_device
*device
)
1401 return device
? device
->physical
->instance
: NULL
;
1404 static inline struct anv_state_pool
*
1405 anv_binding_table_pool(struct anv_device
*device
)
1407 if (device
->physical
->use_softpin
)
1408 return &device
->binding_table_pool
;
1410 return &device
->surface_state_pool
;
1413 static inline struct anv_state
1414 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1415 if (device
->physical
->use_softpin
)
1416 return anv_state_pool_alloc(&device
->binding_table_pool
,
1417 device
->binding_table_pool
.block_size
, 0);
1419 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1423 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1424 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1427 static inline uint32_t
1428 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1430 if (bo
->is_external
)
1431 return device
->isl_dev
.mocs
.external
;
1433 return device
->isl_dev
.mocs
.internal
;
1436 void anv_device_init_blorp(struct anv_device
*device
);
1437 void anv_device_finish_blorp(struct anv_device
*device
);
1439 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1440 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1441 const char *file
, int line
,
1442 const char *msg
, ...)
1443 anv_printflike(4, 5);
1444 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1445 const char *file
, int line
,
1446 const char *msg
, ...)
1447 anv_printflike(4, 5);
1448 #define anv_device_set_lost(dev, ...) \
1449 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1450 #define anv_queue_set_lost(queue, ...) \
1451 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1454 anv_device_is_lost(struct anv_device
*device
)
1456 return unlikely(p_atomic_read(&device
->_lost
));
1459 VkResult
anv_device_query_status(struct anv_device
*device
);
1462 enum anv_bo_alloc_flags
{
1463 /** Specifies that the BO must have a 32-bit address
1465 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1467 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1469 /** Specifies that the BO may be shared externally */
1470 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1472 /** Specifies that the BO should be mapped */
1473 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1475 /** Specifies that the BO should be snooped so we get coherency */
1476 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1478 /** Specifies that the BO should be captured in error states */
1479 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1481 /** Specifies that the BO will have an address assigned by the caller
1483 * Such BOs do not exist in any VMA heap.
1485 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1487 /** Enables implicit synchronization on the BO
1489 * This is the opposite of EXEC_OBJECT_ASYNC.
1491 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1493 /** Enables implicit synchronization on the BO
1495 * This is equivalent to EXEC_OBJECT_WRITE.
1497 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1499 /** Has an address which is visible to the client */
1500 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1502 /** This buffer has implicit CCS data attached to it */
1503 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1506 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1507 enum anv_bo_alloc_flags alloc_flags
,
1508 uint64_t explicit_address
,
1509 struct anv_bo
**bo
);
1510 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1511 void *host_ptr
, uint32_t size
,
1512 enum anv_bo_alloc_flags alloc_flags
,
1513 uint64_t client_address
,
1514 struct anv_bo
**bo_out
);
1515 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1516 enum anv_bo_alloc_flags alloc_flags
,
1517 uint64_t client_address
,
1518 struct anv_bo
**bo
);
1519 VkResult
anv_device_export_bo(struct anv_device
*device
,
1520 struct anv_bo
*bo
, int *fd_out
);
1521 void anv_device_release_bo(struct anv_device
*device
,
1524 static inline struct anv_bo
*
1525 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1527 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1530 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1531 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1534 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1535 void anv_queue_finish(struct anv_queue
*queue
);
1537 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1538 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1539 struct anv_batch
*batch
);
1541 uint64_t anv_gettime_ns(void);
1542 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1544 void* anv_gem_mmap(struct anv_device
*device
,
1545 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1546 void anv_gem_munmap(struct anv_device
*device
, void *p
, uint64_t size
);
1547 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1548 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1549 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1550 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1551 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1552 int anv_gem_execbuffer(struct anv_device
*device
,
1553 struct drm_i915_gem_execbuffer2
*execbuf
);
1554 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1555 uint32_t stride
, uint32_t tiling
);
1556 int anv_gem_create_context(struct anv_device
*device
);
1557 bool anv_gem_has_context_priority(int fd
);
1558 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1559 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1561 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1563 int anv_gem_get_param(int fd
, uint32_t param
);
1564 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1565 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1566 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1567 uint32_t *active
, uint32_t *pending
);
1568 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1569 int anv_gem_reg_read(int fd
, uint32_t offset
, uint64_t *result
);
1570 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1571 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1572 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1573 uint32_t read_domains
, uint32_t write_domain
);
1574 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1575 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1576 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1577 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1578 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1579 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1581 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1582 uint32_t handle
, int fd
);
1583 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1584 bool anv_gem_supports_syncobj_wait(int fd
);
1585 int anv_gem_syncobj_wait(struct anv_device
*device
,
1586 uint32_t *handles
, uint32_t num_handles
,
1587 int64_t abs_timeout_ns
, bool wait_all
);
1589 uint64_t anv_vma_alloc(struct anv_device
*device
,
1590 uint64_t size
, uint64_t align
,
1591 enum anv_bo_alloc_flags alloc_flags
,
1592 uint64_t client_address
);
1593 void anv_vma_free(struct anv_device
*device
,
1594 uint64_t address
, uint64_t size
);
1596 struct anv_reloc_list
{
1597 uint32_t num_relocs
;
1598 uint32_t array_length
;
1599 struct drm_i915_gem_relocation_entry
* relocs
;
1600 struct anv_bo
** reloc_bos
;
1605 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1606 const VkAllocationCallbacks
*alloc
);
1607 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1608 const VkAllocationCallbacks
*alloc
);
1610 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1611 const VkAllocationCallbacks
*alloc
,
1612 uint32_t offset
, struct anv_bo
*target_bo
,
1613 uint32_t delta
, uint64_t *address_u64_out
);
1615 struct anv_batch_bo
{
1616 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1617 struct list_head link
;
1621 /* Bytes actually consumed in this batch BO */
1624 struct anv_reloc_list relocs
;
1628 const VkAllocationCallbacks
* alloc
;
1630 struct anv_address start_addr
;
1636 struct anv_reloc_list
* relocs
;
1638 /* This callback is called (with the associated user data) in the event
1639 * that the batch runs out of space.
1641 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1645 * Current error status of the command buffer. Used to track inconsistent
1646 * or incomplete command buffer states that are the consequence of run-time
1647 * errors such as out of memory scenarios. We want to track this in the
1648 * batch because the command buffer object is not visible to some parts
1654 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1655 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1656 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1657 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1658 struct anv_address
anv_batch_address(struct anv_batch
*batch
, void *batch_location
);
1661 anv_batch_set_storage(struct anv_batch
*batch
, struct anv_address addr
,
1662 void *map
, size_t size
)
1664 batch
->start_addr
= addr
;
1665 batch
->next
= batch
->start
= map
;
1666 batch
->end
= map
+ size
;
1669 static inline VkResult
1670 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1672 assert(error
!= VK_SUCCESS
);
1673 if (batch
->status
== VK_SUCCESS
)
1674 batch
->status
= error
;
1675 return batch
->status
;
1679 anv_batch_has_error(struct anv_batch
*batch
)
1681 return batch
->status
!= VK_SUCCESS
;
1684 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1687 anv_address_is_null(struct anv_address addr
)
1689 return addr
.bo
== NULL
&& addr
.offset
== 0;
1692 static inline uint64_t
1693 anv_address_physical(struct anv_address addr
)
1695 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1696 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1698 return gen_canonical_address(addr
.offset
);
1701 static inline struct anv_address
1702 anv_address_add(struct anv_address addr
, uint64_t offset
)
1704 addr
.offset
+= offset
;
1709 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1711 unsigned reloc_size
= 0;
1712 if (device
->info
.gen
>= 8) {
1713 reloc_size
= sizeof(uint64_t);
1714 *(uint64_t *)p
= gen_canonical_address(v
);
1716 reloc_size
= sizeof(uint32_t);
1720 if (flush
&& !device
->info
.has_llc
)
1721 gen_flush_range(p
, reloc_size
);
1724 static inline uint64_t
1725 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1726 const struct anv_address address
, uint32_t delta
)
1728 if (address
.bo
== NULL
) {
1729 return address
.offset
+ delta
;
1731 assert(batch
->start
<= location
&& location
< batch
->end
);
1733 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1737 #define __gen_address_type struct anv_address
1738 #define __gen_user_data struct anv_batch
1739 #define __gen_combine_address _anv_combine_address
1741 /* Wrapper macros needed to work around preprocessor argument issues. In
1742 * particular, arguments don't get pre-evaluated if they are concatenated.
1743 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1744 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1745 * We can work around this easily enough with these helpers.
1747 #define __anv_cmd_length(cmd) cmd ## _length
1748 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1749 #define __anv_cmd_header(cmd) cmd ## _header
1750 #define __anv_cmd_pack(cmd) cmd ## _pack
1751 #define __anv_reg_num(reg) reg ## _num
1753 #define anv_pack_struct(dst, struc, ...) do { \
1754 struct struc __template = { \
1757 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1758 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1761 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1762 void *__dst = anv_batch_emit_dwords(batch, n); \
1764 struct cmd __template = { \
1765 __anv_cmd_header(cmd), \
1766 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1769 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1774 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1778 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1779 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1782 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1783 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1784 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1787 #define anv_batch_emit(batch, cmd, name) \
1788 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1789 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1790 __builtin_expect(_dst != NULL, 1); \
1791 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1792 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1796 /* #define __gen_get_batch_dwords anv_batch_emit_dwords */
1797 /* #define __gen_get_batch_address anv_batch_address */
1798 /* #define __gen_address_value anv_address_physical */
1799 /* #define __gen_address_offset anv_address_add */
1801 struct anv_device_memory
{
1802 struct vk_object_base base
;
1804 struct list_head link
;
1807 struct anv_memory_type
* type
;
1808 VkDeviceSize map_size
;
1811 /* If set, we are holding reference to AHardwareBuffer
1812 * which we must release when memory is freed.
1814 struct AHardwareBuffer
* ahw
;
1816 /* If set, this memory comes from a host pointer. */
1821 * Header for Vertex URB Entry (VUE)
1823 struct anv_vue_header
{
1825 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1826 uint32_t ViewportIndex
;
1830 /** Struct representing a sampled image descriptor
1832 * This descriptor layout is used for sampled images, bare sampler, and
1833 * combined image/sampler descriptors.
1835 struct anv_sampled_image_descriptor
{
1836 /** Bindless image handle
1838 * This is expected to already be shifted such that the 20-bit
1839 * SURFACE_STATE table index is in the top 20 bits.
1843 /** Bindless sampler handle
1845 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1846 * to the dynamic state base address.
1851 struct anv_texture_swizzle_descriptor
{
1854 * See also nir_intrinsic_channel_select_intel
1858 /** Unused padding to ensure the struct is a multiple of 64 bits */
1862 /** Struct representing a storage image descriptor */
1863 struct anv_storage_image_descriptor
{
1864 /** Bindless image handles
1866 * These are expected to already be shifted such that the 20-bit
1867 * SURFACE_STATE table index is in the top 20 bits.
1869 uint32_t read_write
;
1870 uint32_t write_only
;
1873 /** Struct representing a address/range descriptor
1875 * The fields of this struct correspond directly to the data layout of
1876 * nir_address_format_64bit_bounded_global addresses. The last field is the
1877 * offset in the NIR address so it must be zero so that when you load the
1878 * descriptor you get a pointer to the start of the range.
1880 struct anv_address_range_descriptor
{
1886 enum anv_descriptor_data
{
1887 /** The descriptor contains a BTI reference to a surface state */
1888 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1889 /** The descriptor contains a BTI reference to a sampler state */
1890 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1891 /** The descriptor contains an actual buffer view */
1892 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1893 /** The descriptor contains auxiliary image layout data */
1894 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1895 /** The descriptor contains auxiliary image layout data */
1896 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1897 /** anv_address_range_descriptor with a buffer address and range */
1898 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1899 /** Bindless surface handle */
1900 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1901 /** Storage image handles */
1902 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1903 /** Storage image handles */
1904 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1907 struct anv_descriptor_set_binding_layout
{
1909 /* The type of the descriptors in this binding */
1910 VkDescriptorType type
;
1913 /* Flags provided when this binding was created */
1914 VkDescriptorBindingFlagsEXT flags
;
1916 /* Bitfield representing the type of data this descriptor contains */
1917 enum anv_descriptor_data data
;
1919 /* Maximum number of YCbCr texture/sampler planes */
1920 uint8_t max_plane_count
;
1922 /* Number of array elements in this binding (or size in bytes for inline
1925 uint16_t array_size
;
1927 /* Index into the flattend descriptor set */
1928 uint16_t descriptor_index
;
1930 /* Index into the dynamic state array for a dynamic buffer */
1931 int16_t dynamic_offset_index
;
1933 /* Index into the descriptor set buffer views */
1934 int16_t buffer_view_index
;
1936 /* Offset into the descriptor buffer where this descriptor lives */
1937 uint32_t descriptor_offset
;
1939 /* Immutable samplers (or NULL if no immutable samplers) */
1940 struct anv_sampler
**immutable_samplers
;
1943 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1945 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1946 VkDescriptorType type
);
1948 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1949 const struct anv_descriptor_set_binding_layout
*binding
,
1952 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1953 const struct anv_descriptor_set_binding_layout
*binding
,
1956 struct anv_descriptor_set_layout
{
1957 struct vk_object_base base
;
1959 /* Descriptor set layouts can be destroyed at almost any time */
1962 /* Number of bindings in this descriptor set */
1963 uint16_t binding_count
;
1965 /* Total size of the descriptor set with room for all array entries */
1968 /* Shader stages affected by this descriptor set */
1969 uint16_t shader_stages
;
1971 /* Number of buffer views in this descriptor set */
1972 uint16_t buffer_view_count
;
1974 /* Number of dynamic offsets used by this descriptor set */
1975 uint16_t dynamic_offset_count
;
1977 /* For each shader stage, which offsets apply to that stage */
1978 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1980 /* Size of the descriptor buffer for this descriptor set */
1981 uint32_t descriptor_buffer_size
;
1983 /* Bindings in this descriptor set */
1984 struct anv_descriptor_set_binding_layout binding
[0];
1987 void anv_descriptor_set_layout_destroy(struct anv_device
*device
,
1988 struct anv_descriptor_set_layout
*layout
);
1991 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1993 assert(layout
&& layout
->ref_cnt
>= 1);
1994 p_atomic_inc(&layout
->ref_cnt
);
1998 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1999 struct anv_descriptor_set_layout
*layout
)
2001 assert(layout
&& layout
->ref_cnt
>= 1);
2002 if (p_atomic_dec_zero(&layout
->ref_cnt
))
2003 anv_descriptor_set_layout_destroy(device
, layout
);
2006 struct anv_descriptor
{
2007 VkDescriptorType type
;
2011 VkImageLayout layout
;
2012 struct anv_image_view
*image_view
;
2013 struct anv_sampler
*sampler
;
2017 struct anv_buffer
*buffer
;
2022 struct anv_buffer_view
*buffer_view
;
2026 struct anv_descriptor_set
{
2027 struct vk_object_base base
;
2029 struct anv_descriptor_pool
*pool
;
2030 struct anv_descriptor_set_layout
*layout
;
2032 /* Amount of space occupied in the the pool by this descriptor set. It can
2033 * be larger than the size of the descriptor set.
2037 /* State relative to anv_descriptor_pool::bo */
2038 struct anv_state desc_mem
;
2039 /* Surface state for the descriptor buffer */
2040 struct anv_state desc_surface_state
;
2042 uint32_t buffer_view_count
;
2043 struct anv_buffer_view
*buffer_views
;
2045 /* Link to descriptor pool's desc_sets list . */
2046 struct list_head pool_link
;
2048 struct anv_descriptor descriptors
[0];
2051 struct anv_buffer_view
{
2052 struct vk_object_base base
;
2054 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
2055 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2057 struct anv_address address
;
2059 struct anv_state surface_state
;
2060 struct anv_state storage_surface_state
;
2061 struct anv_state writeonly_storage_surface_state
;
2063 struct brw_image_param storage_image_param
;
2066 struct anv_push_descriptor_set
{
2067 struct anv_descriptor_set set
;
2069 /* Put this field right behind anv_descriptor_set so it fills up the
2070 * descriptors[0] field. */
2071 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
2073 /** True if the descriptor set buffer has been referenced by a draw or
2076 bool set_used_on_gpu
;
2078 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
2081 struct anv_descriptor_pool
{
2082 struct vk_object_base base
;
2089 struct util_vma_heap bo_heap
;
2091 struct anv_state_stream surface_state_stream
;
2092 void *surface_state_free_list
;
2094 struct list_head desc_sets
;
2099 enum anv_descriptor_template_entry_type
{
2100 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2101 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2102 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2105 struct anv_descriptor_template_entry
{
2106 /* The type of descriptor in this entry */
2107 VkDescriptorType type
;
2109 /* Binding in the descriptor set */
2112 /* Offset at which to write into the descriptor set binding */
2113 uint32_t array_element
;
2115 /* Number of elements to write into the descriptor set binding */
2116 uint32_t array_count
;
2118 /* Offset into the user provided data */
2121 /* Stride between elements into the user provided data */
2125 struct anv_descriptor_update_template
{
2126 struct vk_object_base base
;
2128 VkPipelineBindPoint bind_point
;
2130 /* The descriptor set this template corresponds to. This value is only
2131 * valid if the template was created with the templateType
2132 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2136 /* Number of entries in this template */
2137 uint32_t entry_count
;
2139 /* Entries of the template */
2140 struct anv_descriptor_template_entry entries
[0];
2144 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2147 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2148 struct anv_descriptor_set
*set
,
2149 const VkDescriptorImageInfo
* const info
,
2150 VkDescriptorType type
,
2155 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2156 struct anv_descriptor_set
*set
,
2157 VkDescriptorType type
,
2158 struct anv_buffer_view
*buffer_view
,
2163 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2164 struct anv_descriptor_set
*set
,
2165 struct anv_state_stream
*alloc_stream
,
2166 VkDescriptorType type
,
2167 struct anv_buffer
*buffer
,
2170 VkDeviceSize offset
,
2171 VkDeviceSize range
);
2173 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2174 struct anv_descriptor_set
*set
,
2181 anv_descriptor_set_write_template(struct anv_device
*device
,
2182 struct anv_descriptor_set
*set
,
2183 struct anv_state_stream
*alloc_stream
,
2184 const struct anv_descriptor_update_template
*template,
2188 anv_descriptor_set_create(struct anv_device
*device
,
2189 struct anv_descriptor_pool
*pool
,
2190 struct anv_descriptor_set_layout
*layout
,
2191 struct anv_descriptor_set
**out_set
);
2194 anv_descriptor_set_destroy(struct anv_device
*device
,
2195 struct anv_descriptor_pool
*pool
,
2196 struct anv_descriptor_set
*set
);
2198 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2199 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2200 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2201 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2202 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2203 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2205 struct anv_pipeline_binding
{
2206 /** Index in the descriptor set
2208 * This is a flattened index; the descriptor set layout is already taken
2213 /** The descriptor set this surface corresponds to.
2215 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2216 * binding is not a normal descriptor set but something else.
2221 /** Plane in the binding index for images */
2224 /** Input attachment index (relative to the subpass) */
2225 uint8_t input_attachment_index
;
2227 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2228 uint8_t dynamic_offset_index
;
2231 /** For a storage image, whether it is write-only */
2234 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2235 * assuming POD zero-initialization.
2240 struct anv_push_range
{
2241 /** Index in the descriptor set */
2244 /** Descriptor set index */
2247 /** Dynamic offset index (for dynamic UBOs) */
2248 uint8_t dynamic_offset_index
;
2250 /** Start offset in units of 32B */
2253 /** Range in units of 32B */
2257 struct anv_pipeline_layout
{
2258 struct vk_object_base base
;
2261 struct anv_descriptor_set_layout
*layout
;
2262 uint32_t dynamic_offset_start
;
2267 unsigned char sha1
[20];
2271 struct vk_object_base base
;
2273 struct anv_device
* device
;
2276 VkBufferUsageFlags usage
;
2278 /* Set when bound */
2279 struct anv_address address
;
2282 static inline uint64_t
2283 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2285 assert(offset
<= buffer
->size
);
2286 if (range
== VK_WHOLE_SIZE
) {
2287 return buffer
->size
- offset
;
2289 assert(range
+ offset
>= range
);
2290 assert(range
+ offset
<= buffer
->size
);
2295 enum anv_cmd_dirty_bits
{
2296 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2297 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2298 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2299 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2300 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2301 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2302 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2303 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2304 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2305 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2306 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2307 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2308 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2309 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2310 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE
= 1 << 14, /* VK_DYNAMIC_STATE_CULL_MODE_EXT */
2311 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE
= 1 << 15, /* VK_DYNAMIC_STATE_FRONT_FACE_EXT */
2312 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
= 1 << 16, /* VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT */
2313 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
= 1 << 17, /* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT */
2314 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
= 1 << 18, /* VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT */
2315 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
= 1 << 19, /* VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT */
2316 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
= 1 << 20, /* VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT */
2317 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
= 1 << 21, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT */
2318 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
= 1 << 22, /* VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT */
2319 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP
= 1 << 23, /* VK_DYNAMIC_STATE_STENCIL_OP_EXT */
2321 typedef uint32_t anv_cmd_dirty_mask_t
;
2323 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2324 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2325 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2326 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2327 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2328 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2329 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2330 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2331 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2332 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2333 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE | \
2334 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE | \
2335 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE | \
2336 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | \
2337 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE | \
2338 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | \
2339 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE | \
2340 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | \
2341 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE | \
2342 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE | \
2343 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2345 static inline enum anv_cmd_dirty_bits
2346 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2349 case VK_DYNAMIC_STATE_VIEWPORT
:
2350 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
2351 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2352 case VK_DYNAMIC_STATE_SCISSOR
:
2353 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
2354 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2355 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2356 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2357 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2358 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2359 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2360 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2361 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2362 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2363 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2364 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2365 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2366 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2367 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2368 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2369 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2370 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2371 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
2372 return ANV_CMD_DIRTY_DYNAMIC_CULL_MODE
;
2373 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
2374 return ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE
;
2375 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
2376 return ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
;
2377 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
2378 return ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
2379 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
2380 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
;
2381 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
2382 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
;
2383 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
2384 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
;
2385 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
2386 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
2387 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
2388 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
;
2389 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
2390 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP
;
2392 assert(!"Unsupported dynamic state");
2398 enum anv_pipe_bits
{
2399 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2400 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2401 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2402 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2403 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2404 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2405 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2406 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2407 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2408 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2409 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2410 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2411 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2413 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2414 * a flush has happened but not a CS stall. The next time we do any sort
2415 * of invalidation we need to insert a CS stall at that time. Otherwise,
2416 * we would have to CS stall on every flush which could be bad.
2418 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2420 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2421 * target operations related to transfer commands with VkBuffer as
2422 * destination are ongoing. Some operations like copies on the command
2423 * streamer might need to be aware of this to trigger the appropriate stall
2424 * before they can proceed with the copy.
2426 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2428 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2429 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2430 * done by writing the AUX-TT register.
2432 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2434 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2435 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2436 * implement a workaround for Gen9.
2438 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2441 #define ANV_PIPE_FLUSH_BITS ( \
2442 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2443 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2444 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2445 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2447 #define ANV_PIPE_STALL_BITS ( \
2448 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2449 ANV_PIPE_DEPTH_STALL_BIT | \
2450 ANV_PIPE_CS_STALL_BIT)
2452 #define ANV_PIPE_INVALIDATE_BITS ( \
2453 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2454 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2455 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2456 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2457 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2458 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2459 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2461 static inline enum anv_pipe_bits
2462 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2464 enum anv_pipe_bits pipe_bits
= 0;
2467 for_each_bit(b
, flags
) {
2468 switch ((VkAccessFlagBits
)(1 << b
)) {
2469 case VK_ACCESS_SHADER_WRITE_BIT
:
2470 /* We're transitioning a buffer that was previously used as write
2471 * destination through the data port. To make its content available
2472 * to future operations, flush the data cache.
2474 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2476 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2477 /* We're transitioning a buffer that was previously used as render
2478 * target. To make its content available to future operations, flush
2479 * the render target cache.
2481 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2483 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2484 /* We're transitioning a buffer that was previously used as depth
2485 * buffer. To make its content available to future operations, flush
2488 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2490 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2491 /* We're transitioning a buffer that was previously used as a
2492 * transfer write destination. Generic write operations include color
2493 * & depth operations as well as buffer operations like :
2494 * - vkCmdClearColorImage()
2495 * - vkCmdClearDepthStencilImage()
2496 * - vkCmdBlitImage()
2497 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2499 * Most of these operations are implemented using Blorp which writes
2500 * through the render target, so flush that cache to make it visible
2501 * to future operations. And for depth related operations we also
2502 * need to flush the depth cache.
2504 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2505 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2507 case VK_ACCESS_MEMORY_WRITE_BIT
:
2508 /* We're transitioning a buffer for generic write operations. Flush
2511 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2514 break; /* Nothing to do */
2521 static inline enum anv_pipe_bits
2522 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2524 enum anv_pipe_bits pipe_bits
= 0;
2527 for_each_bit(b
, flags
) {
2528 switch ((VkAccessFlagBits
)(1 << b
)) {
2529 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2530 /* Indirect draw commands take a buffer as input that we're going to
2531 * read from the command streamer to load some of the HW registers
2532 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2533 * command streamer stall so that all the cache flushes have
2534 * completed before the command streamer loads from memory.
2536 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2537 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2538 * through a vertex buffer, so invalidate that cache.
2540 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2541 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2542 * UBO from the buffer, so we need to invalidate constant cache.
2544 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2546 case VK_ACCESS_INDEX_READ_BIT
:
2547 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2548 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2549 * commands, so we invalidate the VF cache to make sure there is no
2550 * stale data when we start rendering.
2552 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2554 case VK_ACCESS_UNIFORM_READ_BIT
:
2555 /* We transitioning a buffer to be used as uniform data. Because
2556 * uniform is accessed through the data port & sampler, we need to
2557 * invalidate the texture cache (sampler) & constant cache (data
2558 * port) to avoid stale data.
2560 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2561 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2563 case VK_ACCESS_SHADER_READ_BIT
:
2564 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2565 case VK_ACCESS_TRANSFER_READ_BIT
:
2566 /* Transitioning a buffer to be read through the sampler, so
2567 * invalidate the texture cache, we don't want any stale data.
2569 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2571 case VK_ACCESS_MEMORY_READ_BIT
:
2572 /* Transitioning a buffer for generic read, invalidate all the
2575 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2577 case VK_ACCESS_MEMORY_WRITE_BIT
:
2578 /* Generic write, make sure all previously written things land in
2581 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2583 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2584 /* Transitioning a buffer for conditional rendering. We'll load the
2585 * content of this buffer into HW registers using the command
2586 * streamer, so we need to stall the command streamer to make sure
2587 * any in-flight flush operations have completed.
2589 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2592 break; /* Nothing to do */
2599 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2600 VK_IMAGE_ASPECT_COLOR_BIT | \
2601 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2602 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2603 VK_IMAGE_ASPECT_PLANE_2_BIT)
2604 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2605 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2606 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2607 VK_IMAGE_ASPECT_PLANE_2_BIT)
2609 struct anv_vertex_binding
{
2610 struct anv_buffer
* buffer
;
2611 VkDeviceSize offset
;
2612 VkDeviceSize stride
;
2616 struct anv_xfb_binding
{
2617 struct anv_buffer
* buffer
;
2618 VkDeviceSize offset
;
2622 struct anv_push_constants
{
2623 /** Push constant data provided by the client through vkPushConstants */
2624 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2626 /** Dynamic offsets for dynamic UBOs and SSBOs */
2627 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2629 uint64_t push_reg_mask
;
2631 /** Pad out to a multiple of 32 bytes */
2635 /** Base workgroup ID
2637 * Used for vkCmdDispatchBase.
2639 uint32_t base_work_group_id
[3];
2643 * This is never set by software but is implicitly filled out when
2644 * uploading the push constants for compute shaders.
2646 uint32_t subgroup_id
;
2650 struct anv_dynamic_state
{
2653 VkViewport viewports
[MAX_VIEWPORTS
];
2658 VkRect2D scissors
[MAX_SCISSORS
];
2669 float blend_constants
[4];
2679 } stencil_compare_mask
;
2684 } stencil_write_mask
;
2689 } stencil_reference
;
2693 VkStencilOp fail_op
;
2694 VkStencilOp pass_op
;
2695 VkStencilOp depth_fail_op
;
2696 VkCompareOp compare_op
;
2699 VkStencilOp fail_op
;
2700 VkStencilOp pass_op
;
2701 VkStencilOp depth_fail_op
;
2702 VkCompareOp compare_op
;
2711 VkCullModeFlags cull_mode
;
2712 VkFrontFace front_face
;
2713 VkPrimitiveTopology primitive_topology
;
2714 bool depth_test_enable
;
2715 bool depth_write_enable
;
2716 VkCompareOp depth_compare_op
;
2717 bool depth_bounds_test_enable
;
2718 bool stencil_test_enable
;
2719 bool dyn_vbo_stride
;
2723 extern const struct anv_dynamic_state default_dynamic_state
;
2725 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2726 const struct anv_dynamic_state
*src
,
2727 uint32_t copy_mask
);
2729 struct anv_surface_state
{
2730 struct anv_state state
;
2731 /** Address of the surface referred to by this state
2733 * This address is relative to the start of the BO.
2735 struct anv_address address
;
2736 /* Address of the aux surface, if any
2738 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2740 * With the exception of gen8, the bottom 12 bits of this address' offset
2741 * include extra aux information.
2743 struct anv_address aux_address
;
2744 /* Address of the clear color, if any
2746 * This address is relative to the start of the BO.
2748 struct anv_address clear_address
;
2752 * Attachment state when recording a renderpass instance.
2754 * The clear value is valid only if there exists a pending clear.
2756 struct anv_attachment_state
{
2757 enum isl_aux_usage aux_usage
;
2758 struct anv_surface_state color
;
2759 struct anv_surface_state input
;
2761 VkImageLayout current_layout
;
2762 VkImageLayout current_stencil_layout
;
2763 VkImageAspectFlags pending_clear_aspects
;
2764 VkImageAspectFlags pending_load_aspects
;
2766 VkClearValue clear_value
;
2768 /* When multiview is active, attachments with a renderpass clear
2769 * operation have their respective layers cleared on the first
2770 * subpass that uses them, and only in that subpass. We keep track
2771 * of this using a bitfield to indicate which layers of an attachment
2772 * have not been cleared yet when multiview is active.
2774 uint32_t pending_clear_views
;
2775 struct anv_image_view
* image_view
;
2778 /** State tracking for vertex buffer flushes
2780 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2781 * addresses. If you happen to have two vertex buffers which get placed
2782 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2783 * collisions. In order to solve this problem, we track vertex address ranges
2784 * which are live in the cache and invalidate the cache if one ever exceeds 32
2787 struct anv_vb_cache_range
{
2788 /* Virtual address at which the live vertex buffer cache range starts for
2789 * this vertex buffer index.
2793 /* Virtual address of the byte after where vertex buffer cache range ends.
2794 * This is exclusive such that end - start is the size of the range.
2799 /** State tracking for particular pipeline bind point
2801 * This struct is the base struct for anv_cmd_graphics_state and
2802 * anv_cmd_compute_state. These are used to track state which is bound to a
2803 * particular type of pipeline. Generic state that applies per-stage such as
2804 * binding table offsets and push constants is tracked generically with a
2805 * per-stage array in anv_cmd_state.
2807 struct anv_cmd_pipeline_state
{
2808 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2809 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2812 /** State tracking for graphics pipeline
2814 * This has anv_cmd_pipeline_state as a base struct to track things which get
2815 * bound to a graphics pipeline. Along with general pipeline bind point state
2816 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2817 * state which is graphics-specific.
2819 struct anv_cmd_graphics_state
{
2820 struct anv_cmd_pipeline_state base
;
2822 struct anv_graphics_pipeline
*pipeline
;
2824 anv_cmd_dirty_mask_t dirty
;
2827 struct anv_vb_cache_range ib_bound_range
;
2828 struct anv_vb_cache_range ib_dirty_range
;
2829 struct anv_vb_cache_range vb_bound_ranges
[33];
2830 struct anv_vb_cache_range vb_dirty_ranges
[33];
2832 struct anv_dynamic_state dynamic
;
2834 uint32_t primitive_topology
;
2837 struct anv_buffer
*index_buffer
;
2838 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2839 uint32_t index_offset
;
2843 /** State tracking for compute pipeline
2845 * This has anv_cmd_pipeline_state as a base struct to track things which get
2846 * bound to a compute pipeline. Along with general pipeline bind point state
2847 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2848 * state which is compute-specific.
2850 struct anv_cmd_compute_state
{
2851 struct anv_cmd_pipeline_state base
;
2853 struct anv_compute_pipeline
*pipeline
;
2855 bool pipeline_dirty
;
2857 struct anv_address num_workgroups
;
2860 /** State required while building cmd buffer */
2861 struct anv_cmd_state
{
2862 /* PIPELINE_SELECT.PipelineSelection */
2863 uint32_t current_pipeline
;
2864 const struct gen_l3_config
* current_l3_config
;
2865 uint32_t last_aux_map_state
;
2867 struct anv_cmd_graphics_state gfx
;
2868 struct anv_cmd_compute_state compute
;
2870 enum anv_pipe_bits pending_pipe_bits
;
2871 VkShaderStageFlags descriptors_dirty
;
2872 VkShaderStageFlags push_constants_dirty
;
2874 struct anv_framebuffer
* framebuffer
;
2875 struct anv_render_pass
* pass
;
2876 struct anv_subpass
* subpass
;
2877 VkRect2D render_area
;
2878 uint32_t restart_index
;
2879 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2881 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2882 VkShaderStageFlags push_constant_stages
;
2883 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2884 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2885 struct anv_state samplers
[MESA_SHADER_STAGES
];
2887 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2888 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2889 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2892 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2893 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2894 * and before invoking the secondary in ExecuteCommands.
2896 bool pma_fix_enabled
;
2899 * Whether or not we know for certain that HiZ is enabled for the current
2900 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2901 * enabled or not, this will be false.
2905 bool conditional_render_enabled
;
2908 * Last rendering scale argument provided to
2909 * genX(cmd_buffer_emit_hashing_mode)().
2911 unsigned current_hash_scale
;
2914 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2915 * valid only when recording a render pass instance.
2917 struct anv_attachment_state
* attachments
;
2920 * Surface states for color render targets. These are stored in a single
2921 * flat array. For depth-stencil attachments, the surface state is simply
2924 struct anv_state attachment_states
;
2927 * A null surface state of the right size to match the framebuffer. This
2928 * is one of the states in attachment_states.
2930 struct anv_state null_surface_state
;
2933 struct anv_cmd_pool
{
2934 struct vk_object_base base
;
2935 VkAllocationCallbacks alloc
;
2936 struct list_head cmd_buffers
;
2939 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2941 enum anv_cmd_buffer_exec_mode
{
2942 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2943 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2944 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2945 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2946 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2947 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN
,
2950 struct anv_cmd_buffer
{
2951 struct vk_object_base base
;
2953 struct anv_device
* device
;
2955 struct anv_cmd_pool
* pool
;
2956 struct list_head pool_link
;
2958 struct anv_batch batch
;
2960 /* Fields required for the actual chain of anv_batch_bo's.
2962 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2964 struct list_head batch_bos
;
2965 enum anv_cmd_buffer_exec_mode exec_mode
;
2967 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2968 * referenced by this command buffer
2970 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2972 struct u_vector seen_bbos
;
2974 /* A vector of int32_t's for every block of binding tables.
2976 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2978 struct u_vector bt_block_states
;
2979 struct anv_state bt_next
;
2981 struct anv_reloc_list surface_relocs
;
2982 /** Last seen surface state block pool center bo offset */
2983 uint32_t last_ss_pool_center
;
2985 /* Serial for tracking buffer completion */
2988 /* Stream objects for storing temporary data */
2989 struct anv_state_stream surface_state_stream
;
2990 struct anv_state_stream dynamic_state_stream
;
2992 VkCommandBufferUsageFlags usage_flags
;
2993 VkCommandBufferLevel level
;
2995 struct anv_query_pool
*perf_query_pool
;
2997 struct anv_cmd_state state
;
2999 struct anv_address return_addr
;
3001 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
3002 uint64_t intel_perf_marker
;
3005 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
3006 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
3007 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
3008 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
3009 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
3010 struct anv_cmd_buffer
*secondary
);
3011 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
3012 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
3013 struct anv_cmd_buffer
*cmd_buffer
,
3014 const VkSemaphore
*in_semaphores
,
3015 const uint64_t *in_wait_values
,
3016 uint32_t num_in_semaphores
,
3017 const VkSemaphore
*out_semaphores
,
3018 const uint64_t *out_signal_values
,
3019 uint32_t num_out_semaphores
,
3021 int perf_query_pass
);
3023 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
3025 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
3026 const void *data
, uint32_t size
, uint32_t alignment
);
3027 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
3028 uint32_t *a
, uint32_t *b
,
3029 uint32_t dwords
, uint32_t alignment
);
3032 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
3034 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
3035 uint32_t entries
, uint32_t *state_offset
);
3037 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
3039 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
3040 uint32_t size
, uint32_t alignment
);
3043 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
3045 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
3046 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
3047 bool depth_clamp_enable
);
3048 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
3050 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
3051 struct anv_render_pass
*pass
,
3052 struct anv_framebuffer
*framebuffer
,
3053 const VkClearValue
*clear_values
);
3055 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
3058 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3059 gl_shader_stage stage
);
3061 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
3063 const struct anv_image_view
*
3064 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
3067 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
3068 uint32_t num_entries
,
3069 uint32_t *state_offset
,
3070 struct anv_state
*bt_state
);
3072 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
3074 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
3076 enum anv_fence_type
{
3077 ANV_FENCE_TYPE_NONE
= 0,
3079 ANV_FENCE_TYPE_WSI_BO
,
3080 ANV_FENCE_TYPE_SYNCOBJ
,
3084 enum anv_bo_fence_state
{
3085 /** Indicates that this is a new (or newly reset fence) */
3086 ANV_BO_FENCE_STATE_RESET
,
3088 /** Indicates that this fence has been submitted to the GPU but is still
3089 * (as far as we know) in use by the GPU.
3091 ANV_BO_FENCE_STATE_SUBMITTED
,
3093 ANV_BO_FENCE_STATE_SIGNALED
,
3096 struct anv_fence_impl
{
3097 enum anv_fence_type type
;
3100 /** Fence implementation for BO fences
3102 * These fences use a BO and a set of CPU-tracked state flags. The BO
3103 * is added to the object list of the last execbuf call in a QueueSubmit
3104 * and is marked EXEC_WRITE. The state flags track when the BO has been
3105 * submitted to the kernel. We need to do this because Vulkan lets you
3106 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
3107 * will say it's idle in this case.
3111 enum anv_bo_fence_state state
;
3114 /** DRM syncobj handle for syncobj-based fences */
3118 struct wsi_fence
*fence_wsi
;
3123 struct vk_object_base base
;
3125 /* Permanent fence state. Every fence has some form of permanent state
3126 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3127 * cross-process fences) or it could just be a dummy for use internally.
3129 struct anv_fence_impl permanent
;
3131 /* Temporary fence state. A fence *may* have temporary state. That state
3132 * is added to the fence by an import operation and is reset back to
3133 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3134 * state cannot be signaled because the fence must already be signaled
3135 * before the temporary state can be exported from the fence in the other
3136 * process and imported here.
3138 struct anv_fence_impl temporary
;
3141 void anv_fence_reset_temporary(struct anv_device
*device
,
3142 struct anv_fence
*fence
);
3145 struct vk_object_base base
;
3147 struct anv_state state
;
3150 enum anv_semaphore_type
{
3151 ANV_SEMAPHORE_TYPE_NONE
= 0,
3152 ANV_SEMAPHORE_TYPE_DUMMY
,
3153 ANV_SEMAPHORE_TYPE_BO
,
3154 ANV_SEMAPHORE_TYPE_WSI_BO
,
3155 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
3156 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
3157 ANV_SEMAPHORE_TYPE_TIMELINE
,
3160 struct anv_timeline_point
{
3161 struct list_head link
;
3165 /* Number of waiter on this point, when > 0 the point should not be garbage
3170 /* BO used for synchronization. */
3174 struct anv_timeline
{
3175 pthread_mutex_t mutex
;
3176 pthread_cond_t cond
;
3178 uint64_t highest_past
;
3179 uint64_t highest_pending
;
3181 struct list_head points
;
3182 struct list_head free_points
;
3185 struct anv_semaphore_impl
{
3186 enum anv_semaphore_type type
;
3189 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3190 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3191 * object list on any execbuf2 calls for which this semaphore is used as
3192 * a wait or signal fence. When used as a signal fence or when type ==
3193 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3197 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3198 * If the semaphore is in the unsignaled state due to either just being
3199 * created or because it has been used for a wait, fd will be -1.
3203 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3204 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3205 * import so we don't need to bother with a userspace cache.
3209 /* Non shareable timeline semaphore
3211 * Used when kernel don't have support for timeline semaphores.
3213 struct anv_timeline timeline
;
3217 struct anv_semaphore
{
3218 struct vk_object_base base
;
3222 /* Permanent semaphore state. Every semaphore has some form of permanent
3223 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3224 * (for cross-process semaphores0 or it could just be a dummy for use
3227 struct anv_semaphore_impl permanent
;
3229 /* Temporary semaphore state. A semaphore *may* have temporary state.
3230 * That state is added to the semaphore by an import operation and is reset
3231 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3232 * semaphore with temporary state cannot be signaled because the semaphore
3233 * must already be signaled before the temporary state can be exported from
3234 * the semaphore in the other process and imported here.
3236 struct anv_semaphore_impl temporary
;
3239 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3240 struct anv_semaphore
*semaphore
);
3242 struct anv_shader_module
{
3243 struct vk_object_base base
;
3245 unsigned char sha1
[20];
3250 static inline gl_shader_stage
3251 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3253 assert(__builtin_popcount(vk_stage
) == 1);
3254 return ffs(vk_stage
) - 1;
3257 static inline VkShaderStageFlagBits
3258 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3260 return (1 << mesa_stage
);
3263 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3265 #define anv_foreach_stage(stage, stage_bits) \
3266 for (gl_shader_stage stage, \
3267 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3268 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3269 __tmp &= ~(1 << (stage)))
3271 struct anv_pipeline_bind_map
{
3272 unsigned char surface_sha1
[20];
3273 unsigned char sampler_sha1
[20];
3274 unsigned char push_sha1
[20];
3276 uint32_t surface_count
;
3277 uint32_t sampler_count
;
3279 struct anv_pipeline_binding
* surface_to_descriptor
;
3280 struct anv_pipeline_binding
* sampler_to_descriptor
;
3282 struct anv_push_range push_ranges
[4];
3285 struct anv_shader_bin_key
{
3290 struct anv_shader_bin
{
3293 gl_shader_stage stage
;
3295 const struct anv_shader_bin_key
*key
;
3297 struct anv_state kernel
;
3298 uint32_t kernel_size
;
3300 struct anv_state constant_data
;
3301 uint32_t constant_data_size
;
3303 const struct brw_stage_prog_data
*prog_data
;
3304 uint32_t prog_data_size
;
3306 struct brw_compile_stats stats
[3];
3309 struct nir_xfb_info
*xfb_info
;
3311 struct anv_pipeline_bind_map bind_map
;
3314 struct anv_shader_bin
*
3315 anv_shader_bin_create(struct anv_device
*device
,
3316 gl_shader_stage stage
,
3317 const void *key
, uint32_t key_size
,
3318 const void *kernel
, uint32_t kernel_size
,
3319 const void *constant_data
, uint32_t constant_data_size
,
3320 const struct brw_stage_prog_data
*prog_data
,
3321 uint32_t prog_data_size
,
3322 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3323 const struct nir_xfb_info
*xfb_info
,
3324 const struct anv_pipeline_bind_map
*bind_map
);
3327 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3330 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3332 assert(shader
&& shader
->ref_cnt
>= 1);
3333 p_atomic_inc(&shader
->ref_cnt
);
3337 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3339 assert(shader
&& shader
->ref_cnt
>= 1);
3340 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3341 anv_shader_bin_destroy(device
, shader
);
3344 struct anv_pipeline_executable
{
3345 gl_shader_stage stage
;
3347 struct brw_compile_stats stats
;
3353 enum anv_pipeline_type
{
3354 ANV_PIPELINE_GRAPHICS
,
3355 ANV_PIPELINE_COMPUTE
,
3358 struct anv_pipeline
{
3359 struct vk_object_base base
;
3361 struct anv_device
* device
;
3363 struct anv_batch batch
;
3364 struct anv_reloc_list batch_relocs
;
3368 enum anv_pipeline_type type
;
3369 VkPipelineCreateFlags flags
;
3371 struct util_dynarray executables
;
3373 const struct gen_l3_config
* l3_config
;
3376 struct anv_graphics_pipeline
{
3377 struct anv_pipeline base
;
3379 uint32_t batch_data
[512];
3381 anv_cmd_dirty_mask_t dynamic_state_mask
;
3382 struct anv_dynamic_state dynamic_state
;
3386 struct anv_subpass
* subpass
;
3388 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3390 VkShaderStageFlags active_stages
;
3392 bool primitive_restart
;
3394 bool depth_test_enable
;
3395 bool writes_stencil
;
3396 bool stencil_test_enable
;
3397 bool depth_clamp_enable
;
3398 bool depth_clip_enable
;
3399 bool sample_shading_enable
;
3401 bool depth_bounds_test_enable
;
3403 /* When primitive replication is used, subpass->view_mask will describe what
3404 * views to replicate.
3406 bool use_primitive_replication
;
3408 struct anv_state blend_state
;
3411 struct anv_pipeline_vertex_binding
{
3414 uint32_t instance_divisor
;
3419 uint32_t depth_stencil_state
[3];
3426 uint32_t wm_depth_stencil
[3];
3430 uint32_t wm_depth_stencil
[4];
3434 struct anv_compute_pipeline
{
3435 struct anv_pipeline base
;
3437 struct anv_shader_bin
* cs
;
3438 uint32_t cs_right_mask
;
3439 uint32_t batch_data
[9];
3440 uint32_t interface_descriptor_data
[8];
3443 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3444 static inline struct anv_##pipe_type##_pipeline * \
3445 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3447 assert(pipeline->type == pipe_enum); \
3448 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3451 ANV_DECL_PIPELINE_DOWNCAST(graphics
, ANV_PIPELINE_GRAPHICS
)
3452 ANV_DECL_PIPELINE_DOWNCAST(compute
, ANV_PIPELINE_COMPUTE
)
3455 anv_pipeline_has_stage(const struct anv_graphics_pipeline
*pipeline
,
3456 gl_shader_stage stage
)
3458 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3461 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3462 static inline const struct brw_##prefix##_prog_data * \
3463 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3465 if (anv_pipeline_has_stage(pipeline, stage)) { \
3466 return (const struct brw_##prefix##_prog_data *) \
3467 pipeline->shaders[stage]->prog_data; \
3473 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3474 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3475 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3476 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3477 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3479 static inline const struct brw_cs_prog_data
*
3480 get_cs_prog_data(const struct anv_compute_pipeline
*pipeline
)
3482 assert(pipeline
->cs
);
3483 return (const struct brw_cs_prog_data
*) pipeline
->cs
->prog_data
;
3486 static inline const struct brw_vue_prog_data
*
3487 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline
*pipeline
)
3489 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3490 return &get_gs_prog_data(pipeline
)->base
;
3491 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3492 return &get_tes_prog_data(pipeline
)->base
;
3494 return &get_vs_prog_data(pipeline
)->base
;
3498 anv_pipeline_init(struct anv_pipeline
*pipeline
,
3499 struct anv_device
*device
,
3500 enum anv_pipeline_type type
,
3501 VkPipelineCreateFlags flags
,
3502 const VkAllocationCallbacks
*pAllocator
);
3505 anv_pipeline_finish(struct anv_pipeline
*pipeline
,
3506 struct anv_device
*device
,
3507 const VkAllocationCallbacks
*pAllocator
);
3510 anv_graphics_pipeline_init(struct anv_graphics_pipeline
*pipeline
, struct anv_device
*device
,
3511 struct anv_pipeline_cache
*cache
,
3512 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3513 const VkAllocationCallbacks
*alloc
);
3516 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
3517 struct anv_pipeline_cache
*cache
,
3518 const VkComputePipelineCreateInfo
*info
,
3519 const struct anv_shader_module
*module
,
3520 const char *entrypoint
,
3521 const VkSpecializationInfo
*spec_info
);
3523 struct anv_cs_parameters
{
3524 uint32_t group_size
;
3529 struct anv_cs_parameters
3530 anv_cs_parameters(const struct anv_compute_pipeline
*pipeline
);
3532 struct anv_format_plane
{
3533 enum isl_format isl_format
:16;
3534 struct isl_swizzle swizzle
;
3536 /* Whether this plane contains chroma channels */
3539 /* For downscaling of YUV planes */
3540 uint8_t denominator_scales
[2];
3542 /* How to map sampled ycbcr planes to a single 4 component element. */
3543 struct isl_swizzle ycbcr_swizzle
;
3545 /* What aspect is associated to this plane */
3546 VkImageAspectFlags aspect
;
3551 struct anv_format_plane planes
[3];
3558 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3559 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3560 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3561 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3563 static inline uint32_t
3564 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3565 VkImageAspectFlags aspect_mask
)
3567 switch (aspect_mask
) {
3568 case VK_IMAGE_ASPECT_COLOR_BIT
:
3569 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3570 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3572 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3573 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3576 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3578 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3581 /* Purposefully assert with depth/stencil aspects. */
3582 unreachable("invalid image aspect");
3586 static inline VkImageAspectFlags
3587 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3590 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3591 if (util_bitcount(image_aspects
) > 1)
3592 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3593 return VK_IMAGE_ASPECT_COLOR_BIT
;
3595 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3596 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3597 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3598 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3601 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3602 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3604 const struct anv_format
*
3605 anv_get_format(VkFormat format
);
3607 static inline uint32_t
3608 anv_get_format_planes(VkFormat vk_format
)
3610 const struct anv_format
*format
= anv_get_format(vk_format
);
3612 return format
!= NULL
? format
->n_planes
: 0;
3615 struct anv_format_plane
3616 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3617 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3619 static inline enum isl_format
3620 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3621 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3623 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3626 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3627 VkImageCreateFlags create_flags
,
3629 VkImageTiling vk_tiling
,
3630 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3632 static inline struct isl_swizzle
3633 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3635 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3636 * RGB as RGBA for texturing
3638 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3639 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3641 /* But it doesn't matter what we render to that channel */
3642 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3648 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3651 * Subsurface of an anv_image.
3653 struct anv_surface
{
3654 /** Valid only if isl_surf::size_B > 0. */
3655 struct isl_surf isl
;
3658 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3664 struct vk_object_base base
;
3666 VkImageType type
; /**< VkImageCreateInfo::imageType */
3667 /* The original VkFormat provided by the client. This may not match any
3668 * of the actual surface formats.
3671 const struct anv_format
*format
;
3673 VkImageAspectFlags aspects
;
3676 uint32_t array_size
;
3677 uint32_t samples
; /**< VkImageCreateInfo::samples */
3679 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3680 VkImageUsageFlags stencil_usage
;
3681 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3682 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3684 /** True if this is needs to be bound to an appropriately tiled BO.
3686 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3687 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3688 * we require a dedicated allocation so that we can know to allocate a
3691 bool needs_set_tiling
;
3694 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3695 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3697 uint64_t drm_format_mod
;
3702 /* Whether the image is made of several underlying buffer objects rather a
3703 * single one with different offsets.
3707 /* Image was created with external format. */
3708 bool external_format
;
3713 * For each foo, anv_image::planes[x].surface is valid if and only if
3714 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3715 * to figure the number associated with a given aspect.
3717 * The hardware requires that the depth buffer and stencil buffer be
3718 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3719 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3720 * allocate the depth and stencil buffers as separate surfaces in the same
3725 * -----------------------
3727 * ----------------------- |
3728 * | shadow surface0 | |
3729 * ----------------------- | Plane 0
3730 * | aux surface0 | |
3731 * ----------------------- |
3732 * | fast clear colors0 | \|/
3733 * -----------------------
3735 * ----------------------- |
3736 * | shadow surface1 | |
3737 * ----------------------- | Plane 1
3738 * | aux surface1 | |
3739 * ----------------------- |
3740 * | fast clear colors1 | \|/
3741 * -----------------------
3744 * -----------------------
3748 * Offset of the entire plane (whenever the image is disjoint this is
3756 struct anv_surface surface
;
3759 * A surface which shadows the main surface and may have different
3760 * tiling. This is used for sampling using a tiling that isn't supported
3761 * for other operations.
3763 struct anv_surface shadow_surface
;
3766 * The base aux usage for this image. For color images, this can be
3767 * either CCS_E or CCS_D depending on whether or not we can reliably
3768 * leave CCS on all the time.
3770 enum isl_aux_usage aux_usage
;
3772 struct anv_surface aux_surface
;
3775 * Offset of the fast clear state (used to compute the
3776 * fast_clear_state_offset of the following planes).
3778 uint32_t fast_clear_state_offset
;
3781 * BO associated with this plane, set when bound.
3783 struct anv_address address
;
3786 * When destroying the image, also free the bo.
3792 /* The ordering of this enum is important */
3793 enum anv_fast_clear_type
{
3794 /** Image does not have/support any fast-clear blocks */
3795 ANV_FAST_CLEAR_NONE
= 0,
3796 /** Image has/supports fast-clear but only to the default value */
3797 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3798 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3799 ANV_FAST_CLEAR_ANY
= 2,
3802 /* Returns the number of auxiliary buffer levels attached to an image. */
3803 static inline uint8_t
3804 anv_image_aux_levels(const struct anv_image
* const image
,
3805 VkImageAspectFlagBits aspect
)
3807 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3808 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3811 /* The Gen12 CCS aux surface is represented with only one level. */
3812 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3813 image
->planes
[plane
].surface
.isl
.levels
:
3814 image
->planes
[plane
].aux_surface
.isl
.levels
;
3817 /* Returns the number of auxiliary buffer layers attached to an image. */
3818 static inline uint32_t
3819 anv_image_aux_layers(const struct anv_image
* const image
,
3820 VkImageAspectFlagBits aspect
,
3821 const uint8_t miplevel
)
3825 /* The miplevel must exist in the main buffer. */
3826 assert(miplevel
< image
->levels
);
3828 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3829 /* There are no layers with auxiliary data because the miplevel has no
3834 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3836 /* The Gen12 CCS aux surface is represented with only one layer. */
3837 const struct isl_extent4d
*aux_logical_level0_px
=
3838 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3839 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3840 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3842 return MAX2(aux_logical_level0_px
->array_len
,
3843 aux_logical_level0_px
->depth
>> miplevel
);
3847 static inline struct anv_address
3848 anv_image_get_clear_color_addr(UNUSED
const struct anv_device
*device
,
3849 const struct anv_image
*image
,
3850 VkImageAspectFlagBits aspect
)
3852 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3854 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3855 return anv_address_add(image
->planes
[plane
].address
,
3856 image
->planes
[plane
].fast_clear_state_offset
);
3859 static inline struct anv_address
3860 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3861 const struct anv_image
*image
,
3862 VkImageAspectFlagBits aspect
)
3864 struct anv_address addr
=
3865 anv_image_get_clear_color_addr(device
, image
, aspect
);
3867 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3868 device
->isl_dev
.ss
.clear_color_state_size
:
3869 device
->isl_dev
.ss
.clear_value_size
;
3870 return anv_address_add(addr
, clear_color_state_size
);
3873 static inline struct anv_address
3874 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3875 const struct anv_image
*image
,
3876 VkImageAspectFlagBits aspect
,
3877 uint32_t level
, uint32_t array_layer
)
3879 assert(level
< anv_image_aux_levels(image
, aspect
));
3880 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3881 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3882 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3884 struct anv_address addr
=
3885 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3886 addr
.offset
+= 4; /* Go past the fast clear type */
3888 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3889 for (uint32_t l
= 0; l
< level
; l
++)
3890 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3892 addr
.offset
+= level
* image
->array_size
* 4;
3894 addr
.offset
+= array_layer
* 4;
3896 assert(addr
.offset
<
3897 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3901 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3903 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3904 const struct anv_image
*image
)
3906 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3909 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3910 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3913 * "If this field is set to AUX_HIZ, Number of Multisamples must
3914 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3916 if (image
->type
== VK_IMAGE_TYPE_3D
)
3919 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3920 * struct. There's documentation which suggests that this feature actually
3921 * reduces performance on BDW, but it has only been observed to help so
3922 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3923 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3925 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3928 return image
->samples
== 1;
3932 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3933 const struct anv_image
*image
,
3936 return device
->info
.has_aux_map
&&
3937 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3941 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3942 const struct anv_image
*image
,
3943 VkImageAspectFlagBits aspect
,
3944 enum isl_aux_usage aux_usage
,
3946 uint32_t base_layer
,
3947 uint32_t layer_count
);
3950 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3951 const struct anv_image
*image
,
3952 VkImageAspectFlagBits aspect
,
3953 enum isl_aux_usage aux_usage
,
3954 enum isl_format format
, struct isl_swizzle swizzle
,
3955 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3956 VkRect2D area
, union isl_color_value clear_color
);
3958 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3959 const struct anv_image
*image
,
3960 VkImageAspectFlags aspects
,
3961 enum isl_aux_usage depth_aux_usage
,
3963 uint32_t base_layer
, uint32_t layer_count
,
3965 float depth_value
, uint8_t stencil_value
);
3967 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3968 const struct anv_image
*src_image
,
3969 enum isl_aux_usage src_aux_usage
,
3970 uint32_t src_level
, uint32_t src_base_layer
,
3971 const struct anv_image
*dst_image
,
3972 enum isl_aux_usage dst_aux_usage
,
3973 uint32_t dst_level
, uint32_t dst_base_layer
,
3974 VkImageAspectFlagBits aspect
,
3975 uint32_t src_x
, uint32_t src_y
,
3976 uint32_t dst_x
, uint32_t dst_y
,
3977 uint32_t width
, uint32_t height
,
3978 uint32_t layer_count
,
3979 enum blorp_filter filter
);
3981 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3982 const struct anv_image
*image
,
3983 VkImageAspectFlagBits aspect
, uint32_t level
,
3984 uint32_t base_layer
, uint32_t layer_count
,
3985 enum isl_aux_op hiz_op
);
3987 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3988 const struct anv_image
*image
,
3989 VkImageAspectFlags aspects
,
3991 uint32_t base_layer
, uint32_t layer_count
,
3992 VkRect2D area
, uint8_t stencil_value
);
3994 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3995 const struct anv_image
*image
,
3996 enum isl_format format
, struct isl_swizzle swizzle
,
3997 VkImageAspectFlagBits aspect
,
3998 uint32_t base_layer
, uint32_t layer_count
,
3999 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
4002 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
4003 const struct anv_image
*image
,
4004 enum isl_format format
, struct isl_swizzle swizzle
,
4005 VkImageAspectFlagBits aspect
, uint32_t level
,
4006 uint32_t base_layer
, uint32_t layer_count
,
4007 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
4011 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
4012 const struct anv_image
*image
,
4013 VkImageAspectFlagBits aspect
,
4014 uint32_t base_level
, uint32_t level_count
,
4015 uint32_t base_layer
, uint32_t layer_count
);
4018 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
4019 const struct anv_image
*image
,
4020 const VkImageAspectFlagBits aspect
,
4021 const VkImageLayout layout
);
4024 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
4025 const struct anv_image
*image
,
4026 const VkImageAspectFlagBits aspect
,
4027 const VkImageUsageFlagBits usage
,
4028 const VkImageLayout layout
);
4030 enum anv_fast_clear_type
4031 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
4032 const struct anv_image
* const image
,
4033 const VkImageAspectFlagBits aspect
,
4034 const VkImageLayout layout
);
4036 /* This is defined as a macro so that it works for both
4037 * VkImageSubresourceRange and VkImageSubresourceLayers
4039 #define anv_get_layerCount(_image, _range) \
4040 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
4041 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
4043 static inline uint32_t
4044 anv_get_levelCount(const struct anv_image
*image
,
4045 const VkImageSubresourceRange
*range
)
4047 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
4048 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
4051 static inline VkImageAspectFlags
4052 anv_image_expand_aspects(const struct anv_image
*image
,
4053 VkImageAspectFlags aspects
)
4055 /* If the underlying image has color plane aspects and
4056 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
4057 * the underlying image. */
4058 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
4059 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
4060 return image
->aspects
;
4066 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
4067 VkImageAspectFlags aspects2
)
4069 if (aspects1
== aspects2
)
4072 /* Only 1 color aspects are compatibles. */
4073 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
4074 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
4075 util_bitcount(aspects1
) == util_bitcount(aspects2
))
4081 struct anv_image_view
{
4082 struct vk_object_base base
;
4084 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
4086 VkImageAspectFlags aspect_mask
;
4088 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
4092 uint32_t image_plane
;
4094 struct isl_view isl
;
4097 * RENDER_SURFACE_STATE when using image as a sampler surface with an
4098 * image layout of SHADER_READ_ONLY_OPTIMAL or
4099 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
4101 struct anv_surface_state optimal_sampler_surface_state
;
4104 * RENDER_SURFACE_STATE when using image as a sampler surface with an
4105 * image layout of GENERAL.
4107 struct anv_surface_state general_sampler_surface_state
;
4110 * RENDER_SURFACE_STATE when using image as a storage image. Separate
4111 * states for write-only and readable, using the real format for
4112 * write-only and the lowered format for readable.
4114 struct anv_surface_state storage_surface_state
;
4115 struct anv_surface_state writeonly_storage_surface_state
;
4117 struct brw_image_param storage_image_param
;
4121 enum anv_image_view_state_flags
{
4122 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
4123 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
4126 void anv_image_fill_surface_state(struct anv_device
*device
,
4127 const struct anv_image
*image
,
4128 VkImageAspectFlagBits aspect
,
4129 const struct isl_view
*view
,
4130 isl_surf_usage_flags_t view_usage
,
4131 enum isl_aux_usage aux_usage
,
4132 const union isl_color_value
*clear_color
,
4133 enum anv_image_view_state_flags flags
,
4134 struct anv_surface_state
*state_inout
,
4135 struct brw_image_param
*image_param_out
);
4137 struct anv_image_create_info
{
4138 const VkImageCreateInfo
*vk_info
;
4140 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
4141 isl_tiling_flags_t isl_tiling_flags
;
4143 /** These flags will be added to any derived from VkImageCreateInfo. */
4144 isl_surf_usage_flags_t isl_extra_usage_flags
;
4147 bool external_format
;
4150 VkResult
anv_image_create(VkDevice _device
,
4151 const struct anv_image_create_info
*info
,
4152 const VkAllocationCallbacks
* alloc
,
4156 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
4158 static inline VkExtent3D
4159 anv_sanitize_image_extent(const VkImageType imageType
,
4160 const VkExtent3D imageExtent
)
4162 switch (imageType
) {
4163 case VK_IMAGE_TYPE_1D
:
4164 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
4165 case VK_IMAGE_TYPE_2D
:
4166 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
4167 case VK_IMAGE_TYPE_3D
:
4170 unreachable("invalid image type");
4174 static inline VkOffset3D
4175 anv_sanitize_image_offset(const VkImageType imageType
,
4176 const VkOffset3D imageOffset
)
4178 switch (imageType
) {
4179 case VK_IMAGE_TYPE_1D
:
4180 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
4181 case VK_IMAGE_TYPE_2D
:
4182 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
4183 case VK_IMAGE_TYPE_3D
:
4186 unreachable("invalid image type");
4190 VkFormatFeatureFlags
4191 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
4193 const struct anv_format
*anv_format
,
4194 VkImageTiling vk_tiling
);
4196 void anv_fill_buffer_surface_state(struct anv_device
*device
,
4197 struct anv_state state
,
4198 enum isl_format format
,
4199 struct anv_address address
,
4200 uint32_t range
, uint32_t stride
);
4203 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
4204 const struct anv_attachment_state
*att_state
,
4205 const struct anv_image_view
*iview
)
4207 const struct isl_format_layout
*view_fmtl
=
4208 isl_format_get_layout(iview
->planes
[0].isl
.format
);
4210 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
4211 if (view_fmtl->channels.c.bits) \
4212 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
4214 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
4215 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
4216 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
4217 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
4219 #undef COPY_CLEAR_COLOR_CHANNEL
4223 /* Haswell border color is a bit of a disaster. Float and unorm formats use a
4224 * straightforward 32-bit float color in the first 64 bytes. Instead of using
4225 * a nice float/integer union like Gen8+, Haswell specifies the integer border
4226 * color as a separate entry /after/ the float color. The layout of this entry
4227 * also depends on the format's bpp (with extra hacks for RG32), and overlaps.
4229 * Since we don't know the format/bpp, we can't make any of the border colors
4230 * containing '1' work for all formats, as it would be in the wrong place for
4231 * some of them. We opt to make 32-bit integers work as this seems like the
4232 * most common option. Fortunately, transparent black works regardless, as
4233 * all zeroes is the same in every bit-size.
4235 struct hsw_border_color
{
4239 uint32_t _pad1
[108];
4242 struct gen8_border_color
{
4247 /* Pad out to 64 bytes */
4251 struct anv_ycbcr_conversion
{
4252 struct vk_object_base base
;
4254 const struct anv_format
* format
;
4255 VkSamplerYcbcrModelConversion ycbcr_model
;
4256 VkSamplerYcbcrRange ycbcr_range
;
4257 VkComponentSwizzle mapping
[4];
4258 VkChromaLocation chroma_offsets
[2];
4259 VkFilter chroma_filter
;
4260 bool chroma_reconstruction
;
4263 struct anv_sampler
{
4264 struct vk_object_base base
;
4266 uint32_t state
[3][4];
4268 struct anv_ycbcr_conversion
*conversion
;
4270 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
4271 * and with a 32-byte stride for use as bindless samplers.
4273 struct anv_state bindless_state
;
4275 struct anv_state custom_border_color
;
4278 struct anv_framebuffer
{
4279 struct vk_object_base base
;
4285 uint32_t attachment_count
;
4286 struct anv_image_view
* attachments
[0];
4289 struct anv_subpass_attachment
{
4290 VkImageUsageFlagBits usage
;
4291 uint32_t attachment
;
4292 VkImageLayout layout
;
4294 /* Used only with attachment containing stencil data. */
4295 VkImageLayout stencil_layout
;
4298 struct anv_subpass
{
4299 uint32_t attachment_count
;
4302 * A pointer to all attachment references used in this subpass.
4303 * Only valid if ::attachment_count > 0.
4305 struct anv_subpass_attachment
* attachments
;
4306 uint32_t input_count
;
4307 struct anv_subpass_attachment
* input_attachments
;
4308 uint32_t color_count
;
4309 struct anv_subpass_attachment
* color_attachments
;
4310 struct anv_subpass_attachment
* resolve_attachments
;
4312 struct anv_subpass_attachment
* depth_stencil_attachment
;
4313 struct anv_subpass_attachment
* ds_resolve_attachment
;
4314 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4315 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4319 /** Subpass has a depth/stencil self-dependency */
4320 bool has_ds_self_dep
;
4322 /** Subpass has at least one color resolve attachment */
4323 bool has_color_resolve
;
4326 static inline unsigned
4327 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4329 return MAX2(1, util_bitcount(subpass
->view_mask
));
4332 struct anv_render_pass_attachment
{
4333 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4334 * its members individually.
4338 VkImageUsageFlags usage
;
4339 VkAttachmentLoadOp load_op
;
4340 VkAttachmentStoreOp store_op
;
4341 VkAttachmentLoadOp stencil_load_op
;
4342 VkImageLayout initial_layout
;
4343 VkImageLayout final_layout
;
4344 VkImageLayout first_subpass_layout
;
4346 VkImageLayout stencil_initial_layout
;
4347 VkImageLayout stencil_final_layout
;
4349 /* The subpass id in which the attachment will be used last. */
4350 uint32_t last_subpass_idx
;
4353 struct anv_render_pass
{
4354 struct vk_object_base base
;
4356 uint32_t attachment_count
;
4357 uint32_t subpass_count
;
4358 /* An array of subpass_count+1 flushes, one per subpass boundary */
4359 enum anv_pipe_bits
* subpass_flushes
;
4360 struct anv_render_pass_attachment
* attachments
;
4361 struct anv_subpass subpasses
[0];
4364 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4366 #define OA_SNAPSHOT_SIZE (256)
4367 #define ANV_KHR_PERF_QUERY_SIZE (ALIGN(sizeof(uint64_t), 64) + 2 * OA_SNAPSHOT_SIZE)
4369 struct anv_query_pool
{
4370 struct vk_object_base base
;
4373 VkQueryPipelineStatisticFlags pipeline_statistics
;
4374 /** Stride between slots, in bytes */
4376 /** Number of slots in this query pool */
4380 /* Perf queries : */
4381 struct anv_bo reset_bo
;
4382 uint32_t n_counters
;
4383 struct gen_perf_counter_pass
*counter_pass
;
4385 struct gen_perf_query_info
**pass_query
;
4388 static inline uint32_t khr_perf_query_preamble_offset(struct anv_query_pool
*pool
,
4391 return pass
* ANV_KHR_PERF_QUERY_SIZE
+ 8;
4394 int anv_get_instance_entrypoint_index(const char *name
);
4395 int anv_get_device_entrypoint_index(const char *name
);
4396 int anv_get_physical_device_entrypoint_index(const char *name
);
4398 const char *anv_get_instance_entry_name(int index
);
4399 const char *anv_get_physical_device_entry_name(int index
);
4400 const char *anv_get_device_entry_name(int index
);
4403 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4404 const struct anv_instance_extension_table
*instance
);
4406 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4407 const struct anv_instance_extension_table
*instance
);
4409 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4410 const struct anv_instance_extension_table
*instance
,
4411 const struct anv_device_extension_table
*device
);
4413 void *anv_resolve_device_entrypoint(const struct gen_device_info
*devinfo
,
4415 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4418 void anv_dump_image_to_ppm(struct anv_device
*device
,
4419 struct anv_image
*image
, unsigned miplevel
,
4420 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4421 const char *filename
);
4423 enum anv_dump_action
{
4424 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4430 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4434 void anv_dump_finish(void);
4436 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4438 static inline uint32_t
4439 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4441 /* This function must be called from within a subpass. */
4442 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4444 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4446 /* The id of this subpass shouldn't exceed the number of subpasses in this
4447 * render pass minus 1.
4449 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4453 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4454 void anv_device_perf_init(struct anv_device
*device
);
4455 void anv_perf_write_pass_results(struct gen_perf_config
*perf
,
4456 struct anv_query_pool
*pool
, uint32_t pass
,
4457 const struct gen_perf_query_result
*accumulated_results
,
4458 union VkPerformanceCounterResultKHR
*results
);
4460 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4461 VK_FROM_HANDLE(__anv_type, __name, __handle)
4463 VK_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, base
, VkCommandBuffer
,
4464 VK_OBJECT_TYPE_COMMAND_BUFFER
)
4465 VK_DEFINE_HANDLE_CASTS(anv_device
, vk
.base
, VkDevice
, VK_OBJECT_TYPE_DEVICE
)
4466 VK_DEFINE_HANDLE_CASTS(anv_instance
, base
, VkInstance
, VK_OBJECT_TYPE_INSTANCE
)
4467 VK_DEFINE_HANDLE_CASTS(anv_physical_device
, base
, VkPhysicalDevice
,
4468 VK_OBJECT_TYPE_PHYSICAL_DEVICE
)
4469 VK_DEFINE_HANDLE_CASTS(anv_queue
, base
, VkQueue
, VK_OBJECT_TYPE_QUEUE
)
4471 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, base
, VkCommandPool
,
4472 VK_OBJECT_TYPE_COMMAND_POOL
)
4473 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, base
, VkBuffer
,
4474 VK_OBJECT_TYPE_BUFFER
)
4475 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, base
, VkBufferView
,
4476 VK_OBJECT_TYPE_BUFFER_VIEW
)
4477 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, base
, VkDescriptorPool
,
4478 VK_OBJECT_TYPE_DESCRIPTOR_POOL
)
4479 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, base
, VkDescriptorSet
,
4480 VK_OBJECT_TYPE_DESCRIPTOR_SET
)
4481 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, base
,
4482 VkDescriptorSetLayout
,
4483 VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT
)
4484 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, base
,
4485 VkDescriptorUpdateTemplate
,
4486 VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE
)
4487 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, base
, VkDeviceMemory
,
4488 VK_OBJECT_TYPE_DEVICE_MEMORY
)
4489 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, base
, VkFence
, VK_OBJECT_TYPE_FENCE
)
4490 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, base
, VkEvent
, VK_OBJECT_TYPE_EVENT
)
4491 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, base
, VkFramebuffer
,
4492 VK_OBJECT_TYPE_FRAMEBUFFER
)
4493 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, base
, VkImage
, VK_OBJECT_TYPE_IMAGE
)
4494 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, base
, VkImageView
,
4495 VK_OBJECT_TYPE_IMAGE_VIEW
);
4496 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, base
, VkPipelineCache
,
4497 VK_OBJECT_TYPE_PIPELINE_CACHE
)
4498 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, base
, VkPipeline
,
4499 VK_OBJECT_TYPE_PIPELINE
)
4500 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, base
, VkPipelineLayout
,
4501 VK_OBJECT_TYPE_PIPELINE_LAYOUT
)
4502 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, base
, VkQueryPool
,
4503 VK_OBJECT_TYPE_QUERY_POOL
)
4504 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, base
, VkRenderPass
,
4505 VK_OBJECT_TYPE_RENDER_PASS
)
4506 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, base
, VkSampler
,
4507 VK_OBJECT_TYPE_SAMPLER
)
4508 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, base
, VkSemaphore
,
4509 VK_OBJECT_TYPE_SEMAPHORE
)
4510 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, base
, VkShaderModule
,
4511 VK_OBJECT_TYPE_SHADER_MODULE
)
4512 VK_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, base
,
4513 VkSamplerYcbcrConversion
,
4514 VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION
)
4516 /* Gen-specific function declarations */
4518 # include "anv_genX.h"
4520 # define genX(x) gen7_##x
4521 # include "anv_genX.h"
4523 # define genX(x) gen75_##x
4524 # include "anv_genX.h"
4526 # define genX(x) gen8_##x
4527 # include "anv_genX.h"
4529 # define genX(x) gen9_##x
4530 # include "anv_genX.h"
4532 # define genX(x) gen10_##x
4533 # include "anv_genX.h"
4535 # define genX(x) gen11_##x
4536 # include "anv_genX.h"
4538 # define genX(x) gen12_##x
4539 # include "anv_genX.h"
4543 #endif /* ANV_PRIVATE_H */