anv: move push constant allocation tracking into gfx pipeline state
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include "drm-uapi/i915_drm.h"
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #ifndef NDEBUG
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
41 #endif
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
61 #include "util/vma.h"
62 #include "util/xmlconfig.h"
63 #include "vk_alloc.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 struct anv_batch;
75 struct anv_buffer;
76 struct anv_buffer_view;
77 struct anv_image_view;
78 struct anv_instance;
79
80 struct gen_aux_map_context;
81 struct gen_perf_config;
82 struct gen_perf_counter_pass;
83 struct gen_perf_query_result;
84
85 #include <vulkan/vulkan.h>
86 #include <vulkan/vulkan_intel.h>
87 #include <vulkan/vk_icd.h>
88
89 #include "anv_android.h"
90 #include "anv_entrypoints.h"
91 #include "anv_extensions.h"
92 #include "isl/isl.h"
93
94 #include "dev/gen_debug.h"
95 #include "common/intel_log.h"
96 #include "wsi_common.h"
97
98 #define NSEC_PER_SEC 1000000000ull
99
100 /* anv Virtual Memory Layout
101 * =========================
102 *
103 * When the anv driver is determining the virtual graphics addresses of memory
104 * objects itself using the softpin mechanism, the following memory ranges
105 * will be used.
106 *
107 * Three special considerations to notice:
108 *
109 * (1) the dynamic state pool is located within the same 4 GiB as the low
110 * heap. This is to work around a VF cache issue described in a comment in
111 * anv_physical_device_init_heaps.
112 *
113 * (2) the binding table pool is located at lower addresses than the surface
114 * state pool, within a 4 GiB range. This allows surface state base addresses
115 * to cover both binding tables (16 bit offsets) and surface states (32 bit
116 * offsets).
117 *
118 * (3) the last 4 GiB of the address space is withheld from the high
119 * heap. Various hardware units will read past the end of an object for
120 * various reasons. This healthy margin prevents reads from wrapping around
121 * 48-bit addresses.
122 */
123 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
124 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
125 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
126 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
127 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
128 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
129 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
130 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
131 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
132 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
133 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
134 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
135 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
136
137 #define LOW_HEAP_SIZE \
138 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
139 #define DYNAMIC_STATE_POOL_SIZE \
140 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
141 #define BINDING_TABLE_POOL_SIZE \
142 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
143 #define SURFACE_STATE_POOL_SIZE \
144 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
145 #define INSTRUCTION_STATE_POOL_SIZE \
146 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
147 #define CLIENT_VISIBLE_HEAP_SIZE \
148 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
149
150 /* Allowing different clear colors requires us to perform a depth resolve at
151 * the end of certain render passes. This is because while slow clears store
152 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
153 * See the PRMs for examples describing when additional resolves would be
154 * necessary. To enable fast clears without requiring extra resolves, we set
155 * the clear value to a globally-defined one. We could allow different values
156 * if the user doesn't expect coherent data during or after a render passes
157 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
158 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
159 * 1.0f seems to be the only value used. The only application that doesn't set
160 * this value does so through the usage of an seemingly uninitialized clear
161 * value.
162 */
163 #define ANV_HZ_FC_VAL 1.0f
164
165 #define MAX_VBS 28
166 #define MAX_XFB_BUFFERS 4
167 #define MAX_XFB_STREAMS 4
168 #define MAX_SETS 8
169 #define MAX_RTS 8
170 #define MAX_VIEWPORTS 16
171 #define MAX_SCISSORS 16
172 #define MAX_PUSH_CONSTANTS_SIZE 128
173 #define MAX_DYNAMIC_BUFFERS 16
174 #define MAX_IMAGES 64
175 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
176 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
177 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
178 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
179 * use 64 here to avoid cache issues. This could most likely bring it back to
180 * 32 if we had different virtual addresses for the different views on a given
181 * GEM object.
182 */
183 #define ANV_UBO_ALIGNMENT 64
184 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
185 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
186
187 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
188 *
189 * "The surface state model is used when a Binding Table Index (specified
190 * in the message descriptor) of less than 240 is specified. In this model,
191 * the Binding Table Index is used to index into the binding table, and the
192 * binding table entry contains a pointer to the SURFACE_STATE."
193 *
194 * Binding table values above 240 are used for various things in the hardware
195 * such as stateless, stateless with incoherent cache, SLM, and bindless.
196 */
197 #define MAX_BINDING_TABLE_SIZE 240
198
199 /* The kernel relocation API has a limitation of a 32-bit delta value
200 * applied to the address before it is written which, in spite of it being
201 * unsigned, is treated as signed . Because of the way that this maps to
202 * the Vulkan API, we cannot handle an offset into a buffer that does not
203 * fit into a signed 32 bits. The only mechanism we have for dealing with
204 * this at the moment is to limit all VkDeviceMemory objects to a maximum
205 * of 2GB each. The Vulkan spec allows us to do this:
206 *
207 * "Some platforms may have a limit on the maximum size of a single
208 * allocation. For example, certain systems may fail to create
209 * allocations with a size greater than or equal to 4GB. Such a limit is
210 * implementation-dependent, and if such a failure occurs then the error
211 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
212 *
213 * We don't use vk_error here because it's not an error so much as an
214 * indication to the application that the allocation is too large.
215 */
216 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
217
218 #define ANV_SVGS_VB_INDEX MAX_VBS
219 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
220
221 /* We reserve this MI ALU register for the purpose of handling predication.
222 * Other code which uses the MI ALU should leave it alone.
223 */
224 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
225
226 /* We reserve this MI ALU register to pass around an offset computed from
227 * VkPerformanceQuerySubmitInfoKHR::counterPassIndex VK_KHR_performance_query.
228 * Other code which uses the MI ALU should leave it alone.
229 */
230 #define ANV_PERF_QUERY_OFFSET_REG 0x2670 /* MI_ALU_REG14 */
231
232 /* For gen12 we set the streamout buffers using 4 separate commands
233 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
234 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
235 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
236 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
237 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
238 * 3DSTATE_SO_BUFFER_INDEX_0.
239 */
240 #define SO_BUFFER_INDEX_0_CMD 0x60
241 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
242
243 static inline uint32_t
244 align_down_npot_u32(uint32_t v, uint32_t a)
245 {
246 return v - (v % a);
247 }
248
249 static inline uint32_t
250 align_down_u32(uint32_t v, uint32_t a)
251 {
252 assert(a != 0 && a == (a & -a));
253 return v & ~(a - 1);
254 }
255
256 static inline uint32_t
257 align_u32(uint32_t v, uint32_t a)
258 {
259 assert(a != 0 && a == (a & -a));
260 return align_down_u32(v + a - 1, a);
261 }
262
263 static inline uint64_t
264 align_down_u64(uint64_t v, uint64_t a)
265 {
266 assert(a != 0 && a == (a & -a));
267 return v & ~(a - 1);
268 }
269
270 static inline uint64_t
271 align_u64(uint64_t v, uint64_t a)
272 {
273 return align_down_u64(v + a - 1, a);
274 }
275
276 static inline int32_t
277 align_i32(int32_t v, int32_t a)
278 {
279 assert(a != 0 && a == (a & -a));
280 return (v + a - 1) & ~(a - 1);
281 }
282
283 /** Alignment must be a power of 2. */
284 static inline bool
285 anv_is_aligned(uintmax_t n, uintmax_t a)
286 {
287 assert(a == (a & -a));
288 return (n & (a - 1)) == 0;
289 }
290
291 static inline uint32_t
292 anv_minify(uint32_t n, uint32_t levels)
293 {
294 if (unlikely(n == 0))
295 return 0;
296 else
297 return MAX2(n >> levels, 1);
298 }
299
300 static inline float
301 anv_clamp_f(float f, float min, float max)
302 {
303 assert(min < max);
304
305 if (f > max)
306 return max;
307 else if (f < min)
308 return min;
309 else
310 return f;
311 }
312
313 static inline bool
314 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
315 {
316 if (*inout_mask & clear_mask) {
317 *inout_mask &= ~clear_mask;
318 return true;
319 } else {
320 return false;
321 }
322 }
323
324 static inline union isl_color_value
325 vk_to_isl_color(VkClearColorValue color)
326 {
327 return (union isl_color_value) {
328 .u32 = {
329 color.uint32[0],
330 color.uint32[1],
331 color.uint32[2],
332 color.uint32[3],
333 },
334 };
335 }
336
337 static inline void *anv_unpack_ptr(uintptr_t ptr, int bits, int *flags)
338 {
339 uintptr_t mask = (1ull << bits) - 1;
340 *flags = ptr & mask;
341 return (void *) (ptr & ~mask);
342 }
343
344 static inline uintptr_t anv_pack_ptr(void *ptr, int bits, int flags)
345 {
346 uintptr_t value = (uintptr_t) ptr;
347 uintptr_t mask = (1ull << bits) - 1;
348 return value | (mask & flags);
349 }
350
351 #define for_each_bit(b, dword) \
352 for (uint32_t __dword = (dword); \
353 (b) = __builtin_ffs(__dword) - 1, __dword; \
354 __dword &= ~(1 << (b)))
355
356 #define typed_memcpy(dest, src, count) ({ \
357 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
358 memcpy((dest), (src), (count) * sizeof(*(src))); \
359 })
360
361 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
362 * to be added here in order to utilize mapping in debug/error/perf macros.
363 */
364 #define REPORT_OBJECT_TYPE(o) \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
443 __builtin_choose_expr ( \
444 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
445 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
446 __builtin_choose_expr ( \
447 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
448 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
449 __builtin_choose_expr ( \
450 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
451 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
452 __builtin_choose_expr ( \
453 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
454 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
455 __builtin_choose_expr ( \
456 __builtin_types_compatible_p (__typeof (o), void*), \
457 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
458 /* The void expression results in a compile-time error \
459 when assigning the result to something. */ \
460 (void)0)))))))))))))))))))))))))))))))
461
462 /* Whenever we generate an error, pass it through this function. Useful for
463 * debugging, where we can break on it. Only call at error site, not when
464 * propagating errors. Might be useful to plug in a stack trace here.
465 */
466
467 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
468 VkDebugReportObjectTypeEXT type, VkResult error,
469 const char *file, int line, const char *format,
470 va_list args);
471
472 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
473 VkDebugReportObjectTypeEXT type, VkResult error,
474 const char *file, int line, const char *format, ...)
475 anv_printflike(7, 8);
476
477 #ifdef DEBUG
478 #define vk_error(error) __vk_errorf(NULL, NULL,\
479 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
480 error, __FILE__, __LINE__, NULL)
481 #define vk_errorfi(instance, obj, error, format, ...)\
482 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
483 __FILE__, __LINE__, format, ## __VA_ARGS__)
484 #define vk_errorf(device, obj, error, format, ...)\
485 vk_errorfi(anv_device_instance_or_null(device),\
486 obj, error, format, ## __VA_ARGS__)
487 #else
488 #define vk_error(error) error
489 #define vk_errorfi(instance, obj, error, format, ...) error
490 #define vk_errorf(device, obj, error, format, ...) error
491 #endif
492
493 /**
494 * Warn on ignored extension structs.
495 *
496 * The Vulkan spec requires us to ignore unsupported or unknown structs in
497 * a pNext chain. In debug mode, emitting warnings for ignored structs may
498 * help us discover structs that we should not have ignored.
499 *
500 *
501 * From the Vulkan 1.0.38 spec:
502 *
503 * Any component of the implementation (the loader, any enabled layers,
504 * and drivers) must skip over, without processing (other than reading the
505 * sType and pNext members) any chained structures with sType values not
506 * defined by extensions supported by that component.
507 */
508 #define anv_debug_ignored_stype(sType) \
509 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
510
511 void __anv_perf_warn(struct anv_device *device, const void *object,
512 VkDebugReportObjectTypeEXT type, const char *file,
513 int line, const char *format, ...)
514 anv_printflike(6, 7);
515 void anv_loge(const char *format, ...) anv_printflike(1, 2);
516 void anv_loge_v(const char *format, va_list va);
517
518 /**
519 * Print a FINISHME message, including its source location.
520 */
521 #define anv_finishme(format, ...) \
522 do { \
523 static bool reported = false; \
524 if (!reported) { \
525 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
526 ##__VA_ARGS__); \
527 reported = true; \
528 } \
529 } while (0)
530
531 /**
532 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
533 */
534 #define anv_perf_warn(instance, obj, format, ...) \
535 do { \
536 static bool reported = false; \
537 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
538 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
539 format, ##__VA_ARGS__); \
540 reported = true; \
541 } \
542 } while (0)
543
544 /* A non-fatal assert. Useful for debugging. */
545 #ifdef DEBUG
546 #define anv_assert(x) ({ \
547 if (unlikely(!(x))) \
548 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
549 })
550 #else
551 #define anv_assert(x)
552 #endif
553
554 /* A multi-pointer allocator
555 *
556 * When copying data structures from the user (such as a render pass), it's
557 * common to need to allocate data for a bunch of different things. Instead
558 * of doing several allocations and having to handle all of the error checking
559 * that entails, it can be easier to do a single allocation. This struct
560 * helps facilitate that. The intended usage looks like this:
561 *
562 * ANV_MULTIALLOC(ma)
563 * anv_multialloc_add(&ma, &main_ptr, 1);
564 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
565 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
566 *
567 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
568 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
569 */
570 struct anv_multialloc {
571 size_t size;
572 size_t align;
573
574 uint32_t ptr_count;
575 void **ptrs[8];
576 };
577
578 #define ANV_MULTIALLOC_INIT \
579 ((struct anv_multialloc) { 0, })
580
581 #define ANV_MULTIALLOC(_name) \
582 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
583
584 __attribute__((always_inline))
585 static inline void
586 _anv_multialloc_add(struct anv_multialloc *ma,
587 void **ptr, size_t size, size_t align)
588 {
589 size_t offset = align_u64(ma->size, align);
590 ma->size = offset + size;
591 ma->align = MAX2(ma->align, align);
592
593 /* Store the offset in the pointer. */
594 *ptr = (void *)(uintptr_t)offset;
595
596 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
597 ma->ptrs[ma->ptr_count++] = ptr;
598 }
599
600 #define anv_multialloc_add_size(_ma, _ptr, _size) \
601 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
602
603 #define anv_multialloc_add(_ma, _ptr, _count) \
604 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
605
606 __attribute__((always_inline))
607 static inline void *
608 anv_multialloc_alloc(struct anv_multialloc *ma,
609 const VkAllocationCallbacks *alloc,
610 VkSystemAllocationScope scope)
611 {
612 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
613 if (!ptr)
614 return NULL;
615
616 /* Fill out each of the pointers with their final value.
617 *
618 * for (uint32_t i = 0; i < ma->ptr_count; i++)
619 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
620 *
621 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
622 * constant, GCC is incapable of figuring this out and unrolling the loop
623 * so we have to give it a little help.
624 */
625 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
626 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
627 if ((_i) < ma->ptr_count) \
628 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
629 _ANV_MULTIALLOC_UPDATE_POINTER(0);
630 _ANV_MULTIALLOC_UPDATE_POINTER(1);
631 _ANV_MULTIALLOC_UPDATE_POINTER(2);
632 _ANV_MULTIALLOC_UPDATE_POINTER(3);
633 _ANV_MULTIALLOC_UPDATE_POINTER(4);
634 _ANV_MULTIALLOC_UPDATE_POINTER(5);
635 _ANV_MULTIALLOC_UPDATE_POINTER(6);
636 _ANV_MULTIALLOC_UPDATE_POINTER(7);
637 #undef _ANV_MULTIALLOC_UPDATE_POINTER
638
639 return ptr;
640 }
641
642 __attribute__((always_inline))
643 static inline void *
644 anv_multialloc_alloc2(struct anv_multialloc *ma,
645 const VkAllocationCallbacks *parent_alloc,
646 const VkAllocationCallbacks *alloc,
647 VkSystemAllocationScope scope)
648 {
649 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
650 }
651
652 struct anv_bo {
653 uint32_t gem_handle;
654
655 uint32_t refcount;
656
657 /* Index into the current validation list. This is used by the
658 * validation list building alrogithm to track which buffers are already
659 * in the validation list so that we can ensure uniqueness.
660 */
661 uint32_t index;
662
663 /* Index for use with util_sparse_array_free_list */
664 uint32_t free_index;
665
666 /* Last known offset. This value is provided by the kernel when we
667 * execbuf and is used as the presumed offset for the next bunch of
668 * relocations.
669 */
670 uint64_t offset;
671
672 /** Size of the buffer not including implicit aux */
673 uint64_t size;
674
675 /* Map for internally mapped BOs.
676 *
677 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
678 */
679 void *map;
680
681 /** Size of the implicit CCS range at the end of the buffer
682 *
683 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
684 * page of main surface data maps to a 256B chunk of CCS data and that
685 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
686 * addresses in the main surface to virtual memory addresses for CCS data.
687 *
688 * Because we can't change these maps around easily and because Vulkan
689 * allows two VkImages to be bound to overlapping memory regions (as long
690 * as the app is careful), it's not feasible to make this mapping part of
691 * the image. (On Gen11 and earlier, the mapping was provided via
692 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
693 * Instead, we attach the CCS data directly to the buffer object and setup
694 * the AUX table mapping at BO creation time.
695 *
696 * This field is for internal tracking use by the BO allocator only and
697 * should not be touched by other parts of the code. If something wants to
698 * know if a BO has implicit CCS data, it should instead look at the
699 * has_implicit_ccs boolean below.
700 *
701 * This data is not included in maps of this buffer.
702 */
703 uint32_t _ccs_size;
704
705 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
706 uint32_t flags;
707
708 /** True if this BO may be shared with other processes */
709 bool is_external:1;
710
711 /** True if this BO is a wrapper
712 *
713 * When set to true, none of the fields in this BO are meaningful except
714 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
715 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
716 * is set in the physical device.
717 */
718 bool is_wrapper:1;
719
720 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
721 bool has_fixed_address:1;
722
723 /** True if this BO wraps a host pointer */
724 bool from_host_ptr:1;
725
726 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
727 bool has_client_visible_address:1;
728
729 /** True if this BO has implicit CCS data attached to it */
730 bool has_implicit_ccs:1;
731 };
732
733 static inline struct anv_bo *
734 anv_bo_ref(struct anv_bo *bo)
735 {
736 p_atomic_inc(&bo->refcount);
737 return bo;
738 }
739
740 static inline struct anv_bo *
741 anv_bo_unwrap(struct anv_bo *bo)
742 {
743 while (bo->is_wrapper)
744 bo = bo->map;
745 return bo;
746 }
747
748 /* Represents a lock-free linked list of "free" things. This is used by
749 * both the block pool and the state pools. Unfortunately, in order to
750 * solve the ABA problem, we can't use a single uint32_t head.
751 */
752 union anv_free_list {
753 struct {
754 uint32_t offset;
755
756 /* A simple count that is incremented every time the head changes. */
757 uint32_t count;
758 };
759 /* Make sure it's aligned to 64 bits. This will make atomic operations
760 * faster on 32 bit platforms.
761 */
762 uint64_t u64 __attribute__ ((aligned (8)));
763 };
764
765 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
766
767 struct anv_block_state {
768 union {
769 struct {
770 uint32_t next;
771 uint32_t end;
772 };
773 /* Make sure it's aligned to 64 bits. This will make atomic operations
774 * faster on 32 bit platforms.
775 */
776 uint64_t u64 __attribute__ ((aligned (8)));
777 };
778 };
779
780 #define anv_block_pool_foreach_bo(bo, pool) \
781 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
782 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
783 _pp_bo++)
784
785 #define ANV_MAX_BLOCK_POOL_BOS 20
786
787 struct anv_block_pool {
788 struct anv_device *device;
789 bool use_softpin;
790
791 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
792 * around the actual BO so that we grow the pool after the wrapper BO has
793 * been put in a relocation list. This is only used in the non-softpin
794 * case.
795 */
796 struct anv_bo wrapper_bo;
797
798 struct anv_bo *bos[ANV_MAX_BLOCK_POOL_BOS];
799 struct anv_bo *bo;
800 uint32_t nbos;
801
802 uint64_t size;
803
804 /* The address where the start of the pool is pinned. The various bos that
805 * are created as the pool grows will have addresses in the range
806 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
807 */
808 uint64_t start_address;
809
810 /* The offset from the start of the bo to the "center" of the block
811 * pool. Pointers to allocated blocks are given by
812 * bo.map + center_bo_offset + offsets.
813 */
814 uint32_t center_bo_offset;
815
816 /* Current memory map of the block pool. This pointer may or may not
817 * point to the actual beginning of the block pool memory. If
818 * anv_block_pool_alloc_back has ever been called, then this pointer
819 * will point to the "center" position of the buffer and all offsets
820 * (negative or positive) given out by the block pool alloc functions
821 * will be valid relative to this pointer.
822 *
823 * In particular, map == bo.map + center_offset
824 *
825 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
826 * since it will handle the softpin case as well, where this points to NULL.
827 */
828 void *map;
829 int fd;
830
831 /**
832 * Array of mmaps and gem handles owned by the block pool, reclaimed when
833 * the block pool is destroyed.
834 */
835 struct u_vector mmap_cleanups;
836
837 struct anv_block_state state;
838
839 struct anv_block_state back_state;
840 };
841
842 /* Block pools are backed by a fixed-size 1GB memfd */
843 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
844
845 /* The center of the block pool is also the middle of the memfd. This may
846 * change in the future if we decide differently for some reason.
847 */
848 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
849
850 static inline uint32_t
851 anv_block_pool_size(struct anv_block_pool *pool)
852 {
853 return pool->state.end + pool->back_state.end;
854 }
855
856 struct anv_state {
857 int32_t offset;
858 uint32_t alloc_size;
859 void *map;
860 uint32_t idx;
861 };
862
863 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
864
865 struct anv_fixed_size_state_pool {
866 union anv_free_list free_list;
867 struct anv_block_state block;
868 };
869
870 #define ANV_MIN_STATE_SIZE_LOG2 6
871 #define ANV_MAX_STATE_SIZE_LOG2 21
872
873 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
874
875 struct anv_free_entry {
876 uint32_t next;
877 struct anv_state state;
878 };
879
880 struct anv_state_table {
881 struct anv_device *device;
882 int fd;
883 struct anv_free_entry *map;
884 uint32_t size;
885 struct anv_block_state state;
886 struct u_vector cleanups;
887 };
888
889 struct anv_state_pool {
890 struct anv_block_pool block_pool;
891
892 /* Offset into the relevant state base address where the state pool starts
893 * allocating memory.
894 */
895 int32_t start_offset;
896
897 struct anv_state_table table;
898
899 /* The size of blocks which will be allocated from the block pool */
900 uint32_t block_size;
901
902 /** Free list for "back" allocations */
903 union anv_free_list back_alloc_free_list;
904
905 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
906 };
907
908 struct anv_state_reserved_pool {
909 struct anv_state_pool *pool;
910 union anv_free_list reserved_blocks;
911 uint32_t count;
912 };
913
914 struct anv_state_stream {
915 struct anv_state_pool *state_pool;
916
917 /* The size of blocks to allocate from the state pool */
918 uint32_t block_size;
919
920 /* Current block we're allocating from */
921 struct anv_state block;
922
923 /* Offset into the current block at which to allocate the next state */
924 uint32_t next;
925
926 /* List of all blocks allocated from this pool */
927 struct util_dynarray all_blocks;
928 };
929
930 /* The block_pool functions exported for testing only. The block pool should
931 * only be used via a state pool (see below).
932 */
933 VkResult anv_block_pool_init(struct anv_block_pool *pool,
934 struct anv_device *device,
935 uint64_t start_address,
936 uint32_t initial_size);
937 void anv_block_pool_finish(struct anv_block_pool *pool);
938 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
939 uint32_t block_size, uint32_t *padding);
940 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
941 uint32_t block_size);
942 void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset, uint32_t
943 size);
944
945 VkResult anv_state_pool_init(struct anv_state_pool *pool,
946 struct anv_device *device,
947 uint64_t base_address,
948 int32_t start_offset,
949 uint32_t block_size);
950 void anv_state_pool_finish(struct anv_state_pool *pool);
951 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
952 uint32_t state_size, uint32_t alignment);
953 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
954 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
955 void anv_state_stream_init(struct anv_state_stream *stream,
956 struct anv_state_pool *state_pool,
957 uint32_t block_size);
958 void anv_state_stream_finish(struct anv_state_stream *stream);
959 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
960 uint32_t size, uint32_t alignment);
961
962 void anv_state_reserved_pool_init(struct anv_state_reserved_pool *pool,
963 struct anv_state_pool *parent,
964 uint32_t count, uint32_t size,
965 uint32_t alignment);
966 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool *pool);
967 struct anv_state anv_state_reserved_pool_alloc(struct anv_state_reserved_pool *pool);
968 void anv_state_reserved_pool_free(struct anv_state_reserved_pool *pool,
969 struct anv_state state);
970
971 VkResult anv_state_table_init(struct anv_state_table *table,
972 struct anv_device *device,
973 uint32_t initial_entries);
974 void anv_state_table_finish(struct anv_state_table *table);
975 VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx,
976 uint32_t count);
977 void anv_free_list_push(union anv_free_list *list,
978 struct anv_state_table *table,
979 uint32_t idx, uint32_t count);
980 struct anv_state* anv_free_list_pop(union anv_free_list *list,
981 struct anv_state_table *table);
982
983
984 static inline struct anv_state *
985 anv_state_table_get(struct anv_state_table *table, uint32_t idx)
986 {
987 return &table->map[idx].state;
988 }
989 /**
990 * Implements a pool of re-usable BOs. The interface is identical to that
991 * of block_pool except that each block is its own BO.
992 */
993 struct anv_bo_pool {
994 struct anv_device *device;
995
996 struct util_sparse_array_free_list free_list[16];
997 };
998
999 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
1000 void anv_bo_pool_finish(struct anv_bo_pool *pool);
1001 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, uint32_t size,
1002 struct anv_bo **bo_out);
1003 void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
1004
1005 struct anv_scratch_pool {
1006 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
1007 struct anv_bo *bos[16][MESA_SHADER_STAGES];
1008 };
1009
1010 void anv_scratch_pool_init(struct anv_device *device,
1011 struct anv_scratch_pool *pool);
1012 void anv_scratch_pool_finish(struct anv_device *device,
1013 struct anv_scratch_pool *pool);
1014 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
1015 struct anv_scratch_pool *pool,
1016 gl_shader_stage stage,
1017 unsigned per_thread_scratch);
1018
1019 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1020 struct anv_bo_cache {
1021 struct util_sparse_array bo_map;
1022 pthread_mutex_t mutex;
1023 };
1024
1025 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
1026 void anv_bo_cache_finish(struct anv_bo_cache *cache);
1027
1028 struct anv_memory_type {
1029 /* Standard bits passed on to the client */
1030 VkMemoryPropertyFlags propertyFlags;
1031 uint32_t heapIndex;
1032 };
1033
1034 struct anv_memory_heap {
1035 /* Standard bits passed on to the client */
1036 VkDeviceSize size;
1037 VkMemoryHeapFlags flags;
1038
1039 /** Driver-internal book-keeping.
1040 *
1041 * Align it to 64 bits to make atomic operations faster on 32 bit platforms.
1042 */
1043 VkDeviceSize used __attribute__ ((aligned (8)));
1044 };
1045
1046 struct anv_physical_device {
1047 struct vk_object_base base;
1048
1049 /* Link in anv_instance::physical_devices */
1050 struct list_head link;
1051
1052 struct anv_instance * instance;
1053 bool no_hw;
1054 char path[20];
1055 const char * name;
1056 struct {
1057 uint16_t domain;
1058 uint8_t bus;
1059 uint8_t device;
1060 uint8_t function;
1061 } pci_info;
1062 struct gen_device_info info;
1063 /** Amount of "GPU memory" we want to advertise
1064 *
1065 * Clearly, this value is bogus since Intel is a UMA architecture. On
1066 * gen7 platforms, we are limited by GTT size unless we want to implement
1067 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1068 * practically unlimited. However, we will never report more than 3/4 of
1069 * the total system ram to try and avoid running out of RAM.
1070 */
1071 bool supports_48bit_addresses;
1072 struct brw_compiler * compiler;
1073 struct isl_device isl_dev;
1074 struct gen_perf_config * perf;
1075 int cmd_parser_version;
1076 bool has_softpin;
1077 bool has_exec_async;
1078 bool has_exec_capture;
1079 bool has_exec_fence;
1080 bool has_syncobj;
1081 bool has_syncobj_wait;
1082 bool has_context_priority;
1083 bool has_context_isolation;
1084 bool has_mem_available;
1085 bool has_mmap_offset;
1086 uint64_t gtt_size;
1087
1088 bool use_softpin;
1089 bool always_use_bindless;
1090 bool use_call_secondary;
1091
1092 /** True if we can access buffers using A64 messages */
1093 bool has_a64_buffer_access;
1094 /** True if we can use bindless access for images */
1095 bool has_bindless_images;
1096 /** True if we can use bindless access for samplers */
1097 bool has_bindless_samplers;
1098
1099 /** True if we can read the GPU timestamp register
1100 *
1101 * When running in a virtual context, the timestamp register is unreadable
1102 * on Gen12+.
1103 */
1104 bool has_reg_timestamp;
1105
1106 /** True if this device has implicit AUX
1107 *
1108 * If true, CCS is handled as an implicit attachment to the BO rather than
1109 * as an explicitly bound surface.
1110 */
1111 bool has_implicit_ccs;
1112
1113 bool always_flush_cache;
1114
1115 struct anv_device_extension_table supported_extensions;
1116
1117 uint32_t eu_total;
1118 uint32_t subslice_total;
1119
1120 struct {
1121 uint32_t type_count;
1122 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
1123 uint32_t heap_count;
1124 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
1125 } memory;
1126
1127 uint8_t driver_build_sha1[20];
1128 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
1129 uint8_t driver_uuid[VK_UUID_SIZE];
1130 uint8_t device_uuid[VK_UUID_SIZE];
1131
1132 struct disk_cache * disk_cache;
1133
1134 struct wsi_device wsi_device;
1135 int local_fd;
1136 int master_fd;
1137 };
1138
1139 struct anv_app_info {
1140 const char* app_name;
1141 uint32_t app_version;
1142 const char* engine_name;
1143 uint32_t engine_version;
1144 uint32_t api_version;
1145 };
1146
1147 struct anv_instance {
1148 struct vk_object_base base;
1149
1150 VkAllocationCallbacks alloc;
1151
1152 struct anv_app_info app_info;
1153
1154 struct anv_instance_extension_table enabled_extensions;
1155 struct anv_instance_dispatch_table dispatch;
1156 struct anv_physical_device_dispatch_table physical_device_dispatch;
1157 struct anv_device_dispatch_table device_dispatch;
1158
1159 bool physical_devices_enumerated;
1160 struct list_head physical_devices;
1161
1162 bool pipeline_cache_enabled;
1163
1164 struct vk_debug_report_instance debug_report_callbacks;
1165
1166 struct driOptionCache dri_options;
1167 struct driOptionCache available_dri_options;
1168 };
1169
1170 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
1171 void anv_finish_wsi(struct anv_physical_device *physical_device);
1172
1173 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
1174 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
1175 const char *name);
1176
1177 struct anv_queue_submit {
1178 struct anv_cmd_buffer * cmd_buffer;
1179
1180 uint32_t fence_count;
1181 uint32_t fence_array_length;
1182 struct drm_i915_gem_exec_fence * fences;
1183
1184 uint32_t temporary_semaphore_count;
1185 uint32_t temporary_semaphore_array_length;
1186 struct anv_semaphore_impl * temporary_semaphores;
1187
1188 /* Semaphores to be signaled with a SYNC_FD. */
1189 struct anv_semaphore ** sync_fd_semaphores;
1190 uint32_t sync_fd_semaphore_count;
1191 uint32_t sync_fd_semaphore_array_length;
1192
1193 /* Allocated only with non shareable timelines. */
1194 struct anv_timeline ** wait_timelines;
1195 uint32_t wait_timeline_count;
1196 uint32_t wait_timeline_array_length;
1197 uint64_t * wait_timeline_values;
1198
1199 struct anv_timeline ** signal_timelines;
1200 uint32_t signal_timeline_count;
1201 uint32_t signal_timeline_array_length;
1202 uint64_t * signal_timeline_values;
1203
1204 int in_fence;
1205 bool need_out_fence;
1206 int out_fence;
1207
1208 uint32_t fence_bo_count;
1209 uint32_t fence_bo_array_length;
1210 /* An array of struct anv_bo pointers with lower bit used as a flag to
1211 * signal we will wait on that BO (see anv_(un)pack_ptr).
1212 */
1213 uintptr_t * fence_bos;
1214
1215 int perf_query_pass;
1216
1217 const VkAllocationCallbacks * alloc;
1218 VkSystemAllocationScope alloc_scope;
1219
1220 struct anv_bo * simple_bo;
1221 uint32_t simple_bo_size;
1222
1223 struct list_head link;
1224 };
1225
1226 struct anv_queue {
1227 struct vk_object_base base;
1228
1229 struct anv_device * device;
1230
1231 /*
1232 * A list of struct anv_queue_submit to be submitted to i915.
1233 */
1234 struct list_head queued_submits;
1235
1236 VkDeviceQueueCreateFlags flags;
1237 };
1238
1239 struct anv_pipeline_cache {
1240 struct vk_object_base base;
1241 struct anv_device * device;
1242 pthread_mutex_t mutex;
1243
1244 struct hash_table * nir_cache;
1245
1246 struct hash_table * cache;
1247
1248 bool external_sync;
1249 };
1250
1251 struct nir_xfb_info;
1252 struct anv_pipeline_bind_map;
1253
1254 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
1255 struct anv_device *device,
1256 bool cache_enabled,
1257 bool external_sync);
1258 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
1259
1260 struct anv_shader_bin *
1261 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
1262 const void *key, uint32_t key_size);
1263 struct anv_shader_bin *
1264 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
1265 gl_shader_stage stage,
1266 const void *key_data, uint32_t key_size,
1267 const void *kernel_data, uint32_t kernel_size,
1268 const void *constant_data,
1269 uint32_t constant_data_size,
1270 const struct brw_stage_prog_data *prog_data,
1271 uint32_t prog_data_size,
1272 const struct brw_compile_stats *stats,
1273 uint32_t num_stats,
1274 const struct nir_xfb_info *xfb_info,
1275 const struct anv_pipeline_bind_map *bind_map);
1276
1277 struct anv_shader_bin *
1278 anv_device_search_for_kernel(struct anv_device *device,
1279 struct anv_pipeline_cache *cache,
1280 const void *key_data, uint32_t key_size,
1281 bool *user_cache_bit);
1282
1283 struct anv_shader_bin *
1284 anv_device_upload_kernel(struct anv_device *device,
1285 struct anv_pipeline_cache *cache,
1286 gl_shader_stage stage,
1287 const void *key_data, uint32_t key_size,
1288 const void *kernel_data, uint32_t kernel_size,
1289 const void *constant_data,
1290 uint32_t constant_data_size,
1291 const struct brw_stage_prog_data *prog_data,
1292 uint32_t prog_data_size,
1293 const struct brw_compile_stats *stats,
1294 uint32_t num_stats,
1295 const struct nir_xfb_info *xfb_info,
1296 const struct anv_pipeline_bind_map *bind_map);
1297
1298 struct nir_shader;
1299 struct nir_shader_compiler_options;
1300
1301 struct nir_shader *
1302 anv_device_search_for_nir(struct anv_device *device,
1303 struct anv_pipeline_cache *cache,
1304 const struct nir_shader_compiler_options *nir_options,
1305 unsigned char sha1_key[20],
1306 void *mem_ctx);
1307
1308 void
1309 anv_device_upload_nir(struct anv_device *device,
1310 struct anv_pipeline_cache *cache,
1311 const struct nir_shader *nir,
1312 unsigned char sha1_key[20]);
1313
1314 struct anv_address {
1315 struct anv_bo *bo;
1316 uint32_t offset;
1317 };
1318
1319 struct anv_device {
1320 struct vk_device vk;
1321
1322 struct anv_physical_device * physical;
1323 bool no_hw;
1324 struct gen_device_info info;
1325 struct isl_device isl_dev;
1326 int context_id;
1327 int fd;
1328 bool can_chain_batches;
1329 bool robust_buffer_access;
1330 struct anv_device_extension_table enabled_extensions;
1331 struct anv_device_dispatch_table dispatch;
1332
1333 pthread_mutex_t vma_mutex;
1334 struct util_vma_heap vma_lo;
1335 struct util_vma_heap vma_cva;
1336 struct util_vma_heap vma_hi;
1337
1338 /** List of all anv_device_memory objects */
1339 struct list_head memory_objects;
1340
1341 struct anv_bo_pool batch_bo_pool;
1342
1343 struct anv_bo_cache bo_cache;
1344
1345 struct anv_state_pool dynamic_state_pool;
1346 struct anv_state_pool instruction_state_pool;
1347 struct anv_state_pool binding_table_pool;
1348 struct anv_state_pool surface_state_pool;
1349
1350 struct anv_state_reserved_pool custom_border_colors;
1351
1352 /** BO used for various workarounds
1353 *
1354 * There are a number of workarounds on our hardware which require writing
1355 * data somewhere and it doesn't really matter where. For that, we use
1356 * this BO and just write to the first dword or so.
1357 *
1358 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1359 * For that, we use the high bytes (>= 1024) of the workaround BO.
1360 */
1361 struct anv_bo * workaround_bo;
1362 struct anv_address workaround_address;
1363
1364 struct anv_bo * trivial_batch_bo;
1365 struct anv_bo * hiz_clear_bo;
1366 struct anv_state null_surface_state;
1367
1368 struct anv_pipeline_cache default_pipeline_cache;
1369 struct blorp_context blorp;
1370
1371 struct anv_state border_colors;
1372
1373 struct anv_state slice_hash;
1374
1375 struct anv_queue queue;
1376
1377 struct anv_scratch_pool scratch_pool;
1378
1379 pthread_mutex_t mutex;
1380 pthread_cond_t queue_submit;
1381 int _lost;
1382
1383 struct gen_batch_decode_ctx decoder_ctx;
1384 /*
1385 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1386 * the cmd_buffer's list.
1387 */
1388 struct anv_cmd_buffer *cmd_buffer_being_decoded;
1389
1390 int perf_fd; /* -1 if no opened */
1391 uint64_t perf_metric; /* 0 if unset */
1392
1393 struct gen_aux_map_context *aux_map_ctx;
1394
1395 struct gen_debug_block_frame *debug_frame_desc;
1396 };
1397
1398 static inline struct anv_instance *
1399 anv_device_instance_or_null(const struct anv_device *device)
1400 {
1401 return device ? device->physical->instance : NULL;
1402 }
1403
1404 static inline struct anv_state_pool *
1405 anv_binding_table_pool(struct anv_device *device)
1406 {
1407 if (device->physical->use_softpin)
1408 return &device->binding_table_pool;
1409 else
1410 return &device->surface_state_pool;
1411 }
1412
1413 static inline struct anv_state
1414 anv_binding_table_pool_alloc(struct anv_device *device) {
1415 if (device->physical->use_softpin)
1416 return anv_state_pool_alloc(&device->binding_table_pool,
1417 device->binding_table_pool.block_size, 0);
1418 else
1419 return anv_state_pool_alloc_back(&device->surface_state_pool);
1420 }
1421
1422 static inline void
1423 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1424 anv_state_pool_free(anv_binding_table_pool(device), state);
1425 }
1426
1427 static inline uint32_t
1428 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1429 {
1430 if (bo->is_external)
1431 return device->isl_dev.mocs.external;
1432 else
1433 return device->isl_dev.mocs.internal;
1434 }
1435
1436 void anv_device_init_blorp(struct anv_device *device);
1437 void anv_device_finish_blorp(struct anv_device *device);
1438
1439 void _anv_device_set_all_queue_lost(struct anv_device *device);
1440 VkResult _anv_device_set_lost(struct anv_device *device,
1441 const char *file, int line,
1442 const char *msg, ...)
1443 anv_printflike(4, 5);
1444 VkResult _anv_queue_set_lost(struct anv_queue *queue,
1445 const char *file, int line,
1446 const char *msg, ...)
1447 anv_printflike(4, 5);
1448 #define anv_device_set_lost(dev, ...) \
1449 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1450 #define anv_queue_set_lost(queue, ...) \
1451 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1452
1453 static inline bool
1454 anv_device_is_lost(struct anv_device *device)
1455 {
1456 return unlikely(p_atomic_read(&device->_lost));
1457 }
1458
1459 VkResult anv_device_query_status(struct anv_device *device);
1460
1461
1462 enum anv_bo_alloc_flags {
1463 /** Specifies that the BO must have a 32-bit address
1464 *
1465 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1466 */
1467 ANV_BO_ALLOC_32BIT_ADDRESS = (1 << 0),
1468
1469 /** Specifies that the BO may be shared externally */
1470 ANV_BO_ALLOC_EXTERNAL = (1 << 1),
1471
1472 /** Specifies that the BO should be mapped */
1473 ANV_BO_ALLOC_MAPPED = (1 << 2),
1474
1475 /** Specifies that the BO should be snooped so we get coherency */
1476 ANV_BO_ALLOC_SNOOPED = (1 << 3),
1477
1478 /** Specifies that the BO should be captured in error states */
1479 ANV_BO_ALLOC_CAPTURE = (1 << 4),
1480
1481 /** Specifies that the BO will have an address assigned by the caller
1482 *
1483 * Such BOs do not exist in any VMA heap.
1484 */
1485 ANV_BO_ALLOC_FIXED_ADDRESS = (1 << 5),
1486
1487 /** Enables implicit synchronization on the BO
1488 *
1489 * This is the opposite of EXEC_OBJECT_ASYNC.
1490 */
1491 ANV_BO_ALLOC_IMPLICIT_SYNC = (1 << 6),
1492
1493 /** Enables implicit synchronization on the BO
1494 *
1495 * This is equivalent to EXEC_OBJECT_WRITE.
1496 */
1497 ANV_BO_ALLOC_IMPLICIT_WRITE = (1 << 7),
1498
1499 /** Has an address which is visible to the client */
1500 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS = (1 << 8),
1501
1502 /** This buffer has implicit CCS data attached to it */
1503 ANV_BO_ALLOC_IMPLICIT_CCS = (1 << 9),
1504 };
1505
1506 VkResult anv_device_alloc_bo(struct anv_device *device, uint64_t size,
1507 enum anv_bo_alloc_flags alloc_flags,
1508 uint64_t explicit_address,
1509 struct anv_bo **bo);
1510 VkResult anv_device_import_bo_from_host_ptr(struct anv_device *device,
1511 void *host_ptr, uint32_t size,
1512 enum anv_bo_alloc_flags alloc_flags,
1513 uint64_t client_address,
1514 struct anv_bo **bo_out);
1515 VkResult anv_device_import_bo(struct anv_device *device, int fd,
1516 enum anv_bo_alloc_flags alloc_flags,
1517 uint64_t client_address,
1518 struct anv_bo **bo);
1519 VkResult anv_device_export_bo(struct anv_device *device,
1520 struct anv_bo *bo, int *fd_out);
1521 void anv_device_release_bo(struct anv_device *device,
1522 struct anv_bo *bo);
1523
1524 static inline struct anv_bo *
1525 anv_device_lookup_bo(struct anv_device *device, uint32_t gem_handle)
1526 {
1527 return util_sparse_array_get(&device->bo_cache.bo_map, gem_handle);
1528 }
1529
1530 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1531 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1532 int64_t timeout);
1533
1534 VkResult anv_queue_init(struct anv_device *device, struct anv_queue *queue);
1535 void anv_queue_finish(struct anv_queue *queue);
1536
1537 VkResult anv_queue_execbuf_locked(struct anv_queue *queue, struct anv_queue_submit *submit);
1538 VkResult anv_queue_submit_simple_batch(struct anv_queue *queue,
1539 struct anv_batch *batch);
1540
1541 uint64_t anv_gettime_ns(void);
1542 uint64_t anv_get_absolute_timeout(uint64_t timeout);
1543
1544 void* anv_gem_mmap(struct anv_device *device,
1545 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1546 void anv_gem_munmap(struct anv_device *device, void *p, uint64_t size);
1547 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1548 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1549 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1550 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1551 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1552 int anv_gem_execbuffer(struct anv_device *device,
1553 struct drm_i915_gem_execbuffer2 *execbuf);
1554 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1555 uint32_t stride, uint32_t tiling);
1556 int anv_gem_create_context(struct anv_device *device);
1557 bool anv_gem_has_context_priority(int fd);
1558 int anv_gem_destroy_context(struct anv_device *device, int context);
1559 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1560 uint64_t value);
1561 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1562 uint64_t *value);
1563 int anv_gem_get_param(int fd, uint32_t param);
1564 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1565 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1566 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1567 uint32_t *active, uint32_t *pending);
1568 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1569 int anv_gem_reg_read(int fd, uint32_t offset, uint64_t *result);
1570 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1571 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1572 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1573 uint32_t read_domains, uint32_t write_domain);
1574 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1575 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1576 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1577 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1578 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1579 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1580 uint32_t handle);
1581 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1582 uint32_t handle, int fd);
1583 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1584 bool anv_gem_supports_syncobj_wait(int fd);
1585 int anv_gem_syncobj_wait(struct anv_device *device,
1586 uint32_t *handles, uint32_t num_handles,
1587 int64_t abs_timeout_ns, bool wait_all);
1588
1589 uint64_t anv_vma_alloc(struct anv_device *device,
1590 uint64_t size, uint64_t align,
1591 enum anv_bo_alloc_flags alloc_flags,
1592 uint64_t client_address);
1593 void anv_vma_free(struct anv_device *device,
1594 uint64_t address, uint64_t size);
1595
1596 struct anv_reloc_list {
1597 uint32_t num_relocs;
1598 uint32_t array_length;
1599 struct drm_i915_gem_relocation_entry * relocs;
1600 struct anv_bo ** reloc_bos;
1601 uint32_t dep_words;
1602 BITSET_WORD * deps;
1603 };
1604
1605 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1606 const VkAllocationCallbacks *alloc);
1607 void anv_reloc_list_finish(struct anv_reloc_list *list,
1608 const VkAllocationCallbacks *alloc);
1609
1610 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1611 const VkAllocationCallbacks *alloc,
1612 uint32_t offset, struct anv_bo *target_bo,
1613 uint32_t delta, uint64_t *address_u64_out);
1614
1615 struct anv_batch_bo {
1616 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1617 struct list_head link;
1618
1619 struct anv_bo * bo;
1620
1621 /* Bytes actually consumed in this batch BO */
1622 uint32_t length;
1623
1624 struct anv_reloc_list relocs;
1625 };
1626
1627 struct anv_batch {
1628 const VkAllocationCallbacks * alloc;
1629
1630 struct anv_address start_addr;
1631
1632 void * start;
1633 void * end;
1634 void * next;
1635
1636 struct anv_reloc_list * relocs;
1637
1638 /* This callback is called (with the associated user data) in the event
1639 * that the batch runs out of space.
1640 */
1641 VkResult (*extend_cb)(struct anv_batch *, void *);
1642 void * user_data;
1643
1644 /**
1645 * Current error status of the command buffer. Used to track inconsistent
1646 * or incomplete command buffer states that are the consequence of run-time
1647 * errors such as out of memory scenarios. We want to track this in the
1648 * batch because the command buffer object is not visible to some parts
1649 * of the driver.
1650 */
1651 VkResult status;
1652 };
1653
1654 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1655 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1656 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1657 void *location, struct anv_bo *bo, uint32_t offset);
1658 struct anv_address anv_batch_address(struct anv_batch *batch, void *batch_location);
1659
1660 static inline void
1661 anv_batch_set_storage(struct anv_batch *batch, struct anv_address addr,
1662 void *map, size_t size)
1663 {
1664 batch->start_addr = addr;
1665 batch->next = batch->start = map;
1666 batch->end = map + size;
1667 }
1668
1669 static inline VkResult
1670 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1671 {
1672 assert(error != VK_SUCCESS);
1673 if (batch->status == VK_SUCCESS)
1674 batch->status = error;
1675 return batch->status;
1676 }
1677
1678 static inline bool
1679 anv_batch_has_error(struct anv_batch *batch)
1680 {
1681 return batch->status != VK_SUCCESS;
1682 }
1683
1684 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1685
1686 static inline bool
1687 anv_address_is_null(struct anv_address addr)
1688 {
1689 return addr.bo == NULL && addr.offset == 0;
1690 }
1691
1692 static inline uint64_t
1693 anv_address_physical(struct anv_address addr)
1694 {
1695 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1696 return gen_canonical_address(addr.bo->offset + addr.offset);
1697 else
1698 return gen_canonical_address(addr.offset);
1699 }
1700
1701 static inline struct anv_address
1702 anv_address_add(struct anv_address addr, uint64_t offset)
1703 {
1704 addr.offset += offset;
1705 return addr;
1706 }
1707
1708 static inline void
1709 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1710 {
1711 unsigned reloc_size = 0;
1712 if (device->info.gen >= 8) {
1713 reloc_size = sizeof(uint64_t);
1714 *(uint64_t *)p = gen_canonical_address(v);
1715 } else {
1716 reloc_size = sizeof(uint32_t);
1717 *(uint32_t *)p = v;
1718 }
1719
1720 if (flush && !device->info.has_llc)
1721 gen_flush_range(p, reloc_size);
1722 }
1723
1724 static inline uint64_t
1725 _anv_combine_address(struct anv_batch *batch, void *location,
1726 const struct anv_address address, uint32_t delta)
1727 {
1728 if (address.bo == NULL) {
1729 return address.offset + delta;
1730 } else {
1731 assert(batch->start <= location && location < batch->end);
1732
1733 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1734 }
1735 }
1736
1737 #define __gen_address_type struct anv_address
1738 #define __gen_user_data struct anv_batch
1739 #define __gen_combine_address _anv_combine_address
1740
1741 /* Wrapper macros needed to work around preprocessor argument issues. In
1742 * particular, arguments don't get pre-evaluated if they are concatenated.
1743 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1744 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1745 * We can work around this easily enough with these helpers.
1746 */
1747 #define __anv_cmd_length(cmd) cmd ## _length
1748 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1749 #define __anv_cmd_header(cmd) cmd ## _header
1750 #define __anv_cmd_pack(cmd) cmd ## _pack
1751 #define __anv_reg_num(reg) reg ## _num
1752
1753 #define anv_pack_struct(dst, struc, ...) do { \
1754 struct struc __template = { \
1755 __VA_ARGS__ \
1756 }; \
1757 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1758 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1759 } while (0)
1760
1761 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1762 void *__dst = anv_batch_emit_dwords(batch, n); \
1763 if (__dst) { \
1764 struct cmd __template = { \
1765 __anv_cmd_header(cmd), \
1766 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1767 __VA_ARGS__ \
1768 }; \
1769 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1770 } \
1771 __dst; \
1772 })
1773
1774 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1775 do { \
1776 uint32_t *dw; \
1777 \
1778 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1779 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1780 if (!dw) \
1781 break; \
1782 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1783 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1784 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1785 } while (0)
1786
1787 #define anv_batch_emit(batch, cmd, name) \
1788 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1789 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1790 __builtin_expect(_dst != NULL, 1); \
1791 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1792 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1793 _dst = NULL; \
1794 }))
1795
1796 /* #define __gen_get_batch_dwords anv_batch_emit_dwords */
1797 /* #define __gen_get_batch_address anv_batch_address */
1798 /* #define __gen_address_value anv_address_physical */
1799 /* #define __gen_address_offset anv_address_add */
1800
1801 struct anv_device_memory {
1802 struct vk_object_base base;
1803
1804 struct list_head link;
1805
1806 struct anv_bo * bo;
1807 struct anv_memory_type * type;
1808 VkDeviceSize map_size;
1809 void * map;
1810
1811 /* If set, we are holding reference to AHardwareBuffer
1812 * which we must release when memory is freed.
1813 */
1814 struct AHardwareBuffer * ahw;
1815
1816 /* If set, this memory comes from a host pointer. */
1817 void * host_ptr;
1818 };
1819
1820 /**
1821 * Header for Vertex URB Entry (VUE)
1822 */
1823 struct anv_vue_header {
1824 uint32_t Reserved;
1825 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1826 uint32_t ViewportIndex;
1827 float PointWidth;
1828 };
1829
1830 /** Struct representing a sampled image descriptor
1831 *
1832 * This descriptor layout is used for sampled images, bare sampler, and
1833 * combined image/sampler descriptors.
1834 */
1835 struct anv_sampled_image_descriptor {
1836 /** Bindless image handle
1837 *
1838 * This is expected to already be shifted such that the 20-bit
1839 * SURFACE_STATE table index is in the top 20 bits.
1840 */
1841 uint32_t image;
1842
1843 /** Bindless sampler handle
1844 *
1845 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1846 * to the dynamic state base address.
1847 */
1848 uint32_t sampler;
1849 };
1850
1851 struct anv_texture_swizzle_descriptor {
1852 /** Texture swizzle
1853 *
1854 * See also nir_intrinsic_channel_select_intel
1855 */
1856 uint8_t swizzle[4];
1857
1858 /** Unused padding to ensure the struct is a multiple of 64 bits */
1859 uint32_t _pad;
1860 };
1861
1862 /** Struct representing a storage image descriptor */
1863 struct anv_storage_image_descriptor {
1864 /** Bindless image handles
1865 *
1866 * These are expected to already be shifted such that the 20-bit
1867 * SURFACE_STATE table index is in the top 20 bits.
1868 */
1869 uint32_t read_write;
1870 uint32_t write_only;
1871 };
1872
1873 /** Struct representing a address/range descriptor
1874 *
1875 * The fields of this struct correspond directly to the data layout of
1876 * nir_address_format_64bit_bounded_global addresses. The last field is the
1877 * offset in the NIR address so it must be zero so that when you load the
1878 * descriptor you get a pointer to the start of the range.
1879 */
1880 struct anv_address_range_descriptor {
1881 uint64_t address;
1882 uint32_t range;
1883 uint32_t zero;
1884 };
1885
1886 enum anv_descriptor_data {
1887 /** The descriptor contains a BTI reference to a surface state */
1888 ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0),
1889 /** The descriptor contains a BTI reference to a sampler state */
1890 ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1),
1891 /** The descriptor contains an actual buffer view */
1892 ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2),
1893 /** The descriptor contains auxiliary image layout data */
1894 ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3),
1895 /** The descriptor contains auxiliary image layout data */
1896 ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4),
1897 /** anv_address_range_descriptor with a buffer address and range */
1898 ANV_DESCRIPTOR_ADDRESS_RANGE = (1 << 5),
1899 /** Bindless surface handle */
1900 ANV_DESCRIPTOR_SAMPLED_IMAGE = (1 << 6),
1901 /** Storage image handles */
1902 ANV_DESCRIPTOR_STORAGE_IMAGE = (1 << 7),
1903 /** Storage image handles */
1904 ANV_DESCRIPTOR_TEXTURE_SWIZZLE = (1 << 8),
1905 };
1906
1907 struct anv_descriptor_set_binding_layout {
1908 #ifndef NDEBUG
1909 /* The type of the descriptors in this binding */
1910 VkDescriptorType type;
1911 #endif
1912
1913 /* Flags provided when this binding was created */
1914 VkDescriptorBindingFlagsEXT flags;
1915
1916 /* Bitfield representing the type of data this descriptor contains */
1917 enum anv_descriptor_data data;
1918
1919 /* Maximum number of YCbCr texture/sampler planes */
1920 uint8_t max_plane_count;
1921
1922 /* Number of array elements in this binding (or size in bytes for inline
1923 * uniform data)
1924 */
1925 uint16_t array_size;
1926
1927 /* Index into the flattend descriptor set */
1928 uint16_t descriptor_index;
1929
1930 /* Index into the dynamic state array for a dynamic buffer */
1931 int16_t dynamic_offset_index;
1932
1933 /* Index into the descriptor set buffer views */
1934 int16_t buffer_view_index;
1935
1936 /* Offset into the descriptor buffer where this descriptor lives */
1937 uint32_t descriptor_offset;
1938
1939 /* Immutable samplers (or NULL if no immutable samplers) */
1940 struct anv_sampler **immutable_samplers;
1941 };
1942
1943 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout);
1944
1945 unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice,
1946 VkDescriptorType type);
1947
1948 bool anv_descriptor_supports_bindless(const struct anv_physical_device *pdevice,
1949 const struct anv_descriptor_set_binding_layout *binding,
1950 bool sampler);
1951
1952 bool anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice,
1953 const struct anv_descriptor_set_binding_layout *binding,
1954 bool sampler);
1955
1956 struct anv_descriptor_set_layout {
1957 struct vk_object_base base;
1958
1959 /* Descriptor set layouts can be destroyed at almost any time */
1960 uint32_t ref_cnt;
1961
1962 /* Number of bindings in this descriptor set */
1963 uint16_t binding_count;
1964
1965 /* Total size of the descriptor set with room for all array entries */
1966 uint16_t size;
1967
1968 /* Shader stages affected by this descriptor set */
1969 uint16_t shader_stages;
1970
1971 /* Number of buffer views in this descriptor set */
1972 uint16_t buffer_view_count;
1973
1974 /* Number of dynamic offsets used by this descriptor set */
1975 uint16_t dynamic_offset_count;
1976
1977 /* For each shader stage, which offsets apply to that stage */
1978 uint16_t stage_dynamic_offsets[MESA_SHADER_STAGES];
1979
1980 /* Size of the descriptor buffer for this descriptor set */
1981 uint32_t descriptor_buffer_size;
1982
1983 /* Bindings in this descriptor set */
1984 struct anv_descriptor_set_binding_layout binding[0];
1985 };
1986
1987 void anv_descriptor_set_layout_destroy(struct anv_device *device,
1988 struct anv_descriptor_set_layout *layout);
1989
1990 static inline void
1991 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1992 {
1993 assert(layout && layout->ref_cnt >= 1);
1994 p_atomic_inc(&layout->ref_cnt);
1995 }
1996
1997 static inline void
1998 anv_descriptor_set_layout_unref(struct anv_device *device,
1999 struct anv_descriptor_set_layout *layout)
2000 {
2001 assert(layout && layout->ref_cnt >= 1);
2002 if (p_atomic_dec_zero(&layout->ref_cnt))
2003 anv_descriptor_set_layout_destroy(device, layout);
2004 }
2005
2006 struct anv_descriptor {
2007 VkDescriptorType type;
2008
2009 union {
2010 struct {
2011 VkImageLayout layout;
2012 struct anv_image_view *image_view;
2013 struct anv_sampler *sampler;
2014 };
2015
2016 struct {
2017 struct anv_buffer *buffer;
2018 uint64_t offset;
2019 uint64_t range;
2020 };
2021
2022 struct anv_buffer_view *buffer_view;
2023 };
2024 };
2025
2026 struct anv_descriptor_set {
2027 struct vk_object_base base;
2028
2029 struct anv_descriptor_pool *pool;
2030 struct anv_descriptor_set_layout *layout;
2031
2032 /* Amount of space occupied in the the pool by this descriptor set. It can
2033 * be larger than the size of the descriptor set.
2034 */
2035 uint32_t size;
2036
2037 /* State relative to anv_descriptor_pool::bo */
2038 struct anv_state desc_mem;
2039 /* Surface state for the descriptor buffer */
2040 struct anv_state desc_surface_state;
2041
2042 uint32_t buffer_view_count;
2043 struct anv_buffer_view *buffer_views;
2044
2045 /* Link to descriptor pool's desc_sets list . */
2046 struct list_head pool_link;
2047
2048 struct anv_descriptor descriptors[0];
2049 };
2050
2051 struct anv_buffer_view {
2052 struct vk_object_base base;
2053
2054 enum isl_format format; /**< VkBufferViewCreateInfo::format */
2055 uint64_t range; /**< VkBufferViewCreateInfo::range */
2056
2057 struct anv_address address;
2058
2059 struct anv_state surface_state;
2060 struct anv_state storage_surface_state;
2061 struct anv_state writeonly_storage_surface_state;
2062
2063 struct brw_image_param storage_image_param;
2064 };
2065
2066 struct anv_push_descriptor_set {
2067 struct anv_descriptor_set set;
2068
2069 /* Put this field right behind anv_descriptor_set so it fills up the
2070 * descriptors[0] field. */
2071 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
2072
2073 /** True if the descriptor set buffer has been referenced by a draw or
2074 * dispatch command.
2075 */
2076 bool set_used_on_gpu;
2077
2078 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
2079 };
2080
2081 struct anv_descriptor_pool {
2082 struct vk_object_base base;
2083
2084 uint32_t size;
2085 uint32_t next;
2086 uint32_t free_list;
2087
2088 struct anv_bo *bo;
2089 struct util_vma_heap bo_heap;
2090
2091 struct anv_state_stream surface_state_stream;
2092 void *surface_state_free_list;
2093
2094 struct list_head desc_sets;
2095
2096 char data[0];
2097 };
2098
2099 enum anv_descriptor_template_entry_type {
2100 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
2101 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
2102 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2103 };
2104
2105 struct anv_descriptor_template_entry {
2106 /* The type of descriptor in this entry */
2107 VkDescriptorType type;
2108
2109 /* Binding in the descriptor set */
2110 uint32_t binding;
2111
2112 /* Offset at which to write into the descriptor set binding */
2113 uint32_t array_element;
2114
2115 /* Number of elements to write into the descriptor set binding */
2116 uint32_t array_count;
2117
2118 /* Offset into the user provided data */
2119 size_t offset;
2120
2121 /* Stride between elements into the user provided data */
2122 size_t stride;
2123 };
2124
2125 struct anv_descriptor_update_template {
2126 struct vk_object_base base;
2127
2128 VkPipelineBindPoint bind_point;
2129
2130 /* The descriptor set this template corresponds to. This value is only
2131 * valid if the template was created with the templateType
2132 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2133 */
2134 uint8_t set;
2135
2136 /* Number of entries in this template */
2137 uint32_t entry_count;
2138
2139 /* Entries of the template */
2140 struct anv_descriptor_template_entry entries[0];
2141 };
2142
2143 size_t
2144 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
2145
2146 void
2147 anv_descriptor_set_write_image_view(struct anv_device *device,
2148 struct anv_descriptor_set *set,
2149 const VkDescriptorImageInfo * const info,
2150 VkDescriptorType type,
2151 uint32_t binding,
2152 uint32_t element);
2153
2154 void
2155 anv_descriptor_set_write_buffer_view(struct anv_device *device,
2156 struct anv_descriptor_set *set,
2157 VkDescriptorType type,
2158 struct anv_buffer_view *buffer_view,
2159 uint32_t binding,
2160 uint32_t element);
2161
2162 void
2163 anv_descriptor_set_write_buffer(struct anv_device *device,
2164 struct anv_descriptor_set *set,
2165 struct anv_state_stream *alloc_stream,
2166 VkDescriptorType type,
2167 struct anv_buffer *buffer,
2168 uint32_t binding,
2169 uint32_t element,
2170 VkDeviceSize offset,
2171 VkDeviceSize range);
2172 void
2173 anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
2174 struct anv_descriptor_set *set,
2175 uint32_t binding,
2176 const void *data,
2177 size_t offset,
2178 size_t size);
2179
2180 void
2181 anv_descriptor_set_write_template(struct anv_device *device,
2182 struct anv_descriptor_set *set,
2183 struct anv_state_stream *alloc_stream,
2184 const struct anv_descriptor_update_template *template,
2185 const void *data);
2186
2187 VkResult
2188 anv_descriptor_set_create(struct anv_device *device,
2189 struct anv_descriptor_pool *pool,
2190 struct anv_descriptor_set_layout *layout,
2191 struct anv_descriptor_set **out_set);
2192
2193 void
2194 anv_descriptor_set_destroy(struct anv_device *device,
2195 struct anv_descriptor_pool *pool,
2196 struct anv_descriptor_set *set);
2197
2198 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2199 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2200 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2201 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2202 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2203 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2204
2205 struct anv_pipeline_binding {
2206 /** Index in the descriptor set
2207 *
2208 * This is a flattened index; the descriptor set layout is already taken
2209 * into account.
2210 */
2211 uint32_t index;
2212
2213 /** The descriptor set this surface corresponds to.
2214 *
2215 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2216 * binding is not a normal descriptor set but something else.
2217 */
2218 uint8_t set;
2219
2220 union {
2221 /** Plane in the binding index for images */
2222 uint8_t plane;
2223
2224 /** Input attachment index (relative to the subpass) */
2225 uint8_t input_attachment_index;
2226
2227 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2228 uint8_t dynamic_offset_index;
2229 };
2230
2231 /** For a storage image, whether it is write-only */
2232 uint8_t write_only;
2233
2234 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2235 * assuming POD zero-initialization.
2236 */
2237 uint8_t pad;
2238 };
2239
2240 struct anv_push_range {
2241 /** Index in the descriptor set */
2242 uint32_t index;
2243
2244 /** Descriptor set index */
2245 uint8_t set;
2246
2247 /** Dynamic offset index (for dynamic UBOs) */
2248 uint8_t dynamic_offset_index;
2249
2250 /** Start offset in units of 32B */
2251 uint8_t start;
2252
2253 /** Range in units of 32B */
2254 uint8_t length;
2255 };
2256
2257 struct anv_pipeline_layout {
2258 struct vk_object_base base;
2259
2260 struct {
2261 struct anv_descriptor_set_layout *layout;
2262 uint32_t dynamic_offset_start;
2263 } set[MAX_SETS];
2264
2265 uint32_t num_sets;
2266
2267 unsigned char sha1[20];
2268 };
2269
2270 struct anv_buffer {
2271 struct vk_object_base base;
2272
2273 struct anv_device * device;
2274 VkDeviceSize size;
2275
2276 VkBufferUsageFlags usage;
2277
2278 /* Set when bound */
2279 struct anv_address address;
2280 };
2281
2282 static inline uint64_t
2283 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
2284 {
2285 assert(offset <= buffer->size);
2286 if (range == VK_WHOLE_SIZE) {
2287 return buffer->size - offset;
2288 } else {
2289 assert(range + offset >= range);
2290 assert(range + offset <= buffer->size);
2291 return range;
2292 }
2293 }
2294
2295 enum anv_cmd_dirty_bits {
2296 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2297 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2298 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2299 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2300 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2301 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2302 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2303 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2304 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2305 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
2306 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
2307 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
2308 ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
2309 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2310 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 14, /* VK_DYNAMIC_STATE_CULL_MODE_EXT */
2311 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 15, /* VK_DYNAMIC_STATE_FRONT_FACE_EXT */
2312 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 16, /* VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT */
2313 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 17, /* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT */
2314 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 18, /* VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT */
2315 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 19, /* VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT */
2316 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 20, /* VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT */
2317 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 21, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT */
2318 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 22, /* VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT */
2319 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 23, /* VK_DYNAMIC_STATE_STENCIL_OP_EXT */
2320 };
2321 typedef uint32_t anv_cmd_dirty_mask_t;
2322
2323 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2324 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2325 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2326 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2327 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2328 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2329 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2330 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2331 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2332 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2333 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE | \
2334 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE | \
2335 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE | \
2336 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | \
2337 ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE | \
2338 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE | \
2339 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE | \
2340 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP | \
2341 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE | \
2342 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE | \
2343 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)
2344
2345 static inline enum anv_cmd_dirty_bits
2346 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
2347 {
2348 switch (vk_state) {
2349 case VK_DYNAMIC_STATE_VIEWPORT:
2350 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
2351 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2352 case VK_DYNAMIC_STATE_SCISSOR:
2353 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
2354 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
2355 case VK_DYNAMIC_STATE_LINE_WIDTH:
2356 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2357 case VK_DYNAMIC_STATE_DEPTH_BIAS:
2358 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2359 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
2360 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2361 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
2362 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2363 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
2364 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2365 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
2366 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2367 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2368 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2369 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
2370 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
2371 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
2372 return ANV_CMD_DIRTY_DYNAMIC_CULL_MODE;
2373 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
2374 return ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
2375 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
2376 return ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
2377 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
2378 return ANV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
2379 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
2380 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE;
2381 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
2382 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE;
2383 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
2384 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP;
2385 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
2386 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
2387 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
2388 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
2389 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
2390 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP;
2391 default:
2392 assert(!"Unsupported dynamic state");
2393 return 0;
2394 }
2395 }
2396
2397
2398 enum anv_pipe_bits {
2399 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
2400 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
2401 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
2402 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
2403 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
2404 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
2405 ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
2406 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
2407 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
2408 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
2409 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
2410 ANV_PIPE_CS_STALL_BIT = (1 << 20),
2411 ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
2412
2413 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2414 * a flush has happened but not a CS stall. The next time we do any sort
2415 * of invalidation we need to insert a CS stall at that time. Otherwise,
2416 * we would have to CS stall on every flush which could be bad.
2417 */
2418 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT = (1 << 22),
2419
2420 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2421 * target operations related to transfer commands with VkBuffer as
2422 * destination are ongoing. Some operations like copies on the command
2423 * streamer might need to be aware of this to trigger the appropriate stall
2424 * before they can proceed with the copy.
2425 */
2426 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 23),
2427
2428 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2429 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2430 * done by writing the AUX-TT register.
2431 */
2432 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 24),
2433
2434 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2435 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2436 * implement a workaround for Gen9.
2437 */
2438 ANV_PIPE_POST_SYNC_BIT = (1 << 25),
2439 };
2440
2441 #define ANV_PIPE_FLUSH_BITS ( \
2442 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2443 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2444 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2445 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2446
2447 #define ANV_PIPE_STALL_BITS ( \
2448 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2449 ANV_PIPE_DEPTH_STALL_BIT | \
2450 ANV_PIPE_CS_STALL_BIT)
2451
2452 #define ANV_PIPE_INVALIDATE_BITS ( \
2453 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2454 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2455 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2456 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2457 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2458 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2459 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2460
2461 static inline enum anv_pipe_bits
2462 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
2463 {
2464 enum anv_pipe_bits pipe_bits = 0;
2465
2466 unsigned b;
2467 for_each_bit(b, flags) {
2468 switch ((VkAccessFlagBits)(1 << b)) {
2469 case VK_ACCESS_SHADER_WRITE_BIT:
2470 /* We're transitioning a buffer that was previously used as write
2471 * destination through the data port. To make its content available
2472 * to future operations, flush the data cache.
2473 */
2474 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2475 break;
2476 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2477 /* We're transitioning a buffer that was previously used as render
2478 * target. To make its content available to future operations, flush
2479 * the render target cache.
2480 */
2481 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2482 break;
2483 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2484 /* We're transitioning a buffer that was previously used as depth
2485 * buffer. To make its content available to future operations, flush
2486 * the depth cache.
2487 */
2488 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2489 break;
2490 case VK_ACCESS_TRANSFER_WRITE_BIT:
2491 /* We're transitioning a buffer that was previously used as a
2492 * transfer write destination. Generic write operations include color
2493 * & depth operations as well as buffer operations like :
2494 * - vkCmdClearColorImage()
2495 * - vkCmdClearDepthStencilImage()
2496 * - vkCmdBlitImage()
2497 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2498 *
2499 * Most of these operations are implemented using Blorp which writes
2500 * through the render target, so flush that cache to make it visible
2501 * to future operations. And for depth related operations we also
2502 * need to flush the depth cache.
2503 */
2504 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2505 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2506 break;
2507 case VK_ACCESS_MEMORY_WRITE_BIT:
2508 /* We're transitioning a buffer for generic write operations. Flush
2509 * all the caches.
2510 */
2511 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2512 break;
2513 default:
2514 break; /* Nothing to do */
2515 }
2516 }
2517
2518 return pipe_bits;
2519 }
2520
2521 static inline enum anv_pipe_bits
2522 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
2523 {
2524 enum anv_pipe_bits pipe_bits = 0;
2525
2526 unsigned b;
2527 for_each_bit(b, flags) {
2528 switch ((VkAccessFlagBits)(1 << b)) {
2529 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2530 /* Indirect draw commands take a buffer as input that we're going to
2531 * read from the command streamer to load some of the HW registers
2532 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2533 * command streamer stall so that all the cache flushes have
2534 * completed before the command streamer loads from memory.
2535 */
2536 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2537 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2538 * through a vertex buffer, so invalidate that cache.
2539 */
2540 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2541 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2542 * UBO from the buffer, so we need to invalidate constant cache.
2543 */
2544 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2545 break;
2546 case VK_ACCESS_INDEX_READ_BIT:
2547 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2548 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2549 * commands, so we invalidate the VF cache to make sure there is no
2550 * stale data when we start rendering.
2551 */
2552 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2553 break;
2554 case VK_ACCESS_UNIFORM_READ_BIT:
2555 /* We transitioning a buffer to be used as uniform data. Because
2556 * uniform is accessed through the data port & sampler, we need to
2557 * invalidate the texture cache (sampler) & constant cache (data
2558 * port) to avoid stale data.
2559 */
2560 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2561 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2562 break;
2563 case VK_ACCESS_SHADER_READ_BIT:
2564 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2565 case VK_ACCESS_TRANSFER_READ_BIT:
2566 /* Transitioning a buffer to be read through the sampler, so
2567 * invalidate the texture cache, we don't want any stale data.
2568 */
2569 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2570 break;
2571 case VK_ACCESS_MEMORY_READ_BIT:
2572 /* Transitioning a buffer for generic read, invalidate all the
2573 * caches.
2574 */
2575 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
2576 break;
2577 case VK_ACCESS_MEMORY_WRITE_BIT:
2578 /* Generic write, make sure all previously written things land in
2579 * memory.
2580 */
2581 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2582 break;
2583 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
2584 /* Transitioning a buffer for conditional rendering. We'll load the
2585 * content of this buffer into HW registers using the command
2586 * streamer, so we need to stall the command streamer to make sure
2587 * any in-flight flush operations have completed.
2588 */
2589 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2590 break;
2591 default:
2592 break; /* Nothing to do */
2593 }
2594 }
2595
2596 return pipe_bits;
2597 }
2598
2599 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2600 VK_IMAGE_ASPECT_COLOR_BIT | \
2601 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2602 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2603 VK_IMAGE_ASPECT_PLANE_2_BIT)
2604 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2605 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2606 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2607 VK_IMAGE_ASPECT_PLANE_2_BIT)
2608
2609 struct anv_vertex_binding {
2610 struct anv_buffer * buffer;
2611 VkDeviceSize offset;
2612 VkDeviceSize stride;
2613 VkDeviceSize size;
2614 };
2615
2616 struct anv_xfb_binding {
2617 struct anv_buffer * buffer;
2618 VkDeviceSize offset;
2619 VkDeviceSize size;
2620 };
2621
2622 struct anv_push_constants {
2623 /** Push constant data provided by the client through vkPushConstants */
2624 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
2625
2626 /** Dynamic offsets for dynamic UBOs and SSBOs */
2627 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2628
2629 uint64_t push_reg_mask;
2630
2631 /** Pad out to a multiple of 32 bytes */
2632 uint32_t pad[2];
2633
2634 struct {
2635 /** Base workgroup ID
2636 *
2637 * Used for vkCmdDispatchBase.
2638 */
2639 uint32_t base_work_group_id[3];
2640
2641 /** Subgroup ID
2642 *
2643 * This is never set by software but is implicitly filled out when
2644 * uploading the push constants for compute shaders.
2645 */
2646 uint32_t subgroup_id;
2647 } cs;
2648 };
2649
2650 struct anv_dynamic_state {
2651 struct {
2652 uint32_t count;
2653 VkViewport viewports[MAX_VIEWPORTS];
2654 } viewport;
2655
2656 struct {
2657 uint32_t count;
2658 VkRect2D scissors[MAX_SCISSORS];
2659 } scissor;
2660
2661 float line_width;
2662
2663 struct {
2664 float bias;
2665 float clamp;
2666 float slope;
2667 } depth_bias;
2668
2669 float blend_constants[4];
2670
2671 struct {
2672 float min;
2673 float max;
2674 } depth_bounds;
2675
2676 struct {
2677 uint32_t front;
2678 uint32_t back;
2679 } stencil_compare_mask;
2680
2681 struct {
2682 uint32_t front;
2683 uint32_t back;
2684 } stencil_write_mask;
2685
2686 struct {
2687 uint32_t front;
2688 uint32_t back;
2689 } stencil_reference;
2690
2691 struct {
2692 struct {
2693 VkStencilOp fail_op;
2694 VkStencilOp pass_op;
2695 VkStencilOp depth_fail_op;
2696 VkCompareOp compare_op;
2697 } front;
2698 struct {
2699 VkStencilOp fail_op;
2700 VkStencilOp pass_op;
2701 VkStencilOp depth_fail_op;
2702 VkCompareOp compare_op;
2703 } back;
2704 } stencil_op;
2705
2706 struct {
2707 uint32_t factor;
2708 uint16_t pattern;
2709 } line_stipple;
2710
2711 VkCullModeFlags cull_mode;
2712 VkFrontFace front_face;
2713 VkPrimitiveTopology primitive_topology;
2714 bool depth_test_enable;
2715 bool depth_write_enable;
2716 VkCompareOp depth_compare_op;
2717 bool depth_bounds_test_enable;
2718 bool stencil_test_enable;
2719 bool dyn_vbo_stride;
2720 bool dyn_vbo_size;
2721 };
2722
2723 extern const struct anv_dynamic_state default_dynamic_state;
2724
2725 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state *dest,
2726 const struct anv_dynamic_state *src,
2727 uint32_t copy_mask);
2728
2729 struct anv_surface_state {
2730 struct anv_state state;
2731 /** Address of the surface referred to by this state
2732 *
2733 * This address is relative to the start of the BO.
2734 */
2735 struct anv_address address;
2736 /* Address of the aux surface, if any
2737 *
2738 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2739 *
2740 * With the exception of gen8, the bottom 12 bits of this address' offset
2741 * include extra aux information.
2742 */
2743 struct anv_address aux_address;
2744 /* Address of the clear color, if any
2745 *
2746 * This address is relative to the start of the BO.
2747 */
2748 struct anv_address clear_address;
2749 };
2750
2751 /**
2752 * Attachment state when recording a renderpass instance.
2753 *
2754 * The clear value is valid only if there exists a pending clear.
2755 */
2756 struct anv_attachment_state {
2757 enum isl_aux_usage aux_usage;
2758 struct anv_surface_state color;
2759 struct anv_surface_state input;
2760
2761 VkImageLayout current_layout;
2762 VkImageLayout current_stencil_layout;
2763 VkImageAspectFlags pending_clear_aspects;
2764 VkImageAspectFlags pending_load_aspects;
2765 bool fast_clear;
2766 VkClearValue clear_value;
2767
2768 /* When multiview is active, attachments with a renderpass clear
2769 * operation have their respective layers cleared on the first
2770 * subpass that uses them, and only in that subpass. We keep track
2771 * of this using a bitfield to indicate which layers of an attachment
2772 * have not been cleared yet when multiview is active.
2773 */
2774 uint32_t pending_clear_views;
2775 struct anv_image_view * image_view;
2776 };
2777
2778 /** State tracking for vertex buffer flushes
2779 *
2780 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2781 * addresses. If you happen to have two vertex buffers which get placed
2782 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2783 * collisions. In order to solve this problem, we track vertex address ranges
2784 * which are live in the cache and invalidate the cache if one ever exceeds 32
2785 * bits.
2786 */
2787 struct anv_vb_cache_range {
2788 /* Virtual address at which the live vertex buffer cache range starts for
2789 * this vertex buffer index.
2790 */
2791 uint64_t start;
2792
2793 /* Virtual address of the byte after where vertex buffer cache range ends.
2794 * This is exclusive such that end - start is the size of the range.
2795 */
2796 uint64_t end;
2797 };
2798
2799 /** State tracking for particular pipeline bind point
2800 *
2801 * This struct is the base struct for anv_cmd_graphics_state and
2802 * anv_cmd_compute_state. These are used to track state which is bound to a
2803 * particular type of pipeline. Generic state that applies per-stage such as
2804 * binding table offsets and push constants is tracked generically with a
2805 * per-stage array in anv_cmd_state.
2806 */
2807 struct anv_cmd_pipeline_state {
2808 struct anv_descriptor_set *descriptors[MAX_SETS];
2809 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2810 };
2811
2812 /** State tracking for graphics pipeline
2813 *
2814 * This has anv_cmd_pipeline_state as a base struct to track things which get
2815 * bound to a graphics pipeline. Along with general pipeline bind point state
2816 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2817 * state which is graphics-specific.
2818 */
2819 struct anv_cmd_graphics_state {
2820 struct anv_cmd_pipeline_state base;
2821
2822 struct anv_graphics_pipeline *pipeline;
2823
2824 anv_cmd_dirty_mask_t dirty;
2825 uint32_t vb_dirty;
2826
2827 struct anv_vb_cache_range ib_bound_range;
2828 struct anv_vb_cache_range ib_dirty_range;
2829 struct anv_vb_cache_range vb_bound_ranges[33];
2830 struct anv_vb_cache_range vb_dirty_ranges[33];
2831
2832 VkShaderStageFlags push_constant_stages;
2833
2834 struct anv_dynamic_state dynamic;
2835
2836 uint32_t primitive_topology;
2837
2838 struct {
2839 struct anv_buffer *index_buffer;
2840 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2841 uint32_t index_offset;
2842 } gen7;
2843 };
2844
2845 /** State tracking for compute pipeline
2846 *
2847 * This has anv_cmd_pipeline_state as a base struct to track things which get
2848 * bound to a compute pipeline. Along with general pipeline bind point state
2849 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2850 * state which is compute-specific.
2851 */
2852 struct anv_cmd_compute_state {
2853 struct anv_cmd_pipeline_state base;
2854
2855 struct anv_compute_pipeline *pipeline;
2856
2857 bool pipeline_dirty;
2858
2859 struct anv_address num_workgroups;
2860 };
2861
2862 /** State required while building cmd buffer */
2863 struct anv_cmd_state {
2864 /* PIPELINE_SELECT.PipelineSelection */
2865 uint32_t current_pipeline;
2866 const struct gen_l3_config * current_l3_config;
2867 uint32_t last_aux_map_state;
2868
2869 struct anv_cmd_graphics_state gfx;
2870 struct anv_cmd_compute_state compute;
2871
2872 enum anv_pipe_bits pending_pipe_bits;
2873 VkShaderStageFlags descriptors_dirty;
2874 VkShaderStageFlags push_constants_dirty;
2875
2876 struct anv_framebuffer * framebuffer;
2877 struct anv_render_pass * pass;
2878 struct anv_subpass * subpass;
2879 VkRect2D render_area;
2880 uint32_t restart_index;
2881 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2882 bool xfb_enabled;
2883 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
2884 struct anv_push_constants push_constants[MESA_SHADER_STAGES];
2885 struct anv_state binding_tables[MESA_SHADER_STAGES];
2886 struct anv_state samplers[MESA_SHADER_STAGES];
2887
2888 unsigned char sampler_sha1s[MESA_SHADER_STAGES][20];
2889 unsigned char surface_sha1s[MESA_SHADER_STAGES][20];
2890 unsigned char push_sha1s[MESA_SHADER_STAGES][20];
2891
2892 /**
2893 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2894 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2895 * and before invoking the secondary in ExecuteCommands.
2896 */
2897 bool pma_fix_enabled;
2898
2899 /**
2900 * Whether or not we know for certain that HiZ is enabled for the current
2901 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2902 * enabled or not, this will be false.
2903 */
2904 bool hiz_enabled;
2905
2906 bool conditional_render_enabled;
2907
2908 /**
2909 * Last rendering scale argument provided to
2910 * genX(cmd_buffer_emit_hashing_mode)().
2911 */
2912 unsigned current_hash_scale;
2913
2914 /**
2915 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2916 * valid only when recording a render pass instance.
2917 */
2918 struct anv_attachment_state * attachments;
2919
2920 /**
2921 * Surface states for color render targets. These are stored in a single
2922 * flat array. For depth-stencil attachments, the surface state is simply
2923 * left blank.
2924 */
2925 struct anv_state attachment_states;
2926
2927 /**
2928 * A null surface state of the right size to match the framebuffer. This
2929 * is one of the states in attachment_states.
2930 */
2931 struct anv_state null_surface_state;
2932 };
2933
2934 struct anv_cmd_pool {
2935 struct vk_object_base base;
2936 VkAllocationCallbacks alloc;
2937 struct list_head cmd_buffers;
2938 };
2939
2940 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2941
2942 enum anv_cmd_buffer_exec_mode {
2943 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2944 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2945 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2946 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2947 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2948 ANV_CMD_BUFFER_EXEC_MODE_CALL_AND_RETURN,
2949 };
2950
2951 struct anv_cmd_buffer {
2952 struct vk_object_base base;
2953
2954 struct anv_device * device;
2955
2956 struct anv_cmd_pool * pool;
2957 struct list_head pool_link;
2958
2959 struct anv_batch batch;
2960
2961 /* Fields required for the actual chain of anv_batch_bo's.
2962 *
2963 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2964 */
2965 struct list_head batch_bos;
2966 enum anv_cmd_buffer_exec_mode exec_mode;
2967
2968 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2969 * referenced by this command buffer
2970 *
2971 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2972 */
2973 struct u_vector seen_bbos;
2974
2975 /* A vector of int32_t's for every block of binding tables.
2976 *
2977 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2978 */
2979 struct u_vector bt_block_states;
2980 struct anv_state bt_next;
2981
2982 struct anv_reloc_list surface_relocs;
2983 /** Last seen surface state block pool center bo offset */
2984 uint32_t last_ss_pool_center;
2985
2986 /* Serial for tracking buffer completion */
2987 uint32_t serial;
2988
2989 /* Stream objects for storing temporary data */
2990 struct anv_state_stream surface_state_stream;
2991 struct anv_state_stream dynamic_state_stream;
2992
2993 VkCommandBufferUsageFlags usage_flags;
2994 VkCommandBufferLevel level;
2995
2996 struct anv_query_pool *perf_query_pool;
2997
2998 struct anv_cmd_state state;
2999
3000 struct anv_address return_addr;
3001
3002 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
3003 uint64_t intel_perf_marker;
3004 };
3005
3006 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3007 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3008 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
3009 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
3010 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
3011 struct anv_cmd_buffer *secondary);
3012 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
3013 VkResult anv_cmd_buffer_execbuf(struct anv_queue *queue,
3014 struct anv_cmd_buffer *cmd_buffer,
3015 const VkSemaphore *in_semaphores,
3016 const uint64_t *in_wait_values,
3017 uint32_t num_in_semaphores,
3018 const VkSemaphore *out_semaphores,
3019 const uint64_t *out_signal_values,
3020 uint32_t num_out_semaphores,
3021 VkFence fence,
3022 int perf_query_pass);
3023
3024 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
3025
3026 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
3027 const void *data, uint32_t size, uint32_t alignment);
3028 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
3029 uint32_t *a, uint32_t *b,
3030 uint32_t dwords, uint32_t alignment);
3031
3032 struct anv_address
3033 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
3034 struct anv_state
3035 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
3036 uint32_t entries, uint32_t *state_offset);
3037 struct anv_state
3038 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
3039 struct anv_state
3040 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
3041 uint32_t size, uint32_t alignment);
3042
3043 VkResult
3044 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
3045
3046 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
3047 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
3048 bool depth_clamp_enable);
3049 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
3050
3051 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
3052 struct anv_render_pass *pass,
3053 struct anv_framebuffer *framebuffer,
3054 const VkClearValue *clear_values);
3055
3056 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
3057
3058 struct anv_state
3059 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
3060 gl_shader_stage stage);
3061 struct anv_state
3062 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
3063
3064 const struct anv_image_view *
3065 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
3066
3067 VkResult
3068 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
3069 uint32_t num_entries,
3070 uint32_t *state_offset,
3071 struct anv_state *bt_state);
3072
3073 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
3074
3075 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer);
3076
3077 enum anv_fence_type {
3078 ANV_FENCE_TYPE_NONE = 0,
3079 ANV_FENCE_TYPE_BO,
3080 ANV_FENCE_TYPE_WSI_BO,
3081 ANV_FENCE_TYPE_SYNCOBJ,
3082 ANV_FENCE_TYPE_WSI,
3083 };
3084
3085 enum anv_bo_fence_state {
3086 /** Indicates that this is a new (or newly reset fence) */
3087 ANV_BO_FENCE_STATE_RESET,
3088
3089 /** Indicates that this fence has been submitted to the GPU but is still
3090 * (as far as we know) in use by the GPU.
3091 */
3092 ANV_BO_FENCE_STATE_SUBMITTED,
3093
3094 ANV_BO_FENCE_STATE_SIGNALED,
3095 };
3096
3097 struct anv_fence_impl {
3098 enum anv_fence_type type;
3099
3100 union {
3101 /** Fence implementation for BO fences
3102 *
3103 * These fences use a BO and a set of CPU-tracked state flags. The BO
3104 * is added to the object list of the last execbuf call in a QueueSubmit
3105 * and is marked EXEC_WRITE. The state flags track when the BO has been
3106 * submitted to the kernel. We need to do this because Vulkan lets you
3107 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
3108 * will say it's idle in this case.
3109 */
3110 struct {
3111 struct anv_bo *bo;
3112 enum anv_bo_fence_state state;
3113 } bo;
3114
3115 /** DRM syncobj handle for syncobj-based fences */
3116 uint32_t syncobj;
3117
3118 /** WSI fence */
3119 struct wsi_fence *fence_wsi;
3120 };
3121 };
3122
3123 struct anv_fence {
3124 struct vk_object_base base;
3125
3126 /* Permanent fence state. Every fence has some form of permanent state
3127 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3128 * cross-process fences) or it could just be a dummy for use internally.
3129 */
3130 struct anv_fence_impl permanent;
3131
3132 /* Temporary fence state. A fence *may* have temporary state. That state
3133 * is added to the fence by an import operation and is reset back to
3134 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3135 * state cannot be signaled because the fence must already be signaled
3136 * before the temporary state can be exported from the fence in the other
3137 * process and imported here.
3138 */
3139 struct anv_fence_impl temporary;
3140 };
3141
3142 void anv_fence_reset_temporary(struct anv_device *device,
3143 struct anv_fence *fence);
3144
3145 struct anv_event {
3146 struct vk_object_base base;
3147 uint64_t semaphore;
3148 struct anv_state state;
3149 };
3150
3151 enum anv_semaphore_type {
3152 ANV_SEMAPHORE_TYPE_NONE = 0,
3153 ANV_SEMAPHORE_TYPE_DUMMY,
3154 ANV_SEMAPHORE_TYPE_BO,
3155 ANV_SEMAPHORE_TYPE_WSI_BO,
3156 ANV_SEMAPHORE_TYPE_SYNC_FILE,
3157 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
3158 ANV_SEMAPHORE_TYPE_TIMELINE,
3159 };
3160
3161 struct anv_timeline_point {
3162 struct list_head link;
3163
3164 uint64_t serial;
3165
3166 /* Number of waiter on this point, when > 0 the point should not be garbage
3167 * collected.
3168 */
3169 int waiting;
3170
3171 /* BO used for synchronization. */
3172 struct anv_bo *bo;
3173 };
3174
3175 struct anv_timeline {
3176 pthread_mutex_t mutex;
3177 pthread_cond_t cond;
3178
3179 uint64_t highest_past;
3180 uint64_t highest_pending;
3181
3182 struct list_head points;
3183 struct list_head free_points;
3184 };
3185
3186 struct anv_semaphore_impl {
3187 enum anv_semaphore_type type;
3188
3189 union {
3190 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3191 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3192 * object list on any execbuf2 calls for which this semaphore is used as
3193 * a wait or signal fence. When used as a signal fence or when type ==
3194 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3195 */
3196 struct anv_bo *bo;
3197
3198 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3199 * If the semaphore is in the unsignaled state due to either just being
3200 * created or because it has been used for a wait, fd will be -1.
3201 */
3202 int fd;
3203
3204 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3205 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3206 * import so we don't need to bother with a userspace cache.
3207 */
3208 uint32_t syncobj;
3209
3210 /* Non shareable timeline semaphore
3211 *
3212 * Used when kernel don't have support for timeline semaphores.
3213 */
3214 struct anv_timeline timeline;
3215 };
3216 };
3217
3218 struct anv_semaphore {
3219 struct vk_object_base base;
3220
3221 uint32_t refcount;
3222
3223 /* Permanent semaphore state. Every semaphore has some form of permanent
3224 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3225 * (for cross-process semaphores0 or it could just be a dummy for use
3226 * internally.
3227 */
3228 struct anv_semaphore_impl permanent;
3229
3230 /* Temporary semaphore state. A semaphore *may* have temporary state.
3231 * That state is added to the semaphore by an import operation and is reset
3232 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3233 * semaphore with temporary state cannot be signaled because the semaphore
3234 * must already be signaled before the temporary state can be exported from
3235 * the semaphore in the other process and imported here.
3236 */
3237 struct anv_semaphore_impl temporary;
3238 };
3239
3240 void anv_semaphore_reset_temporary(struct anv_device *device,
3241 struct anv_semaphore *semaphore);
3242
3243 struct anv_shader_module {
3244 struct vk_object_base base;
3245
3246 unsigned char sha1[20];
3247 uint32_t size;
3248 char data[0];
3249 };
3250
3251 static inline gl_shader_stage
3252 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
3253 {
3254 assert(__builtin_popcount(vk_stage) == 1);
3255 return ffs(vk_stage) - 1;
3256 }
3257
3258 static inline VkShaderStageFlagBits
3259 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
3260 {
3261 return (1 << mesa_stage);
3262 }
3263
3264 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3265
3266 #define anv_foreach_stage(stage, stage_bits) \
3267 for (gl_shader_stage stage, \
3268 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3269 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3270 __tmp &= ~(1 << (stage)))
3271
3272 struct anv_pipeline_bind_map {
3273 unsigned char surface_sha1[20];
3274 unsigned char sampler_sha1[20];
3275 unsigned char push_sha1[20];
3276
3277 uint32_t surface_count;
3278 uint32_t sampler_count;
3279
3280 struct anv_pipeline_binding * surface_to_descriptor;
3281 struct anv_pipeline_binding * sampler_to_descriptor;
3282
3283 struct anv_push_range push_ranges[4];
3284 };
3285
3286 struct anv_shader_bin_key {
3287 uint32_t size;
3288 uint8_t data[0];
3289 };
3290
3291 struct anv_shader_bin {
3292 uint32_t ref_cnt;
3293
3294 gl_shader_stage stage;
3295
3296 const struct anv_shader_bin_key *key;
3297
3298 struct anv_state kernel;
3299 uint32_t kernel_size;
3300
3301 struct anv_state constant_data;
3302 uint32_t constant_data_size;
3303
3304 const struct brw_stage_prog_data *prog_data;
3305 uint32_t prog_data_size;
3306
3307 struct brw_compile_stats stats[3];
3308 uint32_t num_stats;
3309
3310 struct nir_xfb_info *xfb_info;
3311
3312 struct anv_pipeline_bind_map bind_map;
3313 };
3314
3315 struct anv_shader_bin *
3316 anv_shader_bin_create(struct anv_device *device,
3317 gl_shader_stage stage,
3318 const void *key, uint32_t key_size,
3319 const void *kernel, uint32_t kernel_size,
3320 const void *constant_data, uint32_t constant_data_size,
3321 const struct brw_stage_prog_data *prog_data,
3322 uint32_t prog_data_size,
3323 const struct brw_compile_stats *stats, uint32_t num_stats,
3324 const struct nir_xfb_info *xfb_info,
3325 const struct anv_pipeline_bind_map *bind_map);
3326
3327 void
3328 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
3329
3330 static inline void
3331 anv_shader_bin_ref(struct anv_shader_bin *shader)
3332 {
3333 assert(shader && shader->ref_cnt >= 1);
3334 p_atomic_inc(&shader->ref_cnt);
3335 }
3336
3337 static inline void
3338 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
3339 {
3340 assert(shader && shader->ref_cnt >= 1);
3341 if (p_atomic_dec_zero(&shader->ref_cnt))
3342 anv_shader_bin_destroy(device, shader);
3343 }
3344
3345 struct anv_pipeline_executable {
3346 gl_shader_stage stage;
3347
3348 struct brw_compile_stats stats;
3349
3350 char *nir;
3351 char *disasm;
3352 };
3353
3354 enum anv_pipeline_type {
3355 ANV_PIPELINE_GRAPHICS,
3356 ANV_PIPELINE_COMPUTE,
3357 };
3358
3359 struct anv_pipeline {
3360 struct vk_object_base base;
3361
3362 struct anv_device * device;
3363
3364 struct anv_batch batch;
3365 struct anv_reloc_list batch_relocs;
3366
3367 void * mem_ctx;
3368
3369 enum anv_pipeline_type type;
3370 VkPipelineCreateFlags flags;
3371
3372 struct util_dynarray executables;
3373
3374 const struct gen_l3_config * l3_config;
3375 };
3376
3377 struct anv_graphics_pipeline {
3378 struct anv_pipeline base;
3379
3380 uint32_t batch_data[512];
3381
3382 anv_cmd_dirty_mask_t dynamic_state_mask;
3383 struct anv_dynamic_state dynamic_state;
3384
3385 uint32_t topology;
3386
3387 struct anv_subpass * subpass;
3388
3389 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
3390
3391 VkShaderStageFlags active_stages;
3392
3393 bool primitive_restart;
3394 bool writes_depth;
3395 bool depth_test_enable;
3396 bool writes_stencil;
3397 bool stencil_test_enable;
3398 bool depth_clamp_enable;
3399 bool depth_clip_enable;
3400 bool sample_shading_enable;
3401 bool kill_pixel;
3402 bool depth_bounds_test_enable;
3403
3404 /* When primitive replication is used, subpass->view_mask will describe what
3405 * views to replicate.
3406 */
3407 bool use_primitive_replication;
3408
3409 struct anv_state blend_state;
3410
3411 uint32_t vb_used;
3412 struct anv_pipeline_vertex_binding {
3413 uint32_t stride;
3414 bool instanced;
3415 uint32_t instance_divisor;
3416 } vb[MAX_VBS];
3417
3418 struct {
3419 uint32_t sf[7];
3420 uint32_t depth_stencil_state[3];
3421 uint32_t clip[4];
3422 } gen7;
3423
3424 struct {
3425 uint32_t sf[4];
3426 uint32_t raster[5];
3427 uint32_t wm_depth_stencil[3];
3428 } gen8;
3429
3430 struct {
3431 uint32_t wm_depth_stencil[4];
3432 } gen9;
3433 };
3434
3435 struct anv_compu