da1ca29f64c3c38086ffa63d9e26d793b0a0a895
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include <i915_drm.h>
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
40 #else
41 #define VG(x)
42 #endif
43
44 #include "common/gen_device_info.h"
45 #include "blorp/blorp.h"
46 #include "brw_compiler.h"
47 #include "util/macros.h"
48 #include "util/list.h"
49 #include "util/u_vector.h"
50 #include "util/vk_alloc.h"
51
52 /* Pre-declarations needed for WSI entrypoints */
53 struct wl_surface;
54 struct wl_display;
55 typedef struct xcb_connection_t xcb_connection_t;
56 typedef uint32_t xcb_visualid_t;
57 typedef uint32_t xcb_window_t;
58
59 struct gen_l3_config;
60
61 #include <vulkan/vulkan.h>
62 #include <vulkan/vulkan_intel.h>
63 #include <vulkan/vk_icd.h>
64
65 #include "anv_entrypoints.h"
66 #include "brw_context.h"
67 #include "isl/isl.h"
68
69 #include "wsi_common.h"
70
71 #ifdef __cplusplus
72 extern "C" {
73 #endif
74
75 /* Allowing different clear colors requires us to perform a depth resolve at
76 * the end of certain render passes. This is because while slow clears store
77 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
78 * See the PRMs for examples describing when additional resolves would be
79 * necessary. To enable fast clears without requiring extra resolves, we set
80 * the clear value to a globally-defined one. We could allow different values
81 * if the user doesn't expect coherent data during or after a render passes
82 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
83 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
84 * 1.0f seems to be the only value used. The only application that doesn't set
85 * this value does so through the usage of an seemingly uninitialized clear
86 * value.
87 */
88 #define ANV_HZ_FC_VAL 1.0f
89
90 #define MAX_VBS 31
91 #define MAX_SETS 8
92 #define MAX_RTS 8
93 #define MAX_VIEWPORTS 16
94 #define MAX_SCISSORS 16
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_DYNAMIC_BUFFERS 16
97 #define MAX_IMAGES 8
98
99 #define ANV_SVGS_VB_INDEX MAX_VBS
100 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
101
102 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
103
104 static inline uint32_t
105 align_down_npot_u32(uint32_t v, uint32_t a)
106 {
107 return v - (v % a);
108 }
109
110 static inline uint32_t
111 align_u32(uint32_t v, uint32_t a)
112 {
113 assert(a != 0 && a == (a & -a));
114 return (v + a - 1) & ~(a - 1);
115 }
116
117 static inline uint64_t
118 align_u64(uint64_t v, uint64_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline int32_t
125 align_i32(int32_t v, int32_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 /** Alignment must be a power of 2. */
132 static inline bool
133 anv_is_aligned(uintmax_t n, uintmax_t a)
134 {
135 assert(a == (a & -a));
136 return (n & (a - 1)) == 0;
137 }
138
139 static inline uint32_t
140 anv_minify(uint32_t n, uint32_t levels)
141 {
142 if (unlikely(n == 0))
143 return 0;
144 else
145 return MAX2(n >> levels, 1);
146 }
147
148 static inline float
149 anv_clamp_f(float f, float min, float max)
150 {
151 assert(min < max);
152
153 if (f > max)
154 return max;
155 else if (f < min)
156 return min;
157 else
158 return f;
159 }
160
161 static inline bool
162 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
163 {
164 if (*inout_mask & clear_mask) {
165 *inout_mask &= ~clear_mask;
166 return true;
167 } else {
168 return false;
169 }
170 }
171
172 static inline union isl_color_value
173 vk_to_isl_color(VkClearColorValue color)
174 {
175 return (union isl_color_value) {
176 .u32 = {
177 color.uint32[0],
178 color.uint32[1],
179 color.uint32[2],
180 color.uint32[3],
181 },
182 };
183 }
184
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
189
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
193 })
194
195 /* Whenever we generate an error, pass it through this function. Useful for
196 * debugging, where we can break on it. Only call at error site, not when
197 * propagating errors. Might be useful to plug in a stack trace here.
198 */
199
200 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
201
202 #ifdef DEBUG
203 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
204 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
205 #define anv_debug(format, ...) fprintf(stderr, "debug: " format, ##__VA_ARGS__)
206 #else
207 #define vk_error(error) error
208 #define vk_errorf(error, format, ...) error
209 #define anv_debug(format, ...)
210 #endif
211
212 /**
213 * Warn on ignored extension structs.
214 *
215 * The Vulkan spec requires us to ignore unsupported or unknown structs in
216 * a pNext chain. In debug mode, emitting warnings for ignored structs may
217 * help us discover structs that we should not have ignored.
218 *
219 *
220 * From the Vulkan 1.0.38 spec:
221 *
222 * Any component of the implementation (the loader, any enabled layers,
223 * and drivers) must skip over, without processing (other than reading the
224 * sType and pNext members) any chained structures with sType values not
225 * defined by extensions supported by that component.
226 */
227 #define anv_debug_ignored_stype(sType) \
228 anv_debug("debug: %s: ignored VkStructureType %u\n", __func__, (sType))
229
230 void __anv_finishme(const char *file, int line, const char *format, ...)
231 anv_printflike(3, 4);
232 void anv_loge(const char *format, ...) anv_printflike(1, 2);
233 void anv_loge_v(const char *format, va_list va);
234
235 /**
236 * Print a FINISHME message, including its source location.
237 */
238 #define anv_finishme(format, ...) \
239 do { \
240 static bool reported = false; \
241 if (!reported) { \
242 __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
243 reported = true; \
244 } \
245 } while (0)
246
247 /* A non-fatal assert. Useful for debugging. */
248 #ifdef DEBUG
249 #define anv_assert(x) ({ \
250 if (unlikely(!(x))) \
251 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
252 })
253 #else
254 #define anv_assert(x)
255 #endif
256
257 /**
258 * If a block of code is annotated with anv_validate, then the block runs only
259 * in debug builds.
260 */
261 #ifdef DEBUG
262 #define anv_validate if (1)
263 #else
264 #define anv_validate if (0)
265 #endif
266
267 #define stub_return(v) \
268 do { \
269 anv_finishme("stub %s", __func__); \
270 return (v); \
271 } while (0)
272
273 #define stub() \
274 do { \
275 anv_finishme("stub %s", __func__); \
276 return; \
277 } while (0)
278
279 /**
280 * A dynamically growable, circular buffer. Elements are added at head and
281 * removed from tail. head and tail are free-running uint32_t indices and we
282 * only compute the modulo with size when accessing the array. This way,
283 * number of bytes in the queue is always head - tail, even in case of
284 * wraparound.
285 */
286
287 struct anv_bo {
288 uint32_t gem_handle;
289
290 /* Index into the current validation list. This is used by the
291 * validation list building alrogithm to track which buffers are already
292 * in the validation list so that we can ensure uniqueness.
293 */
294 uint32_t index;
295
296 /* Last known offset. This value is provided by the kernel when we
297 * execbuf and is used as the presumed offset for the next bunch of
298 * relocations.
299 */
300 uint64_t offset;
301
302 uint64_t size;
303 void *map;
304
305 /* We need to set the WRITE flag on winsys bos so GEM will know we're
306 * writing to them and synchronize uses on other rings (eg if the display
307 * server uses the blitter ring).
308 */
309 bool is_winsys_bo;
310 };
311
312 static inline void
313 anv_bo_init(struct anv_bo *bo, uint32_t gem_handle, uint64_t size)
314 {
315 bo->gem_handle = gem_handle;
316 bo->index = 0;
317 bo->offset = -1;
318 bo->size = size;
319 bo->map = NULL;
320 bo->is_winsys_bo = false;
321 }
322
323 /* Represents a lock-free linked list of "free" things. This is used by
324 * both the block pool and the state pools. Unfortunately, in order to
325 * solve the ABA problem, we can't use a single uint32_t head.
326 */
327 union anv_free_list {
328 struct {
329 int32_t offset;
330
331 /* A simple count that is incremented every time the head changes. */
332 uint32_t count;
333 };
334 uint64_t u64;
335 };
336
337 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { 1, 0 } })
338
339 struct anv_block_state {
340 union {
341 struct {
342 uint32_t next;
343 uint32_t end;
344 };
345 uint64_t u64;
346 };
347 };
348
349 struct anv_block_pool {
350 struct anv_device *device;
351
352 struct anv_bo bo;
353
354 /* The offset from the start of the bo to the "center" of the block
355 * pool. Pointers to allocated blocks are given by
356 * bo.map + center_bo_offset + offsets.
357 */
358 uint32_t center_bo_offset;
359
360 /* Current memory map of the block pool. This pointer may or may not
361 * point to the actual beginning of the block pool memory. If
362 * anv_block_pool_alloc_back has ever been called, then this pointer
363 * will point to the "center" position of the buffer and all offsets
364 * (negative or positive) given out by the block pool alloc functions
365 * will be valid relative to this pointer.
366 *
367 * In particular, map == bo.map + center_offset
368 */
369 void *map;
370 int fd;
371
372 /**
373 * Array of mmaps and gem handles owned by the block pool, reclaimed when
374 * the block pool is destroyed.
375 */
376 struct u_vector mmap_cleanups;
377
378 uint32_t block_size;
379
380 union anv_free_list free_list;
381 struct anv_block_state state;
382
383 union anv_free_list back_free_list;
384 struct anv_block_state back_state;
385 };
386
387 /* Block pools are backed by a fixed-size 2GB memfd */
388 #define BLOCK_POOL_MEMFD_SIZE (1ull << 32)
389
390 /* The center of the block pool is also the middle of the memfd. This may
391 * change in the future if we decide differently for some reason.
392 */
393 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
394
395 static inline uint32_t
396 anv_block_pool_size(struct anv_block_pool *pool)
397 {
398 return pool->state.end + pool->back_state.end;
399 }
400
401 struct anv_state {
402 int32_t offset;
403 uint32_t alloc_size;
404 void *map;
405 };
406
407 struct anv_fixed_size_state_pool {
408 size_t state_size;
409 union anv_free_list free_list;
410 struct anv_block_state block;
411 };
412
413 #define ANV_MIN_STATE_SIZE_LOG2 6
414 #define ANV_MAX_STATE_SIZE_LOG2 20
415
416 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
417
418 struct anv_state_pool {
419 struct anv_block_pool *block_pool;
420 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
421 };
422
423 struct anv_state_stream_block;
424
425 struct anv_state_stream {
426 struct anv_block_pool *block_pool;
427
428 /* The current working block */
429 struct anv_state_stream_block *block;
430
431 /* Offset at which the current block starts */
432 uint32_t start;
433 /* Offset at which to allocate the next state */
434 uint32_t next;
435 /* Offset at which the current block ends */
436 uint32_t end;
437 };
438
439 #define CACHELINE_SIZE 64
440 #define CACHELINE_MASK 63
441
442 static inline void
443 anv_clflush_range(void *start, size_t size)
444 {
445 void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
446 void *end = start + size;
447
448 __builtin_ia32_mfence();
449 while (p < end) {
450 __builtin_ia32_clflush(p);
451 p += CACHELINE_SIZE;
452 }
453 }
454
455 static void inline
456 anv_state_clflush(struct anv_state state)
457 {
458 anv_clflush_range(state.map, state.alloc_size);
459 }
460
461 VkResult anv_block_pool_init(struct anv_block_pool *pool,
462 struct anv_device *device, uint32_t block_size);
463 void anv_block_pool_finish(struct anv_block_pool *pool);
464 int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
465 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
466 void anv_block_pool_free(struct anv_block_pool *pool, int32_t offset);
467 void anv_state_pool_init(struct anv_state_pool *pool,
468 struct anv_block_pool *block_pool);
469 void anv_state_pool_finish(struct anv_state_pool *pool);
470 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
471 size_t state_size, size_t alignment);
472 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
473 void anv_state_stream_init(struct anv_state_stream *stream,
474 struct anv_block_pool *block_pool);
475 void anv_state_stream_finish(struct anv_state_stream *stream);
476 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
477 uint32_t size, uint32_t alignment);
478
479 /**
480 * Implements a pool of re-usable BOs. The interface is identical to that
481 * of block_pool except that each block is its own BO.
482 */
483 struct anv_bo_pool {
484 struct anv_device *device;
485
486 void *free_list[16];
487 };
488
489 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
490 void anv_bo_pool_finish(struct anv_bo_pool *pool);
491 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, struct anv_bo *bo,
492 uint32_t size);
493 void anv_bo_pool_free(struct anv_bo_pool *pool, const struct anv_bo *bo);
494
495 struct anv_scratch_bo {
496 bool exists;
497 struct anv_bo bo;
498 };
499
500 struct anv_scratch_pool {
501 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
502 struct anv_scratch_bo bos[16][MESA_SHADER_STAGES];
503 };
504
505 void anv_scratch_pool_init(struct anv_device *device,
506 struct anv_scratch_pool *pool);
507 void anv_scratch_pool_finish(struct anv_device *device,
508 struct anv_scratch_pool *pool);
509 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
510 struct anv_scratch_pool *pool,
511 gl_shader_stage stage,
512 unsigned per_thread_scratch);
513
514 extern struct anv_dispatch_table dtable;
515
516 struct anv_physical_device {
517 VK_LOADER_DATA _loader_data;
518
519 struct anv_instance * instance;
520 uint32_t chipset_id;
521 char path[20];
522 const char * name;
523 struct gen_device_info info;
524 uint64_t aperture_size;
525 struct brw_compiler * compiler;
526 struct isl_device isl_dev;
527 int cmd_parser_version;
528
529 uint32_t eu_total;
530 uint32_t subslice_total;
531
532 uint8_t uuid[VK_UUID_SIZE];
533
534 struct wsi_device wsi_device;
535 };
536
537 struct anv_instance {
538 VK_LOADER_DATA _loader_data;
539
540 VkAllocationCallbacks alloc;
541
542 uint32_t apiVersion;
543 int physicalDeviceCount;
544 struct anv_physical_device physicalDevice;
545 };
546
547 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
548 void anv_finish_wsi(struct anv_physical_device *physical_device);
549
550 struct anv_queue {
551 VK_LOADER_DATA _loader_data;
552
553 struct anv_device * device;
554
555 struct anv_state_pool * pool;
556 };
557
558 struct anv_pipeline_cache {
559 struct anv_device * device;
560 pthread_mutex_t mutex;
561
562 struct hash_table * cache;
563 };
564
565 struct anv_pipeline_bind_map;
566
567 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
568 struct anv_device *device,
569 bool cache_enabled);
570 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
571
572 struct anv_shader_bin *
573 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
574 const void *key, uint32_t key_size);
575 struct anv_shader_bin *
576 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
577 const void *key_data, uint32_t key_size,
578 const void *kernel_data, uint32_t kernel_size,
579 const struct brw_stage_prog_data *prog_data,
580 uint32_t prog_data_size,
581 const struct anv_pipeline_bind_map *bind_map);
582
583 struct anv_device {
584 VK_LOADER_DATA _loader_data;
585
586 VkAllocationCallbacks alloc;
587
588 struct anv_instance * instance;
589 uint32_t chipset_id;
590 struct gen_device_info info;
591 struct isl_device isl_dev;
592 int context_id;
593 int fd;
594 bool can_chain_batches;
595 bool robust_buffer_access;
596
597 struct anv_bo_pool batch_bo_pool;
598
599 struct anv_block_pool dynamic_state_block_pool;
600 struct anv_state_pool dynamic_state_pool;
601
602 struct anv_block_pool instruction_block_pool;
603 struct anv_state_pool instruction_state_pool;
604
605 struct anv_block_pool surface_state_block_pool;
606 struct anv_state_pool surface_state_pool;
607
608 struct anv_bo workaround_bo;
609
610 struct anv_pipeline_cache blorp_shader_cache;
611 struct blorp_context blorp;
612
613 struct anv_state border_colors;
614
615 struct anv_queue queue;
616
617 struct anv_scratch_pool scratch_pool;
618
619 uint32_t default_mocs;
620
621 pthread_mutex_t mutex;
622 pthread_cond_t queue_submit;
623 };
624
625 void anv_device_init_blorp(struct anv_device *device);
626 void anv_device_finish_blorp(struct anv_device *device);
627
628 VkResult anv_device_execbuf(struct anv_device *device,
629 struct drm_i915_gem_execbuffer2 *execbuf,
630 struct anv_bo **execbuf_bos);
631
632 void* anv_gem_mmap(struct anv_device *device,
633 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
634 void anv_gem_munmap(void *p, uint64_t size);
635 uint32_t anv_gem_create(struct anv_device *device, size_t size);
636 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
637 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
638 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
639 int anv_gem_execbuffer(struct anv_device *device,
640 struct drm_i915_gem_execbuffer2 *execbuf);
641 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
642 uint32_t stride, uint32_t tiling);
643 int anv_gem_create_context(struct anv_device *device);
644 int anv_gem_destroy_context(struct anv_device *device, int context);
645 int anv_gem_get_param(int fd, uint32_t param);
646 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
647 int anv_gem_get_aperture(int fd, uint64_t *size);
648 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
649 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
650 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
651 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
652 uint32_t read_domains, uint32_t write_domain);
653
654 VkResult anv_bo_init_new(struct anv_bo *bo, struct anv_device *device, uint64_t size);
655
656 struct anv_reloc_list {
657 size_t num_relocs;
658 size_t array_length;
659 struct drm_i915_gem_relocation_entry * relocs;
660 struct anv_bo ** reloc_bos;
661 };
662
663 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
664 const VkAllocationCallbacks *alloc);
665 void anv_reloc_list_finish(struct anv_reloc_list *list,
666 const VkAllocationCallbacks *alloc);
667
668 uint64_t anv_reloc_list_add(struct anv_reloc_list *list,
669 const VkAllocationCallbacks *alloc,
670 uint32_t offset, struct anv_bo *target_bo,
671 uint32_t delta);
672
673 struct anv_batch_bo {
674 /* Link in the anv_cmd_buffer.owned_batch_bos list */
675 struct list_head link;
676
677 struct anv_bo bo;
678
679 /* Bytes actually consumed in this batch BO */
680 size_t length;
681
682 struct anv_reloc_list relocs;
683 };
684
685 struct anv_batch {
686 const VkAllocationCallbacks * alloc;
687
688 void * start;
689 void * end;
690 void * next;
691
692 struct anv_reloc_list * relocs;
693
694 /* This callback is called (with the associated user data) in the event
695 * that the batch runs out of space.
696 */
697 VkResult (*extend_cb)(struct anv_batch *, void *);
698 void * user_data;
699 };
700
701 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
702 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
703 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
704 void *location, struct anv_bo *bo, uint32_t offset);
705 VkResult anv_device_submit_simple_batch(struct anv_device *device,
706 struct anv_batch *batch);
707
708 struct anv_address {
709 struct anv_bo *bo;
710 uint32_t offset;
711 };
712
713 static inline uint64_t
714 _anv_combine_address(struct anv_batch *batch, void *location,
715 const struct anv_address address, uint32_t delta)
716 {
717 if (address.bo == NULL) {
718 return address.offset + delta;
719 } else {
720 assert(batch->start <= location && location < batch->end);
721
722 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
723 }
724 }
725
726 #define __gen_address_type struct anv_address
727 #define __gen_user_data struct anv_batch
728 #define __gen_combine_address _anv_combine_address
729
730 /* Wrapper macros needed to work around preprocessor argument issues. In
731 * particular, arguments don't get pre-evaluated if they are concatenated.
732 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
733 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
734 * We can work around this easily enough with these helpers.
735 */
736 #define __anv_cmd_length(cmd) cmd ## _length
737 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
738 #define __anv_cmd_header(cmd) cmd ## _header
739 #define __anv_cmd_pack(cmd) cmd ## _pack
740 #define __anv_reg_num(reg) reg ## _num
741
742 #define anv_pack_struct(dst, struc, ...) do { \
743 struct struc __template = { \
744 __VA_ARGS__ \
745 }; \
746 __anv_cmd_pack(struc)(NULL, dst, &__template); \
747 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
748 } while (0)
749
750 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
751 void *__dst = anv_batch_emit_dwords(batch, n); \
752 struct cmd __template = { \
753 __anv_cmd_header(cmd), \
754 .DWordLength = n - __anv_cmd_length_bias(cmd), \
755 __VA_ARGS__ \
756 }; \
757 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
758 __dst; \
759 })
760
761 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
762 do { \
763 uint32_t *dw; \
764 \
765 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
766 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
767 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
768 dw[i] = (dwords0)[i] | (dwords1)[i]; \
769 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
770 } while (0)
771
772 #define anv_batch_emit(batch, cmd, name) \
773 for (struct cmd name = { __anv_cmd_header(cmd) }, \
774 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
775 __builtin_expect(_dst != NULL, 1); \
776 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
777 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
778 _dst = NULL; \
779 }))
780
781 #define anv_state_pool_emit(pool, cmd, align, ...) ({ \
782 const uint32_t __size = __anv_cmd_length(cmd) * 4; \
783 struct anv_state __state = \
784 anv_state_pool_alloc((pool), __size, align); \
785 struct cmd __template = { \
786 __VA_ARGS__ \
787 }; \
788 __anv_cmd_pack(cmd)(NULL, __state.map, &__template); \
789 VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 4)); \
790 if (!(pool)->block_pool->device->info.has_llc) \
791 anv_state_clflush(__state); \
792 __state; \
793 })
794
795 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) { \
796 .GraphicsDataTypeGFDT = 0, \
797 .LLCCacheabilityControlLLCCC = 0, \
798 .L3CacheabilityControlL3CC = 1, \
799 }
800
801 #define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
802 .LLCeLLCCacheabilityControlLLCCC = 0, \
803 .L3CacheabilityControlL3CC = 1, \
804 }
805
806 #define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
807 .MemoryTypeLLCeLLCCacheabilityControl = WB, \
808 .TargetCache = L3DefertoPATforLLCeLLCselection, \
809 .AgeforQUADLRU = 0 \
810 }
811
812 /* Skylake: MOCS is now an index into an array of 62 different caching
813 * configurations programmed by the kernel.
814 */
815
816 #define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
817 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
818 .IndextoMOCSTables = 2 \
819 }
820
821 #define GEN9_MOCS_PTE { \
822 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
823 .IndextoMOCSTables = 1 \
824 }
825
826 struct anv_device_memory {
827 struct anv_bo bo;
828 uint32_t type_index;
829 VkDeviceSize map_size;
830 void * map;
831 };
832
833 /**
834 * Header for Vertex URB Entry (VUE)
835 */
836 struct anv_vue_header {
837 uint32_t Reserved;
838 uint32_t RTAIndex; /* RenderTargetArrayIndex */
839 uint32_t ViewportIndex;
840 float PointWidth;
841 };
842
843 struct anv_descriptor_set_binding_layout {
844 #ifndef NDEBUG
845 /* The type of the descriptors in this binding */
846 VkDescriptorType type;
847 #endif
848
849 /* Number of array elements in this binding */
850 uint16_t array_size;
851
852 /* Index into the flattend descriptor set */
853 uint16_t descriptor_index;
854
855 /* Index into the dynamic state array for a dynamic buffer */
856 int16_t dynamic_offset_index;
857
858 /* Index into the descriptor set buffer views */
859 int16_t buffer_index;
860
861 struct {
862 /* Index into the binding table for the associated surface */
863 int16_t surface_index;
864
865 /* Index into the sampler table for the associated sampler */
866 int16_t sampler_index;
867
868 /* Index into the image table for the associated image */
869 int16_t image_index;
870 } stage[MESA_SHADER_STAGES];
871
872 /* Immutable samplers (or NULL if no immutable samplers) */
873 struct anv_sampler **immutable_samplers;
874 };
875
876 struct anv_descriptor_set_layout {
877 /* Number of bindings in this descriptor set */
878 uint16_t binding_count;
879
880 /* Total size of the descriptor set with room for all array entries */
881 uint16_t size;
882
883 /* Shader stages affected by this descriptor set */
884 uint16_t shader_stages;
885
886 /* Number of buffers in this descriptor set */
887 uint16_t buffer_count;
888
889 /* Number of dynamic offsets used by this descriptor set */
890 uint16_t dynamic_offset_count;
891
892 /* Bindings in this descriptor set */
893 struct anv_descriptor_set_binding_layout binding[0];
894 };
895
896 struct anv_descriptor {
897 VkDescriptorType type;
898
899 union {
900 struct {
901 struct anv_image_view *image_view;
902 struct anv_sampler *sampler;
903 };
904
905 struct anv_buffer_view *buffer_view;
906 };
907 };
908
909 struct anv_descriptor_set {
910 const struct anv_descriptor_set_layout *layout;
911 uint32_t size;
912 uint32_t buffer_count;
913 struct anv_buffer_view *buffer_views;
914 struct anv_descriptor descriptors[0];
915 };
916
917 struct anv_descriptor_pool {
918 uint32_t size;
919 uint32_t next;
920 uint32_t free_list;
921
922 struct anv_state_stream surface_state_stream;
923 void *surface_state_free_list;
924
925 char data[0];
926 };
927
928 VkResult
929 anv_descriptor_set_create(struct anv_device *device,
930 struct anv_descriptor_pool *pool,
931 const struct anv_descriptor_set_layout *layout,
932 struct anv_descriptor_set **out_set);
933
934 void
935 anv_descriptor_set_destroy(struct anv_device *device,
936 struct anv_descriptor_pool *pool,
937 struct anv_descriptor_set *set);
938
939 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
940
941 struct anv_pipeline_binding {
942 /* The descriptor set this surface corresponds to. The special value of
943 * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
944 * to a color attachment and not a regular descriptor.
945 */
946 uint8_t set;
947
948 /* Binding in the descriptor set */
949 uint8_t binding;
950
951 /* Index in the binding */
952 uint8_t index;
953
954 /* Input attachment index (relative to the subpass) */
955 uint8_t input_attachment_index;
956
957 /* For a storage image, whether it is write-only */
958 bool write_only;
959 };
960
961 struct anv_pipeline_layout {
962 struct {
963 struct anv_descriptor_set_layout *layout;
964 uint32_t dynamic_offset_start;
965 } set[MAX_SETS];
966
967 uint32_t num_sets;
968
969 struct {
970 bool has_dynamic_offsets;
971 } stage[MESA_SHADER_STAGES];
972
973 unsigned char sha1[20];
974 };
975
976 struct anv_buffer {
977 struct anv_device * device;
978 VkDeviceSize size;
979
980 VkBufferUsageFlags usage;
981
982 /* Set when bound */
983 struct anv_bo * bo;
984 VkDeviceSize offset;
985 };
986
987 enum anv_cmd_dirty_bits {
988 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
989 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
990 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
991 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
992 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
993 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
994 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
995 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
996 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
997 ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
998 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
999 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
1000 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
1001 };
1002 typedef uint32_t anv_cmd_dirty_mask_t;
1003
1004 enum anv_pipe_bits {
1005 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
1006 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
1007 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
1008 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
1009 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
1010 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
1011 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
1012 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
1013 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
1014 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
1015 ANV_PIPE_CS_STALL_BIT = (1 << 20),
1016
1017 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
1018 * a flush has happened but not a CS stall. The next time we do any sort
1019 * of invalidation we need to insert a CS stall at that time. Otherwise,
1020 * we would have to CS stall on every flush which could be bad.
1021 */
1022 ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
1023 };
1024
1025 #define ANV_PIPE_FLUSH_BITS ( \
1026 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
1027 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1028 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
1029
1030 #define ANV_PIPE_STALL_BITS ( \
1031 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
1032 ANV_PIPE_DEPTH_STALL_BIT | \
1033 ANV_PIPE_CS_STALL_BIT)
1034
1035 #define ANV_PIPE_INVALIDATE_BITS ( \
1036 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
1037 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
1038 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
1039 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
1040 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
1041 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)
1042
1043 struct anv_vertex_binding {
1044 struct anv_buffer * buffer;
1045 VkDeviceSize offset;
1046 };
1047
1048 struct anv_push_constants {
1049 /* Current allocated size of this push constants data structure.
1050 * Because a decent chunk of it may not be used (images on SKL, for
1051 * instance), we won't actually allocate the entire structure up-front.
1052 */
1053 uint32_t size;
1054
1055 /* Push constant data provided by the client through vkPushConstants */
1056 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
1057
1058 /* Our hardware only provides zero-based vertex and instance id so, in
1059 * order to satisfy the vulkan requirements, we may have to push one or
1060 * both of these into the shader.
1061 */
1062 uint32_t base_vertex;
1063 uint32_t base_instance;
1064
1065 /* Offsets and ranges for dynamically bound buffers */
1066 struct {
1067 uint32_t offset;
1068 uint32_t range;
1069 } dynamic[MAX_DYNAMIC_BUFFERS];
1070
1071 /* Image data for image_load_store on pre-SKL */
1072 struct brw_image_param images[MAX_IMAGES];
1073 };
1074
1075 struct anv_dynamic_state {
1076 struct {
1077 uint32_t count;
1078 VkViewport viewports[MAX_VIEWPORTS];
1079 } viewport;
1080
1081 struct {
1082 uint32_t count;
1083 VkRect2D scissors[MAX_SCISSORS];
1084 } scissor;
1085
1086 float line_width;
1087
1088 struct {
1089 float bias;
1090 float clamp;
1091 float slope;
1092 } depth_bias;
1093
1094 float blend_constants[4];
1095
1096 struct {
1097 float min;
1098 float max;
1099 } depth_bounds;
1100
1101 struct {
1102 uint32_t front;
1103 uint32_t back;
1104 } stencil_compare_mask;
1105
1106 struct {
1107 uint32_t front;
1108 uint32_t back;
1109 } stencil_write_mask;
1110
1111 struct {
1112 uint32_t front;
1113 uint32_t back;
1114 } stencil_reference;
1115 };
1116
1117 extern const struct anv_dynamic_state default_dynamic_state;
1118
1119 void anv_dynamic_state_copy(struct anv_dynamic_state *dest,
1120 const struct anv_dynamic_state *src,
1121 uint32_t copy_mask);
1122
1123 /**
1124 * Attachment state when recording a renderpass instance.
1125 *
1126 * The clear value is valid only if there exists a pending clear.
1127 */
1128 struct anv_attachment_state {
1129 enum isl_aux_usage aux_usage;
1130 enum isl_aux_usage input_aux_usage;
1131 struct anv_state color_rt_state;
1132 struct anv_state input_att_state;
1133
1134 VkImageLayout current_layout;
1135 VkImageAspectFlags pending_clear_aspects;
1136 bool fast_clear;
1137 VkClearValue clear_value;
1138 bool clear_color_is_zero_one;
1139 };
1140
1141 /** State required while building cmd buffer */
1142 struct anv_cmd_state {
1143 /* PIPELINE_SELECT.PipelineSelection */
1144 uint32_t current_pipeline;
1145 const struct gen_l3_config * current_l3_config;
1146 uint32_t vb_dirty;
1147 anv_cmd_dirty_mask_t dirty;
1148 anv_cmd_dirty_mask_t compute_dirty;
1149 enum anv_pipe_bits pending_pipe_bits;
1150 uint32_t num_workgroups_offset;
1151 struct anv_bo *num_workgroups_bo;
1152 VkShaderStageFlags descriptors_dirty;
1153 VkShaderStageFlags push_constants_dirty;
1154 uint32_t scratch_size;
1155 struct anv_pipeline * pipeline;
1156 struct anv_pipeline * compute_pipeline;
1157 struct anv_framebuffer * framebuffer;
1158 struct anv_render_pass * pass;
1159 struct anv_subpass * subpass;
1160 VkRect2D render_area;
1161 uint32_t restart_index;
1162 struct anv_vertex_binding vertex_bindings[MAX_VBS];
1163 struct anv_descriptor_set * descriptors[MAX_SETS];
1164 VkShaderStageFlags push_constant_stages;
1165 struct anv_push_constants * push_constants[MESA_SHADER_STAGES];
1166 struct anv_state binding_tables[MESA_SHADER_STAGES];
1167 struct anv_state samplers[MESA_SHADER_STAGES];
1168 struct anv_dynamic_state dynamic;
1169 bool need_query_wa;
1170
1171 /**
1172 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
1173 * of any command buffer it is disabled by disabling it in EndCommandBuffer
1174 * and before invoking the secondary in ExecuteCommands.
1175 */
1176 bool pma_fix_enabled;
1177
1178 /**
1179 * Whether or not we know for certain that HiZ is enabled for the current
1180 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
1181 * enabled or not, this will be false.
1182 */
1183 bool hiz_enabled;
1184
1185 /**
1186 * Array length is anv_cmd_state::pass::attachment_count. Array content is
1187 * valid only when recording a render pass instance.
1188 */
1189 struct anv_attachment_state * attachments;
1190
1191 /**
1192 * Surface states for color render targets. These are stored in a single
1193 * flat array. For depth-stencil attachments, the surface state is simply
1194 * left blank.
1195 */
1196 struct anv_state render_pass_states;
1197
1198 /**
1199 * A null surface state of the right size to match the framebuffer. This
1200 * is one of the states in render_pass_states.
1201 */
1202 struct anv_state null_surface_state;
1203
1204 struct {
1205 struct anv_buffer * index_buffer;
1206 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
1207 uint32_t index_offset;
1208 } gen7;
1209 };
1210
1211 struct anv_cmd_pool {
1212 VkAllocationCallbacks alloc;
1213 struct list_head cmd_buffers;
1214 };
1215
1216 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
1217
1218 enum anv_cmd_buffer_exec_mode {
1219 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
1220 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
1221 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
1222 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
1223 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
1224 };
1225
1226 struct anv_cmd_buffer {
1227 VK_LOADER_DATA _loader_data;
1228
1229 struct anv_device * device;
1230
1231 struct anv_cmd_pool * pool;
1232 struct list_head pool_link;
1233
1234 struct anv_batch batch;
1235
1236 /* Fields required for the actual chain of anv_batch_bo's.
1237 *
1238 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
1239 */
1240 struct list_head batch_bos;
1241 enum anv_cmd_buffer_exec_mode exec_mode;
1242
1243 /* A vector of anv_batch_bo pointers for every batch or surface buffer
1244 * referenced by this command buffer
1245 *
1246 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1247 */
1248 struct u_vector seen_bbos;
1249
1250 /* A vector of int32_t's for every block of binding tables.
1251 *
1252 * initialized by anv_cmd_buffer_init_batch_bo_chain()
1253 */
1254 struct u_vector bt_blocks;
1255 uint32_t bt_next;
1256
1257 struct anv_reloc_list surface_relocs;
1258 /** Last seen surface state block pool center bo offset */
1259 uint32_t last_ss_pool_center;
1260
1261 /* Serial for tracking buffer completion */
1262 uint32_t serial;
1263
1264 /* Stream objects for storing temporary data */
1265 struct anv_state_stream surface_state_stream;
1266 struct anv_state_stream dynamic_state_stream;
1267
1268 VkCommandBufferUsageFlags usage_flags;
1269 VkCommandBufferLevel level;
1270
1271 struct anv_cmd_state state;
1272 };
1273
1274 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1275 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1276 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
1277 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
1278 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
1279 struct anv_cmd_buffer *secondary);
1280 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
1281 VkResult anv_cmd_buffer_execbuf(struct anv_device *device,
1282 struct anv_cmd_buffer *cmd_buffer);
1283
1284 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
1285
1286 VkResult
1287 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
1288 gl_shader_stage stage, uint32_t size);
1289 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
1290 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
1291 (offsetof(struct anv_push_constants, field) + \
1292 sizeof(cmd_buffer->state.push_constants[0]->field)))
1293
1294 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
1295 const void *data, uint32_t size, uint32_t alignment);
1296 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
1297 uint32_t *a, uint32_t *b,
1298 uint32_t dwords, uint32_t alignment);
1299
1300 struct anv_address
1301 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
1302 struct anv_state
1303 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
1304 uint32_t entries, uint32_t *state_offset);
1305 struct anv_state
1306 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
1307 struct anv_state
1308 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
1309 uint32_t size, uint32_t alignment);
1310
1311 VkResult
1312 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
1313
1314 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
1315 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
1316 bool depth_clamp_enable);
1317 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
1318
1319 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
1320 struct anv_render_pass *pass,
1321 struct anv_framebuffer *framebuffer,
1322 const VkClearValue *clear_values);
1323
1324 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
1325
1326 struct anv_state
1327 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
1328 gl_shader_stage stage);
1329 struct anv_state
1330 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
1331
1332 void anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer);
1333 void anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer);
1334
1335 const struct anv_image_view *
1336 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
1337
1338 struct anv_state
1339 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
1340 uint32_t num_entries,
1341 uint32_t *state_offset);
1342
1343 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
1344
1345 enum anv_fence_state {
1346 /** Indicates that this is a new (or newly reset fence) */
1347 ANV_FENCE_STATE_RESET,
1348
1349 /** Indicates that this fence has been submitted to the GPU but is still
1350 * (as far as we know) in use by the GPU.
1351 */
1352 ANV_FENCE_STATE_SUBMITTED,
1353
1354 ANV_FENCE_STATE_SIGNALED,
1355 };
1356
1357 struct anv_fence {
1358 struct anv_bo bo;
1359 struct drm_i915_gem_execbuffer2 execbuf;
1360 struct drm_i915_gem_exec_object2 exec2_objects[1];
1361 enum anv_fence_state state;
1362 };
1363
1364 struct anv_event {
1365 uint64_t semaphore;
1366 struct anv_state state;
1367 };
1368
1369 struct anv_shader_module {
1370 unsigned char sha1[20];
1371 uint32_t size;
1372 char data[0];
1373 };
1374
1375 void anv_hash_shader(unsigned char *hash, const void *key, size_t key_size,
1376 struct anv_shader_module *module,
1377 const char *entrypoint,
1378 const struct anv_pipeline_layout *pipeline_layout,
1379 const VkSpecializationInfo *spec_info);
1380
1381 static inline gl_shader_stage
1382 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1383 {
1384 assert(__builtin_popcount(vk_stage) == 1);
1385 return ffs(vk_stage) - 1;
1386 }
1387
1388 static inline VkShaderStageFlagBits
1389 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1390 {
1391 return (1 << mesa_stage);
1392 }
1393
1394 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1395
1396 #define anv_foreach_stage(stage, stage_bits) \
1397 for (gl_shader_stage stage, \
1398 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
1399 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1400 __tmp &= ~(1 << (stage)))
1401
1402 struct anv_pipeline_bind_map {
1403 uint32_t surface_count;
1404 uint32_t sampler_count;
1405 uint32_t image_count;
1406
1407 struct anv_pipeline_binding * surface_to_descriptor;
1408 struct anv_pipeline_binding * sampler_to_descriptor;
1409 };
1410
1411 struct anv_shader_bin_key {
1412 uint32_t size;
1413 uint8_t data[0];
1414 };
1415
1416 struct anv_shader_bin {
1417 uint32_t ref_cnt;
1418
1419 const struct anv_shader_bin_key *key;
1420
1421 struct anv_state kernel;
1422 uint32_t kernel_size;
1423
1424 const struct brw_stage_prog_data *prog_data;
1425 uint32_t prog_data_size;
1426
1427 struct anv_pipeline_bind_map bind_map;
1428
1429 /* Prog data follows, then params, then the key, all aligned to 8-bytes */
1430 };
1431
1432 struct anv_shader_bin *
1433 anv_shader_bin_create(struct anv_device *device,
1434 const void *key, uint32_t key_size,
1435 const void *kernel, uint32_t kernel_size,
1436 const struct brw_stage_prog_data *prog_data,
1437 uint32_t prog_data_size, const void *prog_data_param,
1438 const struct anv_pipeline_bind_map *bind_map);
1439
1440 void
1441 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
1442
1443 static inline void
1444 anv_shader_bin_ref(struct anv_shader_bin *shader)
1445 {
1446 assert(shader->ref_cnt >= 1);
1447 __sync_fetch_and_add(&shader->ref_cnt, 1);
1448 }
1449
1450 static inline void
1451 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
1452 {
1453 assert(shader->ref_cnt >= 1);
1454 if (__sync_fetch_and_add(&shader->ref_cnt, -1) == 1)
1455 anv_shader_bin_destroy(device, shader);
1456 }
1457
1458 struct anv_pipeline {
1459 struct anv_device * device;
1460 struct anv_batch batch;
1461 uint32_t batch_data[512];
1462 struct anv_reloc_list batch_relocs;
1463 uint32_t dynamic_state_mask;
1464 struct anv_dynamic_state dynamic_state;
1465
1466 struct anv_pipeline_layout * layout;
1467
1468 bool needs_data_cache;
1469
1470 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
1471
1472 struct {
1473 const struct gen_l3_config * l3_config;
1474 uint32_t total_size;
1475 } urb;
1476
1477 VkShaderStageFlags active_stages;
1478 struct anv_state blend_state;
1479
1480 uint32_t vb_used;
1481 uint32_t binding_stride[MAX_VBS];
1482 bool instancing_enable[MAX_VBS];
1483 bool primitive_restart;
1484 uint32_t topology;
1485
1486 uint32_t cs_right_mask;
1487
1488 bool writes_depth;
1489 bool depth_test_enable;
1490 bool writes_stencil;
1491 bool stencil_test_enable;
1492 bool depth_clamp_enable;
1493 bool kill_pixel;
1494
1495 struct {
1496 uint32_t sf[7];
1497 uint32_t depth_stencil_state[3];
1498 } gen7;
1499
1500 struct {
1501 uint32_t sf[4];
1502 uint32_t raster[5];
1503 uint32_t wm_depth_stencil[3];
1504 } gen8;
1505
1506 struct {
1507 uint32_t wm_depth_stencil[4];
1508 } gen9;
1509
1510 uint32_t interface_descriptor_data[8];
1511 };
1512
1513 static inline bool
1514 anv_pipeline_has_stage(const struct anv_pipeline *pipeline,
1515 gl_shader_stage stage)
1516 {
1517 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
1518 }
1519
1520 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
1521 static inline const struct brw_##prefix##_prog_data * \
1522 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
1523 { \
1524 if (anv_pipeline_has_stage(pipeline, stage)) { \
1525 return (const struct brw_##prefix##_prog_data *) \
1526 pipeline->shaders[stage]->prog_data; \
1527 } else { \
1528 return NULL; \
1529 } \
1530 }
1531
1532 ANV_DECL_GET_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
1533 ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
1534 ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
1535 ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
1536 ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
1537 ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
1538
1539 static inline const struct brw_vue_prog_data *
1540 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)
1541 {
1542 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
1543 return &get_gs_prog_data(pipeline)->base;
1544 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
1545 return &get_tes_prog_data(pipeline)->base;
1546 else
1547 return &get_vs_prog_data(pipeline)->base;
1548 }
1549
1550 VkResult
1551 anv_pipeline_init(struct anv_pipeline *pipeline, struct anv_device *device,
1552 struct anv_pipeline_cache *cache,
1553 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1554 const VkAllocationCallbacks *alloc);
1555
1556 VkResult
1557 anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
1558 struct anv_pipeline_cache *cache,
1559 const VkComputePipelineCreateInfo *info,
1560 struct anv_shader_module *module,
1561 const char *entrypoint,
1562 const VkSpecializationInfo *spec_info);
1563
1564 struct anv_format {
1565 enum isl_format isl_format:16;
1566 struct isl_swizzle swizzle;
1567 };
1568
1569 struct anv_format
1570 anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
1571 VkImageAspectFlags aspect, VkImageTiling tiling);
1572
1573 static inline enum isl_format
1574 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
1575 VkImageAspectFlags aspect, VkImageTiling tiling)
1576 {
1577 return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
1578 }
1579
1580 static inline struct isl_swizzle
1581 anv_swizzle_for_render(struct isl_swizzle swizzle)
1582 {
1583 /* Sometimes the swizzle will have alpha map to one. We do this to fake
1584 * RGB as RGBA for texturing
1585 */
1586 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
1587 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
1588
1589 /* But it doesn't matter what we render to that channel */
1590 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
1591
1592 return swizzle;
1593 }
1594
1595 void
1596 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
1597
1598 /**
1599 * Subsurface of an anv_image.
1600 */
1601 struct anv_surface {
1602 /** Valid only if isl_surf::size > 0. */
1603 struct isl_surf isl;
1604
1605 /**
1606 * Offset from VkImage's base address, as bound by vkBindImageMemory().
1607 */
1608 uint32_t offset;
1609 };
1610
1611 struct anv_image {
1612 VkImageType type;
1613 /* The original VkFormat provided by the client. This may not match any
1614 * of the actual surface formats.
1615 */
1616 VkFormat vk_format;
1617 VkImageAspectFlags aspects;
1618 VkExtent3D extent;
1619 uint32_t levels;
1620 uint32_t array_size;
1621 uint32_t samples; /**< VkImageCreateInfo::samples */
1622 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1623 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1624
1625 VkDeviceSize size;
1626 uint32_t alignment;
1627
1628 /* Set when bound */
1629 struct anv_bo *bo;
1630 VkDeviceSize offset;
1631
1632 /**
1633 * Image subsurfaces
1634 *
1635 * For each foo, anv_image::foo_surface is valid if and only if
1636 * anv_image::aspects has a foo aspect.
1637 *
1638 * The hardware requires that the depth buffer and stencil buffer be
1639 * separate surfaces. From Vulkan's perspective, though, depth and stencil
1640 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
1641 * allocate the depth and stencil buffers as separate surfaces in the same
1642 * bo.
1643 */
1644 union {
1645 struct anv_surface color_surface;
1646
1647 struct {
1648 struct anv_surface depth_surface;
1649 struct anv_surface stencil_surface;
1650 };
1651 };
1652
1653 /**
1654 * For color images, this is the aux usage for this image when not used as a
1655 * color attachment.
1656 *
1657 * For depth/stencil images, this is set to ISL_AUX_USAGE_HIZ if the image
1658 * has a HiZ buffer.
1659 */
1660 enum isl_aux_usage aux_usage;
1661
1662 struct anv_surface aux_surface;
1663 };
1664
1665 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
1666 static inline bool
1667 anv_can_sample_with_hiz(uint8_t gen, uint32_t samples)
1668 {
1669 return gen >= 8 && samples == 1;
1670 }
1671
1672 void
1673 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
1674 const struct anv_image *image,
1675 enum blorp_hiz_op op);
1676
1677 static inline uint32_t
1678 anv_get_layerCount(const struct anv_image *image,
1679 const VkImageSubresourceRange *range)
1680 {
1681 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1682 image->array_size - range->baseArrayLayer : range->layerCount;
1683 }
1684
1685 static inline uint32_t
1686 anv_get_levelCount(const struct anv_image *image,
1687 const VkImageSubresourceRange *range)
1688 {
1689 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1690 image->levels - range->baseMipLevel : range->levelCount;
1691 }
1692
1693
1694 struct anv_image_view {
1695 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
1696 struct anv_bo *bo;
1697 uint32_t offset; /**< Offset into bo. */
1698
1699 struct isl_view isl;
1700
1701 VkImageAspectFlags aspect_mask;
1702 VkFormat vk_format;
1703 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1704
1705 /** RENDER_SURFACE_STATE when using image as a sampler surface. */
1706 struct anv_state sampler_surface_state;
1707
1708 /**
1709 * RENDER_SURFACE_STATE when using image as a storage image. Separate states
1710 * for write-only and readable, using the real format for write-only and the
1711 * lowered format for readable.
1712 */
1713 struct anv_state storage_surface_state;
1714 struct anv_state writeonly_storage_surface_state;
1715
1716 struct brw_image_param storage_image_param;
1717 };
1718
1719 struct anv_image_create_info {
1720 const VkImageCreateInfo *vk_info;
1721
1722 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
1723 isl_tiling_flags_t isl_tiling_flags;
1724
1725 uint32_t stride;
1726 };
1727
1728 VkResult anv_image_create(VkDevice _device,
1729 const struct anv_image_create_info *info,
1730 const VkAllocationCallbacks* alloc,
1731 VkImage *pImage);
1732
1733 const struct anv_surface *
1734 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1735 VkImageAspectFlags aspect_mask);
1736
1737 struct anv_buffer_view {
1738 enum isl_format format; /**< VkBufferViewCreateInfo::format */
1739 struct anv_bo *bo;
1740 uint32_t offset; /**< Offset into bo. */
1741 uint64_t range; /**< VkBufferViewCreateInfo::range */
1742
1743 struct anv_state surface_state;
1744 struct anv_state storage_surface_state;
1745 struct anv_state writeonly_storage_surface_state;
1746
1747 struct brw_image_param storage_image_param;
1748 };
1749
1750 enum isl_format
1751 anv_isl_format_for_descriptor_type(VkDescriptorType type);
1752
1753 static inline struct VkExtent3D
1754 anv_sanitize_image_extent(const VkImageType imageType,
1755 const struct VkExtent3D imageExtent)
1756 {
1757 switch (imageType) {
1758 case VK_IMAGE_TYPE_1D:
1759 return (VkExtent3D) { imageExtent.width, 1, 1 };
1760 case VK_IMAGE_TYPE_2D:
1761 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1762 case VK_IMAGE_TYPE_3D:
1763 return imageExtent;
1764 default:
1765 unreachable("invalid image type");
1766 }
1767 }
1768
1769 static inline struct VkOffset3D
1770 anv_sanitize_image_offset(const VkImageType imageType,
1771 const struct VkOffset3D imageOffset)
1772 {
1773 switch (imageType) {
1774 case VK_IMAGE_TYPE_1D:
1775 return (VkOffset3D) { imageOffset.x, 0, 0 };
1776 case VK_IMAGE_TYPE_2D:
1777 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1778 case VK_IMAGE_TYPE_3D:
1779 return imageOffset;
1780 default:
1781 unreachable("invalid image type");
1782 }
1783 }
1784
1785
1786 void anv_fill_buffer_surface_state(struct anv_device *device,
1787 struct anv_state state,
1788 enum isl_format format,
1789 uint32_t offset, uint32_t range,
1790 uint32_t stride);
1791
1792 void anv_image_view_fill_image_param(struct anv_device *device,
1793 struct anv_image_view *view,
1794 struct brw_image_param *param);
1795 void anv_buffer_view_fill_image_param(struct anv_device *device,
1796 struct anv_buffer_view *view,
1797 struct brw_image_param *param);
1798
1799 struct anv_sampler {
1800 uint32_t state[4];
1801 };
1802
1803 struct anv_framebuffer {
1804 uint32_t width;
1805 uint32_t height;
1806 uint32_t layers;
1807
1808 uint32_t attachment_count;
1809 struct anv_image_view * attachments[0];
1810 };
1811
1812 struct anv_subpass {
1813 uint32_t input_count;
1814 uint32_t * input_attachments;
1815 uint32_t color_count;
1816 uint32_t * color_attachments;
1817 uint32_t * resolve_attachments;
1818
1819 /* TODO: Consider storing the depth/stencil VkAttachmentReference
1820 * instead of its two structure members (below) individually.
1821 */
1822 uint32_t depth_stencil_attachment;
1823 VkImageLayout depth_stencil_layout;
1824
1825 /** Subpass has a depth/stencil self-dependency */
1826 bool has_ds_self_dep;
1827
1828 /** Subpass has at least one resolve attachment */
1829 bool has_resolve;
1830 };
1831
1832 enum anv_subpass_usage {
1833 ANV_SUBPASS_USAGE_DRAW = (1 << 0),
1834 ANV_SUBPASS_USAGE_INPUT = (1 << 1),
1835 ANV_SUBPASS_USAGE_RESOLVE_SRC = (1 << 2),
1836 ANV_SUBPASS_USAGE_RESOLVE_DST = (1 << 3),
1837 };
1838
1839 struct anv_render_pass_attachment {
1840 /* TODO: Consider using VkAttachmentDescription instead of storing each of
1841 * its members individually.
1842 */
1843 VkFormat format;
1844 uint32_t samples;
1845 VkImageUsageFlags usage;
1846 VkAttachmentLoadOp load_op;
1847 VkAttachmentStoreOp store_op;
1848 VkAttachmentLoadOp stencil_load_op;
1849 VkImageLayout initial_layout;
1850 VkImageLayout final_layout;
1851
1852 /* An array, indexed by subpass id, of how the attachment will be used. */
1853 enum anv_subpass_usage * subpass_usage;
1854
1855 /* The subpass id in which the attachment will be used last. */
1856 uint32_t last_subpass_idx;
1857 };
1858
1859 struct anv_render_pass {
1860 uint32_t attachment_count;
1861 uint32_t subpass_count;
1862 uint32_t * subpass_attachments;
1863 enum anv_subpass_usage * subpass_usages;
1864 struct anv_render_pass_attachment * attachments;
1865 struct anv_subpass subpasses[0];
1866 };
1867
1868 struct anv_query_pool_slot {
1869 uint64_t begin;
1870 uint64_t end;
1871 uint64_t available;
1872 };
1873
1874 struct anv_query_pool {
1875 VkQueryType type;
1876 uint32_t slots;
1877 struct anv_bo bo;
1878 };
1879
1880 void *anv_lookup_entrypoint(const struct gen_device_info *devinfo,
1881 const char *name);
1882
1883 void anv_dump_image_to_ppm(struct anv_device *device,
1884 struct anv_image *image, unsigned miplevel,
1885 unsigned array_layer, VkImageAspectFlagBits aspect,
1886 const char *filename);
1887
1888 enum anv_dump_action {
1889 ANV_DUMP_FRAMEBUFFERS_BIT = 0x1,
1890 };
1891
1892 void anv_dump_start(struct anv_device *device, enum anv_dump_action actions);
1893 void anv_dump_finish(void);
1894
1895 void anv_dump_add_framebuffer(struct anv_cmd_buffer *cmd_buffer,
1896 struct anv_framebuffer *fb);
1897
1898 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
1899 \
1900 static inline struct __anv_type * \
1901 __anv_type ## _from_handle(__VkType _handle) \
1902 { \
1903 return (struct __anv_type *) _handle; \
1904 } \
1905 \
1906 static inline __VkType \
1907 __anv_type ## _to_handle(struct __anv_type *_obj) \
1908 { \
1909 return (__VkType) _obj; \
1910 }
1911
1912 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
1913 \
1914 static inline struct __anv_type * \
1915 __anv_type ## _from_handle(__VkType _handle) \
1916 { \
1917 return (struct __anv_type *)(uintptr_t) _handle; \
1918 } \
1919 \
1920 static inline __VkType \
1921 __anv_type ## _to_handle(struct __anv_type *_obj) \
1922 { \
1923 return (__VkType)(uintptr_t) _obj; \
1924 }
1925
1926 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
1927 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
1928
1929 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer, VkCommandBuffer)
1930 ANV_DEFINE_HANDLE_CASTS(anv_device, VkDevice)
1931 ANV_DEFINE_HANDLE_CASTS(anv_instance, VkInstance)
1932 ANV_DEFINE_HANDLE_CASTS(anv_physical_device, VkPhysicalDevice)
1933 ANV_DEFINE_HANDLE_CASTS(anv_queue, VkQueue)
1934
1935 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
1936 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
1937 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
1938 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
1939 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
1940 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
1941 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
1942 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence, VkFence)
1943 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event, VkEvent)
1944 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer, VkFramebuffer)
1945 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image, VkImage)
1946 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, VkImageView);
1947 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache, VkPipelineCache)
1948 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, VkPipeline)
1949 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout, VkPipelineLayout)
1950 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, VkQueryPool)
1951 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass, VkRenderPass)
1952 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, VkSampler)
1953 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module, VkShaderModule)
1954
1955 /* Gen-specific function declarations */
1956 #ifdef genX
1957 # include "anv_genX.h"
1958 #else
1959 # define genX(x) gen7_##x
1960 # include "anv_genX.h"
1961 # undef genX
1962 # define genX(x) gen75_##x
1963 # include "anv_genX.h"
1964 # undef genX
1965 # define genX(x) gen8_##x
1966 # include "anv_genX.h"
1967 # undef genX
1968 # define genX(x) gen9_##x
1969 # include "anv_genX.h"
1970 # undef genX
1971 #endif
1972
1973 #ifdef __cplusplus
1974 }
1975 #endif
1976
1977 #endif /* ANV_PRIVATE_H */