e2914a2800fd06cf54854d6d03e391c39ed239ca
[mesa.git] / src / intel / vulkan / anv_private.h
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef ANV_PRIVATE_H
25 #define ANV_PRIVATE_H
26
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdbool.h>
30 #include <pthread.h>
31 #include <assert.h>
32 #include <stdint.h>
33 #include "drm-uapi/i915_drm.h"
34
35 #ifdef HAVE_VALGRIND
36 #include <valgrind.h>
37 #include <memcheck.h>
38 #define VG(x) x
39 #ifndef NDEBUG
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
41 #endif
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
61 #include "util/vma.h"
62 #include "util/xmlconfig.h"
63 #include "vk_alloc.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 struct anv_batch;
75 struct anv_buffer;
76 struct anv_buffer_view;
77 struct anv_image_view;
78 struct anv_instance;
79
80 struct gen_aux_map_context;
81 struct gen_perf_config;
82
83 #include <vulkan/vulkan.h>
84 #include <vulkan/vulkan_intel.h>
85 #include <vulkan/vk_icd.h>
86
87 #include "anv_android.h"
88 #include "anv_entrypoints.h"
89 #include "anv_extensions.h"
90 #include "isl/isl.h"
91
92 #include "dev/gen_debug.h"
93 #include "common/intel_log.h"
94 #include "wsi_common.h"
95
96 #define NSEC_PER_SEC 1000000000ull
97
98 /* anv Virtual Memory Layout
99 * =========================
100 *
101 * When the anv driver is determining the virtual graphics addresses of memory
102 * objects itself using the softpin mechanism, the following memory ranges
103 * will be used.
104 *
105 * Three special considerations to notice:
106 *
107 * (1) the dynamic state pool is located within the same 4 GiB as the low
108 * heap. This is to work around a VF cache issue described in a comment in
109 * anv_physical_device_init_heaps.
110 *
111 * (2) the binding table pool is located at lower addresses than the surface
112 * state pool, within a 4 GiB range. This allows surface state base addresses
113 * to cover both binding tables (16 bit offsets) and surface states (32 bit
114 * offsets).
115 *
116 * (3) the last 4 GiB of the address space is withheld from the high
117 * heap. Various hardware units will read past the end of an object for
118 * various reasons. This healthy margin prevents reads from wrapping around
119 * 48-bit addresses.
120 */
121 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
122 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
123 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
124 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
125 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
126 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
127 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
128 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
129 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
130 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
131 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
133 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134
135 #define LOW_HEAP_SIZE \
136 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
137 #define DYNAMIC_STATE_POOL_SIZE \
138 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
139 #define BINDING_TABLE_POOL_SIZE \
140 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
141 #define SURFACE_STATE_POOL_SIZE \
142 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
143 #define INSTRUCTION_STATE_POOL_SIZE \
144 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
145 #define CLIENT_VISIBLE_HEAP_SIZE \
146 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147
148 /* Allowing different clear colors requires us to perform a depth resolve at
149 * the end of certain render passes. This is because while slow clears store
150 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
151 * See the PRMs for examples describing when additional resolves would be
152 * necessary. To enable fast clears without requiring extra resolves, we set
153 * the clear value to a globally-defined one. We could allow different values
154 * if the user doesn't expect coherent data during or after a render passes
155 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
156 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
157 * 1.0f seems to be the only value used. The only application that doesn't set
158 * this value does so through the usage of an seemingly uninitialized clear
159 * value.
160 */
161 #define ANV_HZ_FC_VAL 1.0f
162
163 #define MAX_VBS 28
164 #define MAX_XFB_BUFFERS 4
165 #define MAX_XFB_STREAMS 4
166 #define MAX_SETS 8
167 #define MAX_RTS 8
168 #define MAX_VIEWPORTS 16
169 #define MAX_SCISSORS 16
170 #define MAX_PUSH_CONSTANTS_SIZE 128
171 #define MAX_DYNAMIC_BUFFERS 16
172 #define MAX_IMAGES 64
173 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
174 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
175 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we
177 * use 64 here to avoid cache issues. This could most likely bring it back to
178 * 32 if we had different virtual addresses for the different views on a given
179 * GEM object.
180 */
181 #define ANV_UBO_ALIGNMENT 64
182 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
183 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
184
185 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
186 *
187 * "The surface state model is used when a Binding Table Index (specified
188 * in the message descriptor) of less than 240 is specified. In this model,
189 * the Binding Table Index is used to index into the binding table, and the
190 * binding table entry contains a pointer to the SURFACE_STATE."
191 *
192 * Binding table values above 240 are used for various things in the hardware
193 * such as stateless, stateless with incoherent cache, SLM, and bindless.
194 */
195 #define MAX_BINDING_TABLE_SIZE 240
196
197 /* The kernel relocation API has a limitation of a 32-bit delta value
198 * applied to the address before it is written which, in spite of it being
199 * unsigned, is treated as signed . Because of the way that this maps to
200 * the Vulkan API, we cannot handle an offset into a buffer that does not
201 * fit into a signed 32 bits. The only mechanism we have for dealing with
202 * this at the moment is to limit all VkDeviceMemory objects to a maximum
203 * of 2GB each. The Vulkan spec allows us to do this:
204 *
205 * "Some platforms may have a limit on the maximum size of a single
206 * allocation. For example, certain systems may fail to create
207 * allocations with a size greater than or equal to 4GB. Such a limit is
208 * implementation-dependent, and if such a failure occurs then the error
209 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
210 *
211 * We don't use vk_error here because it's not an error so much as an
212 * indication to the application that the allocation is too large.
213 */
214 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
215
216 #define ANV_SVGS_VB_INDEX MAX_VBS
217 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
218
219 /* We reserve this MI ALU register for the purpose of handling predication.
220 * Other code which uses the MI ALU should leave it alone.
221 */
222 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
223
224 /* For gen12 we set the streamout buffers using 4 separate commands
225 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
226 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
227 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
228 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
229 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
230 * 3DSTATE_SO_BUFFER_INDEX_0.
231 */
232 #define SO_BUFFER_INDEX_0_CMD 0x60
233 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
234
235 static inline uint32_t
236 align_down_npot_u32(uint32_t v, uint32_t a)
237 {
238 return v - (v % a);
239 }
240
241 static inline uint32_t
242 align_down_u32(uint32_t v, uint32_t a)
243 {
244 assert(a != 0 && a == (a & -a));
245 return v & ~(a - 1);
246 }
247
248 static inline uint32_t
249 align_u32(uint32_t v, uint32_t a)
250 {
251 assert(a != 0 && a == (a & -a));
252 return align_down_u32(v + a - 1, a);
253 }
254
255 static inline uint64_t
256 align_down_u64(uint64_t v, uint64_t a)
257 {
258 assert(a != 0 && a == (a & -a));
259 return v & ~(a - 1);
260 }
261
262 static inline uint64_t
263 align_u64(uint64_t v, uint64_t a)
264 {
265 return align_down_u64(v + a - 1, a);
266 }
267
268 static inline int32_t
269 align_i32(int32_t v, int32_t a)
270 {
271 assert(a != 0 && a == (a & -a));
272 return (v + a - 1) & ~(a - 1);
273 }
274
275 /** Alignment must be a power of 2. */
276 static inline bool
277 anv_is_aligned(uintmax_t n, uintmax_t a)
278 {
279 assert(a == (a & -a));
280 return (n & (a - 1)) == 0;
281 }
282
283 static inline uint32_t
284 anv_minify(uint32_t n, uint32_t levels)
285 {
286 if (unlikely(n == 0))
287 return 0;
288 else
289 return MAX2(n >> levels, 1);
290 }
291
292 static inline float
293 anv_clamp_f(float f, float min, float max)
294 {
295 assert(min < max);
296
297 if (f > max)
298 return max;
299 else if (f < min)
300 return min;
301 else
302 return f;
303 }
304
305 static inline bool
306 anv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
307 {
308 if (*inout_mask & clear_mask) {
309 *inout_mask &= ~clear_mask;
310 return true;
311 } else {
312 return false;
313 }
314 }
315
316 static inline union isl_color_value
317 vk_to_isl_color(VkClearColorValue color)
318 {
319 return (union isl_color_value) {
320 .u32 = {
321 color.uint32[0],
322 color.uint32[1],
323 color.uint32[2],
324 color.uint32[3],
325 },
326 };
327 }
328
329 static inline void *anv_unpack_ptr(uintptr_t ptr, int bits, int *flags)
330 {
331 uintptr_t mask = (1ull << bits) - 1;
332 *flags = ptr & mask;
333 return (void *) (ptr & ~mask);
334 }
335
336 static inline uintptr_t anv_pack_ptr(void *ptr, int bits, int flags)
337 {
338 uintptr_t value = (uintptr_t) ptr;
339 uintptr_t mask = (1ull << bits) - 1;
340 return value | (mask & flags);
341 }
342
343 #define for_each_bit(b, dword) \
344 for (uint32_t __dword = (dword); \
345 (b) = __builtin_ffs(__dword) - 1, __dword; \
346 __dword &= ~(1 << (b)))
347
348 #define typed_memcpy(dest, src, count) ({ \
349 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
350 memcpy((dest), (src), (count) * sizeof(*(src))); \
351 })
352
353 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
354 * to be added here in order to utilize mapping in debug/error/perf macros.
355 */
356 #define REPORT_OBJECT_TYPE(o) \
357 __builtin_choose_expr ( \
358 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
359 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
360 __builtin_choose_expr ( \
361 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
362 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
363 __builtin_choose_expr ( \
364 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
365 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
366 __builtin_choose_expr ( \
367 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
368 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
369 __builtin_choose_expr ( \
370 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
371 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
372 __builtin_choose_expr ( \
373 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
374 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
375 __builtin_choose_expr ( \
376 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
377 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
378 __builtin_choose_expr ( \
379 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
380 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
381 __builtin_choose_expr ( \
382 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
383 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
384 __builtin_choose_expr ( \
385 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
386 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
387 __builtin_choose_expr ( \
388 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
389 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
390 __builtin_choose_expr ( \
391 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
392 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
393 __builtin_choose_expr ( \
394 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
395 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
396 __builtin_choose_expr ( \
397 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
398 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
399 __builtin_choose_expr ( \
400 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
401 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
402 __builtin_choose_expr ( \
403 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
404 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
405 __builtin_choose_expr ( \
406 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
407 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
408 __builtin_choose_expr ( \
409 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
410 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
411 __builtin_choose_expr ( \
412 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
413 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
414 __builtin_choose_expr ( \
415 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
416 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
417 __builtin_choose_expr ( \
418 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
419 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
420 __builtin_choose_expr ( \
421 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
422 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
423 __builtin_choose_expr ( \
424 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
425 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
426 __builtin_choose_expr ( \
427 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
428 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
429 __builtin_choose_expr ( \
430 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
431 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
432 __builtin_choose_expr ( \
433 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
434 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
435 __builtin_choose_expr ( \
436 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
437 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
438 __builtin_choose_expr ( \
439 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
440 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
441 __builtin_choose_expr ( \
442 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
443 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
444 __builtin_choose_expr ( \
445 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
446 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
447 __builtin_choose_expr ( \
448 __builtin_types_compatible_p (__typeof (o), void*), \
449 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
450 /* The void expression results in a compile-time error \
451 when assigning the result to something. */ \
452 (void)0)))))))))))))))))))))))))))))))
453
454 /* Whenever we generate an error, pass it through this function. Useful for
455 * debugging, where we can break on it. Only call at error site, not when
456 * propagating errors. Might be useful to plug in a stack trace here.
457 */
458
459 VkResult __vk_errorv(struct anv_instance *instance, const void *object,
460 VkDebugReportObjectTypeEXT type, VkResult error,
461 const char *file, int line, const char *format,
462 va_list args);
463
464 VkResult __vk_errorf(struct anv_instance *instance, const void *object,
465 VkDebugReportObjectTypeEXT type, VkResult error,
466 const char *file, int line, const char *format, ...)
467 anv_printflike(7, 8);
468
469 #ifdef DEBUG
470 #define vk_error(error) __vk_errorf(NULL, NULL,\
471 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
472 error, __FILE__, __LINE__, NULL)
473 #define vk_errorfi(instance, obj, error, format, ...)\
474 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
475 __FILE__, __LINE__, format, ## __VA_ARGS__)
476 #define vk_errorf(device, obj, error, format, ...)\
477 vk_errorfi(anv_device_instance_or_null(device),\
478 obj, error, format, ## __VA_ARGS__)
479 #else
480 #define vk_error(error) error
481 #define vk_errorfi(instance, obj, error, format, ...) error
482 #define vk_errorf(device, obj, error, format, ...) error
483 #endif
484
485 /**
486 * Warn on ignored extension structs.
487 *
488 * The Vulkan spec requires us to ignore unsupported or unknown structs in
489 * a pNext chain. In debug mode, emitting warnings for ignored structs may
490 * help us discover structs that we should not have ignored.
491 *
492 *
493 * From the Vulkan 1.0.38 spec:
494 *
495 * Any component of the implementation (the loader, any enabled layers,
496 * and drivers) must skip over, without processing (other than reading the
497 * sType and pNext members) any chained structures with sType values not
498 * defined by extensions supported by that component.
499 */
500 #define anv_debug_ignored_stype(sType) \
501 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
502
503 void __anv_perf_warn(struct anv_device *device, const void *object,
504 VkDebugReportObjectTypeEXT type, const char *file,
505 int line, const char *format, ...)
506 anv_printflike(6, 7);
507 void anv_loge(const char *format, ...) anv_printflike(1, 2);
508 void anv_loge_v(const char *format, va_list va);
509
510 /**
511 * Print a FINISHME message, including its source location.
512 */
513 #define anv_finishme(format, ...) \
514 do { \
515 static bool reported = false; \
516 if (!reported) { \
517 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
518 ##__VA_ARGS__); \
519 reported = true; \
520 } \
521 } while (0)
522
523 /**
524 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
525 */
526 #define anv_perf_warn(instance, obj, format, ...) \
527 do { \
528 static bool reported = false; \
529 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
530 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
531 format, ##__VA_ARGS__); \
532 reported = true; \
533 } \
534 } while (0)
535
536 /* A non-fatal assert. Useful for debugging. */
537 #ifdef DEBUG
538 #define anv_assert(x) ({ \
539 if (unlikely(!(x))) \
540 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
541 })
542 #else
543 #define anv_assert(x)
544 #endif
545
546 /* A multi-pointer allocator
547 *
548 * When copying data structures from the user (such as a render pass), it's
549 * common to need to allocate data for a bunch of different things. Instead
550 * of doing several allocations and having to handle all of the error checking
551 * that entails, it can be easier to do a single allocation. This struct
552 * helps facilitate that. The intended usage looks like this:
553 *
554 * ANV_MULTIALLOC(ma)
555 * anv_multialloc_add(&ma, &main_ptr, 1);
556 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
557 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
558 *
559 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
560 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
561 */
562 struct anv_multialloc {
563 size_t size;
564 size_t align;
565
566 uint32_t ptr_count;
567 void **ptrs[8];
568 };
569
570 #define ANV_MULTIALLOC_INIT \
571 ((struct anv_multialloc) { 0, })
572
573 #define ANV_MULTIALLOC(_name) \
574 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
575
576 __attribute__((always_inline))
577 static inline void
578 _anv_multialloc_add(struct anv_multialloc *ma,
579 void **ptr, size_t size, size_t align)
580 {
581 size_t offset = align_u64(ma->size, align);
582 ma->size = offset + size;
583 ma->align = MAX2(ma->align, align);
584
585 /* Store the offset in the pointer. */
586 *ptr = (void *)(uintptr_t)offset;
587
588 assert(ma->ptr_count < ARRAY_SIZE(ma->ptrs));
589 ma->ptrs[ma->ptr_count++] = ptr;
590 }
591
592 #define anv_multialloc_add_size(_ma, _ptr, _size) \
593 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
594
595 #define anv_multialloc_add(_ma, _ptr, _count) \
596 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
597
598 __attribute__((always_inline))
599 static inline void *
600 anv_multialloc_alloc(struct anv_multialloc *ma,
601 const VkAllocationCallbacks *alloc,
602 VkSystemAllocationScope scope)
603 {
604 void *ptr = vk_alloc(alloc, ma->size, ma->align, scope);
605 if (!ptr)
606 return NULL;
607
608 /* Fill out each of the pointers with their final value.
609 *
610 * for (uint32_t i = 0; i < ma->ptr_count; i++)
611 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
612 *
613 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
614 * constant, GCC is incapable of figuring this out and unrolling the loop
615 * so we have to give it a little help.
616 */
617 STATIC_ASSERT(ARRAY_SIZE(ma->ptrs) == 8);
618 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
619 if ((_i) < ma->ptr_count) \
620 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
621 _ANV_MULTIALLOC_UPDATE_POINTER(0);
622 _ANV_MULTIALLOC_UPDATE_POINTER(1);
623 _ANV_MULTIALLOC_UPDATE_POINTER(2);
624 _ANV_MULTIALLOC_UPDATE_POINTER(3);
625 _ANV_MULTIALLOC_UPDATE_POINTER(4);
626 _ANV_MULTIALLOC_UPDATE_POINTER(5);
627 _ANV_MULTIALLOC_UPDATE_POINTER(6);
628 _ANV_MULTIALLOC_UPDATE_POINTER(7);
629 #undef _ANV_MULTIALLOC_UPDATE_POINTER
630
631 return ptr;
632 }
633
634 __attribute__((always_inline))
635 static inline void *
636 anv_multialloc_alloc2(struct anv_multialloc *ma,
637 const VkAllocationCallbacks *parent_alloc,
638 const VkAllocationCallbacks *alloc,
639 VkSystemAllocationScope scope)
640 {
641 return anv_multialloc_alloc(ma, alloc ? alloc : parent_alloc, scope);
642 }
643
644 struct anv_bo {
645 uint32_t gem_handle;
646
647 uint32_t refcount;
648
649 /* Index into the current validation list. This is used by the
650 * validation list building alrogithm to track which buffers are already
651 * in the validation list so that we can ensure uniqueness.
652 */
653 uint32_t index;
654
655 /* Index for use with util_sparse_array_free_list */
656 uint32_t free_index;
657
658 /* Last known offset. This value is provided by the kernel when we
659 * execbuf and is used as the presumed offset for the next bunch of
660 * relocations.
661 */
662 uint64_t offset;
663
664 /** Size of the buffer not including implicit aux */
665 uint64_t size;
666
667 /* Map for internally mapped BOs.
668 *
669 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
670 */
671 void *map;
672
673 /** Size of the implicit CCS range at the end of the buffer
674 *
675 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
676 * page of main surface data maps to a 256B chunk of CCS data and that
677 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
678 * addresses in the main surface to virtual memory addresses for CCS data.
679 *
680 * Because we can't change these maps around easily and because Vulkan
681 * allows two VkImages to be bound to overlapping memory regions (as long
682 * as the app is careful), it's not feasible to make this mapping part of
683 * the image. (On Gen11 and earlier, the mapping was provided via
684 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
685 * Instead, we attach the CCS data directly to the buffer object and setup
686 * the AUX table mapping at BO creation time.
687 *
688 * This field is for internal tracking use by the BO allocator only and
689 * should not be touched by other parts of the code. If something wants to
690 * know if a BO has implicit CCS data, it should instead look at the
691 * has_implicit_ccs boolean below.
692 *
693 * This data is not included in maps of this buffer.
694 */
695 uint32_t _ccs_size;
696
697 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
698 uint32_t flags;
699
700 /** True if this BO may be shared with other processes */
701 bool is_external:1;
702
703 /** True if this BO is a wrapper
704 *
705 * When set to true, none of the fields in this BO are meaningful except
706 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
707 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
708 * is set in the physical device.
709 */
710 bool is_wrapper:1;
711
712 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
713 bool has_fixed_address:1;
714
715 /** True if this BO wraps a host pointer */
716 bool from_host_ptr:1;
717
718 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
719 bool has_client_visible_address:1;
720
721 /** True if this BO has implicit CCS data attached to it */
722 bool has_implicit_ccs:1;
723 };
724
725 static inline struct anv_bo *
726 anv_bo_ref(struct anv_bo *bo)
727 {
728 p_atomic_inc(&bo->refcount);
729 return bo;
730 }
731
732 static inline struct anv_bo *
733 anv_bo_unwrap(struct anv_bo *bo)
734 {
735 while (bo->is_wrapper)
736 bo = bo->map;
737 return bo;
738 }
739
740 /* Represents a lock-free linked list of "free" things. This is used by
741 * both the block pool and the state pools. Unfortunately, in order to
742 * solve the ABA problem, we can't use a single uint32_t head.
743 */
744 union anv_free_list {
745 struct {
746 uint32_t offset;
747
748 /* A simple count that is incremented every time the head changes. */
749 uint32_t count;
750 };
751 /* Make sure it's aligned to 64 bits. This will make atomic operations
752 * faster on 32 bit platforms.
753 */
754 uint64_t u64 __attribute__ ((aligned (8)));
755 };
756
757 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
758
759 struct anv_block_state {
760 union {
761 struct {
762 uint32_t next;
763 uint32_t end;
764 };
765 /* Make sure it's aligned to 64 bits. This will make atomic operations
766 * faster on 32 bit platforms.
767 */
768 uint64_t u64 __attribute__ ((aligned (8)));
769 };
770 };
771
772 #define anv_block_pool_foreach_bo(bo, pool) \
773 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
774 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
775 _pp_bo++)
776
777 #define ANV_MAX_BLOCK_POOL_BOS 20
778
779 struct anv_block_pool {
780 struct anv_device *device;
781 bool use_softpin;
782
783 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
784 * around the actual BO so that we grow the pool after the wrapper BO has
785 * been put in a relocation list. This is only used in the non-softpin
786 * case.
787 */
788 struct anv_bo wrapper_bo;
789
790 struct anv_bo *bos[ANV_MAX_BLOCK_POOL_BOS];
791 struct anv_bo *bo;
792 uint32_t nbos;
793
794 uint64_t size;
795
796 /* The address where the start of the pool is pinned. The various bos that
797 * are created as the pool grows will have addresses in the range
798 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
799 */
800 uint64_t start_address;
801
802 /* The offset from the start of the bo to the "center" of the block
803 * pool. Pointers to allocated blocks are given by
804 * bo.map + center_bo_offset + offsets.
805 */
806 uint32_t center_bo_offset;
807
808 /* Current memory map of the block pool. This pointer may or may not
809 * point to the actual beginning of the block pool memory. If
810 * anv_block_pool_alloc_back has ever been called, then this pointer
811 * will point to the "center" position of the buffer and all offsets
812 * (negative or positive) given out by the block pool alloc functions
813 * will be valid relative to this pointer.
814 *
815 * In particular, map == bo.map + center_offset
816 *
817 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
818 * since it will handle the softpin case as well, where this points to NULL.
819 */
820 void *map;
821 int fd;
822
823 /**
824 * Array of mmaps and gem handles owned by the block pool, reclaimed when
825 * the block pool is destroyed.
826 */
827 struct u_vector mmap_cleanups;
828
829 struct anv_block_state state;
830
831 struct anv_block_state back_state;
832 };
833
834 /* Block pools are backed by a fixed-size 1GB memfd */
835 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
836
837 /* The center of the block pool is also the middle of the memfd. This may
838 * change in the future if we decide differently for some reason.
839 */
840 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
841
842 static inline uint32_t
843 anv_block_pool_size(struct anv_block_pool *pool)
844 {
845 return pool->state.end + pool->back_state.end;
846 }
847
848 struct anv_state {
849 int32_t offset;
850 uint32_t alloc_size;
851 void *map;
852 uint32_t idx;
853 };
854
855 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
856
857 struct anv_fixed_size_state_pool {
858 union anv_free_list free_list;
859 struct anv_block_state block;
860 };
861
862 #define ANV_MIN_STATE_SIZE_LOG2 6
863 #define ANV_MAX_STATE_SIZE_LOG2 21
864
865 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
866
867 struct anv_free_entry {
868 uint32_t next;
869 struct anv_state state;
870 };
871
872 struct anv_state_table {
873 struct anv_device *device;
874 int fd;
875 struct anv_free_entry *map;
876 uint32_t size;
877 struct anv_block_state state;
878 struct u_vector cleanups;
879 };
880
881 struct anv_state_pool {
882 struct anv_block_pool block_pool;
883
884 /* Offset into the relevant state base address where the state pool starts
885 * allocating memory.
886 */
887 int32_t start_offset;
888
889 struct anv_state_table table;
890
891 /* The size of blocks which will be allocated from the block pool */
892 uint32_t block_size;
893
894 /** Free list for "back" allocations */
895 union anv_free_list back_alloc_free_list;
896
897 struct anv_fixed_size_state_pool buckets[ANV_STATE_BUCKETS];
898 };
899
900 struct anv_state_reserved_pool {
901 struct anv_state_pool *pool;
902 union anv_free_list reserved_blocks;
903 uint32_t count;
904 };
905
906 struct anv_state_stream {
907 struct anv_state_pool *state_pool;
908
909 /* The size of blocks to allocate from the state pool */
910 uint32_t block_size;
911
912 /* Current block we're allocating from */
913 struct anv_state block;
914
915 /* Offset into the current block at which to allocate the next state */
916 uint32_t next;
917
918 /* List of all blocks allocated from this pool */
919 struct util_dynarray all_blocks;
920 };
921
922 /* The block_pool functions exported for testing only. The block pool should
923 * only be used via a state pool (see below).
924 */
925 VkResult anv_block_pool_init(struct anv_block_pool *pool,
926 struct anv_device *device,
927 uint64_t start_address,
928 uint32_t initial_size);
929 void anv_block_pool_finish(struct anv_block_pool *pool);
930 int32_t anv_block_pool_alloc(struct anv_block_pool *pool,
931 uint32_t block_size, uint32_t *padding);
932 int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool,
933 uint32_t block_size);
934 void* anv_block_pool_map(struct anv_block_pool *pool, int32_t offset, uint32_t
935 size);
936
937 VkResult anv_state_pool_init(struct anv_state_pool *pool,
938 struct anv_device *device,
939 uint64_t base_address,
940 int32_t start_offset,
941 uint32_t block_size);
942 void anv_state_pool_finish(struct anv_state_pool *pool);
943 struct anv_state anv_state_pool_alloc(struct anv_state_pool *pool,
944 uint32_t state_size, uint32_t alignment);
945 struct anv_state anv_state_pool_alloc_back(struct anv_state_pool *pool);
946 void anv_state_pool_free(struct anv_state_pool *pool, struct anv_state state);
947 void anv_state_stream_init(struct anv_state_stream *stream,
948 struct anv_state_pool *state_pool,
949 uint32_t block_size);
950 void anv_state_stream_finish(struct anv_state_stream *stream);
951 struct anv_state anv_state_stream_alloc(struct anv_state_stream *stream,
952 uint32_t size, uint32_t alignment);
953
954 void anv_state_reserved_pool_init(struct anv_state_reserved_pool *pool,
955 struct anv_state_pool *parent,
956 uint32_t count, uint32_t size,
957 uint32_t alignment);
958 void anv_state_reserved_pool_finish(struct anv_state_reserved_pool *pool);
959 struct anv_state anv_state_reserved_pool_alloc(struct anv_state_reserved_pool *pool);
960 void anv_state_reserved_pool_free(struct anv_state_reserved_pool *pool,
961 struct anv_state state);
962
963 VkResult anv_state_table_init(struct anv_state_table *table,
964 struct anv_device *device,
965 uint32_t initial_entries);
966 void anv_state_table_finish(struct anv_state_table *table);
967 VkResult anv_state_table_add(struct anv_state_table *table, uint32_t *idx,
968 uint32_t count);
969 void anv_free_list_push(union anv_free_list *list,
970 struct anv_state_table *table,
971 uint32_t idx, uint32_t count);
972 struct anv_state* anv_free_list_pop(union anv_free_list *list,
973 struct anv_state_table *table);
974
975
976 static inline struct anv_state *
977 anv_state_table_get(struct anv_state_table *table, uint32_t idx)
978 {
979 return &table->map[idx].state;
980 }
981 /**
982 * Implements a pool of re-usable BOs. The interface is identical to that
983 * of block_pool except that each block is its own BO.
984 */
985 struct anv_bo_pool {
986 struct anv_device *device;
987
988 struct util_sparse_array_free_list free_list[16];
989 };
990
991 void anv_bo_pool_init(struct anv_bo_pool *pool, struct anv_device *device);
992 void anv_bo_pool_finish(struct anv_bo_pool *pool);
993 VkResult anv_bo_pool_alloc(struct anv_bo_pool *pool, uint32_t size,
994 struct anv_bo **bo_out);
995 void anv_bo_pool_free(struct anv_bo_pool *pool, struct anv_bo *bo);
996
997 struct anv_scratch_pool {
998 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
999 struct anv_bo *bos[16][MESA_SHADER_STAGES];
1000 };
1001
1002 void anv_scratch_pool_init(struct anv_device *device,
1003 struct anv_scratch_pool *pool);
1004 void anv_scratch_pool_finish(struct anv_device *device,
1005 struct anv_scratch_pool *pool);
1006 struct anv_bo *anv_scratch_pool_alloc(struct anv_device *device,
1007 struct anv_scratch_pool *pool,
1008 gl_shader_stage stage,
1009 unsigned per_thread_scratch);
1010
1011 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
1012 struct anv_bo_cache {
1013 struct util_sparse_array bo_map;
1014 pthread_mutex_t mutex;
1015 };
1016
1017 VkResult anv_bo_cache_init(struct anv_bo_cache *cache);
1018 void anv_bo_cache_finish(struct anv_bo_cache *cache);
1019
1020 struct anv_memory_type {
1021 /* Standard bits passed on to the client */
1022 VkMemoryPropertyFlags propertyFlags;
1023 uint32_t heapIndex;
1024 };
1025
1026 struct anv_memory_heap {
1027 /* Standard bits passed on to the client */
1028 VkDeviceSize size;
1029 VkMemoryHeapFlags flags;
1030
1031 /* Driver-internal book-keeping */
1032 VkDeviceSize used;
1033 };
1034
1035 struct anv_physical_device {
1036 struct vk_object_base base;
1037
1038 /* Link in anv_instance::physical_devices */
1039 struct list_head link;
1040
1041 struct anv_instance * instance;
1042 bool no_hw;
1043 char path[20];
1044 const char * name;
1045 struct {
1046 uint16_t domain;
1047 uint8_t bus;
1048 uint8_t device;
1049 uint8_t function;
1050 } pci_info;
1051 struct gen_device_info info;
1052 /** Amount of "GPU memory" we want to advertise
1053 *
1054 * Clearly, this value is bogus since Intel is a UMA architecture. On
1055 * gen7 platforms, we are limited by GTT size unless we want to implement
1056 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1057 * practically unlimited. However, we will never report more than 3/4 of
1058 * the total system ram to try and avoid running out of RAM.
1059 */
1060 bool supports_48bit_addresses;
1061 struct brw_compiler * compiler;
1062 struct isl_device isl_dev;
1063 struct gen_perf_config * perf;
1064 int cmd_parser_version;
1065 bool has_softpin;
1066 bool has_exec_async;
1067 bool has_exec_capture;
1068 bool has_exec_fence;
1069 bool has_syncobj;
1070 bool has_syncobj_wait;
1071 bool has_context_priority;
1072 bool has_context_isolation;
1073 bool has_mem_available;
1074 bool has_mmap_offset;
1075 uint64_t gtt_size;
1076
1077 bool use_softpin;
1078 bool always_use_bindless;
1079
1080 /** True if we can access buffers using A64 messages */
1081 bool has_a64_buffer_access;
1082 /** True if we can use bindless access for images */
1083 bool has_bindless_images;
1084 /** True if we can use bindless access for samplers */
1085 bool has_bindless_samplers;
1086
1087 /** True if this device has implicit AUX
1088 *
1089 * If true, CCS is handled as an implicit attachment to the BO rather than
1090 * as an explicitly bound surface.
1091 */
1092 bool has_implicit_ccs;
1093
1094 bool always_flush_cache;
1095
1096 struct anv_device_extension_table supported_extensions;
1097
1098 uint32_t eu_total;
1099 uint32_t subslice_total;
1100
1101 struct {
1102 uint32_t type_count;
1103 struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
1104 uint32_t heap_count;
1105 struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
1106 } memory;
1107
1108 uint8_t driver_build_sha1[20];
1109 uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
1110 uint8_t driver_uuid[VK_UUID_SIZE];
1111 uint8_t device_uuid[VK_UUID_SIZE];
1112
1113 struct disk_cache * disk_cache;
1114
1115 struct wsi_device wsi_device;
1116 int local_fd;
1117 int master_fd;
1118 };
1119
1120 struct anv_app_info {
1121 const char* app_name;
1122 uint32_t app_version;
1123 const char* engine_name;
1124 uint32_t engine_version;
1125 uint32_t api_version;
1126 };
1127
1128 struct anv_instance {
1129 struct vk_object_base base;
1130
1131 VkAllocationCallbacks alloc;
1132
1133 struct anv_app_info app_info;
1134
1135 struct anv_instance_extension_table enabled_extensions;
1136 struct anv_instance_dispatch_table dispatch;
1137 struct anv_physical_device_dispatch_table physical_device_dispatch;
1138 struct anv_device_dispatch_table device_dispatch;
1139
1140 bool physical_devices_enumerated;
1141 struct list_head physical_devices;
1142
1143 bool pipeline_cache_enabled;
1144
1145 struct vk_debug_report_instance debug_report_callbacks;
1146
1147 struct driOptionCache dri_options;
1148 struct driOptionCache available_dri_options;
1149 };
1150
1151 VkResult anv_init_wsi(struct anv_physical_device *physical_device);
1152 void anv_finish_wsi(struct anv_physical_device *physical_device);
1153
1154 uint32_t anv_physical_device_api_version(struct anv_physical_device *dev);
1155 bool anv_physical_device_extension_supported(struct anv_physical_device *dev,
1156 const char *name);
1157
1158 struct anv_queue_submit {
1159 struct anv_cmd_buffer * cmd_buffer;
1160
1161 uint32_t fence_count;
1162 uint32_t fence_array_length;
1163 struct drm_i915_gem_exec_fence * fences;
1164
1165 uint32_t temporary_semaphore_count;
1166 uint32_t temporary_semaphore_array_length;
1167 struct anv_semaphore_impl * temporary_semaphores;
1168
1169 /* Semaphores to be signaled with a SYNC_FD. */
1170 struct anv_semaphore ** sync_fd_semaphores;
1171 uint32_t sync_fd_semaphore_count;
1172 uint32_t sync_fd_semaphore_array_length;
1173
1174 /* Allocated only with non shareable timelines. */
1175 struct anv_timeline ** wait_timelines;
1176 uint32_t wait_timeline_count;
1177 uint32_t wait_timeline_array_length;
1178 uint64_t * wait_timeline_values;
1179
1180 struct anv_timeline ** signal_timelines;
1181 uint32_t signal_timeline_count;
1182 uint32_t signal_timeline_array_length;
1183 uint64_t * signal_timeline_values;
1184
1185 int in_fence;
1186 bool need_out_fence;
1187 int out_fence;
1188
1189 uint32_t fence_bo_count;
1190 uint32_t fence_bo_array_length;
1191 /* An array of struct anv_bo pointers with lower bit used as a flag to
1192 * signal we will wait on that BO (see anv_(un)pack_ptr).
1193 */
1194 uintptr_t * fence_bos;
1195
1196 const VkAllocationCallbacks * alloc;
1197 VkSystemAllocationScope alloc_scope;
1198
1199 struct anv_bo * simple_bo;
1200 uint32_t simple_bo_size;
1201
1202 struct list_head link;
1203 };
1204
1205 struct anv_queue {
1206 struct vk_object_base base;
1207
1208 struct anv_device * device;
1209
1210 /*
1211 * A list of struct anv_queue_submit to be submitted to i915.
1212 */
1213 struct list_head queued_submits;
1214
1215 VkDeviceQueueCreateFlags flags;
1216 };
1217
1218 struct anv_pipeline_cache {
1219 struct vk_object_base base;
1220 struct anv_device * device;
1221 pthread_mutex_t mutex;
1222
1223 struct hash_table * nir_cache;
1224
1225 struct hash_table * cache;
1226 };
1227
1228 struct nir_xfb_info;
1229 struct anv_pipeline_bind_map;
1230
1231 void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
1232 struct anv_device *device,
1233 bool cache_enabled);
1234 void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
1235
1236 struct anv_shader_bin *
1237 anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
1238 const void *key, uint32_t key_size);
1239 struct anv_shader_bin *
1240 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
1241 gl_shader_stage stage,
1242 const void *key_data, uint32_t key_size,
1243 const void *kernel_data, uint32_t kernel_size,
1244 const void *constant_data,
1245 uint32_t constant_data_size,
1246 const struct brw_stage_prog_data *prog_data,
1247 uint32_t prog_data_size,
1248 const struct brw_compile_stats *stats,
1249 uint32_t num_stats,
1250 const struct nir_xfb_info *xfb_info,
1251 const struct anv_pipeline_bind_map *bind_map);
1252
1253 struct anv_shader_bin *
1254 anv_device_search_for_kernel(struct anv_device *device,
1255 struct anv_pipeline_cache *cache,
1256 const void *key_data, uint32_t key_size,
1257 bool *user_cache_bit);
1258
1259 struct anv_shader_bin *
1260 anv_device_upload_kernel(struct anv_device *device,
1261 struct anv_pipeline_cache *cache,
1262 gl_shader_stage stage,
1263 const void *key_data, uint32_t key_size,
1264 const void *kernel_data, uint32_t kernel_size,
1265 const void *constant_data,
1266 uint32_t constant_data_size,
1267 const struct brw_stage_prog_data *prog_data,
1268 uint32_t prog_data_size,
1269 const struct brw_compile_stats *stats,
1270 uint32_t num_stats,
1271 const struct nir_xfb_info *xfb_info,
1272 const struct anv_pipeline_bind_map *bind_map);
1273
1274 struct nir_shader;
1275 struct nir_shader_compiler_options;
1276
1277 struct nir_shader *
1278 anv_device_search_for_nir(struct anv_device *device,
1279 struct anv_pipeline_cache *cache,
1280 const struct nir_shader_compiler_options *nir_options,
1281 unsigned char sha1_key[20],
1282 void *mem_ctx);
1283
1284 void
1285 anv_device_upload_nir(struct anv_device *device,
1286 struct anv_pipeline_cache *cache,
1287 const struct nir_shader *nir,
1288 unsigned char sha1_key[20]);
1289
1290 struct anv_device {
1291 struct vk_device vk;
1292
1293 struct anv_physical_device * physical;
1294 bool no_hw;
1295 struct gen_device_info info;
1296 struct isl_device isl_dev;
1297 int context_id;
1298 int fd;
1299 bool can_chain_batches;
1300 bool robust_buffer_access;
1301 struct anv_device_extension_table enabled_extensions;
1302 struct anv_device_dispatch_table dispatch;
1303
1304 pthread_mutex_t vma_mutex;
1305 struct util_vma_heap vma_lo;
1306 struct util_vma_heap vma_cva;
1307 struct util_vma_heap vma_hi;
1308
1309 /** List of all anv_device_memory objects */
1310 struct list_head memory_objects;
1311
1312 struct anv_bo_pool batch_bo_pool;
1313
1314 struct anv_bo_cache bo_cache;
1315
1316 struct anv_state_pool dynamic_state_pool;
1317 struct anv_state_pool instruction_state_pool;
1318 struct anv_state_pool binding_table_pool;
1319 struct anv_state_pool surface_state_pool;
1320
1321 /** BO used for various workarounds
1322 *
1323 * There are a number of workarounds on our hardware which require writing
1324 * data somewhere and it doesn't really matter where. For that, we use
1325 * this BO and just write to the first dword or so.
1326 *
1327 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1328 * For that, we use the high bytes (>= 1024) of the workaround BO.
1329 */
1330 struct anv_bo * workaround_bo;
1331 struct anv_bo * trivial_batch_bo;
1332 struct anv_bo * hiz_clear_bo;
1333 struct anv_state null_surface_state;
1334
1335 struct anv_pipeline_cache default_pipeline_cache;
1336 struct blorp_context blorp;
1337
1338 struct anv_state border_colors;
1339
1340 struct anv_state slice_hash;
1341
1342 struct anv_queue queue;
1343
1344 struct anv_scratch_pool scratch_pool;
1345
1346 pthread_mutex_t mutex;
1347 pthread_cond_t queue_submit;
1348 int _lost;
1349
1350 struct gen_batch_decode_ctx decoder_ctx;
1351 /*
1352 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1353 * the cmd_buffer's list.
1354 */
1355 struct anv_cmd_buffer *cmd_buffer_being_decoded;
1356
1357 int perf_fd; /* -1 if no opened */
1358 uint64_t perf_metric; /* 0 if unset */
1359
1360 struct gen_aux_map_context *aux_map_ctx;
1361 };
1362
1363 static inline struct anv_instance *
1364 anv_device_instance_or_null(const struct anv_device *device)
1365 {
1366 return device ? device->physical->instance : NULL;
1367 }
1368
1369 static inline struct anv_state_pool *
1370 anv_binding_table_pool(struct anv_device *device)
1371 {
1372 if (device->physical->use_softpin)
1373 return &device->binding_table_pool;
1374 else
1375 return &device->surface_state_pool;
1376 }
1377
1378 static inline struct anv_state
1379 anv_binding_table_pool_alloc(struct anv_device *device) {
1380 if (device->physical->use_softpin)
1381 return anv_state_pool_alloc(&device->binding_table_pool,
1382 device->binding_table_pool.block_size, 0);
1383 else
1384 return anv_state_pool_alloc_back(&device->surface_state_pool);
1385 }
1386
1387 static inline void
1388 anv_binding_table_pool_free(struct anv_device *device, struct anv_state state) {
1389 anv_state_pool_free(anv_binding_table_pool(device), state);
1390 }
1391
1392 static inline uint32_t
1393 anv_mocs_for_bo(const struct anv_device *device, const struct anv_bo *bo)
1394 {
1395 if (bo->is_external)
1396 return device->isl_dev.mocs.external;
1397 else
1398 return device->isl_dev.mocs.internal;
1399 }
1400
1401 void anv_device_init_blorp(struct anv_device *device);
1402 void anv_device_finish_blorp(struct anv_device *device);
1403
1404 void _anv_device_set_all_queue_lost(struct anv_device *device);
1405 VkResult _anv_device_set_lost(struct anv_device *device,
1406 const char *file, int line,
1407 const char *msg, ...)
1408 anv_printflike(4, 5);
1409 VkResult _anv_queue_set_lost(struct anv_queue *queue,
1410 const char *file, int line,
1411 const char *msg, ...)
1412 anv_printflike(4, 5);
1413 #define anv_device_set_lost(dev, ...) \
1414 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1415 #define anv_queue_set_lost(queue, ...) \
1416 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1417
1418 static inline bool
1419 anv_device_is_lost(struct anv_device *device)
1420 {
1421 return unlikely(p_atomic_read(&device->_lost));
1422 }
1423
1424 VkResult anv_device_query_status(struct anv_device *device);
1425
1426
1427 enum anv_bo_alloc_flags {
1428 /** Specifies that the BO must have a 32-bit address
1429 *
1430 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1431 */
1432 ANV_BO_ALLOC_32BIT_ADDRESS = (1 << 0),
1433
1434 /** Specifies that the BO may be shared externally */
1435 ANV_BO_ALLOC_EXTERNAL = (1 << 1),
1436
1437 /** Specifies that the BO should be mapped */
1438 ANV_BO_ALLOC_MAPPED = (1 << 2),
1439
1440 /** Specifies that the BO should be snooped so we get coherency */
1441 ANV_BO_ALLOC_SNOOPED = (1 << 3),
1442
1443 /** Specifies that the BO should be captured in error states */
1444 ANV_BO_ALLOC_CAPTURE = (1 << 4),
1445
1446 /** Specifies that the BO will have an address assigned by the caller
1447 *
1448 * Such BOs do not exist in any VMA heap.
1449 */
1450 ANV_BO_ALLOC_FIXED_ADDRESS = (1 << 5),
1451
1452 /** Enables implicit synchronization on the BO
1453 *
1454 * This is the opposite of EXEC_OBJECT_ASYNC.
1455 */
1456 ANV_BO_ALLOC_IMPLICIT_SYNC = (1 << 6),
1457
1458 /** Enables implicit synchronization on the BO
1459 *
1460 * This is equivalent to EXEC_OBJECT_WRITE.
1461 */
1462 ANV_BO_ALLOC_IMPLICIT_WRITE = (1 << 7),
1463
1464 /** Has an address which is visible to the client */
1465 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS = (1 << 8),
1466
1467 /** This buffer has implicit CCS data attached to it */
1468 ANV_BO_ALLOC_IMPLICIT_CCS = (1 << 9),
1469 };
1470
1471 VkResult anv_device_alloc_bo(struct anv_device *device, uint64_t size,
1472 enum anv_bo_alloc_flags alloc_flags,
1473 uint64_t explicit_address,
1474 struct anv_bo **bo);
1475 VkResult anv_device_import_bo_from_host_ptr(struct anv_device *device,
1476 void *host_ptr, uint32_t size,
1477 enum anv_bo_alloc_flags alloc_flags,
1478 uint64_t client_address,
1479 struct anv_bo **bo_out);
1480 VkResult anv_device_import_bo(struct anv_device *device, int fd,
1481 enum anv_bo_alloc_flags alloc_flags,
1482 uint64_t client_address,
1483 struct anv_bo **bo);
1484 VkResult anv_device_export_bo(struct anv_device *device,
1485 struct anv_bo *bo, int *fd_out);
1486 void anv_device_release_bo(struct anv_device *device,
1487 struct anv_bo *bo);
1488
1489 static inline struct anv_bo *
1490 anv_device_lookup_bo(struct anv_device *device, uint32_t gem_handle)
1491 {
1492 return util_sparse_array_get(&device->bo_cache.bo_map, gem_handle);
1493 }
1494
1495 VkResult anv_device_bo_busy(struct anv_device *device, struct anv_bo *bo);
1496 VkResult anv_device_wait(struct anv_device *device, struct anv_bo *bo,
1497 int64_t timeout);
1498
1499 VkResult anv_queue_init(struct anv_device *device, struct anv_queue *queue);
1500 void anv_queue_finish(struct anv_queue *queue);
1501
1502 VkResult anv_queue_execbuf_locked(struct anv_queue *queue, struct anv_queue_submit *submit);
1503 VkResult anv_queue_submit_simple_batch(struct anv_queue *queue,
1504 struct anv_batch *batch);
1505
1506 uint64_t anv_gettime_ns(void);
1507 uint64_t anv_get_absolute_timeout(uint64_t timeout);
1508
1509 void* anv_gem_mmap(struct anv_device *device,
1510 uint32_t gem_handle, uint64_t offset, uint64_t size, uint32_t flags);
1511 void anv_gem_munmap(struct anv_device *device, void *p, uint64_t size);
1512 uint32_t anv_gem_create(struct anv_device *device, uint64_t size);
1513 void anv_gem_close(struct anv_device *device, uint32_t gem_handle);
1514 uint32_t anv_gem_userptr(struct anv_device *device, void *mem, size_t size);
1515 int anv_gem_busy(struct anv_device *device, uint32_t gem_handle);
1516 int anv_gem_wait(struct anv_device *device, uint32_t gem_handle, int64_t *timeout_ns);
1517 int anv_gem_execbuffer(struct anv_device *device,
1518 struct drm_i915_gem_execbuffer2 *execbuf);
1519 int anv_gem_set_tiling(struct anv_device *device, uint32_t gem_handle,
1520 uint32_t stride, uint32_t tiling);
1521 int anv_gem_create_context(struct anv_device *device);
1522 bool anv_gem_has_context_priority(int fd);
1523 int anv_gem_destroy_context(struct anv_device *device, int context);
1524 int anv_gem_set_context_param(int fd, int context, uint32_t param,
1525 uint64_t value);
1526 int anv_gem_get_context_param(int fd, int context, uint32_t param,
1527 uint64_t *value);
1528 int anv_gem_get_param(int fd, uint32_t param);
1529 int anv_gem_get_tiling(struct anv_device *device, uint32_t gem_handle);
1530 bool anv_gem_get_bit6_swizzle(int fd, uint32_t tiling);
1531 int anv_gem_get_aperture(int fd, uint64_t *size);
1532 int anv_gem_gpu_get_reset_stats(struct anv_device *device,
1533 uint32_t *active, uint32_t *pending);
1534 int anv_gem_handle_to_fd(struct anv_device *device, uint32_t gem_handle);
1535 int anv_gem_reg_read(struct anv_device *device,
1536 uint32_t offset, uint64_t *result);
1537 uint32_t anv_gem_fd_to_handle(struct anv_device *device, int fd);
1538 int anv_gem_set_caching(struct anv_device *device, uint32_t gem_handle, uint32_t caching);
1539 int anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle,
1540 uint32_t read_domains, uint32_t write_domain);
1541 int anv_gem_sync_file_merge(struct anv_device *device, int fd1, int fd2);
1542 uint32_t anv_gem_syncobj_create(struct anv_device *device, uint32_t flags);
1543 void anv_gem_syncobj_destroy(struct anv_device *device, uint32_t handle);
1544 int anv_gem_syncobj_handle_to_fd(struct anv_device *device, uint32_t handle);
1545 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device *device, int fd);
1546 int anv_gem_syncobj_export_sync_file(struct anv_device *device,
1547 uint32_t handle);
1548 int anv_gem_syncobj_import_sync_file(struct anv_device *device,
1549 uint32_t handle, int fd);
1550 void anv_gem_syncobj_reset(struct anv_device *device, uint32_t handle);
1551 bool anv_gem_supports_syncobj_wait(int fd);
1552 int anv_gem_syncobj_wait(struct anv_device *device,
1553 uint32_t *handles, uint32_t num_handles,
1554 int64_t abs_timeout_ns, bool wait_all);
1555
1556 uint64_t anv_vma_alloc(struct anv_device *device,
1557 uint64_t size, uint64_t align,
1558 enum anv_bo_alloc_flags alloc_flags,
1559 uint64_t client_address);
1560 void anv_vma_free(struct anv_device *device,
1561 uint64_t address, uint64_t size);
1562
1563 struct anv_reloc_list {
1564 uint32_t num_relocs;
1565 uint32_t array_length;
1566 struct drm_i915_gem_relocation_entry * relocs;
1567 struct anv_bo ** reloc_bos;
1568 uint32_t dep_words;
1569 BITSET_WORD * deps;
1570 };
1571
1572 VkResult anv_reloc_list_init(struct anv_reloc_list *list,
1573 const VkAllocationCallbacks *alloc);
1574 void anv_reloc_list_finish(struct anv_reloc_list *list,
1575 const VkAllocationCallbacks *alloc);
1576
1577 VkResult anv_reloc_list_add(struct anv_reloc_list *list,
1578 const VkAllocationCallbacks *alloc,
1579 uint32_t offset, struct anv_bo *target_bo,
1580 uint32_t delta, uint64_t *address_u64_out);
1581
1582 struct anv_batch_bo {
1583 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1584 struct list_head link;
1585
1586 struct anv_bo * bo;
1587
1588 /* Bytes actually consumed in this batch BO */
1589 uint32_t length;
1590
1591 struct anv_reloc_list relocs;
1592 };
1593
1594 struct anv_batch {
1595 const VkAllocationCallbacks * alloc;
1596
1597 void * start;
1598 void * end;
1599 void * next;
1600
1601 struct anv_reloc_list * relocs;
1602
1603 /* This callback is called (with the associated user data) in the event
1604 * that the batch runs out of space.
1605 */
1606 VkResult (*extend_cb)(struct anv_batch *, void *);
1607 void * user_data;
1608
1609 /**
1610 * Current error status of the command buffer. Used to track inconsistent
1611 * or incomplete command buffer states that are the consequence of run-time
1612 * errors such as out of memory scenarios. We want to track this in the
1613 * batch because the command buffer object is not visible to some parts
1614 * of the driver.
1615 */
1616 VkResult status;
1617 };
1618
1619 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
1620 void anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other);
1621 uint64_t anv_batch_emit_reloc(struct anv_batch *batch,
1622 void *location, struct anv_bo *bo, uint32_t offset);
1623
1624 static inline VkResult
1625 anv_batch_set_error(struct anv_batch *batch, VkResult error)
1626 {
1627 assert(error != VK_SUCCESS);
1628 if (batch->status == VK_SUCCESS)
1629 batch->status = error;
1630 return batch->status;
1631 }
1632
1633 static inline bool
1634 anv_batch_has_error(struct anv_batch *batch)
1635 {
1636 return batch->status != VK_SUCCESS;
1637 }
1638
1639 struct anv_address {
1640 struct anv_bo *bo;
1641 uint32_t offset;
1642 };
1643
1644 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1645
1646 static inline bool
1647 anv_address_is_null(struct anv_address addr)
1648 {
1649 return addr.bo == NULL && addr.offset == 0;
1650 }
1651
1652 static inline uint64_t
1653 anv_address_physical(struct anv_address addr)
1654 {
1655 if (addr.bo && (addr.bo->flags & EXEC_OBJECT_PINNED))
1656 return gen_canonical_address(addr.bo->offset + addr.offset);
1657 else
1658 return gen_canonical_address(addr.offset);
1659 }
1660
1661 static inline struct anv_address
1662 anv_address_add(struct anv_address addr, uint64_t offset)
1663 {
1664 addr.offset += offset;
1665 return addr;
1666 }
1667
1668 static inline void
1669 write_reloc(const struct anv_device *device, void *p, uint64_t v, bool flush)
1670 {
1671 unsigned reloc_size = 0;
1672 if (device->info.gen >= 8) {
1673 reloc_size = sizeof(uint64_t);
1674 *(uint64_t *)p = gen_canonical_address(v);
1675 } else {
1676 reloc_size = sizeof(uint32_t);
1677 *(uint32_t *)p = v;
1678 }
1679
1680 if (flush && !device->info.has_llc)
1681 gen_flush_range(p, reloc_size);
1682 }
1683
1684 static inline uint64_t
1685 _anv_combine_address(struct anv_batch *batch, void *location,
1686 const struct anv_address address, uint32_t delta)
1687 {
1688 if (address.bo == NULL) {
1689 return address.offset + delta;
1690 } else {
1691 assert(batch->start <= location && location < batch->end);
1692
1693 return anv_batch_emit_reloc(batch, location, address.bo, address.offset + delta);
1694 }
1695 }
1696
1697 #define __gen_address_type struct anv_address
1698 #define __gen_user_data struct anv_batch
1699 #define __gen_combine_address _anv_combine_address
1700
1701 /* Wrapper macros needed to work around preprocessor argument issues. In
1702 * particular, arguments don't get pre-evaluated if they are concatenated.
1703 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1704 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1705 * We can work around this easily enough with these helpers.
1706 */
1707 #define __anv_cmd_length(cmd) cmd ## _length
1708 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1709 #define __anv_cmd_header(cmd) cmd ## _header
1710 #define __anv_cmd_pack(cmd) cmd ## _pack
1711 #define __anv_reg_num(reg) reg ## _num
1712
1713 #define anv_pack_struct(dst, struc, ...) do { \
1714 struct struc __template = { \
1715 __VA_ARGS__ \
1716 }; \
1717 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1718 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1719 } while (0)
1720
1721 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1722 void *__dst = anv_batch_emit_dwords(batch, n); \
1723 if (__dst) { \
1724 struct cmd __template = { \
1725 __anv_cmd_header(cmd), \
1726 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1727 __VA_ARGS__ \
1728 }; \
1729 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1730 } \
1731 __dst; \
1732 })
1733
1734 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1735 do { \
1736 uint32_t *dw; \
1737 \
1738 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1739 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1740 if (!dw) \
1741 break; \
1742 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1743 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1744 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1745 } while (0)
1746
1747 #define anv_batch_emit(batch, cmd, name) \
1748 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1749 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1750 __builtin_expect(_dst != NULL, 1); \
1751 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1752 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1753 _dst = NULL; \
1754 }))
1755
1756 struct anv_device_memory {
1757 struct vk_object_base base;
1758
1759 struct list_head link;
1760
1761 struct anv_bo * bo;
1762 struct anv_memory_type * type;
1763 VkDeviceSize map_size;
1764 void * map;
1765
1766 /* If set, we are holding reference to AHardwareBuffer
1767 * which we must release when memory is freed.
1768 */
1769 struct AHardwareBuffer * ahw;
1770
1771 /* If set, this memory comes from a host pointer. */
1772 void * host_ptr;
1773 };
1774
1775 /**
1776 * Header for Vertex URB Entry (VUE)
1777 */
1778 struct anv_vue_header {
1779 uint32_t Reserved;
1780 uint32_t RTAIndex; /* RenderTargetArrayIndex */
1781 uint32_t ViewportIndex;
1782 float PointWidth;
1783 };
1784
1785 /** Struct representing a sampled image descriptor
1786 *
1787 * This descriptor layout is used for sampled images, bare sampler, and
1788 * combined image/sampler descriptors.
1789 */
1790 struct anv_sampled_image_descriptor {
1791 /** Bindless image handle
1792 *
1793 * This is expected to already be shifted such that the 20-bit
1794 * SURFACE_STATE table index is in the top 20 bits.
1795 */
1796 uint32_t image;
1797
1798 /** Bindless sampler handle
1799 *
1800 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1801 * to the dynamic state base address.
1802 */
1803 uint32_t sampler;
1804 };
1805
1806 struct anv_texture_swizzle_descriptor {
1807 /** Texture swizzle
1808 *
1809 * See also nir_intrinsic_channel_select_intel
1810 */
1811 uint8_t swizzle[4];
1812
1813 /** Unused padding to ensure the struct is a multiple of 64 bits */
1814 uint32_t _pad;
1815 };
1816
1817 /** Struct representing a storage image descriptor */
1818 struct anv_storage_image_descriptor {
1819 /** Bindless image handles
1820 *
1821 * These are expected to already be shifted such that the 20-bit
1822 * SURFACE_STATE table index is in the top 20 bits.
1823 */
1824 uint32_t read_write;
1825 uint32_t write_only;
1826 };
1827
1828 /** Struct representing a address/range descriptor
1829 *
1830 * The fields of this struct correspond directly to the data layout of
1831 * nir_address_format_64bit_bounded_global addresses. The last field is the
1832 * offset in the NIR address so it must be zero so that when you load the
1833 * descriptor you get a pointer to the start of the range.
1834 */
1835 struct anv_address_range_descriptor {
1836 uint64_t address;
1837 uint32_t range;
1838 uint32_t zero;
1839 };
1840
1841 enum anv_descriptor_data {
1842 /** The descriptor contains a BTI reference to a surface state */
1843 ANV_DESCRIPTOR_SURFACE_STATE = (1 << 0),
1844 /** The descriptor contains a BTI reference to a sampler state */
1845 ANV_DESCRIPTOR_SAMPLER_STATE = (1 << 1),
1846 /** The descriptor contains an actual buffer view */
1847 ANV_DESCRIPTOR_BUFFER_VIEW = (1 << 2),
1848 /** The descriptor contains auxiliary image layout data */
1849 ANV_DESCRIPTOR_IMAGE_PARAM = (1 << 3),
1850 /** The descriptor contains auxiliary image layout data */
1851 ANV_DESCRIPTOR_INLINE_UNIFORM = (1 << 4),
1852 /** anv_address_range_descriptor with a buffer address and range */
1853 ANV_DESCRIPTOR_ADDRESS_RANGE = (1 << 5),
1854 /** Bindless surface handle */
1855 ANV_DESCRIPTOR_SAMPLED_IMAGE = (1 << 6),
1856 /** Storage image handles */
1857 ANV_DESCRIPTOR_STORAGE_IMAGE = (1 << 7),
1858 /** Storage image handles */
1859 ANV_DESCRIPTOR_TEXTURE_SWIZZLE = (1 << 8),
1860 };
1861
1862 struct anv_descriptor_set_binding_layout {
1863 #ifndef NDEBUG
1864 /* The type of the descriptors in this binding */
1865 VkDescriptorType type;
1866 #endif
1867
1868 /* Flags provided when this binding was created */
1869 VkDescriptorBindingFlagsEXT flags;
1870
1871 /* Bitfield representing the type of data this descriptor contains */
1872 enum anv_descriptor_data data;
1873
1874 /* Maximum number of YCbCr texture/sampler planes */
1875 uint8_t max_plane_count;
1876
1877 /* Number of array elements in this binding (or size in bytes for inline
1878 * uniform data)
1879 */
1880 uint16_t array_size;
1881
1882 /* Index into the flattend descriptor set */
1883 uint16_t descriptor_index;
1884
1885 /* Index into the dynamic state array for a dynamic buffer */
1886 int16_t dynamic_offset_index;
1887
1888 /* Index into the descriptor set buffer views */
1889 int16_t buffer_view_index;
1890
1891 /* Offset into the descriptor buffer where this descriptor lives */
1892 uint32_t descriptor_offset;
1893
1894 /* Immutable samplers (or NULL if no immutable samplers) */
1895 struct anv_sampler **immutable_samplers;
1896 };
1897
1898 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout *layout);
1899
1900 unsigned anv_descriptor_type_size(const struct anv_physical_device *pdevice,
1901 VkDescriptorType type);
1902
1903 bool anv_descriptor_supports_bindless(const struct anv_physical_device *pdevice,
1904 const struct anv_descriptor_set_binding_layout *binding,
1905 bool sampler);
1906
1907 bool anv_descriptor_requires_bindless(const struct anv_physical_device *pdevice,
1908 const struct anv_descriptor_set_binding_layout *binding,
1909 bool sampler);
1910
1911 struct anv_descriptor_set_layout {
1912 struct vk_object_base base;
1913
1914 /* Descriptor set layouts can be destroyed at almost any time */
1915 uint32_t ref_cnt;
1916
1917 /* Number of bindings in this descriptor set */
1918 uint16_t binding_count;
1919
1920 /* Total size of the descriptor set with room for all array entries */
1921 uint16_t size;
1922
1923 /* Shader stages affected by this descriptor set */
1924 uint16_t shader_stages;
1925
1926 /* Number of buffer views in this descriptor set */
1927 uint16_t buffer_view_count;
1928
1929 /* Number of dynamic offsets used by this descriptor set */
1930 uint16_t dynamic_offset_count;
1931
1932 /* For each shader stage, which offsets apply to that stage */
1933 uint16_t stage_dynamic_offsets[MESA_SHADER_STAGES];
1934
1935 /* Size of the descriptor buffer for this descriptor set */
1936 uint32_t descriptor_buffer_size;
1937
1938 /* Bindings in this descriptor set */
1939 struct anv_descriptor_set_binding_layout binding[0];
1940 };
1941
1942 void anv_descriptor_set_layout_destroy(struct anv_device *device,
1943 struct anv_descriptor_set_layout *layout);
1944
1945 static inline void
1946 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout *layout)
1947 {
1948 assert(layout && layout->ref_cnt >= 1);
1949 p_atomic_inc(&layout->ref_cnt);
1950 }
1951
1952 static inline void
1953 anv_descriptor_set_layout_unref(struct anv_device *device,
1954 struct anv_descriptor_set_layout *layout)
1955 {
1956 assert(layout && layout->ref_cnt >= 1);
1957 if (p_atomic_dec_zero(&layout->ref_cnt))
1958 anv_descriptor_set_layout_destroy(device, layout);
1959 }
1960
1961 struct anv_descriptor {
1962 VkDescriptorType type;
1963
1964 union {
1965 struct {
1966 VkImageLayout layout;
1967 struct anv_image_view *image_view;
1968 struct anv_sampler *sampler;
1969 };
1970
1971 struct {
1972 struct anv_buffer *buffer;
1973 uint64_t offset;
1974 uint64_t range;
1975 };
1976
1977 struct anv_buffer_view *buffer_view;
1978 };
1979 };
1980
1981 struct anv_descriptor_set {
1982 struct vk_object_base base;
1983
1984 struct anv_descriptor_pool *pool;
1985 struct anv_descriptor_set_layout *layout;
1986 uint32_t size;
1987
1988 /* State relative to anv_descriptor_pool::bo */
1989 struct anv_state desc_mem;
1990 /* Surface state for the descriptor buffer */
1991 struct anv_state desc_surface_state;
1992
1993 uint32_t buffer_view_count;
1994 struct anv_buffer_view *buffer_views;
1995
1996 /* Link to descriptor pool's desc_sets list . */
1997 struct list_head pool_link;
1998
1999 struct anv_descriptor descriptors[0];
2000 };
2001
2002 struct anv_buffer_view {
2003 struct vk_object_base base;
2004
2005 enum isl_format format; /**< VkBufferViewCreateInfo::format */
2006 uint64_t range; /**< VkBufferViewCreateInfo::range */
2007
2008 struct anv_address address;
2009
2010 struct anv_state surface_state;
2011 struct anv_state storage_surface_state;
2012 struct anv_state writeonly_storage_surface_state;
2013
2014 struct brw_image_param storage_image_param;
2015 };
2016
2017 struct anv_push_descriptor_set {
2018 struct anv_descriptor_set set;
2019
2020 /* Put this field right behind anv_descriptor_set so it fills up the
2021 * descriptors[0] field. */
2022 struct anv_descriptor descriptors[MAX_PUSH_DESCRIPTORS];
2023
2024 /** True if the descriptor set buffer has been referenced by a draw or
2025 * dispatch command.
2026 */
2027 bool set_used_on_gpu;
2028
2029 struct anv_buffer_view buffer_views[MAX_PUSH_DESCRIPTORS];
2030 };
2031
2032 struct anv_descriptor_pool {
2033 struct vk_object_base base;
2034
2035 uint32_t size;
2036 uint32_t next;
2037 uint32_t free_list;
2038
2039 struct anv_bo *bo;
2040 struct util_vma_heap bo_heap;
2041
2042 struct anv_state_stream surface_state_stream;
2043 void *surface_state_free_list;
2044
2045 struct list_head desc_sets;
2046
2047 char data[0];
2048 };
2049
2050 enum anv_descriptor_template_entry_type {
2051 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE,
2052 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER,
2053 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2054 };
2055
2056 struct anv_descriptor_template_entry {
2057 /* The type of descriptor in this entry */
2058 VkDescriptorType type;
2059
2060 /* Binding in the descriptor set */
2061 uint32_t binding;
2062
2063 /* Offset at which to write into the descriptor set binding */
2064 uint32_t array_element;
2065
2066 /* Number of elements to write into the descriptor set binding */
2067 uint32_t array_count;
2068
2069 /* Offset into the user provided data */
2070 size_t offset;
2071
2072 /* Stride between elements into the user provided data */
2073 size_t stride;
2074 };
2075
2076 struct anv_descriptor_update_template {
2077 struct vk_object_base base;
2078
2079 VkPipelineBindPoint bind_point;
2080
2081 /* The descriptor set this template corresponds to. This value is only
2082 * valid if the template was created with the templateType
2083 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2084 */
2085 uint8_t set;
2086
2087 /* Number of entries in this template */
2088 uint32_t entry_count;
2089
2090 /* Entries of the template */
2091 struct anv_descriptor_template_entry entries[0];
2092 };
2093
2094 size_t
2095 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout *layout);
2096
2097 void
2098 anv_descriptor_set_write_image_view(struct anv_device *device,
2099 struct anv_descriptor_set *set,
2100 const VkDescriptorImageInfo * const info,
2101 VkDescriptorType type,
2102 uint32_t binding,
2103 uint32_t element);
2104
2105 void
2106 anv_descriptor_set_write_buffer_view(struct anv_device *device,
2107 struct anv_descriptor_set *set,
2108 VkDescriptorType type,
2109 struct anv_buffer_view *buffer_view,
2110 uint32_t binding,
2111 uint32_t element);
2112
2113 void
2114 anv_descriptor_set_write_buffer(struct anv_device *device,
2115 struct anv_descriptor_set *set,
2116 struct anv_state_stream *alloc_stream,
2117 VkDescriptorType type,
2118 struct anv_buffer *buffer,
2119 uint32_t binding,
2120 uint32_t element,
2121 VkDeviceSize offset,
2122 VkDeviceSize range);
2123 void
2124 anv_descriptor_set_write_inline_uniform_data(struct anv_device *device,
2125 struct anv_descriptor_set *set,
2126 uint32_t binding,
2127 const void *data,
2128 size_t offset,
2129 size_t size);
2130
2131 void
2132 anv_descriptor_set_write_template(struct anv_device *device,
2133 struct anv_descriptor_set *set,
2134 struct anv_state_stream *alloc_stream,
2135 const struct anv_descriptor_update_template *template,
2136 const void *data);
2137
2138 VkResult
2139 anv_descriptor_set_create(struct anv_device *device,
2140 struct anv_descriptor_pool *pool,
2141 struct anv_descriptor_set_layout *layout,
2142 struct anv_descriptor_set **out_set);
2143
2144 void
2145 anv_descriptor_set_destroy(struct anv_device *device,
2146 struct anv_descriptor_pool *pool,
2147 struct anv_descriptor_set *set);
2148
2149 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2150 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2151 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2152 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2153 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2154 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2155
2156 struct anv_pipeline_binding {
2157 /** Index in the descriptor set
2158 *
2159 * This is a flattened index; the descriptor set layout is already taken
2160 * into account.
2161 */
2162 uint32_t index;
2163
2164 /** The descriptor set this surface corresponds to.
2165 *
2166 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2167 * binding is not a normal descriptor set but something else.
2168 */
2169 uint8_t set;
2170
2171 union {
2172 /** Plane in the binding index for images */
2173 uint8_t plane;
2174
2175 /** Input attachment index (relative to the subpass) */
2176 uint8_t input_attachment_index;
2177
2178 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2179 uint8_t dynamic_offset_index;
2180 };
2181
2182 /** For a storage image, whether it is write-only */
2183 uint8_t write_only;
2184
2185 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2186 * assuming POD zero-initialization.
2187 */
2188 uint8_t pad;
2189 };
2190
2191 struct anv_push_range {
2192 /** Index in the descriptor set */
2193 uint32_t index;
2194
2195 /** Descriptor set index */
2196 uint8_t set;
2197
2198 /** Dynamic offset index (for dynamic UBOs) */
2199 uint8_t dynamic_offset_index;
2200
2201 /** Start offset in units of 32B */
2202 uint8_t start;
2203
2204 /** Range in units of 32B */
2205 uint8_t length;
2206 };
2207
2208 struct anv_pipeline_layout {
2209 struct vk_object_base base;
2210
2211 struct {
2212 struct anv_descriptor_set_layout *layout;
2213 uint32_t dynamic_offset_start;
2214 } set[MAX_SETS];
2215
2216 uint32_t num_sets;
2217
2218 unsigned char sha1[20];
2219 };
2220
2221 struct anv_buffer {
2222 struct vk_object_base base;
2223
2224 struct anv_device * device;
2225 VkDeviceSize size;
2226
2227 VkBufferUsageFlags usage;
2228
2229 /* Set when bound */
2230 struct anv_address address;
2231 };
2232
2233 static inline uint64_t
2234 anv_buffer_get_range(struct anv_buffer *buffer, uint64_t offset, uint64_t range)
2235 {
2236 assert(offset <= buffer->size);
2237 if (range == VK_WHOLE_SIZE) {
2238 return buffer->size - offset;
2239 } else {
2240 assert(range + offset >= range);
2241 assert(range + offset <= buffer->size);
2242 return range;
2243 }
2244 }
2245
2246 enum anv_cmd_dirty_bits {
2247 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2248 ANV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2249 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2250 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2251 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2252 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2253 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2254 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2255 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2256 ANV_CMD_DIRTY_PIPELINE = 1 << 9,
2257 ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
2258 ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
2259 ANV_CMD_DIRTY_XFB_ENABLE = 1 << 12,
2260 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2261 };
2262 typedef uint32_t anv_cmd_dirty_mask_t;
2263
2264 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2265 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2266 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2267 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2268 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2269 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2270 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2271 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2272 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2273 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2274 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2275
2276 static inline enum anv_cmd_dirty_bits
2277 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
2278 {
2279 switch (vk_state) {
2280 case VK_DYNAMIC_STATE_VIEWPORT:
2281 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2282 case VK_DYNAMIC_STATE_SCISSOR:
2283 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
2284 case VK_DYNAMIC_STATE_LINE_WIDTH:
2285 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2286 case VK_DYNAMIC_STATE_DEPTH_BIAS:
2287 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2288 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
2289 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2290 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
2291 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2292 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
2293 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2294 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
2295 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2296 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
2297 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2298 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
2299 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
2300 default:
2301 assert(!"Unsupported dynamic state");
2302 return 0;
2303 }
2304 }
2305
2306
2307 enum anv_pipe_bits {
2308 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
2309 ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
2310 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT = (1 << 2),
2311 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT = (1 << 3),
2312 ANV_PIPE_VF_CACHE_INVALIDATE_BIT = (1 << 4),
2313 ANV_PIPE_DATA_CACHE_FLUSH_BIT = (1 << 5),
2314 ANV_PIPE_TILE_CACHE_FLUSH_BIT = (1 << 6),
2315 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT = (1 << 10),
2316 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
2317 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
2318 ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
2319 ANV_PIPE_CS_STALL_BIT = (1 << 20),
2320 ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),
2321
2322 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2323 * a flush has happened but not a CS stall. The next time we do any sort
2324 * of invalidation we need to insert a CS stall at that time. Otherwise,
2325 * we would have to CS stall on every flush which could be bad.
2326 */
2327 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT = (1 << 22),
2328
2329 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2330 * target operations related to transfer commands with VkBuffer as
2331 * destination are ongoing. Some operations like copies on the command
2332 * streamer might need to be aware of this to trigger the appropriate stall
2333 * before they can proceed with the copy.
2334 */
2335 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 23),
2336
2337 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2338 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2339 * done by writing the AUX-TT register.
2340 */
2341 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 24),
2342
2343 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2344 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2345 * implement a workaround for Gen9.
2346 */
2347 ANV_PIPE_POST_SYNC_BIT = (1 << 25),
2348 };
2349
2350 #define ANV_PIPE_FLUSH_BITS ( \
2351 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2352 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2353 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2354 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2355
2356 #define ANV_PIPE_STALL_BITS ( \
2357 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2358 ANV_PIPE_DEPTH_STALL_BIT | \
2359 ANV_PIPE_CS_STALL_BIT)
2360
2361 #define ANV_PIPE_INVALIDATE_BITS ( \
2362 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2363 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2364 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2365 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2366 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2367 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2368 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2369
2370 static inline enum anv_pipe_bits
2371 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags)
2372 {
2373 enum anv_pipe_bits pipe_bits = 0;
2374
2375 unsigned b;
2376 for_each_bit(b, flags) {
2377 switch ((VkAccessFlagBits)(1 << b)) {
2378 case VK_ACCESS_SHADER_WRITE_BIT:
2379 /* We're transitioning a buffer that was previously used as write
2380 * destination through the data port. To make its content available
2381 * to future operations, flush the data cache.
2382 */
2383 pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
2384 break;
2385 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2386 /* We're transitioning a buffer that was previously used as render
2387 * target. To make its content available to future operations, flush
2388 * the render target cache.
2389 */
2390 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2391 break;
2392 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2393 /* We're transitioning a buffer that was previously used as depth
2394 * buffer. To make its content available to future operations, flush
2395 * the depth cache.
2396 */
2397 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2398 break;
2399 case VK_ACCESS_TRANSFER_WRITE_BIT:
2400 /* We're transitioning a buffer that was previously used as a
2401 * transfer write destination. Generic write operations include color
2402 * & depth operations as well as buffer operations like :
2403 * - vkCmdClearColorImage()
2404 * - vkCmdClearDepthStencilImage()
2405 * - vkCmdBlitImage()
2406 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2407 *
2408 * Most of these operations are implemented using Blorp which writes
2409 * through the render target, so flush that cache to make it visible
2410 * to future operations. And for depth related operations we also
2411 * need to flush the depth cache.
2412 */
2413 pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
2414 pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
2415 break;
2416 case VK_ACCESS_MEMORY_WRITE_BIT:
2417 /* We're transitioning a buffer for generic write operations. Flush
2418 * all the caches.
2419 */
2420 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2421 break;
2422 default:
2423 break; /* Nothing to do */
2424 }
2425 }
2426
2427 return pipe_bits;
2428 }
2429
2430 static inline enum anv_pipe_bits
2431 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags)
2432 {
2433 enum anv_pipe_bits pipe_bits = 0;
2434
2435 unsigned b;
2436 for_each_bit(b, flags) {
2437 switch ((VkAccessFlagBits)(1 << b)) {
2438 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2439 /* Indirect draw commands take a buffer as input that we're going to
2440 * read from the command streamer to load some of the HW registers
2441 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2442 * command streamer stall so that all the cache flushes have
2443 * completed before the command streamer loads from memory.
2444 */
2445 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2446 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2447 * through a vertex buffer, so invalidate that cache.
2448 */
2449 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2450 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2451 * UBO from the buffer, so we need to invalidate constant cache.
2452 */
2453 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2454 break;
2455 case VK_ACCESS_INDEX_READ_BIT:
2456 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2457 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2458 * commands, so we invalidate the VF cache to make sure there is no
2459 * stale data when we start rendering.
2460 */
2461 pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT;
2462 break;
2463 case VK_ACCESS_UNIFORM_READ_BIT:
2464 /* We transitioning a buffer to be used as uniform data. Because
2465 * uniform is accessed through the data port & sampler, we need to
2466 * invalidate the texture cache (sampler) & constant cache (data
2467 * port) to avoid stale data.
2468 */
2469 pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
2470 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2471 break;
2472 case VK_ACCESS_SHADER_READ_BIT:
2473 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2474 case VK_ACCESS_TRANSFER_READ_BIT:
2475 /* Transitioning a buffer to be read through the sampler, so
2476 * invalidate the texture cache, we don't want any stale data.
2477 */
2478 pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
2479 break;
2480 case VK_ACCESS_MEMORY_READ_BIT:
2481 /* Transitioning a buffer for generic read, invalidate all the
2482 * caches.
2483 */
2484 pipe_bits |= ANV_PIPE_INVALIDATE_BITS;
2485 break;
2486 case VK_ACCESS_MEMORY_WRITE_BIT:
2487 /* Generic write, make sure all previously written things land in
2488 * memory.
2489 */
2490 pipe_bits |= ANV_PIPE_FLUSH_BITS;
2491 break;
2492 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT:
2493 /* Transitioning a buffer for conditional rendering. We'll load the
2494 * content of this buffer into HW registers using the command
2495 * streamer, so we need to stall the command streamer to make sure
2496 * any in-flight flush operations have completed.
2497 */
2498 pipe_bits |= ANV_PIPE_CS_STALL_BIT;
2499 break;
2500 default:
2501 break; /* Nothing to do */
2502 }
2503 }
2504
2505 return pipe_bits;
2506 }
2507
2508 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2509 VK_IMAGE_ASPECT_COLOR_BIT | \
2510 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2511 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2512 VK_IMAGE_ASPECT_PLANE_2_BIT)
2513 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2514 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2515 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2516 VK_IMAGE_ASPECT_PLANE_2_BIT)
2517
2518 struct anv_vertex_binding {
2519 struct anv_buffer * buffer;
2520 VkDeviceSize offset;
2521 };
2522
2523 struct anv_xfb_binding {
2524 struct anv_buffer * buffer;
2525 VkDeviceSize offset;
2526 VkDeviceSize size;
2527 };
2528
2529 struct anv_push_constants {
2530 /** Push constant data provided by the client through vkPushConstants */
2531 uint8_t client_data[MAX_PUSH_CONSTANTS_SIZE];
2532
2533 /** Dynamic offsets for dynamic UBOs and SSBOs */
2534 uint32_t dynamic_offsets[MAX_DYNAMIC_BUFFERS];
2535
2536 uint64_t push_reg_mask;
2537
2538 /** Pad out to a multiple of 32 bytes */
2539 uint32_t pad[2];
2540
2541 struct {
2542 /** Base workgroup ID
2543 *
2544 * Used for vkCmdDispatchBase.
2545 */
2546 uint32_t base_work_group_id[3];
2547
2548 /** Subgroup ID
2549 *
2550 * This is never set by software but is implicitly filled out when
2551 * uploading the push constants for compute shaders.
2552 */
2553 uint32_t subgroup_id;
2554 } cs;
2555 };
2556
2557 struct anv_dynamic_state {
2558 struct {
2559 uint32_t count;
2560 VkViewport viewports[MAX_VIEWPORTS];
2561 } viewport;
2562
2563 struct {
2564 uint32_t count;
2565 VkRect2D scissors[MAX_SCISSORS];
2566 } scissor;
2567
2568 float line_width;
2569
2570 struct {
2571 float bias;
2572 float clamp;
2573 float slope;
2574 } depth_bias;
2575
2576 float blend_constants[4];
2577
2578 struct {
2579 float min;
2580 float max;
2581 } depth_bounds;
2582
2583 struct {
2584 uint32_t front;
2585 uint32_t back;
2586 } stencil_compare_mask;
2587
2588 struct {
2589 uint32_t front;
2590 uint32_t back;
2591 } stencil_write_mask;
2592
2593 struct {
2594 uint32_t front;
2595 uint32_t back;
2596 } stencil_reference;
2597
2598 struct {
2599 uint32_t factor;
2600 uint16_t pattern;
2601 } line_stipple;
2602 };
2603
2604 extern const struct anv_dynamic_state default_dynamic_state;
2605
2606 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state *dest,
2607 const struct anv_dynamic_state *src,
2608 uint32_t copy_mask);
2609
2610 struct anv_surface_state {
2611 struct anv_state state;
2612 /** Address of the surface referred to by this state
2613 *
2614 * This address is relative to the start of the BO.
2615 */
2616 struct anv_address address;
2617 /* Address of the aux surface, if any
2618 *
2619 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2620 *
2621 * With the exception of gen8, the bottom 12 bits of this address' offset
2622 * include extra aux information.
2623 */
2624 struct anv_address aux_address;
2625 /* Address of the clear color, if any
2626 *
2627 * This address is relative to the start of the BO.
2628 */
2629 struct anv_address clear_address;
2630 };
2631
2632 /**
2633 * Attachment state when recording a renderpass instance.
2634 *
2635 * The clear value is valid only if there exists a pending clear.
2636 */
2637 struct anv_attachment_state {
2638 enum isl_aux_usage aux_usage;
2639 struct anv_surface_state color;
2640 struct anv_surface_state input;
2641
2642 VkImageLayout current_layout;
2643 VkImageLayout current_stencil_layout;
2644 VkImageAspectFlags pending_clear_aspects;
2645 VkImageAspectFlags pending_load_aspects;
2646 bool fast_clear;
2647 VkClearValue clear_value;
2648
2649 /* When multiview is active, attachments with a renderpass clear
2650 * operation have their respective layers cleared on the first
2651 * subpass that uses them, and only in that subpass. We keep track
2652 * of this using a bitfield to indicate which layers of an attachment
2653 * have not been cleared yet when multiview is active.
2654 */
2655 uint32_t pending_clear_views;
2656 struct anv_image_view * image_view;
2657 };
2658
2659 /** State tracking for vertex buffer flushes
2660 *
2661 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2662 * addresses. If you happen to have two vertex buffers which get placed
2663 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2664 * collisions. In order to solve this problem, we track vertex address ranges
2665 * which are live in the cache and invalidate the cache if one ever exceeds 32
2666 * bits.
2667 */
2668 struct anv_vb_cache_range {
2669 /* Virtual address at which the live vertex buffer cache range starts for
2670 * this vertex buffer index.
2671 */
2672 uint64_t start;
2673
2674 /* Virtual address of the byte after where vertex buffer cache range ends.
2675 * This is exclusive such that end - start is the size of the range.
2676 */
2677 uint64_t end;
2678 };
2679
2680 /** State tracking for particular pipeline bind point
2681 *
2682 * This struct is the base struct for anv_cmd_graphics_state and
2683 * anv_cmd_compute_state. These are used to track state which is bound to a
2684 * particular type of pipeline. Generic state that applies per-stage such as
2685 * binding table offsets and push constants is tracked generically with a
2686 * per-stage array in anv_cmd_state.
2687 */
2688 struct anv_cmd_pipeline_state {
2689 struct anv_descriptor_set *descriptors[MAX_SETS];
2690 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
2691 };
2692
2693 /** State tracking for graphics pipeline
2694 *
2695 * This has anv_cmd_pipeline_state as a base struct to track things which get
2696 * bound to a graphics pipeline. Along with general pipeline bind point state
2697 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2698 * state which is graphics-specific.
2699 */
2700 struct anv_cmd_graphics_state {
2701 struct anv_cmd_pipeline_state base;
2702
2703 struct anv_graphics_pipeline *pipeline;
2704
2705 anv_cmd_dirty_mask_t dirty;
2706 uint32_t vb_dirty;
2707
2708 struct anv_vb_cache_range ib_bound_range;
2709 struct anv_vb_cache_range ib_dirty_range;
2710 struct anv_vb_cache_range vb_bound_ranges[33];
2711 struct anv_vb_cache_range vb_dirty_ranges[33];
2712
2713 struct anv_dynamic_state dynamic;
2714
2715 struct {
2716 struct anv_buffer *index_buffer;
2717 uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2718 uint32_t index_offset;
2719 } gen7;
2720 };
2721
2722 /** State tracking for compute pipeline
2723 *
2724 * This has anv_cmd_pipeline_state as a base struct to track things which get
2725 * bound to a compute pipeline. Along with general pipeline bind point state
2726 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2727 * state which is compute-specific.
2728 */
2729 struct anv_cmd_compute_state {
2730 struct anv_cmd_pipeline_state base;
2731
2732 struct anv_compute_pipeline *pipeline;
2733
2734 bool pipeline_dirty;
2735
2736 struct anv_address num_workgroups;
2737 };
2738
2739 /** State required while building cmd buffer */
2740 struct anv_cmd_state {
2741 /* PIPELINE_SELECT.PipelineSelection */
2742 uint32_t current_pipeline;
2743 const struct gen_l3_config * current_l3_config;
2744 uint32_t last_aux_map_state;
2745
2746 struct anv_cmd_graphics_state gfx;
2747 struct anv_cmd_compute_state compute;
2748
2749 enum anv_pipe_bits pending_pipe_bits;
2750 VkShaderStageFlags descriptors_dirty;
2751 VkShaderStageFlags push_constants_dirty;
2752
2753 struct anv_framebuffer * framebuffer;
2754 struct anv_render_pass * pass;
2755 struct anv_subpass * subpass;
2756 VkRect2D render_area;
2757 uint32_t restart_index;
2758 struct anv_vertex_binding vertex_bindings[MAX_VBS];
2759 bool xfb_enabled;
2760 struct anv_xfb_binding xfb_bindings[MAX_XFB_BUFFERS];
2761 VkShaderStageFlags push_constant_stages;
2762 struct anv_push_constants push_constants[MESA_SHADER_STAGES];
2763 struct anv_state binding_tables[MESA_SHADER_STAGES];
2764 struct anv_state samplers[MESA_SHADER_STAGES];
2765
2766 unsigned char sampler_sha1s[MESA_SHADER_STAGES][20];
2767 unsigned char surface_sha1s[MESA_SHADER_STAGES][20];
2768 unsigned char push_sha1s[MESA_SHADER_STAGES][20];
2769
2770 /**
2771 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2772 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2773 * and before invoking the secondary in ExecuteCommands.
2774 */
2775 bool pma_fix_enabled;
2776
2777 /**
2778 * Whether or not we know for certain that HiZ is enabled for the current
2779 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2780 * enabled or not, this will be false.
2781 */
2782 bool hiz_enabled;
2783
2784 bool conditional_render_enabled;
2785
2786 /**
2787 * Last rendering scale argument provided to
2788 * genX(cmd_buffer_emit_hashing_mode)().
2789 */
2790 unsigned current_hash_scale;
2791
2792 /**
2793 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2794 * valid only when recording a render pass instance.
2795 */
2796 struct anv_attachment_state * attachments;
2797
2798 /**
2799 * Surface states for color render targets. These are stored in a single
2800 * flat array. For depth-stencil attachments, the surface state is simply
2801 * left blank.
2802 */
2803 struct anv_state attachment_states;
2804
2805 /**
2806 * A null surface state of the right size to match the framebuffer. This
2807 * is one of the states in attachment_states.
2808 */
2809 struct anv_state null_surface_state;
2810 };
2811
2812 struct anv_cmd_pool {
2813 struct vk_object_base base;
2814 VkAllocationCallbacks alloc;
2815 struct list_head cmd_buffers;
2816 };
2817
2818 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2819
2820 enum anv_cmd_buffer_exec_mode {
2821 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
2822 ANV_CMD_BUFFER_EXEC_MODE_EMIT,
2823 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT,
2824 ANV_CMD_BUFFER_EXEC_MODE_CHAIN,
2825 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN,
2826 };
2827
2828 struct anv_cmd_buffer {
2829 struct vk_object_base base;
2830
2831 struct anv_device * device;
2832
2833 struct anv_cmd_pool * pool;
2834 struct list_head pool_link;
2835
2836 struct anv_batch batch;
2837
2838 /* Fields required for the actual chain of anv_batch_bo's.
2839 *
2840 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2841 */
2842 struct list_head batch_bos;
2843 enum anv_cmd_buffer_exec_mode exec_mode;
2844
2845 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2846 * referenced by this command buffer
2847 *
2848 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2849 */
2850 struct u_vector seen_bbos;
2851
2852 /* A vector of int32_t's for every block of binding tables.
2853 *
2854 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2855 */
2856 struct u_vector bt_block_states;
2857 struct anv_state bt_next;
2858
2859 struct anv_reloc_list surface_relocs;
2860 /** Last seen surface state block pool center bo offset */
2861 uint32_t last_ss_pool_center;
2862
2863 /* Serial for tracking buffer completion */
2864 uint32_t serial;
2865
2866 /* Stream objects for storing temporary data */
2867 struct anv_state_stream surface_state_stream;
2868 struct anv_state_stream dynamic_state_stream;
2869
2870 VkCommandBufferUsageFlags usage_flags;
2871 VkCommandBufferLevel level;
2872
2873 struct anv_cmd_state state;
2874
2875 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2876 uint64_t intel_perf_marker;
2877 };
2878
2879 VkResult anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2880 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2881 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer);
2882 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer);
2883 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer *primary,
2884 struct anv_cmd_buffer *secondary);
2885 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer *cmd_buffer);
2886 VkResult anv_cmd_buffer_execbuf(struct anv_queue *queue,
2887 struct anv_cmd_buffer *cmd_buffer,
2888 const VkSemaphore *in_semaphores,
2889 const uint64_t *in_wait_values,
2890 uint32_t num_in_semaphores,
2891 const VkSemaphore *out_semaphores,
2892 const uint64_t *out_signal_values,
2893 uint32_t num_out_semaphores,
2894 VkFence fence);
2895
2896 VkResult anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer);
2897
2898 struct anv_state anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
2899 const void *data, uint32_t size, uint32_t alignment);
2900 struct anv_state anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
2901 uint32_t *a, uint32_t *b,
2902 uint32_t dwords, uint32_t alignment);
2903
2904 struct anv_address
2905 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer *cmd_buffer);
2906 struct anv_state
2907 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer *cmd_buffer,
2908 uint32_t entries, uint32_t *state_offset);
2909 struct anv_state
2910 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer *cmd_buffer);
2911 struct anv_state
2912 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer *cmd_buffer,
2913 uint32_t size, uint32_t alignment);
2914
2915 VkResult
2916 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer *cmd_buffer);
2917
2918 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer);
2919 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer *cmd_buffer,
2920 bool depth_clamp_enable);
2921 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
2922
2923 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
2924 struct anv_render_pass *pass,
2925 struct anv_framebuffer *framebuffer,
2926 const VkClearValue *clear_values);
2927
2928 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
2929
2930 struct anv_state
2931 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
2932 gl_shader_stage stage);
2933 struct anv_state
2934 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer);
2935
2936 const struct anv_image_view *
2937 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
2938
2939 VkResult
2940 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
2941 uint32_t num_entries,
2942 uint32_t *state_offset,
2943 struct anv_state *bt_state);
2944
2945 void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
2946
2947 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer);
2948
2949 enum anv_fence_type {
2950 ANV_FENCE_TYPE_NONE = 0,
2951 ANV_FENCE_TYPE_BO,
2952 ANV_FENCE_TYPE_WSI_BO,
2953 ANV_FENCE_TYPE_SYNCOBJ,
2954 ANV_FENCE_TYPE_WSI,
2955 };
2956
2957 enum anv_bo_fence_state {
2958 /** Indicates that this is a new (or newly reset fence) */
2959 ANV_BO_FENCE_STATE_RESET,
2960
2961 /** Indicates that this fence has been submitted to the GPU but is still
2962 * (as far as we know) in use by the GPU.
2963 */
2964 ANV_BO_FENCE_STATE_SUBMITTED,
2965
2966 ANV_BO_FENCE_STATE_SIGNALED,
2967 };
2968
2969 struct anv_fence_impl {
2970 enum anv_fence_type type;
2971
2972 union {
2973 /** Fence implementation for BO fences
2974 *
2975 * These fences use a BO and a set of CPU-tracked state flags. The BO
2976 * is added to the object list of the last execbuf call in a QueueSubmit
2977 * and is marked EXEC_WRITE. The state flags track when the BO has been
2978 * submitted to the kernel. We need to do this because Vulkan lets you
2979 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2980 * will say it's idle in this case.
2981 */
2982 struct {
2983 struct anv_bo *bo;
2984 enum anv_bo_fence_state state;
2985 } bo;
2986
2987 /** DRM syncobj handle for syncobj-based fences */
2988 uint32_t syncobj;
2989
2990 /** WSI fence */
2991 struct wsi_fence *fence_wsi;
2992 };
2993 };
2994
2995 struct anv_fence {
2996 struct vk_object_base base;
2997
2998 /* Permanent fence state. Every fence has some form of permanent state
2999 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
3000 * cross-process fences) or it could just be a dummy for use internally.
3001 */
3002 struct anv_fence_impl permanent;
3003
3004 /* Temporary fence state. A fence *may* have temporary state. That state
3005 * is added to the fence by an import operation and is reset back to
3006 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
3007 * state cannot be signaled because the fence must already be signaled
3008 * before the temporary state can be exported from the fence in the other
3009 * process and imported here.
3010 */
3011 struct anv_fence_impl temporary;
3012 };
3013
3014 void anv_fence_reset_temporary(struct anv_device *device,
3015 struct anv_fence *fence);
3016
3017 struct anv_event {
3018 struct vk_object_base base;
3019 uint64_t semaphore;
3020 struct anv_state state;
3021 };
3022
3023 enum anv_semaphore_type {
3024 ANV_SEMAPHORE_TYPE_NONE = 0,
3025 ANV_SEMAPHORE_TYPE_DUMMY,
3026 ANV_SEMAPHORE_TYPE_BO,
3027 ANV_SEMAPHORE_TYPE_WSI_BO,
3028 ANV_SEMAPHORE_TYPE_SYNC_FILE,
3029 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ,
3030 ANV_SEMAPHORE_TYPE_TIMELINE,
3031 };
3032
3033 struct anv_timeline_point {
3034 struct list_head link;
3035
3036 uint64_t serial;
3037
3038 /* Number of waiter on this point, when > 0 the point should not be garbage
3039 * collected.
3040 */
3041 int waiting;
3042
3043 /* BO used for synchronization. */
3044 struct anv_bo *bo;
3045 };
3046
3047 struct anv_timeline {
3048 pthread_mutex_t mutex;
3049 pthread_cond_t cond;
3050
3051 uint64_t highest_past;
3052 uint64_t highest_pending;
3053
3054 struct list_head points;
3055 struct list_head free_points;
3056 };
3057
3058 struct anv_semaphore_impl {
3059 enum anv_semaphore_type type;
3060
3061 union {
3062 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3063 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3064 * object list on any execbuf2 calls for which this semaphore is used as
3065 * a wait or signal fence. When used as a signal fence or when type ==
3066 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3067 */
3068 struct anv_bo *bo;
3069
3070 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3071 * If the semaphore is in the unsignaled state due to either just being
3072 * created or because it has been used for a wait, fd will be -1.
3073 */
3074 int fd;
3075
3076 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3077 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3078 * import so we don't need to bother with a userspace cache.
3079 */
3080 uint32_t syncobj;
3081
3082 /* Non shareable timeline semaphore
3083 *
3084 * Used when kernel don't have support for timeline semaphores.
3085 */
3086 struct anv_timeline timeline;
3087 };
3088 };
3089
3090 struct anv_semaphore {
3091 struct vk_object_base base;
3092
3093 uint32_t refcount;
3094
3095 /* Permanent semaphore state. Every semaphore has some form of permanent
3096 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3097 * (for cross-process semaphores0 or it could just be a dummy for use
3098 * internally.
3099 */
3100 struct anv_semaphore_impl permanent;
3101
3102 /* Temporary semaphore state. A semaphore *may* have temporary state.
3103 * That state is added to the semaphore by an import operation and is reset
3104 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3105 * semaphore with temporary state cannot be signaled because the semaphore
3106 * must already be signaled before the temporary state can be exported from
3107 * the semaphore in the other process and imported here.
3108 */
3109 struct anv_semaphore_impl temporary;
3110 };
3111
3112 void anv_semaphore_reset_temporary(struct anv_device *device,
3113 struct anv_semaphore *semaphore);
3114
3115 struct anv_shader_module {
3116 struct vk_object_base base;
3117
3118 unsigned char sha1[20];
3119 uint32_t size;
3120 char data[0];
3121 };
3122
3123 static inline gl_shader_stage
3124 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
3125 {
3126 assert(__builtin_popcount(vk_stage) == 1);
3127 return ffs(vk_stage) - 1;
3128 }
3129
3130 static inline VkShaderStageFlagBits
3131 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
3132 {
3133 return (1 << mesa_stage);
3134 }
3135
3136 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3137
3138 #define anv_foreach_stage(stage, stage_bits) \
3139 for (gl_shader_stage stage, \
3140 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3141 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3142 __tmp &= ~(1 << (stage)))
3143
3144 struct anv_pipeline_bind_map {
3145 unsigned char surface_sha1[20];
3146 unsigned char sampler_sha1[20];
3147 unsigned char push_sha1[20];
3148
3149 uint32_t surface_count;
3150 uint32_t sampler_count;
3151
3152 struct anv_pipeline_binding * surface_to_descriptor;
3153 struct anv_pipeline_binding * sampler_to_descriptor;
3154
3155 struct anv_push_range push_ranges[4];
3156 };
3157
3158 struct anv_shader_bin_key {
3159 uint32_t size;
3160 uint8_t data[0];
3161 };
3162
3163 struct anv_shader_bin {
3164 uint32_t ref_cnt;
3165
3166 gl_shader_stage stage;
3167
3168 const struct anv_shader_bin_key *key;
3169
3170 struct anv_state kernel;
3171 uint32_t kernel_size;
3172
3173 struct anv_state constant_data;
3174 uint32_t constant_data_size;
3175
3176 const struct brw_stage_prog_data *prog_data;
3177 uint32_t prog_data_size;
3178
3179 struct brw_compile_stats stats[3];
3180 uint32_t num_stats;
3181
3182 struct nir_xfb_info *xfb_info;
3183
3184 struct anv_pipeline_bind_map bind_map;
3185 };
3186
3187 struct anv_shader_bin *
3188 anv_shader_bin_create(struct anv_device *device,
3189 gl_shader_stage stage,
3190 const void *key, uint32_t key_size,
3191 const void *kernel, uint32_t kernel_size,
3192 const void *constant_data, uint32_t constant_data_size,
3193 const struct brw_stage_prog_data *prog_data,
3194 uint32_t prog_data_size,
3195 const struct brw_compile_stats *stats, uint32_t num_stats,
3196 const struct nir_xfb_info *xfb_info,
3197 const struct anv_pipeline_bind_map *bind_map);
3198
3199 void
3200 anv_shader_bin_destroy(struct anv_device *device, struct anv_shader_bin *shader);
3201
3202 static inline void
3203 anv_shader_bin_ref(struct anv_shader_bin *shader)
3204 {
3205 assert(shader && shader->ref_cnt >= 1);
3206 p_atomic_inc(&shader->ref_cnt);
3207 }
3208
3209 static inline void
3210 anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
3211 {
3212 assert(shader && shader->ref_cnt >= 1);
3213 if (p_atomic_dec_zero(&shader->ref_cnt))
3214 anv_shader_bin_destroy(device, shader);
3215 }
3216
3217 struct anv_pipeline_executable {
3218 gl_shader_stage stage;
3219
3220 struct brw_compile_stats stats;
3221
3222 char *nir;
3223 char *disasm;
3224 };
3225
3226 enum anv_pipeline_type {
3227 ANV_PIPELINE_GRAPHICS,
3228 ANV_PIPELINE_COMPUTE,
3229 };
3230
3231 struct anv_pipeline {
3232 struct vk_object_base base;
3233
3234 struct anv_device * device;
3235
3236 struct anv_batch batch;
3237 struct anv_reloc_list batch_relocs;
3238
3239 void * mem_ctx;
3240
3241 enum anv_pipeline_type type;
3242 VkPipelineCreateFlags flags;
3243
3244 struct util_dynarray executables;
3245
3246 const struct gen_l3_config * l3_config;
3247 };
3248
3249 struct anv_graphics_pipeline {
3250 struct anv_pipeline base;
3251
3252 uint32_t batch_data[512];
3253
3254 anv_cmd_dirty_mask_t dynamic_state_mask;
3255 struct anv_dynamic_state dynamic_state;
3256
3257 uint32_t topology;
3258
3259 struct anv_subpass * subpass;
3260
3261 struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
3262
3263 VkShaderStageFlags active_stages;
3264
3265 bool primitive_restart;
3266 bool writes_depth;
3267 bool depth_test_enable;
3268 bool writes_stencil;
3269 bool stencil_test_enable;
3270 bool depth_clamp_enable;
3271 bool depth_clip_enable;
3272 bool sample_shading_enable;
3273 bool kill_pixel;
3274 bool depth_bounds_test_enable;
3275
3276 /* When primitive replication is used, subpass->view_mask will describe what
3277 * views to replicate.
3278 */
3279 bool use_primitive_replication;
3280
3281 struct anv_state blend_state;
3282
3283 uint32_t vb_used;
3284 struct anv_pipeline_vertex_binding {
3285 uint32_t stride;
3286 bool instanced;
3287 uint32_t instance_divisor;
3288 } vb[MAX_VBS];
3289
3290 struct {
3291 uint32_t sf[7];
3292 uint32_t depth_stencil_state[3];
3293 } gen7;
3294
3295 struct {
3296 uint32_t sf[4];
3297 uint32_t raster[5];
3298 uint32_t wm_depth_stencil[3];
3299 } gen8;
3300
3301 struct {
3302 uint32_t wm_depth_stencil[4];
3303 } gen9;
3304 };
3305
3306 struct anv_compute_pipeline {
3307 struct anv_pipeline base;
3308
3309 struct anv_shader_bin * cs;
3310 uint32_t cs_right_mask;
3311 uint32_t batch_data[9];
3312 uint32_t interface_descriptor_data[8];
3313 };
3314
3315 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3316 static inline struct anv_##pipe_type##_pipeline * \
3317 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3318 { \
3319 assert(pipeline->type == pipe_enum); \
3320 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3321 }
3322
3323 ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS)
3324 ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE)
3325
3326 static inline bool
3327 anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
3328 gl_shader_stage stage)
3329 {
3330 return (pipeline->active_stages & mesa_to_vk_shader_stage(stage)) != 0;
3331 }
3332
3333 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3334 static inline const struct brw_##prefix##_prog_data * \
3335 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3336 { \
3337 if (anv_pipeline_has_stage(pipeline, stage)) { \
3338 return (const struct brw_##prefix##_prog_data *) \
3339 pipeline->shaders[stage]->prog_data; \
3340 } else { \
3341 return NULL; \
3342 } \
3343 }
3344
3345 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs, MESA_SHADER_VERTEX)
3346 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
3347 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
3348 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
3349 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
3350
3351 static inline const struct brw_cs_prog_data *
3352 get_cs_prog_data(const struct anv_compute_pipeline *pipeline)
3353 {
3354 assert(pipeline->cs);
3355 return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
3356 }
3357
3358 static inline const struct brw_vue_prog_data *
3359 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
3360 {
3361 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
3362 return &get_gs_prog_data(pipeline)->base;
3363 else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
3364 return &get_tes_prog_data(pipeline)->base;
3365 else
3366 return &get_vs_prog_data(pipeline)->base;
3367 }
3368
3369 VkResult
3370 anv_pipeline_init(struct anv_graphics_pipeline *pipeline, struct anv_device *device,
3371 struct anv_pipeline_cache *cache,
3372 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3373 const VkAllocationCallbacks *alloc);
3374
3375 VkResult
3376 anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
3377 struct anv_pipeline_cache *cache,
3378 const VkComputePipelineCreateInfo *info,
3379 const struct anv_shader_module *module,
3380 const char *entrypoint,
3381 const VkSpecializationInfo *spec_info);
3382
3383 uint32_t
3384 anv_cs_workgroup_size(const struct anv_compute_pipeline *pipeline);
3385
3386 uint32_t
3387 anv_cs_threads(const struct anv_compute_pipeline *pipeline);
3388
3389 struct anv_format_plane {
3390 enum isl_format isl_format:16;
3391 struct isl_swizzle swizzle;
3392
3393 /* Whether this plane contains chroma channels */
3394 bool has_chroma;
3395
3396 /* For downscaling of YUV planes */
3397 uint8_t denominator_scales[2];
3398
3399 /* How to map sampled ycbcr planes to a single 4 component element. */
3400 struct isl_swizzle ycbcr_swizzle;
3401
3402 /* What aspect is associated to this plane */
3403 VkImageAspectFlags aspect;
3404 };
3405
3406
3407 struct anv_format {
3408 struct anv_format_plane planes[3];
3409 VkFormat vk_format;
3410 uint8_t n_planes;
3411 bool can_ycbcr;
3412 };
3413
3414 /**
3415 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3416 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3417 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3418 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3419 */
3420 static inline uint32_t
3421 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects,
3422 VkImageAspectFlags aspect_mask)
3423 {
3424 switch (aspect_mask) {
3425 case VK_IMAGE_ASPECT_COLOR_BIT:
3426 case VK_IMAGE_ASPECT_DEPTH_BIT:
3427 case VK_IMAGE_ASPECT_PLANE_0_BIT:
3428 return 0;
3429 case VK_IMAGE_ASPECT_STENCIL_BIT:
3430 if ((image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) == 0)
3431 return 0;
3432 /* Fall-through */
3433 case VK_IMAGE_ASPECT_PLANE_1_BIT:
3434 return 1;
3435 case VK_IMAGE_ASPECT_PLANE_2_BIT:
3436 return 2;
3437 default:
3438 /* Purposefully assert with depth/stencil aspects. */
3439 unreachable("invalid image aspect");
3440 }
3441 }
3442
3443 static inline VkImageAspectFlags
3444 anv_plane_to_aspect(VkImageAspectFlags image_aspects,
3445 uint32_t plane)
3446 {
3447 if (image_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
3448 if (util_bitcount(image_aspects) > 1)
3449 return VK_IMAGE_ASPECT_PLANE_0_BIT << plane;
3450 return VK_IMAGE_ASPECT_COLOR_BIT;
3451 }
3452 if (image_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
3453 return VK_IMAGE_ASPECT_DEPTH_BIT << plane;
3454 assert(image_aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
3455 return VK_IMAGE_ASPECT_STENCIL_BIT;
3456 }
3457
3458 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3459 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3460
3461 const struct anv_format *
3462 anv_get_format(VkFormat format);
3463
3464 static inline uint32_t
3465 anv_get_format_planes(VkFormat vk_format)
3466 {
3467 const struct anv_format *format = anv_get_format(vk_format);
3468
3469 return format != NULL ? format->n_planes : 0;
3470 }
3471
3472 struct anv_format_plane
3473 anv_get_format_plane(const struct gen_device_info *devinfo, VkFormat vk_format,
3474 VkImageAspectFlagBits aspect, VkImageTiling tiling);
3475
3476 static inline enum isl_format
3477 anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
3478 VkImageAspectFlags aspect, VkImageTiling tiling)
3479 {
3480 return anv_get_format_plane(devinfo, vk_format, aspect, tiling).isl_format;
3481 }
3482
3483 bool anv_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
3484 VkImageCreateFlags create_flags,
3485 VkFormat vk_format,
3486 VkImageTiling vk_tiling,
3487 const VkImageFormatListCreateInfoKHR *fmt_list);
3488
3489 static inline struct isl_swizzle
3490 anv_swizzle_for_render(struct isl_swizzle swizzle)
3491 {
3492 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3493 * RGB as RGBA for texturing
3494 */
3495 assert(swizzle.a == ISL_CHANNEL_SELECT_ONE ||
3496 swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
3497
3498 /* But it doesn't matter what we render to that channel */
3499 swizzle.a = ISL_CHANNEL_SELECT_ALPHA;
3500
3501 return swizzle;
3502 }
3503
3504 void
3505 anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
3506
3507 /**
3508 * Subsurface of an anv_image.
3509 */
3510 struct anv_surface {
3511 /** Valid only if isl_surf::size_B > 0. */
3512 struct isl_surf isl;
3513
3514 /**
3515 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3516 */
3517 uint32_t offset;
3518 };
3519
3520 struct anv_image {
3521 struct vk_object_base base;
3522
3523 VkImageType type; /**< VkImageCreateInfo::imageType */
3524 /* The original VkFormat provided by the client. This may not match any
3525 * of the actual surface formats.
3526 */
3527 VkFormat vk_format;
3528 const struct anv_format *format;
3529
3530 VkImageAspectFlags aspects;
3531 VkExtent3D extent;
3532 uint32_t levels;
3533 uint32_t array_size;
3534 uint32_t samples; /**< VkImageCreateInfo::samples */
3535 uint32_t n_planes;
3536 VkImageUsageFlags usage; /**< VkImageCreateInfo::usage. */
3537 VkImageUsageFlags stencil_usage;
3538 VkImageCreateFlags create_flags; /* Flags used when creating image. */
3539 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
3540
3541 /** True if this is needs to be bound to an appropriately tiled BO.
3542 *
3543 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3544 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3545 * we require a dedicated allocation so that we can know to allocate a
3546 * tiled buffer.
3547 */
3548 bool needs_set_tiling;
3549
3550 /**
3551 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3552 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3553 */
3554 uint64_t drm_format_mod;
3555
3556 VkDeviceSize size;
3557 uint32_t alignment;
3558
3559 /* Whether the image is made of several underlying buffer objects rather a
3560 * single one with different offsets.
3561 */
3562 bool disjoint;
3563
3564 /* Image was created with external format. */
3565 bool external_format;
3566
3567 /**
3568 * Image subsurfaces
3569 *
3570 * For each foo, anv_image::planes[x].surface is valid if and only if
3571 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3572 * to figure the number associated with a given aspect.
3573 *
3574 * The hardware requires that the depth buffer and stencil buffer be
3575 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3576 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3577 * allocate the depth and stencil buffers as separate surfaces in the same
3578 * bo.
3579 *
3580 * Memory layout :
3581 *
3582 * -----------------------
3583 * | surface0 | /|\
3584 * ----------------------- |
3585 * | shadow surface0 | |
3586 * ----------------------- | Plane 0
3587 * | aux surface0 | |
3588 * ----------------------- |
3589 * | fast clear colors0 | \|/
3590 * -----------------------
3591 * | surface1 | /|\
3592 * ----------------------- |
3593 * | shadow surface1 | |
3594 * ----------------------- | Plane 1
3595 * | aux surface1 | |
3596 * ----------------------- |
3597 * | fast clear colors1 | \|/
3598 * -----------------------
3599 * | ... |
3600 * | |
3601 * -----------------------
3602 */
3603 struct {
3604 /**
3605 * Offset of the entire plane (whenever the image is disjoint this is
3606 * set to 0).
3607 */
3608 uint32_t offset;
3609
3610 VkDeviceSize size;
3611 uint32_t alignment;
3612
3613 struct anv_surface surface;
3614
3615 /**
3616 * A surface which shadows the main surface and may have different
3617 * tiling. This is used for sampling using a tiling that isn't supported
3618 * for other operations.
3619 */
3620 struct anv_surface shadow_surface;
3621
3622 /**
3623 * The base aux usage for this image. For color images, this can be
3624 * either CCS_E or CCS_D depending on whether or not we can reliably
3625 * leave CCS on all the time.
3626 */
3627 enum isl_aux_usage aux_usage;
3628
3629 struct anv_surface aux_surface;
3630
3631 /**
3632 * Offset of the fast clear state (used to compute the
3633 * fast_clear_state_offset of the following planes).
3634 */
3635 uint32_t fast_clear_state_offset;
3636
3637 /**
3638 * BO associated with this plane, set when bound.
3639 */
3640 struct anv_address address;
3641
3642 /**
3643 * When destroying the image, also free the bo.
3644 * */
3645 bool bo_is_owned;
3646 } planes[3];
3647 };
3648
3649 /* The ordering of this enum is important */
3650 enum anv_fast_clear_type {
3651 /** Image does not have/support any fast-clear blocks */
3652 ANV_FAST_CLEAR_NONE = 0,
3653 /** Image has/supports fast-clear but only to the default value */
3654 ANV_FAST_CLEAR_DEFAULT_VALUE = 1,
3655 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3656 ANV_FAST_CLEAR_ANY = 2,
3657 };
3658
3659 /* Returns the number of auxiliary buffer levels attached to an image. */
3660 static inline uint8_t
3661 anv_image_aux_levels(const struct anv_image * const image,
3662 VkImageAspectFlagBits aspect)
3663 {
3664 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3665 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
3666 return 0;
3667
3668 /* The Gen12 CCS aux surface is represented with only one level. */
3669 return image->planes[plane].aux_surface.isl.tiling == ISL_TILING_GEN12_CCS ?
3670 image->planes[plane].surface.isl.levels :
3671 image->planes[plane].aux_surface.isl.levels;
3672 }
3673
3674 /* Returns the number of auxiliary buffer layers attached to an image. */
3675 static inline uint32_t
3676 anv_image_aux_layers(const struct anv_image * const image,
3677 VkImageAspectFlagBits aspect,
3678 const uint8_t miplevel)
3679 {
3680 assert(image);
3681
3682 /* The miplevel must exist in the main buffer. */
3683 assert(miplevel < image->levels);
3684
3685 if (miplevel >= anv_image_aux_levels(image, aspect)) {
3686 /* There are no layers with auxiliary data because the miplevel has no
3687 * auxiliary data.
3688 */
3689 return 0;
3690 } else {
3691 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3692
3693 /* The Gen12 CCS aux surface is represented with only one layer. */
3694 const struct isl_extent4d *aux_logical_level0_px =
3695 image->planes[plane].aux_surface.isl.tiling == ISL_TILING_GEN12_CCS ?
3696 &image->planes[plane].surface.isl.logical_level0_px :
3697 &image->planes[plane].aux_surface.isl.logical_level0_px;
3698
3699 return MAX2(aux_logical_level0_px->array_len,
3700 aux_logical_level0_px->depth >> miplevel);
3701 }
3702 }
3703
3704 static inline struct anv_address
3705 anv_image_get_clear_color_addr(const struct anv_device *device,
3706 const struct anv_image *image,
3707 VkImageAspectFlagBits aspect)
3708 {
3709 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
3710
3711 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3712 return anv_address_add(image->planes[plane].address,
3713 image->planes[plane].fast_clear_state_offset);
3714 }
3715
3716 static inline struct anv_address
3717 anv_image_get_fast_clear_type_addr(const struct anv_device *device,
3718 const struct anv_image *image,
3719 VkImageAspectFlagBits aspect)
3720 {
3721 struct anv_address addr =
3722 anv_image_get_clear_color_addr(device, image, aspect);
3723
3724 const unsigned clear_color_state_size = device->info.gen >= 10 ?
3725 device->isl_dev.ss.clear_color_state_size :
3726 device->isl_dev.ss.clear_value_size;
3727 return anv_address_add(addr, clear_color_state_size);
3728 }
3729
3730 static inline struct anv_address
3731 anv_image_get_compression_state_addr(const struct anv_device *device,
3732 const struct anv_image *image,
3733 VkImageAspectFlagBits aspect,
3734 uint32_t level, uint32_t array_layer)
3735 {
3736 assert(level < anv_image_aux_levels(image, aspect));
3737 assert(array_layer < anv_image_aux_layers(image, aspect, level));
3738 UNUSED uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
3739 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
3740
3741 struct anv_address addr =
3742 anv_image_get_fast_clear_type_addr(device, image, aspect);
3743 addr.offset += 4; /* Go past the fast clear type */
3744
3745 if (image->type == VK_IMAGE_TYPE_3D) {
3746 for (uint32_t l = 0; l < level; l++)
3747 addr.offset += anv_minify(image->extent.depth, l) * 4;
3748 } else {
3749 addr.offset += level * image->array_size * 4;
3750 }
3751 addr.offset += array_layer * 4;
3752
3753 assert(addr.offset <
3754 image->planes[plane].address.offset + image->planes[plane].size);
3755 return addr;
3756 }
3757
3758 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3759 static inline bool
3760 anv_can_sample_with_hiz(const struct gen_device_info * const devinfo,
3761 const struct anv_image *image)
3762 {
3763 if (!(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
3764 return false;
3765
3766 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3767 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3768 * say:
3769 *
3770 * "If this field is set to AUX_HIZ, Number of Multisamples must
3771 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3772 */
3773 if (image->type == VK_IMAGE_TYPE_3D)
3774 return false;
3775
3776 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3777 * struct. There's documentation which suggests that this feature actually
3778 * reduces performance on BDW, but it has only been observed to help so
3779 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3780 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3781 */
3782 if (devinfo->gen != 8 && !devinfo->has_sample_with_hiz)
3783 return false;
3784
3785 return image->samples == 1;
3786 }
3787
3788 static inline bool
3789 anv_image_plane_uses_aux_map(const struct anv_device *device,
3790 const struct anv_image *image,
3791 uint32_t plane)
3792 {
3793 return device->info.has_aux_map &&
3794 isl_aux_usage_has_ccs(image->planes[plane].aux_usage);
3795 }
3796
3797 void
3798 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
3799 const struct anv_image *image,
3800 VkImageAspectFlagBits aspect,
3801 enum isl_aux_usage aux_usage,
3802 uint32_t level,
3803 uint32_t base_layer,
3804 uint32_t layer_count);
3805
3806 void
3807 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
3808 const struct anv_image *image,
3809 VkImageAspectFlagBits aspect,
3810 enum isl_aux_usage aux_usage,
3811 enum isl_format format, struct isl_swizzle swizzle,
3812 uint32_t level, uint32_t base_layer, uint32_t layer_count,
3813 VkRect2D area, union isl_color_value clear_color);
3814 void
3815 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
3816 const struct anv_image *image,
3817 VkImageAspectFlags aspects,
3818 enum isl_aux_usage depth_aux_usage,
3819 uint32_t level,
3820 uint32_t base_layer, uint32_t layer_count,
3821 VkRect2D area,
3822 float depth_value, uint8_t stencil_value);
3823 void
3824 anv_image_msaa_resolve(struct anv_cmd_buffer *cmd_buffer,
3825 const struct anv_image *src_image,
3826 enum isl_aux_usage src_aux_usage,
3827 uint32_t src_level, uint32_t src_base_layer,
3828 const struct anv_image *dst_image,
3829 enum isl_aux_usage dst_aux_usage,
3830 uint32_t dst_level, uint32_t dst_base_layer,
3831 VkImageAspectFlagBits aspect,
3832 uint32_t src_x, uint32_t src_y,
3833 uint32_t dst_x, uint32_t dst_y,
3834 uint32_t width, uint32_t height,
3835 uint32_t layer_count,
3836 enum blorp_filter filter);
3837 void
3838 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
3839 const struct anv_image *image,
3840 VkImageAspectFlagBits aspect, uint32_t level,
3841 uint32_t base_layer, uint32_t layer_count,
3842 enum isl_aux_op hiz_op);
3843 void
3844 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
3845 const struct anv_image *image,
3846 VkImageAspectFlags aspects,
3847 uint32_t level,
3848 uint32_t base_layer, uint32_t layer_count,
3849 VkRect2D area, uint8_t stencil_value);
3850 void
3851 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
3852 const struct anv_image *image,
3853 enum isl_format format, struct isl_swizzle swizzle,
3854 VkImageAspectFlagBits aspect,
3855 uint32_t base_layer, uint32_t layer_count,
3856 enum isl_aux_op mcs_op, union isl_color_value *clear_value,
3857 bool predicate);
3858 void
3859 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
3860 const struct anv_image *image,
3861 enum isl_format format, struct isl_swizzle swizzle,
3862 VkImageAspectFlagBits aspect, uint32_t level,
3863 uint32_t base_layer, uint32_t layer_count,
3864 enum isl_aux_op ccs_op, union isl_color_value *clear_value,
3865 bool predicate);
3866
3867 void
3868 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
3869 const struct anv_image *image,
3870 VkImageAspectFlagBits aspect,
3871 uint32_t base_level, uint32_t level_count,
3872 uint32_t base_layer, uint32_t layer_count);
3873
3874 enum isl_aux_state
3875 anv_layout_to_aux_state(const struct gen_device_info * const devinfo,
3876 const struct anv_image *image,
3877 const VkImageAspectFlagBits aspect,
3878 const VkImageLayout layout);
3879
3880 enum isl_aux_usage
3881 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
3882 const struct anv_image *image,
3883 const VkImageAspectFlagBits aspect,
3884 const VkImageUsageFlagBits usage,
3885 const VkImageLayout layout);
3886
3887 enum anv_fast_clear_type
3888 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
3889 const struct anv_image * const image,
3890 const VkImageAspectFlagBits aspect,
3891 const VkImageLayout layout);
3892
3893 /* This is defined as a macro so that it works for both
3894 * VkImageSubresourceRange and VkImageSubresourceLayers
3895 */
3896 #define anv_get_layerCount(_image, _range) \
3897 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3898 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3899
3900 static inline uint32_t
3901 anv_get_levelCount(const struct anv_image *image,
3902 const VkImageSubresourceRange *range)
3903 {
3904 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
3905 image->levels - range->baseMipLevel : range->levelCount;
3906 }
3907
3908 static inline VkImageAspectFlags
3909 anv_image_expand_aspects(const struct anv_image *image,
3910 VkImageAspectFlags aspects)
3911 {
3912 /* If the underlying image has color plane aspects and
3913 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3914 * the underlying image. */
3915 if ((image->aspects & VK_IMAGE_ASPECT_PLANES_BITS_ANV) != 0 &&
3916 aspects == VK_IMAGE_ASPECT_COLOR_BIT)
3917 return image->aspects;
3918
3919 return aspects;
3920 }
3921
3922 static inline bool
3923 anv_image_aspects_compatible(VkImageAspectFlags aspects1,
3924 VkImageAspectFlags aspects2)
3925 {
3926 if (aspects1 == aspects2)
3927 return true;
3928
3929 /* Only 1 color aspects are compatibles. */
3930 if ((aspects1 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
3931 (aspects2 & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) != 0 &&
3932 util_bitcount(aspects1) == util_bitcount(aspects2))
3933 return true;
3934
3935 return false;
3936 }
3937
3938 struct anv_image_view {
3939 struct vk_object_base base;
3940
3941 const struct anv_image *image; /**< VkImageViewCreateInfo::image */
3942
3943 VkImageAspectFlags aspect_mask;
3944 VkFormat vk_format;
3945 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3946
3947 unsigned n_planes;
3948 struct {
3949 uint32_t image_plane;
3950
3951 struct isl_view isl;
3952
3953 /**
3954 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3955 * image layout of SHADER_READ_ONLY_OPTIMAL or
3956 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3957 */
3958 struct anv_surface_state optimal_sampler_surface_state;
3959
3960 /**
3961 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3962 * image layout of GENERAL.
3963 */
3964 struct anv_surface_state general_sampler_surface_state;
3965
3966 /**
3967 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3968 * states for write-only and readable, using the real format for
3969 * write-only and the lowered format for readable.
3970 */
3971 struct anv_surface_state storage_surface_state;
3972 struct anv_surface_state writeonly_storage_surface_state;
3973
3974 struct brw_image_param storage_image_param;
3975 } planes[3];
3976 };
3977
3978 enum anv_image_view_state_flags {
3979 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY = (1 << 0),
3980 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL = (1 << 1),
3981 };
3982
3983 void anv_image_fill_surface_state(struct anv_device *device,
3984 const struct anv_image *image,
3985 VkImageAspectFlagBits aspect,
3986 const struct isl_view *view,
3987 isl_surf_usage_flags_t view_usage,
3988 enum isl_aux_usage aux_usage,
3989 const union isl_color_value *clear_color,
3990 enum anv_image_view_state_flags flags,
3991 struct anv_surface_state *state_inout,
3992 struct brw_image_param *image_param_out);
3993
3994 struct anv_image_create_info {
3995 const VkImageCreateInfo *vk_info;
3996
3997 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3998 isl_tiling_flags_t isl_tiling_flags;
3999
4000 /** These flags will be added to any derived from VkImageCreateInfo. */
4001 isl_surf_usage_flags_t isl_extra_usage_flags;
4002
4003 uint32_t stride;
4004 bool external_format;
4005 };
4006
4007 VkResult anv_image_create(VkDevice _device,
4008 const struct anv_image_create_info *info,
4009 const VkAllocationCallbacks* alloc,
4010 VkImage *pImage);<