2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
65 #include "vk_object.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
76 struct anv_buffer_view
;
77 struct anv_image_view
;
80 struct gen_aux_map_context
;
81 struct gen_perf_config
;
83 #include <vulkan/vulkan.h>
84 #include <vulkan/vulkan_intel.h>
85 #include <vulkan/vk_icd.h>
87 #include "anv_android.h"
88 #include "anv_entrypoints.h"
89 #include "anv_extensions.h"
92 #include "dev/gen_debug.h"
93 #include "common/intel_log.h"
94 #include "wsi_common.h"
96 #define NSEC_PER_SEC 1000000000ull
98 /* anv Virtual Memory Layout
99 * =========================
101 * When the anv driver is determining the virtual graphics addresses of memory
102 * objects itself using the softpin mechanism, the following memory ranges
105 * Three special considerations to notice:
107 * (1) the dynamic state pool is located within the same 4 GiB as the low
108 * heap. This is to work around a VF cache issue described in a comment in
109 * anv_physical_device_init_heaps.
111 * (2) the binding table pool is located at lower addresses than the surface
112 * state pool, within a 4 GiB range. This allows surface state base addresses
113 * to cover both binding tables (16 bit offsets) and surface states (32 bit
116 * (3) the last 4 GiB of the address space is withheld from the high
117 * heap. Various hardware units will read past the end of an object for
118 * various reasons. This healthy margin prevents reads from wrapping around
121 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
122 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
123 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
124 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
125 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
126 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
127 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
128 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
129 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
130 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
131 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
132 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
133 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
135 #define LOW_HEAP_SIZE \
136 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
137 #define DYNAMIC_STATE_POOL_SIZE \
138 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
139 #define BINDING_TABLE_POOL_SIZE \
140 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
141 #define SURFACE_STATE_POOL_SIZE \
142 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
143 #define INSTRUCTION_STATE_POOL_SIZE \
144 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
145 #define CLIENT_VISIBLE_HEAP_SIZE \
146 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
148 /* Allowing different clear colors requires us to perform a depth resolve at
149 * the end of certain render passes. This is because while slow clears store
150 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
151 * See the PRMs for examples describing when additional resolves would be
152 * necessary. To enable fast clears without requiring extra resolves, we set
153 * the clear value to a globally-defined one. We could allow different values
154 * if the user doesn't expect coherent data during or after a render passes
155 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
156 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
157 * 1.0f seems to be the only value used. The only application that doesn't set
158 * this value does so through the usage of an seemingly uninitialized clear
161 #define ANV_HZ_FC_VAL 1.0f
164 #define MAX_XFB_BUFFERS 4
165 #define MAX_XFB_STREAMS 4
168 #define MAX_VIEWPORTS 16
169 #define MAX_SCISSORS 16
170 #define MAX_PUSH_CONSTANTS_SIZE 128
171 #define MAX_DYNAMIC_BUFFERS 16
172 #define MAX_IMAGES 64
173 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
174 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
175 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
176 #define ANV_UBO_BOUNDS_CHECK_ALIGNMENT 32
177 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
178 #define MAX_VIEWS_FOR_PRIMITIVE_REPLICATION 16
180 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
182 * "The surface state model is used when a Binding Table Index (specified
183 * in the message descriptor) of less than 240 is specified. In this model,
184 * the Binding Table Index is used to index into the binding table, and the
185 * binding table entry contains a pointer to the SURFACE_STATE."
187 * Binding table values above 240 are used for various things in the hardware
188 * such as stateless, stateless with incoherent cache, SLM, and bindless.
190 #define MAX_BINDING_TABLE_SIZE 240
192 /* The kernel relocation API has a limitation of a 32-bit delta value
193 * applied to the address before it is written which, in spite of it being
194 * unsigned, is treated as signed . Because of the way that this maps to
195 * the Vulkan API, we cannot handle an offset into a buffer that does not
196 * fit into a signed 32 bits. The only mechanism we have for dealing with
197 * this at the moment is to limit all VkDeviceMemory objects to a maximum
198 * of 2GB each. The Vulkan spec allows us to do this:
200 * "Some platforms may have a limit on the maximum size of a single
201 * allocation. For example, certain systems may fail to create
202 * allocations with a size greater than or equal to 4GB. Such a limit is
203 * implementation-dependent, and if such a failure occurs then the error
204 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
206 * We don't use vk_error here because it's not an error so much as an
207 * indication to the application that the allocation is too large.
209 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
211 #define ANV_SVGS_VB_INDEX MAX_VBS
212 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
214 /* We reserve this MI ALU register for the purpose of handling predication.
215 * Other code which uses the MI ALU should leave it alone.
217 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
219 /* For gen12 we set the streamout buffers using 4 separate commands
220 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
221 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
222 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
223 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
224 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
225 * 3DSTATE_SO_BUFFER_INDEX_0.
227 #define SO_BUFFER_INDEX_0_CMD 0x60
228 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
230 static inline uint32_t
231 align_down_npot_u32(uint32_t v
, uint32_t a
)
236 static inline uint32_t
237 align_down_u32(uint32_t v
, uint32_t a
)
239 assert(a
!= 0 && a
== (a
& -a
));
243 static inline uint32_t
244 align_u32(uint32_t v
, uint32_t a
)
246 assert(a
!= 0 && a
== (a
& -a
));
247 return align_down_u32(v
+ a
- 1, a
);
250 static inline uint64_t
251 align_down_u64(uint64_t v
, uint64_t a
)
253 assert(a
!= 0 && a
== (a
& -a
));
257 static inline uint64_t
258 align_u64(uint64_t v
, uint64_t a
)
260 return align_down_u64(v
+ a
- 1, a
);
263 static inline int32_t
264 align_i32(int32_t v
, int32_t a
)
266 assert(a
!= 0 && a
== (a
& -a
));
267 return (v
+ a
- 1) & ~(a
- 1);
270 /** Alignment must be a power of 2. */
272 anv_is_aligned(uintmax_t n
, uintmax_t a
)
274 assert(a
== (a
& -a
));
275 return (n
& (a
- 1)) == 0;
278 static inline uint32_t
279 anv_minify(uint32_t n
, uint32_t levels
)
281 if (unlikely(n
== 0))
284 return MAX2(n
>> levels
, 1);
288 anv_clamp_f(float f
, float min
, float max
)
301 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
303 if (*inout_mask
& clear_mask
) {
304 *inout_mask
&= ~clear_mask
;
311 static inline union isl_color_value
312 vk_to_isl_color(VkClearColorValue color
)
314 return (union isl_color_value
) {
324 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
326 uintptr_t mask
= (1ull << bits
) - 1;
328 return (void *) (ptr
& ~mask
);
331 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
333 uintptr_t value
= (uintptr_t) ptr
;
334 uintptr_t mask
= (1ull << bits
) - 1;
335 return value
| (mask
& flags
);
338 #define for_each_bit(b, dword) \
339 for (uint32_t __dword = (dword); \
340 (b) = __builtin_ffs(__dword) - 1, __dword; \
341 __dword &= ~(1 << (b)))
343 #define typed_memcpy(dest, src, count) ({ \
344 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
345 memcpy((dest), (src), (count) * sizeof(*(src))); \
348 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
349 * to be added here in order to utilize mapping in debug/error/perf macros.
351 #define REPORT_OBJECT_TYPE(o) \
352 __builtin_choose_expr ( \
353 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
354 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
355 __builtin_choose_expr ( \
356 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
357 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
358 __builtin_choose_expr ( \
359 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
360 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
361 __builtin_choose_expr ( \
362 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
363 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
364 __builtin_choose_expr ( \
365 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
366 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
367 __builtin_choose_expr ( \
368 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
369 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
370 __builtin_choose_expr ( \
371 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
372 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
373 __builtin_choose_expr ( \
374 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
375 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
376 __builtin_choose_expr ( \
377 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
378 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
379 __builtin_choose_expr ( \
380 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
381 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
382 __builtin_choose_expr ( \
383 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
384 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
385 __builtin_choose_expr ( \
386 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
387 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
388 __builtin_choose_expr ( \
389 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
390 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
391 __builtin_choose_expr ( \
392 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
393 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
394 __builtin_choose_expr ( \
395 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
396 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
397 __builtin_choose_expr ( \
398 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
399 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
400 __builtin_choose_expr ( \
401 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
402 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
403 __builtin_choose_expr ( \
404 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
405 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
406 __builtin_choose_expr ( \
407 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
408 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
409 __builtin_choose_expr ( \
410 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
411 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
412 __builtin_choose_expr ( \
413 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
414 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
415 __builtin_choose_expr ( \
416 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
417 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
418 __builtin_choose_expr ( \
419 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
420 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
421 __builtin_choose_expr ( \
422 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
423 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
424 __builtin_choose_expr ( \
425 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
426 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
427 __builtin_choose_expr ( \
428 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
429 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
430 __builtin_choose_expr ( \
431 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
432 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
433 __builtin_choose_expr ( \
434 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
435 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
436 __builtin_choose_expr ( \
437 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
438 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
439 __builtin_choose_expr ( \
440 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
441 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
442 __builtin_choose_expr ( \
443 __builtin_types_compatible_p (__typeof (o), void*), \
444 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
445 /* The void expression results in a compile-time error \
446 when assigning the result to something. */ \
447 (void)0)))))))))))))))))))))))))))))))
449 /* Whenever we generate an error, pass it through this function. Useful for
450 * debugging, where we can break on it. Only call at error site, not when
451 * propagating errors. Might be useful to plug in a stack trace here.
454 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
455 VkDebugReportObjectTypeEXT type
, VkResult error
,
456 const char *file
, int line
, const char *format
,
459 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
460 VkDebugReportObjectTypeEXT type
, VkResult error
,
461 const char *file
, int line
, const char *format
, ...)
462 anv_printflike(7, 8);
465 #define vk_error(error) __vk_errorf(NULL, NULL,\
466 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
467 error, __FILE__, __LINE__, NULL)
468 #define vk_errorfi(instance, obj, error, format, ...)\
469 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
470 __FILE__, __LINE__, format, ## __VA_ARGS__)
471 #define vk_errorf(device, obj, error, format, ...)\
472 vk_errorfi(anv_device_instance_or_null(device),\
473 obj, error, format, ## __VA_ARGS__)
475 #define vk_error(error) error
476 #define vk_errorfi(instance, obj, error, format, ...) error
477 #define vk_errorf(device, obj, error, format, ...) error
481 * Warn on ignored extension structs.
483 * The Vulkan spec requires us to ignore unsupported or unknown structs in
484 * a pNext chain. In debug mode, emitting warnings for ignored structs may
485 * help us discover structs that we should not have ignored.
488 * From the Vulkan 1.0.38 spec:
490 * Any component of the implementation (the loader, any enabled layers,
491 * and drivers) must skip over, without processing (other than reading the
492 * sType and pNext members) any chained structures with sType values not
493 * defined by extensions supported by that component.
495 #define anv_debug_ignored_stype(sType) \
496 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
498 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
499 VkDebugReportObjectTypeEXT type
, const char *file
,
500 int line
, const char *format
, ...)
501 anv_printflike(6, 7);
502 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
503 void anv_loge_v(const char *format
, va_list va
);
506 * Print a FINISHME message, including its source location.
508 #define anv_finishme(format, ...) \
510 static bool reported = false; \
512 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
519 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
521 #define anv_perf_warn(instance, obj, format, ...) \
523 static bool reported = false; \
524 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
525 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
526 format, ##__VA_ARGS__); \
531 /* A non-fatal assert. Useful for debugging. */
533 #define anv_assert(x) ({ \
534 if (unlikely(!(x))) \
535 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
538 #define anv_assert(x)
541 /* A multi-pointer allocator
543 * When copying data structures from the user (such as a render pass), it's
544 * common to need to allocate data for a bunch of different things. Instead
545 * of doing several allocations and having to handle all of the error checking
546 * that entails, it can be easier to do a single allocation. This struct
547 * helps facilitate that. The intended usage looks like this:
550 * anv_multialloc_add(&ma, &main_ptr, 1);
551 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
552 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
554 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
555 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
557 struct anv_multialloc
{
565 #define ANV_MULTIALLOC_INIT \
566 ((struct anv_multialloc) { 0, })
568 #define ANV_MULTIALLOC(_name) \
569 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
571 __attribute__((always_inline
))
573 _anv_multialloc_add(struct anv_multialloc
*ma
,
574 void **ptr
, size_t size
, size_t align
)
576 size_t offset
= align_u64(ma
->size
, align
);
577 ma
->size
= offset
+ size
;
578 ma
->align
= MAX2(ma
->align
, align
);
580 /* Store the offset in the pointer. */
581 *ptr
= (void *)(uintptr_t)offset
;
583 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
584 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
587 #define anv_multialloc_add_size(_ma, _ptr, _size) \
588 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
590 #define anv_multialloc_add(_ma, _ptr, _count) \
591 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
593 __attribute__((always_inline
))
595 anv_multialloc_alloc(struct anv_multialloc
*ma
,
596 const VkAllocationCallbacks
*alloc
,
597 VkSystemAllocationScope scope
)
599 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
603 /* Fill out each of the pointers with their final value.
605 * for (uint32_t i = 0; i < ma->ptr_count; i++)
606 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
608 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
609 * constant, GCC is incapable of figuring this out and unrolling the loop
610 * so we have to give it a little help.
612 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
613 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
614 if ((_i) < ma->ptr_count) \
615 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
616 _ANV_MULTIALLOC_UPDATE_POINTER(0);
617 _ANV_MULTIALLOC_UPDATE_POINTER(1);
618 _ANV_MULTIALLOC_UPDATE_POINTER(2);
619 _ANV_MULTIALLOC_UPDATE_POINTER(3);
620 _ANV_MULTIALLOC_UPDATE_POINTER(4);
621 _ANV_MULTIALLOC_UPDATE_POINTER(5);
622 _ANV_MULTIALLOC_UPDATE_POINTER(6);
623 _ANV_MULTIALLOC_UPDATE_POINTER(7);
624 #undef _ANV_MULTIALLOC_UPDATE_POINTER
629 __attribute__((always_inline
))
631 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
632 const VkAllocationCallbacks
*parent_alloc
,
633 const VkAllocationCallbacks
*alloc
,
634 VkSystemAllocationScope scope
)
636 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
644 /* Index into the current validation list. This is used by the
645 * validation list building alrogithm to track which buffers are already
646 * in the validation list so that we can ensure uniqueness.
650 /* Index for use with util_sparse_array_free_list */
653 /* Last known offset. This value is provided by the kernel when we
654 * execbuf and is used as the presumed offset for the next bunch of
659 /** Size of the buffer not including implicit aux */
662 /* Map for internally mapped BOs.
664 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
668 /** Size of the implicit CCS range at the end of the buffer
670 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
671 * page of main surface data maps to a 256B chunk of CCS data and that
672 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
673 * addresses in the main surface to virtual memory addresses for CCS data.
675 * Because we can't change these maps around easily and because Vulkan
676 * allows two VkImages to be bound to overlapping memory regions (as long
677 * as the app is careful), it's not feasible to make this mapping part of
678 * the image. (On Gen11 and earlier, the mapping was provided via
679 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
680 * Instead, we attach the CCS data directly to the buffer object and setup
681 * the AUX table mapping at BO creation time.
683 * This field is for internal tracking use by the BO allocator only and
684 * should not be touched by other parts of the code. If something wants to
685 * know if a BO has implicit CCS data, it should instead look at the
686 * has_implicit_ccs boolean below.
688 * This data is not included in maps of this buffer.
692 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
695 /** True if this BO may be shared with other processes */
698 /** True if this BO is a wrapper
700 * When set to true, none of the fields in this BO are meaningful except
701 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
702 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
703 * is set in the physical device.
707 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
708 bool has_fixed_address
:1;
710 /** True if this BO wraps a host pointer */
711 bool from_host_ptr
:1;
713 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
714 bool has_client_visible_address
:1;
716 /** True if this BO has implicit CCS data attached to it */
717 bool has_implicit_ccs
:1;
720 static inline struct anv_bo
*
721 anv_bo_ref(struct anv_bo
*bo
)
723 p_atomic_inc(&bo
->refcount
);
727 static inline struct anv_bo
*
728 anv_bo_unwrap(struct anv_bo
*bo
)
730 while (bo
->is_wrapper
)
735 /* Represents a lock-free linked list of "free" things. This is used by
736 * both the block pool and the state pools. Unfortunately, in order to
737 * solve the ABA problem, we can't use a single uint32_t head.
739 union anv_free_list
{
743 /* A simple count that is incremented every time the head changes. */
746 /* Make sure it's aligned to 64 bits. This will make atomic operations
747 * faster on 32 bit platforms.
749 uint64_t u64
__attribute__ ((aligned (8)));
752 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
754 struct anv_block_state
{
760 /* Make sure it's aligned to 64 bits. This will make atomic operations
761 * faster on 32 bit platforms.
763 uint64_t u64
__attribute__ ((aligned (8)));
767 #define anv_block_pool_foreach_bo(bo, pool) \
768 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
769 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
772 #define ANV_MAX_BLOCK_POOL_BOS 20
774 struct anv_block_pool
{
775 struct anv_device
*device
;
778 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
779 * around the actual BO so that we grow the pool after the wrapper BO has
780 * been put in a relocation list. This is only used in the non-softpin
783 struct anv_bo wrapper_bo
;
785 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
791 /* The address where the start of the pool is pinned. The various bos that
792 * are created as the pool grows will have addresses in the range
793 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
795 uint64_t start_address
;
797 /* The offset from the start of the bo to the "center" of the block
798 * pool. Pointers to allocated blocks are given by
799 * bo.map + center_bo_offset + offsets.
801 uint32_t center_bo_offset
;
803 /* Current memory map of the block pool. This pointer may or may not
804 * point to the actual beginning of the block pool memory. If
805 * anv_block_pool_alloc_back has ever been called, then this pointer
806 * will point to the "center" position of the buffer and all offsets
807 * (negative or positive) given out by the block pool alloc functions
808 * will be valid relative to this pointer.
810 * In particular, map == bo.map + center_offset
812 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
813 * since it will handle the softpin case as well, where this points to NULL.
819 * Array of mmaps and gem handles owned by the block pool, reclaimed when
820 * the block pool is destroyed.
822 struct u_vector mmap_cleanups
;
824 struct anv_block_state state
;
826 struct anv_block_state back_state
;
829 /* Block pools are backed by a fixed-size 1GB memfd */
830 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
832 /* The center of the block pool is also the middle of the memfd. This may
833 * change in the future if we decide differently for some reason.
835 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
837 static inline uint32_t
838 anv_block_pool_size(struct anv_block_pool
*pool
)
840 return pool
->state
.end
+ pool
->back_state
.end
;
850 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
852 struct anv_fixed_size_state_pool
{
853 union anv_free_list free_list
;
854 struct anv_block_state block
;
857 #define ANV_MIN_STATE_SIZE_LOG2 6
858 #define ANV_MAX_STATE_SIZE_LOG2 21
860 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
862 struct anv_free_entry
{
864 struct anv_state state
;
867 struct anv_state_table
{
868 struct anv_device
*device
;
870 struct anv_free_entry
*map
;
872 struct anv_block_state state
;
873 struct u_vector cleanups
;
876 struct anv_state_pool
{
877 struct anv_block_pool block_pool
;
879 struct anv_state_table table
;
881 /* The size of blocks which will be allocated from the block pool */
884 /** Free list for "back" allocations */
885 union anv_free_list back_alloc_free_list
;
887 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
890 struct anv_state_stream
{
891 struct anv_state_pool
*state_pool
;
893 /* The size of blocks to allocate from the state pool */
896 /* Current block we're allocating from */
897 struct anv_state block
;
899 /* Offset into the current block at which to allocate the next state */
902 /* List of all blocks allocated from this pool */
903 struct util_dynarray all_blocks
;
906 /* The block_pool functions exported for testing only. The block pool should
907 * only be used via a state pool (see below).
909 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
910 struct anv_device
*device
,
911 uint64_t start_address
,
912 uint32_t initial_size
);
913 void anv_block_pool_finish(struct anv_block_pool
*pool
);
914 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
915 uint32_t block_size
, uint32_t *padding
);
916 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
917 uint32_t block_size
);
918 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
921 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
922 struct anv_device
*device
,
923 uint64_t start_address
,
924 uint32_t block_size
);
925 void anv_state_pool_finish(struct anv_state_pool
*pool
);
926 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
927 uint32_t state_size
, uint32_t alignment
);
928 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
929 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
930 void anv_state_stream_init(struct anv_state_stream
*stream
,
931 struct anv_state_pool
*state_pool
,
932 uint32_t block_size
);
933 void anv_state_stream_finish(struct anv_state_stream
*stream
);
934 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
935 uint32_t size
, uint32_t alignment
);
937 VkResult
anv_state_table_init(struct anv_state_table
*table
,
938 struct anv_device
*device
,
939 uint32_t initial_entries
);
940 void anv_state_table_finish(struct anv_state_table
*table
);
941 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
943 void anv_free_list_push(union anv_free_list
*list
,
944 struct anv_state_table
*table
,
945 uint32_t idx
, uint32_t count
);
946 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
947 struct anv_state_table
*table
);
950 static inline struct anv_state
*
951 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
953 return &table
->map
[idx
].state
;
956 * Implements a pool of re-usable BOs. The interface is identical to that
957 * of block_pool except that each block is its own BO.
960 struct anv_device
*device
;
962 struct util_sparse_array_free_list free_list
[16];
965 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
966 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
967 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
968 struct anv_bo
**bo_out
);
969 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
971 struct anv_scratch_pool
{
972 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
973 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
976 void anv_scratch_pool_init(struct anv_device
*device
,
977 struct anv_scratch_pool
*pool
);
978 void anv_scratch_pool_finish(struct anv_device
*device
,
979 struct anv_scratch_pool
*pool
);
980 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
981 struct anv_scratch_pool
*pool
,
982 gl_shader_stage stage
,
983 unsigned per_thread_scratch
);
985 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
986 struct anv_bo_cache
{
987 struct util_sparse_array bo_map
;
988 pthread_mutex_t mutex
;
991 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
992 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
994 struct anv_memory_type
{
995 /* Standard bits passed on to the client */
996 VkMemoryPropertyFlags propertyFlags
;
1000 struct anv_memory_heap
{
1001 /* Standard bits passed on to the client */
1003 VkMemoryHeapFlags flags
;
1005 /* Driver-internal book-keeping */
1009 struct anv_physical_device
{
1010 VK_LOADER_DATA _loader_data
;
1012 /* Link in anv_instance::physical_devices */
1013 struct list_head link
;
1015 struct anv_instance
* instance
;
1025 struct gen_device_info info
;
1026 /** Amount of "GPU memory" we want to advertise
1028 * Clearly, this value is bogus since Intel is a UMA architecture. On
1029 * gen7 platforms, we are limited by GTT size unless we want to implement
1030 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1031 * practically unlimited. However, we will never report more than 3/4 of
1032 * the total system ram to try and avoid running out of RAM.
1034 bool supports_48bit_addresses
;
1035 struct brw_compiler
* compiler
;
1036 struct isl_device isl_dev
;
1037 struct gen_perf_config
* perf
;
1038 int cmd_parser_version
;
1040 bool has_exec_async
;
1041 bool has_exec_capture
;
1042 bool has_exec_fence
;
1044 bool has_syncobj_wait
;
1045 bool has_context_priority
;
1046 bool has_context_isolation
;
1047 bool has_mem_available
;
1048 bool has_mmap_offset
;
1052 bool always_use_bindless
;
1054 /** True if we can access buffers using A64 messages */
1055 bool has_a64_buffer_access
;
1056 /** True if we can use bindless access for images */
1057 bool has_bindless_images
;
1058 /** True if we can use bindless access for samplers */
1059 bool has_bindless_samplers
;
1061 /** True if this device has implicit AUX
1063 * If true, CCS is handled as an implicit attachment to the BO rather than
1064 * as an explicitly bound surface.
1066 bool has_implicit_ccs
;
1068 bool always_flush_cache
;
1070 struct anv_device_extension_table supported_extensions
;
1073 uint32_t subslice_total
;
1076 uint32_t type_count
;
1077 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1078 uint32_t heap_count
;
1079 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1082 uint8_t driver_build_sha1
[20];
1083 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1084 uint8_t driver_uuid
[VK_UUID_SIZE
];
1085 uint8_t device_uuid
[VK_UUID_SIZE
];
1087 struct disk_cache
* disk_cache
;
1089 struct wsi_device wsi_device
;
1094 struct anv_app_info
{
1095 const char* app_name
;
1096 uint32_t app_version
;
1097 const char* engine_name
;
1098 uint32_t engine_version
;
1099 uint32_t api_version
;
1102 struct anv_instance
{
1103 VK_LOADER_DATA _loader_data
;
1105 VkAllocationCallbacks alloc
;
1107 struct anv_app_info app_info
;
1109 struct anv_instance_extension_table enabled_extensions
;
1110 struct anv_instance_dispatch_table dispatch
;
1111 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1112 struct anv_device_dispatch_table device_dispatch
;
1114 bool physical_devices_enumerated
;
1115 struct list_head physical_devices
;
1117 bool pipeline_cache_enabled
;
1119 struct vk_debug_report_instance debug_report_callbacks
;
1121 struct driOptionCache dri_options
;
1122 struct driOptionCache available_dri_options
;
1125 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1126 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1128 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1129 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1132 struct anv_queue_submit
{
1133 struct anv_cmd_buffer
* cmd_buffer
;
1135 uint32_t fence_count
;
1136 uint32_t fence_array_length
;
1137 struct drm_i915_gem_exec_fence
* fences
;
1139 uint32_t temporary_semaphore_count
;
1140 uint32_t temporary_semaphore_array_length
;
1141 struct anv_semaphore_impl
* temporary_semaphores
;
1143 /* Semaphores to be signaled with a SYNC_FD. */
1144 struct anv_semaphore
** sync_fd_semaphores
;
1145 uint32_t sync_fd_semaphore_count
;
1146 uint32_t sync_fd_semaphore_array_length
;
1148 /* Allocated only with non shareable timelines. */
1149 struct anv_timeline
** wait_timelines
;
1150 uint32_t wait_timeline_count
;
1151 uint32_t wait_timeline_array_length
;
1152 uint64_t * wait_timeline_values
;
1154 struct anv_timeline
** signal_timelines
;
1155 uint32_t signal_timeline_count
;
1156 uint32_t signal_timeline_array_length
;
1157 uint64_t * signal_timeline_values
;
1160 bool need_out_fence
;
1163 uint32_t fence_bo_count
;
1164 uint32_t fence_bo_array_length
;
1165 /* An array of struct anv_bo pointers with lower bit used as a flag to
1166 * signal we will wait on that BO (see anv_(un)pack_ptr).
1168 uintptr_t * fence_bos
;
1170 const VkAllocationCallbacks
* alloc
;
1171 VkSystemAllocationScope alloc_scope
;
1173 struct anv_bo
* simple_bo
;
1174 uint32_t simple_bo_size
;
1176 struct list_head link
;
1180 VK_LOADER_DATA _loader_data
;
1182 struct anv_device
* device
;
1185 * A list of struct anv_queue_submit to be submitted to i915.
1187 struct list_head queued_submits
;
1189 VkDeviceQueueCreateFlags flags
;
1192 struct anv_pipeline_cache
{
1193 struct anv_device
* device
;
1194 pthread_mutex_t mutex
;
1196 struct hash_table
* nir_cache
;
1198 struct hash_table
* cache
;
1201 struct nir_xfb_info
;
1202 struct anv_pipeline_bind_map
;
1204 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1205 struct anv_device
*device
,
1206 bool cache_enabled
);
1207 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1209 struct anv_shader_bin
*
1210 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1211 const void *key
, uint32_t key_size
);
1212 struct anv_shader_bin
*
1213 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1214 gl_shader_stage stage
,
1215 const void *key_data
, uint32_t key_size
,
1216 const void *kernel_data
, uint32_t kernel_size
,
1217 const void *constant_data
,
1218 uint32_t constant_data_size
,
1219 const struct brw_stage_prog_data
*prog_data
,
1220 uint32_t prog_data_size
,
1221 const struct brw_compile_stats
*stats
,
1223 const struct nir_xfb_info
*xfb_info
,
1224 const struct anv_pipeline_bind_map
*bind_map
);
1226 struct anv_shader_bin
*
1227 anv_device_search_for_kernel(struct anv_device
*device
,
1228 struct anv_pipeline_cache
*cache
,
1229 const void *key_data
, uint32_t key_size
,
1230 bool *user_cache_bit
);
1232 struct anv_shader_bin
*
1233 anv_device_upload_kernel(struct anv_device
*device
,
1234 struct anv_pipeline_cache
*cache
,
1235 gl_shader_stage stage
,
1236 const void *key_data
, uint32_t key_size
,
1237 const void *kernel_data
, uint32_t kernel_size
,
1238 const void *constant_data
,
1239 uint32_t constant_data_size
,
1240 const struct brw_stage_prog_data
*prog_data
,
1241 uint32_t prog_data_size
,
1242 const struct brw_compile_stats
*stats
,
1244 const struct nir_xfb_info
*xfb_info
,
1245 const struct anv_pipeline_bind_map
*bind_map
);
1248 struct nir_shader_compiler_options
;
1251 anv_device_search_for_nir(struct anv_device
*device
,
1252 struct anv_pipeline_cache
*cache
,
1253 const struct nir_shader_compiler_options
*nir_options
,
1254 unsigned char sha1_key
[20],
1258 anv_device_upload_nir(struct anv_device
*device
,
1259 struct anv_pipeline_cache
*cache
,
1260 const struct nir_shader
*nir
,
1261 unsigned char sha1_key
[20]);
1264 struct vk_device vk
;
1266 struct anv_physical_device
* physical
;
1268 struct gen_device_info info
;
1269 struct isl_device isl_dev
;
1272 bool can_chain_batches
;
1273 bool robust_buffer_access
;
1274 struct anv_device_extension_table enabled_extensions
;
1275 struct anv_device_dispatch_table dispatch
;
1277 pthread_mutex_t vma_mutex
;
1278 struct util_vma_heap vma_lo
;
1279 struct util_vma_heap vma_cva
;
1280 struct util_vma_heap vma_hi
;
1282 /** List of all anv_device_memory objects */
1283 struct list_head memory_objects
;
1285 struct anv_bo_pool batch_bo_pool
;
1287 struct anv_bo_cache bo_cache
;
1289 struct anv_state_pool dynamic_state_pool
;
1290 struct anv_state_pool instruction_state_pool
;
1291 struct anv_state_pool binding_table_pool
;
1292 struct anv_state_pool surface_state_pool
;
1294 /** BO used for various workarounds
1296 * There are a number of workarounds on our hardware which require writing
1297 * data somewhere and it doesn't really matter where. For that, we use
1298 * this BO and just write to the first dword or so.
1300 * We also need to be able to handle NULL buffers bound as pushed UBOs.
1301 * For that, we use the high bytes (>= 1024) of the workaround BO.
1303 struct anv_bo
* workaround_bo
;
1304 struct anv_bo
* trivial_batch_bo
;
1305 struct anv_bo
* hiz_clear_bo
;
1306 struct anv_state null_surface_state
;
1308 struct anv_pipeline_cache default_pipeline_cache
;
1309 struct blorp_context blorp
;
1311 struct anv_state border_colors
;
1313 struct anv_state slice_hash
;
1315 struct anv_queue queue
;
1317 struct anv_scratch_pool scratch_pool
;
1319 pthread_mutex_t mutex
;
1320 pthread_cond_t queue_submit
;
1323 struct gen_batch_decode_ctx decoder_ctx
;
1325 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1326 * the cmd_buffer's list.
1328 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1330 int perf_fd
; /* -1 if no opened */
1331 uint64_t perf_metric
; /* 0 if unset */
1333 struct gen_aux_map_context
*aux_map_ctx
;
1336 static inline struct anv_instance
*
1337 anv_device_instance_or_null(const struct anv_device
*device
)
1339 return device
? device
->physical
->instance
: NULL
;
1342 static inline struct anv_state_pool
*
1343 anv_binding_table_pool(struct anv_device
*device
)
1345 if (device
->physical
->use_softpin
)
1346 return &device
->binding_table_pool
;
1348 return &device
->surface_state_pool
;
1351 static inline struct anv_state
1352 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1353 if (device
->physical
->use_softpin
)
1354 return anv_state_pool_alloc(&device
->binding_table_pool
,
1355 device
->binding_table_pool
.block_size
, 0);
1357 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1361 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1362 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1365 static inline uint32_t
1366 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1368 if (bo
->is_external
)
1369 return device
->isl_dev
.mocs
.external
;
1371 return device
->isl_dev
.mocs
.internal
;
1374 void anv_device_init_blorp(struct anv_device
*device
);
1375 void anv_device_finish_blorp(struct anv_device
*device
);
1377 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1378 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1379 const char *file
, int line
,
1380 const char *msg
, ...)
1381 anv_printflike(4, 5);
1382 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1383 const char *file
, int line
,
1384 const char *msg
, ...)
1385 anv_printflike(4, 5);
1386 #define anv_device_set_lost(dev, ...) \
1387 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1388 #define anv_queue_set_lost(queue, ...) \
1389 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1392 anv_device_is_lost(struct anv_device
*device
)
1394 return unlikely(p_atomic_read(&device
->_lost
));
1397 VkResult
anv_device_query_status(struct anv_device
*device
);
1400 enum anv_bo_alloc_flags
{
1401 /** Specifies that the BO must have a 32-bit address
1403 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1405 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1407 /** Specifies that the BO may be shared externally */
1408 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1410 /** Specifies that the BO should be mapped */
1411 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1413 /** Specifies that the BO should be snooped so we get coherency */
1414 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1416 /** Specifies that the BO should be captured in error states */
1417 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1419 /** Specifies that the BO will have an address assigned by the caller
1421 * Such BOs do not exist in any VMA heap.
1423 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1425 /** Enables implicit synchronization on the BO
1427 * This is the opposite of EXEC_OBJECT_ASYNC.
1429 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1431 /** Enables implicit synchronization on the BO
1433 * This is equivalent to EXEC_OBJECT_WRITE.
1435 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1437 /** Has an address which is visible to the client */
1438 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1440 /** This buffer has implicit CCS data attached to it */
1441 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1444 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1445 enum anv_bo_alloc_flags alloc_flags
,
1446 uint64_t explicit_address
,
1447 struct anv_bo
**bo
);
1448 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1449 void *host_ptr
, uint32_t size
,
1450 enum anv_bo_alloc_flags alloc_flags
,
1451 uint64_t client_address
,
1452 struct anv_bo
**bo_out
);
1453 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1454 enum anv_bo_alloc_flags alloc_flags
,
1455 uint64_t client_address
,
1456 struct anv_bo
**bo
);
1457 VkResult
anv_device_export_bo(struct anv_device
*device
,
1458 struct anv_bo
*bo
, int *fd_out
);
1459 void anv_device_release_bo(struct anv_device
*device
,
1462 static inline struct anv_bo
*
1463 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1465 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1468 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1469 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1472 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1473 void anv_queue_finish(struct anv_queue
*queue
);
1475 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1476 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1477 struct anv_batch
*batch
);
1479 uint64_t anv_gettime_ns(void);
1480 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1482 void* anv_gem_mmap(struct anv_device
*device
,
1483 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1484 void anv_gem_munmap(struct anv_device
*device
, void *p
, uint64_t size
);
1485 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1486 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1487 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1488 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1489 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1490 int anv_gem_execbuffer(struct anv_device
*device
,
1491 struct drm_i915_gem_execbuffer2
*execbuf
);
1492 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1493 uint32_t stride
, uint32_t tiling
);
1494 int anv_gem_create_context(struct anv_device
*device
);
1495 bool anv_gem_has_context_priority(int fd
);
1496 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1497 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1499 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1501 int anv_gem_get_param(int fd
, uint32_t param
);
1502 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1503 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1504 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1505 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1506 uint32_t *active
, uint32_t *pending
);
1507 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1508 int anv_gem_reg_read(struct anv_device
*device
,
1509 uint32_t offset
, uint64_t *result
);
1510 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1511 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1512 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1513 uint32_t read_domains
, uint32_t write_domain
);
1514 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1515 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1516 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1517 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1518 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1519 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1521 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1522 uint32_t handle
, int fd
);
1523 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1524 bool anv_gem_supports_syncobj_wait(int fd
);
1525 int anv_gem_syncobj_wait(struct anv_device
*device
,
1526 uint32_t *handles
, uint32_t num_handles
,
1527 int64_t abs_timeout_ns
, bool wait_all
);
1529 uint64_t anv_vma_alloc(struct anv_device
*device
,
1530 uint64_t size
, uint64_t align
,
1531 enum anv_bo_alloc_flags alloc_flags
,
1532 uint64_t client_address
);
1533 void anv_vma_free(struct anv_device
*device
,
1534 uint64_t address
, uint64_t size
);
1536 struct anv_reloc_list
{
1537 uint32_t num_relocs
;
1538 uint32_t array_length
;
1539 struct drm_i915_gem_relocation_entry
* relocs
;
1540 struct anv_bo
** reloc_bos
;
1545 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1546 const VkAllocationCallbacks
*alloc
);
1547 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1548 const VkAllocationCallbacks
*alloc
);
1550 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1551 const VkAllocationCallbacks
*alloc
,
1552 uint32_t offset
, struct anv_bo
*target_bo
,
1553 uint32_t delta
, uint64_t *address_u64_out
);
1555 struct anv_batch_bo
{
1556 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1557 struct list_head link
;
1561 /* Bytes actually consumed in this batch BO */
1564 struct anv_reloc_list relocs
;
1568 const VkAllocationCallbacks
* alloc
;
1574 struct anv_reloc_list
* relocs
;
1576 /* This callback is called (with the associated user data) in the event
1577 * that the batch runs out of space.
1579 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1583 * Current error status of the command buffer. Used to track inconsistent
1584 * or incomplete command buffer states that are the consequence of run-time
1585 * errors such as out of memory scenarios. We want to track this in the
1586 * batch because the command buffer object is not visible to some parts
1592 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1593 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1594 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1595 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1597 static inline VkResult
1598 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1600 assert(error
!= VK_SUCCESS
);
1601 if (batch
->status
== VK_SUCCESS
)
1602 batch
->status
= error
;
1603 return batch
->status
;
1607 anv_batch_has_error(struct anv_batch
*batch
)
1609 return batch
->status
!= VK_SUCCESS
;
1612 struct anv_address
{
1617 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1620 anv_address_is_null(struct anv_address addr
)
1622 return addr
.bo
== NULL
&& addr
.offset
== 0;
1625 static inline uint64_t
1626 anv_address_physical(struct anv_address addr
)
1628 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1629 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1631 return gen_canonical_address(addr
.offset
);
1634 static inline struct anv_address
1635 anv_address_add(struct anv_address addr
, uint64_t offset
)
1637 addr
.offset
+= offset
;
1642 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1644 unsigned reloc_size
= 0;
1645 if (device
->info
.gen
>= 8) {
1646 reloc_size
= sizeof(uint64_t);
1647 *(uint64_t *)p
= gen_canonical_address(v
);
1649 reloc_size
= sizeof(uint32_t);
1653 if (flush
&& !device
->info
.has_llc
)
1654 gen_flush_range(p
, reloc_size
);
1657 static inline uint64_t
1658 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1659 const struct anv_address address
, uint32_t delta
)
1661 if (address
.bo
== NULL
) {
1662 return address
.offset
+ delta
;
1664 assert(batch
->start
<= location
&& location
< batch
->end
);
1666 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1670 #define __gen_address_type struct anv_address
1671 #define __gen_user_data struct anv_batch
1672 #define __gen_combine_address _anv_combine_address
1674 /* Wrapper macros needed to work around preprocessor argument issues. In
1675 * particular, arguments don't get pre-evaluated if they are concatenated.
1676 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1677 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1678 * We can work around this easily enough with these helpers.
1680 #define __anv_cmd_length(cmd) cmd ## _length
1681 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1682 #define __anv_cmd_header(cmd) cmd ## _header
1683 #define __anv_cmd_pack(cmd) cmd ## _pack
1684 #define __anv_reg_num(reg) reg ## _num
1686 #define anv_pack_struct(dst, struc, ...) do { \
1687 struct struc __template = { \
1690 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1691 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1694 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1695 void *__dst = anv_batch_emit_dwords(batch, n); \
1697 struct cmd __template = { \
1698 __anv_cmd_header(cmd), \
1699 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1702 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1707 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1711 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1712 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1715 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1716 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1717 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1720 #define anv_batch_emit(batch, cmd, name) \
1721 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1722 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1723 __builtin_expect(_dst != NULL, 1); \
1724 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1725 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1729 struct anv_device_memory
{
1730 struct list_head link
;
1733 struct anv_memory_type
* type
;
1734 VkDeviceSize map_size
;
1737 /* If set, we are holding reference to AHardwareBuffer
1738 * which we must release when memory is freed.
1740 struct AHardwareBuffer
* ahw
;
1742 /* If set, this memory comes from a host pointer. */
1747 * Header for Vertex URB Entry (VUE)
1749 struct anv_vue_header
{
1751 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1752 uint32_t ViewportIndex
;
1756 /** Struct representing a sampled image descriptor
1758 * This descriptor layout is used for sampled images, bare sampler, and
1759 * combined image/sampler descriptors.
1761 struct anv_sampled_image_descriptor
{
1762 /** Bindless image handle
1764 * This is expected to already be shifted such that the 20-bit
1765 * SURFACE_STATE table index is in the top 20 bits.
1769 /** Bindless sampler handle
1771 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1772 * to the dynamic state base address.
1777 struct anv_texture_swizzle_descriptor
{
1780 * See also nir_intrinsic_channel_select_intel
1784 /** Unused padding to ensure the struct is a multiple of 64 bits */
1788 /** Struct representing a storage image descriptor */
1789 struct anv_storage_image_descriptor
{
1790 /** Bindless image handles
1792 * These are expected to already be shifted such that the 20-bit
1793 * SURFACE_STATE table index is in the top 20 bits.
1795 uint32_t read_write
;
1796 uint32_t write_only
;
1799 /** Struct representing a address/range descriptor
1801 * The fields of this struct correspond directly to the data layout of
1802 * nir_address_format_64bit_bounded_global addresses. The last field is the
1803 * offset in the NIR address so it must be zero so that when you load the
1804 * descriptor you get a pointer to the start of the range.
1806 struct anv_address_range_descriptor
{
1812 enum anv_descriptor_data
{
1813 /** The descriptor contains a BTI reference to a surface state */
1814 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1815 /** The descriptor contains a BTI reference to a sampler state */
1816 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1817 /** The descriptor contains an actual buffer view */
1818 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1819 /** The descriptor contains auxiliary image layout data */
1820 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1821 /** The descriptor contains auxiliary image layout data */
1822 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1823 /** anv_address_range_descriptor with a buffer address and range */
1824 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1825 /** Bindless surface handle */
1826 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1827 /** Storage image handles */
1828 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1829 /** Storage image handles */
1830 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1833 struct anv_descriptor_set_binding_layout
{
1835 /* The type of the descriptors in this binding */
1836 VkDescriptorType type
;
1839 /* Flags provided when this binding was created */
1840 VkDescriptorBindingFlagsEXT flags
;
1842 /* Bitfield representing the type of data this descriptor contains */
1843 enum anv_descriptor_data data
;
1845 /* Maximum number of YCbCr texture/sampler planes */
1846 uint8_t max_plane_count
;
1848 /* Number of array elements in this binding (or size in bytes for inline
1851 uint16_t array_size
;
1853 /* Index into the flattend descriptor set */
1854 uint16_t descriptor_index
;
1856 /* Index into the dynamic state array for a dynamic buffer */
1857 int16_t dynamic_offset_index
;
1859 /* Index into the descriptor set buffer views */
1860 int16_t buffer_view_index
;
1862 /* Offset into the descriptor buffer where this descriptor lives */
1863 uint32_t descriptor_offset
;
1865 /* Immutable samplers (or NULL if no immutable samplers) */
1866 struct anv_sampler
**immutable_samplers
;
1869 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1871 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1872 VkDescriptorType type
);
1874 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1875 const struct anv_descriptor_set_binding_layout
*binding
,
1878 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1879 const struct anv_descriptor_set_binding_layout
*binding
,
1882 struct anv_descriptor_set_layout
{
1883 /* Descriptor set layouts can be destroyed at almost any time */
1886 /* Number of bindings in this descriptor set */
1887 uint16_t binding_count
;
1889 /* Total size of the descriptor set with room for all array entries */
1892 /* Shader stages affected by this descriptor set */
1893 uint16_t shader_stages
;
1895 /* Number of buffer views in this descriptor set */
1896 uint16_t buffer_view_count
;
1898 /* Number of dynamic offsets used by this descriptor set */
1899 uint16_t dynamic_offset_count
;
1901 /* For each shader stage, which offsets apply to that stage */
1902 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1904 /* Size of the descriptor buffer for this descriptor set */
1905 uint32_t descriptor_buffer_size
;
1907 /* Bindings in this descriptor set */
1908 struct anv_descriptor_set_binding_layout binding
[0];
1912 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1914 assert(layout
&& layout
->ref_cnt
>= 1);
1915 p_atomic_inc(&layout
->ref_cnt
);
1919 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1920 struct anv_descriptor_set_layout
*layout
)
1922 assert(layout
&& layout
->ref_cnt
>= 1);
1923 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1924 vk_free(&device
->vk
.alloc
, layout
);
1927 struct anv_descriptor
{
1928 VkDescriptorType type
;
1932 VkImageLayout layout
;
1933 struct anv_image_view
*image_view
;
1934 struct anv_sampler
*sampler
;
1938 struct anv_buffer
*buffer
;
1943 struct anv_buffer_view
*buffer_view
;
1947 struct anv_descriptor_set
{
1948 struct anv_descriptor_pool
*pool
;
1949 struct anv_descriptor_set_layout
*layout
;
1952 /* State relative to anv_descriptor_pool::bo */
1953 struct anv_state desc_mem
;
1954 /* Surface state for the descriptor buffer */
1955 struct anv_state desc_surface_state
;
1957 uint32_t buffer_view_count
;
1958 struct anv_buffer_view
*buffer_views
;
1960 /* Link to descriptor pool's desc_sets list . */
1961 struct list_head pool_link
;
1963 struct anv_descriptor descriptors
[0];
1966 struct anv_buffer_view
{
1967 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1968 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1970 struct anv_address address
;
1972 struct anv_state surface_state
;
1973 struct anv_state storage_surface_state
;
1974 struct anv_state writeonly_storage_surface_state
;
1976 struct brw_image_param storage_image_param
;
1979 struct anv_push_descriptor_set
{
1980 struct anv_descriptor_set set
;
1982 /* Put this field right behind anv_descriptor_set so it fills up the
1983 * descriptors[0] field. */
1984 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1986 /** True if the descriptor set buffer has been referenced by a draw or
1989 bool set_used_on_gpu
;
1991 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1994 struct anv_descriptor_pool
{
2000 struct util_vma_heap bo_heap
;
2002 struct anv_state_stream surface_state_stream
;
2003 void *surface_state_free_list
;
2005 struct list_head desc_sets
;
2010 enum anv_descriptor_template_entry_type
{
2011 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2012 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2013 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2016 struct anv_descriptor_template_entry
{
2017 /* The type of descriptor in this entry */
2018 VkDescriptorType type
;
2020 /* Binding in the descriptor set */
2023 /* Offset at which to write into the descriptor set binding */
2024 uint32_t array_element
;
2026 /* Number of elements to write into the descriptor set binding */
2027 uint32_t array_count
;
2029 /* Offset into the user provided data */
2032 /* Stride between elements into the user provided data */
2036 struct anv_descriptor_update_template
{
2037 VkPipelineBindPoint bind_point
;
2039 /* The descriptor set this template corresponds to. This value is only
2040 * valid if the template was created with the templateType
2041 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2045 /* Number of entries in this template */
2046 uint32_t entry_count
;
2048 /* Entries of the template */
2049 struct anv_descriptor_template_entry entries
[0];
2053 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2056 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2057 struct anv_descriptor_set
*set
,
2058 const VkDescriptorImageInfo
* const info
,
2059 VkDescriptorType type
,
2064 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2065 struct anv_descriptor_set
*set
,
2066 VkDescriptorType type
,
2067 struct anv_buffer_view
*buffer_view
,
2072 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2073 struct anv_descriptor_set
*set
,
2074 struct anv_state_stream
*alloc_stream
,
2075 VkDescriptorType type
,
2076 struct anv_buffer
*buffer
,
2079 VkDeviceSize offset
,
2080 VkDeviceSize range
);
2082 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2083 struct anv_descriptor_set
*set
,
2090 anv_descriptor_set_write_template(struct anv_device
*device
,
2091 struct anv_descriptor_set
*set
,
2092 struct anv_state_stream
*alloc_stream
,
2093 const struct anv_descriptor_update_template
*template,
2097 anv_descriptor_set_create(struct anv_device
*device
,
2098 struct anv_descriptor_pool
*pool
,
2099 struct anv_descriptor_set_layout
*layout
,
2100 struct anv_descriptor_set
**out_set
);
2103 anv_descriptor_set_destroy(struct anv_device
*device
,
2104 struct anv_descriptor_pool
*pool
,
2105 struct anv_descriptor_set
*set
);
2107 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2108 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2109 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2110 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2111 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2112 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2114 struct anv_pipeline_binding
{
2115 /** Index in the descriptor set
2117 * This is a flattened index; the descriptor set layout is already taken
2122 /** The descriptor set this surface corresponds to.
2124 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2125 * binding is not a normal descriptor set but something else.
2130 /** Plane in the binding index for images */
2133 /** Input attachment index (relative to the subpass) */
2134 uint8_t input_attachment_index
;
2136 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2137 uint8_t dynamic_offset_index
;
2140 /** For a storage image, whether it is write-only */
2143 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2144 * assuming POD zero-initialization.
2149 struct anv_push_range
{
2150 /** Index in the descriptor set */
2153 /** Descriptor set index */
2156 /** Dynamic offset index (for dynamic UBOs) */
2157 uint8_t dynamic_offset_index
;
2159 /** Start offset in units of 32B */
2162 /** Range in units of 32B */
2166 struct anv_pipeline_layout
{
2168 struct anv_descriptor_set_layout
*layout
;
2169 uint32_t dynamic_offset_start
;
2174 unsigned char sha1
[20];
2178 struct anv_device
* device
;
2181 VkBufferUsageFlags usage
;
2183 /* Set when bound */
2184 struct anv_address address
;
2187 static inline uint64_t
2188 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2190 assert(offset
<= buffer
->size
);
2191 if (range
== VK_WHOLE_SIZE
) {
2192 return buffer
->size
- offset
;
2194 assert(range
+ offset
>= range
);
2195 assert(range
+ offset
<= buffer
->size
);
2200 enum anv_cmd_dirty_bits
{
2201 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2202 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2203 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2204 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2205 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2206 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2207 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2208 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2209 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2210 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2211 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2212 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2213 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2214 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2216 typedef uint32_t anv_cmd_dirty_mask_t
;
2218 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2219 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2220 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2221 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2222 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2223 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2224 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2225 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2226 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2227 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2228 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2230 static inline enum anv_cmd_dirty_bits
2231 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2234 case VK_DYNAMIC_STATE_VIEWPORT
:
2235 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2236 case VK_DYNAMIC_STATE_SCISSOR
:
2237 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2238 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2239 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2240 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2241 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2242 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2243 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2244 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2245 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2246 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2247 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2248 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2249 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2250 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2251 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2252 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2253 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2255 assert(!"Unsupported dynamic state");
2261 enum anv_pipe_bits
{
2262 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2263 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2264 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2265 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2266 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2267 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2268 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2269 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2270 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2271 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2272 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2273 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2274 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2276 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2277 * a flush has happened but not a CS stall. The next time we do any sort
2278 * of invalidation we need to insert a CS stall at that time. Otherwise,
2279 * we would have to CS stall on every flush which could be bad.
2281 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2283 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2284 * target operations related to transfer commands with VkBuffer as
2285 * destination are ongoing. Some operations like copies on the command
2286 * streamer might need to be aware of this to trigger the appropriate stall
2287 * before they can proceed with the copy.
2289 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2291 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2292 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2293 * done by writing the AUX-TT register.
2295 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2297 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2298 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2299 * implement a workaround for Gen9.
2301 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2304 #define ANV_PIPE_FLUSH_BITS ( \
2305 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2306 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2307 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2308 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2310 #define ANV_PIPE_STALL_BITS ( \
2311 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2312 ANV_PIPE_DEPTH_STALL_BIT | \
2313 ANV_PIPE_CS_STALL_BIT)
2315 #define ANV_PIPE_INVALIDATE_BITS ( \
2316 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2317 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2318 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2319 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2320 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2321 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2322 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2324 static inline enum anv_pipe_bits
2325 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2327 enum anv_pipe_bits pipe_bits
= 0;
2330 for_each_bit(b
, flags
) {
2331 switch ((VkAccessFlagBits
)(1 << b
)) {
2332 case VK_ACCESS_SHADER_WRITE_BIT
:
2333 /* We're transitioning a buffer that was previously used as write
2334 * destination through the data port. To make its content available
2335 * to future operations, flush the data cache.
2337 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2339 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2340 /* We're transitioning a buffer that was previously used as render
2341 * target. To make its content available to future operations, flush
2342 * the render target cache.
2344 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2346 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2347 /* We're transitioning a buffer that was previously used as depth
2348 * buffer. To make its content available to future operations, flush
2351 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2353 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2354 /* We're transitioning a buffer that was previously used as a
2355 * transfer write destination. Generic write operations include color
2356 * & depth operations as well as buffer operations like :
2357 * - vkCmdClearColorImage()
2358 * - vkCmdClearDepthStencilImage()
2359 * - vkCmdBlitImage()
2360 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2362 * Most of these operations are implemented using Blorp which writes
2363 * through the render target, so flush that cache to make it visible
2364 * to future operations. And for depth related operations we also
2365 * need to flush the depth cache.
2367 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2368 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2370 case VK_ACCESS_MEMORY_WRITE_BIT
:
2371 /* We're transitioning a buffer for generic write operations. Flush
2374 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2377 break; /* Nothing to do */
2384 static inline enum anv_pipe_bits
2385 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2387 enum anv_pipe_bits pipe_bits
= 0;
2390 for_each_bit(b
, flags
) {
2391 switch ((VkAccessFlagBits
)(1 << b
)) {
2392 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2393 /* Indirect draw commands take a buffer as input that we're going to
2394 * read from the command streamer to load some of the HW registers
2395 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2396 * command streamer stall so that all the cache flushes have
2397 * completed before the command streamer loads from memory.
2399 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2400 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2401 * through a vertex buffer, so invalidate that cache.
2403 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2404 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2405 * UBO from the buffer, so we need to invalidate constant cache.
2407 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2409 case VK_ACCESS_INDEX_READ_BIT
:
2410 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2411 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2412 * commands, so we invalidate the VF cache to make sure there is no
2413 * stale data when we start rendering.
2415 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2417 case VK_ACCESS_UNIFORM_READ_BIT
:
2418 /* We transitioning a buffer to be used as uniform data. Because
2419 * uniform is accessed through the data port & sampler, we need to
2420 * invalidate the texture cache (sampler) & constant cache (data
2421 * port) to avoid stale data.
2423 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2424 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2426 case VK_ACCESS_SHADER_READ_BIT
:
2427 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2428 case VK_ACCESS_TRANSFER_READ_BIT
:
2429 /* Transitioning a buffer to be read through the sampler, so
2430 * invalidate the texture cache, we don't want any stale data.
2432 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2434 case VK_ACCESS_MEMORY_READ_BIT
:
2435 /* Transitioning a buffer for generic read, invalidate all the
2438 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2440 case VK_ACCESS_MEMORY_WRITE_BIT
:
2441 /* Generic write, make sure all previously written things land in
2444 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2446 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2447 /* Transitioning a buffer for conditional rendering. We'll load the
2448 * content of this buffer into HW registers using the command
2449 * streamer, so we need to stall the command streamer to make sure
2450 * any in-flight flush operations have completed.
2452 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2455 break; /* Nothing to do */
2462 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2463 VK_IMAGE_ASPECT_COLOR_BIT | \
2464 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2465 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2466 VK_IMAGE_ASPECT_PLANE_2_BIT)
2467 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2468 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2469 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2470 VK_IMAGE_ASPECT_PLANE_2_BIT)
2472 struct anv_vertex_binding
{
2473 struct anv_buffer
* buffer
;
2474 VkDeviceSize offset
;
2477 struct anv_xfb_binding
{
2478 struct anv_buffer
* buffer
;
2479 VkDeviceSize offset
;
2483 struct anv_push_constants
{
2484 /** Push constant data provided by the client through vkPushConstants */
2485 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2487 /** Dynamic offsets for dynamic UBOs and SSBOs */
2488 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2490 uint64_t push_reg_mask
;
2492 /** Pad out to a multiple of 32 bytes */
2496 /** Base workgroup ID
2498 * Used for vkCmdDispatchBase.
2500 uint32_t base_work_group_id
[3];
2504 * This is never set by software but is implicitly filled out when
2505 * uploading the push constants for compute shaders.
2507 uint32_t subgroup_id
;
2511 struct anv_dynamic_state
{
2514 VkViewport viewports
[MAX_VIEWPORTS
];
2519 VkRect2D scissors
[MAX_SCISSORS
];
2530 float blend_constants
[4];
2540 } stencil_compare_mask
;
2545 } stencil_write_mask
;
2550 } stencil_reference
;
2558 extern const struct anv_dynamic_state default_dynamic_state
;
2560 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2561 const struct anv_dynamic_state
*src
,
2562 uint32_t copy_mask
);
2564 struct anv_surface_state
{
2565 struct anv_state state
;
2566 /** Address of the surface referred to by this state
2568 * This address is relative to the start of the BO.
2570 struct anv_address address
;
2571 /* Address of the aux surface, if any
2573 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2575 * With the exception of gen8, the bottom 12 bits of this address' offset
2576 * include extra aux information.
2578 struct anv_address aux_address
;
2579 /* Address of the clear color, if any
2581 * This address is relative to the start of the BO.
2583 struct anv_address clear_address
;
2587 * Attachment state when recording a renderpass instance.
2589 * The clear value is valid only if there exists a pending clear.
2591 struct anv_attachment_state
{
2592 enum isl_aux_usage aux_usage
;
2593 struct anv_surface_state color
;
2594 struct anv_surface_state input
;
2596 VkImageLayout current_layout
;
2597 VkImageLayout current_stencil_layout
;
2598 VkImageAspectFlags pending_clear_aspects
;
2599 VkImageAspectFlags pending_load_aspects
;
2601 VkClearValue clear_value
;
2603 /* When multiview is active, attachments with a renderpass clear
2604 * operation have their respective layers cleared on the first
2605 * subpass that uses them, and only in that subpass. We keep track
2606 * of this using a bitfield to indicate which layers of an attachment
2607 * have not been cleared yet when multiview is active.
2609 uint32_t pending_clear_views
;
2610 struct anv_image_view
* image_view
;
2613 /** State tracking for vertex buffer flushes
2615 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2616 * addresses. If you happen to have two vertex buffers which get placed
2617 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2618 * collisions. In order to solve this problem, we track vertex address ranges
2619 * which are live in the cache and invalidate the cache if one ever exceeds 32
2622 struct anv_vb_cache_range
{
2623 /* Virtual address at which the live vertex buffer cache range starts for
2624 * this vertex buffer index.
2628 /* Virtual address of the byte after where vertex buffer cache range ends.
2629 * This is exclusive such that end - start is the size of the range.
2634 /** State tracking for particular pipeline bind point
2636 * This struct is the base struct for anv_cmd_graphics_state and
2637 * anv_cmd_compute_state. These are used to track state which is bound to a
2638 * particular type of pipeline. Generic state that applies per-stage such as
2639 * binding table offsets and push constants is tracked generically with a
2640 * per-stage array in anv_cmd_state.
2642 struct anv_cmd_pipeline_state
{
2643 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2644 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2647 /** State tracking for graphics pipeline
2649 * This has anv_cmd_pipeline_state as a base struct to track things which get
2650 * bound to a graphics pipeline. Along with general pipeline bind point state
2651 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2652 * state which is graphics-specific.
2654 struct anv_cmd_graphics_state
{
2655 struct anv_cmd_pipeline_state base
;
2657 struct anv_graphics_pipeline
*pipeline
;
2659 anv_cmd_dirty_mask_t dirty
;
2662 struct anv_vb_cache_range ib_bound_range
;
2663 struct anv_vb_cache_range ib_dirty_range
;
2664 struct anv_vb_cache_range vb_bound_ranges
[33];
2665 struct anv_vb_cache_range vb_dirty_ranges
[33];
2667 struct anv_dynamic_state dynamic
;
2670 struct anv_buffer
*index_buffer
;
2671 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2672 uint32_t index_offset
;
2676 /** State tracking for compute pipeline
2678 * This has anv_cmd_pipeline_state as a base struct to track things which get
2679 * bound to a compute pipeline. Along with general pipeline bind point state
2680 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2681 * state which is compute-specific.
2683 struct anv_cmd_compute_state
{
2684 struct anv_cmd_pipeline_state base
;
2686 struct anv_compute_pipeline
*pipeline
;
2688 bool pipeline_dirty
;
2690 struct anv_address num_workgroups
;
2693 /** State required while building cmd buffer */
2694 struct anv_cmd_state
{
2695 /* PIPELINE_SELECT.PipelineSelection */
2696 uint32_t current_pipeline
;
2697 const struct gen_l3_config
* current_l3_config
;
2698 uint32_t last_aux_map_state
;
2700 struct anv_cmd_graphics_state gfx
;
2701 struct anv_cmd_compute_state compute
;
2703 enum anv_pipe_bits pending_pipe_bits
;
2704 VkShaderStageFlags descriptors_dirty
;
2705 VkShaderStageFlags push_constants_dirty
;
2707 struct anv_framebuffer
* framebuffer
;
2708 struct anv_render_pass
* pass
;
2709 struct anv_subpass
* subpass
;
2710 VkRect2D render_area
;
2711 uint32_t restart_index
;
2712 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2714 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2715 VkShaderStageFlags push_constant_stages
;
2716 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2717 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2718 struct anv_state samplers
[MESA_SHADER_STAGES
];
2720 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2721 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2722 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2725 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2726 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2727 * and before invoking the secondary in ExecuteCommands.
2729 bool pma_fix_enabled
;
2732 * Whether or not we know for certain that HiZ is enabled for the current
2733 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2734 * enabled or not, this will be false.
2738 bool conditional_render_enabled
;
2741 * Last rendering scale argument provided to
2742 * genX(cmd_buffer_emit_hashing_mode)().
2744 unsigned current_hash_scale
;
2747 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2748 * valid only when recording a render pass instance.
2750 struct anv_attachment_state
* attachments
;
2753 * Surface states for color render targets. These are stored in a single
2754 * flat array. For depth-stencil attachments, the surface state is simply
2757 struct anv_state attachment_states
;
2760 * A null surface state of the right size to match the framebuffer. This
2761 * is one of the states in attachment_states.
2763 struct anv_state null_surface_state
;
2766 struct anv_cmd_pool
{
2767 VkAllocationCallbacks alloc
;
2768 struct list_head cmd_buffers
;
2771 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2773 enum anv_cmd_buffer_exec_mode
{
2774 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2775 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2776 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2777 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2778 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2781 struct anv_cmd_buffer
{
2782 VK_LOADER_DATA _loader_data
;
2784 struct anv_device
* device
;
2786 struct anv_cmd_pool
* pool
;
2787 struct list_head pool_link
;
2789 struct anv_batch batch
;
2791 /* Fields required for the actual chain of anv_batch_bo's.
2793 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2795 struct list_head batch_bos
;
2796 enum anv_cmd_buffer_exec_mode exec_mode
;
2798 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2799 * referenced by this command buffer
2801 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2803 struct u_vector seen_bbos
;
2805 /* A vector of int32_t's for every block of binding tables.
2807 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2809 struct u_vector bt_block_states
;
2810 struct anv_state bt_next
;
2812 struct anv_reloc_list surface_relocs
;
2813 /** Last seen surface state block pool center bo offset */
2814 uint32_t last_ss_pool_center
;
2816 /* Serial for tracking buffer completion */
2819 /* Stream objects for storing temporary data */
2820 struct anv_state_stream surface_state_stream
;
2821 struct anv_state_stream dynamic_state_stream
;
2823 VkCommandBufferUsageFlags usage_flags
;
2824 VkCommandBufferLevel level
;
2826 struct anv_cmd_state state
;
2828 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2829 uint64_t intel_perf_marker
;
2832 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2833 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2834 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2835 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2836 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2837 struct anv_cmd_buffer
*secondary
);
2838 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2839 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2840 struct anv_cmd_buffer
*cmd_buffer
,
2841 const VkSemaphore
*in_semaphores
,
2842 const uint64_t *in_wait_values
,
2843 uint32_t num_in_semaphores
,
2844 const VkSemaphore
*out_semaphores
,
2845 const uint64_t *out_signal_values
,
2846 uint32_t num_out_semaphores
,
2849 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2851 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2852 const void *data
, uint32_t size
, uint32_t alignment
);
2853 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2854 uint32_t *a
, uint32_t *b
,
2855 uint32_t dwords
, uint32_t alignment
);
2858 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2860 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2861 uint32_t entries
, uint32_t *state_offset
);
2863 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2865 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2866 uint32_t size
, uint32_t alignment
);
2869 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2871 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2872 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2873 bool depth_clamp_enable
);
2874 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2876 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2877 struct anv_render_pass
*pass
,
2878 struct anv_framebuffer
*framebuffer
,
2879 const VkClearValue
*clear_values
);
2881 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2884 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2885 gl_shader_stage stage
);
2887 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2889 const struct anv_image_view
*
2890 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2893 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2894 uint32_t num_entries
,
2895 uint32_t *state_offset
,
2896 struct anv_state
*bt_state
);
2898 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2900 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2902 enum anv_fence_type
{
2903 ANV_FENCE_TYPE_NONE
= 0,
2905 ANV_FENCE_TYPE_WSI_BO
,
2906 ANV_FENCE_TYPE_SYNCOBJ
,
2910 enum anv_bo_fence_state
{
2911 /** Indicates that this is a new (or newly reset fence) */
2912 ANV_BO_FENCE_STATE_RESET
,
2914 /** Indicates that this fence has been submitted to the GPU but is still
2915 * (as far as we know) in use by the GPU.
2917 ANV_BO_FENCE_STATE_SUBMITTED
,
2919 ANV_BO_FENCE_STATE_SIGNALED
,
2922 struct anv_fence_impl
{
2923 enum anv_fence_type type
;
2926 /** Fence implementation for BO fences
2928 * These fences use a BO and a set of CPU-tracked state flags. The BO
2929 * is added to the object list of the last execbuf call in a QueueSubmit
2930 * and is marked EXEC_WRITE. The state flags track when the BO has been
2931 * submitted to the kernel. We need to do this because Vulkan lets you
2932 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2933 * will say it's idle in this case.
2937 enum anv_bo_fence_state state
;
2940 /** DRM syncobj handle for syncobj-based fences */
2944 struct wsi_fence
*fence_wsi
;
2949 /* Permanent fence state. Every fence has some form of permanent state
2950 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2951 * cross-process fences) or it could just be a dummy for use internally.
2953 struct anv_fence_impl permanent
;
2955 /* Temporary fence state. A fence *may* have temporary state. That state
2956 * is added to the fence by an import operation and is reset back to
2957 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2958 * state cannot be signaled because the fence must already be signaled
2959 * before the temporary state can be exported from the fence in the other
2960 * process and imported here.
2962 struct anv_fence_impl temporary
;
2965 void anv_fence_reset_temporary(struct anv_device
*device
,
2966 struct anv_fence
*fence
);
2970 struct anv_state state
;
2973 enum anv_semaphore_type
{
2974 ANV_SEMAPHORE_TYPE_NONE
= 0,
2975 ANV_SEMAPHORE_TYPE_DUMMY
,
2976 ANV_SEMAPHORE_TYPE_BO
,
2977 ANV_SEMAPHORE_TYPE_WSI_BO
,
2978 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2979 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2980 ANV_SEMAPHORE_TYPE_TIMELINE
,
2983 struct anv_timeline_point
{
2984 struct list_head link
;
2988 /* Number of waiter on this point, when > 0 the point should not be garbage
2993 /* BO used for synchronization. */
2997 struct anv_timeline
{
2998 pthread_mutex_t mutex
;
2999 pthread_cond_t cond
;
3001 uint64_t highest_past
;
3002 uint64_t highest_pending
;
3004 struct list_head points
;
3005 struct list_head free_points
;
3008 struct anv_semaphore_impl
{
3009 enum anv_semaphore_type type
;
3012 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3013 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3014 * object list on any execbuf2 calls for which this semaphore is used as
3015 * a wait or signal fence. When used as a signal fence or when type ==
3016 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3020 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3021 * If the semaphore is in the unsignaled state due to either just being
3022 * created or because it has been used for a wait, fd will be -1.
3026 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3027 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3028 * import so we don't need to bother with a userspace cache.
3032 /* Non shareable timeline semaphore
3034 * Used when kernel don't have support for timeline semaphores.
3036 struct anv_timeline timeline
;
3040 struct anv_semaphore
{
3043 /* Permanent semaphore state. Every semaphore has some form of permanent
3044 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3045 * (for cross-process semaphores0 or it could just be a dummy for use
3048 struct anv_semaphore_impl permanent
;
3050 /* Temporary semaphore state. A semaphore *may* have temporary state.
3051 * That state is added to the semaphore by an import operation and is reset
3052 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3053 * semaphore with temporary state cannot be signaled because the semaphore
3054 * must already be signaled before the temporary state can be exported from
3055 * the semaphore in the other process and imported here.
3057 struct anv_semaphore_impl temporary
;
3060 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3061 struct anv_semaphore
*semaphore
);
3063 struct anv_shader_module
{
3064 unsigned char sha1
[20];
3069 static inline gl_shader_stage
3070 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3072 assert(__builtin_popcount(vk_stage
) == 1);
3073 return ffs(vk_stage
) - 1;
3076 static inline VkShaderStageFlagBits
3077 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3079 return (1 << mesa_stage
);
3082 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3084 #define anv_foreach_stage(stage, stage_bits) \
3085 for (gl_shader_stage stage, \
3086 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3087 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3088 __tmp &= ~(1 << (stage)))
3090 struct anv_pipeline_bind_map
{
3091 unsigned char surface_sha1
[20];
3092 unsigned char sampler_sha1
[20];
3093 unsigned char push_sha1
[20];
3095 uint32_t surface_count
;
3096 uint32_t sampler_count
;
3098 struct anv_pipeline_binding
* surface_to_descriptor
;
3099 struct anv_pipeline_binding
* sampler_to_descriptor
;
3101 struct anv_push_range push_ranges
[4];
3104 struct anv_shader_bin_key
{
3109 struct anv_shader_bin
{
3112 gl_shader_stage stage
;
3114 const struct anv_shader_bin_key
*key
;
3116 struct anv_state kernel
;
3117 uint32_t kernel_size
;
3119 struct anv_state constant_data
;
3120 uint32_t constant_data_size
;
3122 const struct brw_stage_prog_data
*prog_data
;
3123 uint32_t prog_data_size
;
3125 struct brw_compile_stats stats
[3];
3128 struct nir_xfb_info
*xfb_info
;
3130 struct anv_pipeline_bind_map bind_map
;
3133 struct anv_shader_bin
*
3134 anv_shader_bin_create(struct anv_device
*device
,
3135 gl_shader_stage stage
,
3136 const void *key
, uint32_t key_size
,
3137 const void *kernel
, uint32_t kernel_size
,
3138 const void *constant_data
, uint32_t constant_data_size
,
3139 const struct brw_stage_prog_data
*prog_data
,
3140 uint32_t prog_data_size
,
3141 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3142 const struct nir_xfb_info
*xfb_info
,
3143 const struct anv_pipeline_bind_map
*bind_map
);
3146 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3149 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3151 assert(shader
&& shader
->ref_cnt
>= 1);
3152 p_atomic_inc(&shader
->ref_cnt
);
3156 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3158 assert(shader
&& shader
->ref_cnt
>= 1);
3159 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3160 anv_shader_bin_destroy(device
, shader
);
3163 struct anv_pipeline_executable
{
3164 gl_shader_stage stage
;
3166 struct brw_compile_stats stats
;
3172 enum anv_pipeline_type
{
3173 ANV_PIPELINE_GRAPHICS
,
3174 ANV_PIPELINE_COMPUTE
,
3177 struct anv_pipeline
{
3178 struct anv_device
* device
;
3180 struct anv_batch batch
;
3181 struct anv_reloc_list batch_relocs
;
3185 enum anv_pipeline_type type
;
3186 VkPipelineCreateFlags flags
;
3188 struct util_dynarray executables
;
3190 const struct gen_l3_config
* l3_config
;
3193 struct anv_graphics_pipeline
{
3194 struct anv_pipeline base
;
3196 uint32_t batch_data
[512];
3198 anv_cmd_dirty_mask_t dynamic_state_mask
;
3199 struct anv_dynamic_state dynamic_state
;
3203 struct anv_subpass
* subpass
;
3205 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3207 VkShaderStageFlags active_stages
;
3209 bool primitive_restart
;
3211 bool depth_test_enable
;
3212 bool writes_stencil
;
3213 bool stencil_test_enable
;
3214 bool depth_clamp_enable
;
3215 bool depth_clip_enable
;
3216 bool sample_shading_enable
;
3218 bool depth_bounds_test_enable
;
3220 /* When primitive replication is used, subpass->view_mask will describe what
3221 * views to replicate.
3223 bool use_primitive_replication
;
3225 struct anv_state blend_state
;
3228 struct anv_pipeline_vertex_binding
{
3231 uint32_t instance_divisor
;
3236 uint32_t depth_stencil_state
[3];
3242 uint32_t wm_depth_stencil
[3];
3246 uint32_t wm_depth_stencil
[4];
3250 struct anv_compute_pipeline
{
3251 struct anv_pipeline base
;
3253 struct anv_shader_bin
* cs
;
3254 uint32_t cs_right_mask
;
3255 uint32_t batch_data
[9];
3256 uint32_t interface_descriptor_data
[8];
3259 #define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
3260 static inline struct anv_##pipe_type##_pipeline * \
3261 anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
3263 assert(pipeline->type == pipe_enum); \
3264 return (struct anv_##pipe_type##_pipeline *) pipeline; \
3267 ANV_DECL_PIPELINE_DOWNCAST(graphics
, ANV_PIPELINE_GRAPHICS
)
3268 ANV_DECL_PIPELINE_DOWNCAST(compute
, ANV_PIPELINE_COMPUTE
)
3271 anv_pipeline_has_stage(const struct anv_graphics_pipeline
*pipeline
,
3272 gl_shader_stage stage
)
3274 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3277 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
3278 static inline const struct brw_##prefix##_prog_data * \
3279 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
3281 if (anv_pipeline_has_stage(pipeline, stage)) { \
3282 return (const struct brw_##prefix##_prog_data *) \
3283 pipeline->shaders[stage]->prog_data; \
3289 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3290 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3291 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3292 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3293 ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3295 static inline const struct brw_cs_prog_data
*
3296 get_cs_prog_data(const struct anv_compute_pipeline
*pipeline
)
3298 assert(pipeline
->cs
);
3299 return (const struct brw_cs_prog_data
*) pipeline
->cs
->prog_data
;
3302 static inline const struct brw_vue_prog_data
*
3303 anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline
*pipeline
)
3305 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3306 return &get_gs_prog_data(pipeline
)->base
;
3307 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3308 return &get_tes_prog_data(pipeline
)->base
;
3310 return &get_vs_prog_data(pipeline
)->base
;
3314 anv_pipeline_init(struct anv_graphics_pipeline
*pipeline
, struct anv_device
*device
,
3315 struct anv_pipeline_cache
*cache
,
3316 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3317 const VkAllocationCallbacks
*alloc
);
3320 anv_pipeline_compile_cs(struct anv_compute_pipeline
*pipeline
,
3321 struct anv_pipeline_cache
*cache
,
3322 const VkComputePipelineCreateInfo
*info
,
3323 const struct anv_shader_module
*module
,
3324 const char *entrypoint
,
3325 const VkSpecializationInfo
*spec_info
);
3328 anv_cs_workgroup_size(const struct anv_compute_pipeline
*pipeline
);
3331 anv_cs_threads(const struct anv_compute_pipeline
*pipeline
);
3333 struct anv_format_plane
{
3334 enum isl_format isl_format
:16;
3335 struct isl_swizzle swizzle
;
3337 /* Whether this plane contains chroma channels */
3340 /* For downscaling of YUV planes */
3341 uint8_t denominator_scales
[2];
3343 /* How to map sampled ycbcr planes to a single 4 component element. */
3344 struct isl_swizzle ycbcr_swizzle
;
3346 /* What aspect is associated to this plane */
3347 VkImageAspectFlags aspect
;
3352 struct anv_format_plane planes
[3];
3359 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3360 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3361 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3362 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3364 static inline uint32_t
3365 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3366 VkImageAspectFlags aspect_mask
)
3368 switch (aspect_mask
) {
3369 case VK_IMAGE_ASPECT_COLOR_BIT
:
3370 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3371 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3373 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3374 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3377 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3379 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3382 /* Purposefully assert with depth/stencil aspects. */
3383 unreachable("invalid image aspect");
3387 static inline VkImageAspectFlags
3388 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3391 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3392 if (util_bitcount(image_aspects
) > 1)
3393 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3394 return VK_IMAGE_ASPECT_COLOR_BIT
;
3396 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3397 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3398 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3399 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3402 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3403 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3405 const struct anv_format
*
3406 anv_get_format(VkFormat format
);
3408 static inline uint32_t
3409 anv_get_format_planes(VkFormat vk_format
)
3411 const struct anv_format
*format
= anv_get_format(vk_format
);
3413 return format
!= NULL
? format
->n_planes
: 0;
3416 struct anv_format_plane
3417 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3418 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3420 static inline enum isl_format
3421 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3422 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3424 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3427 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3428 VkImageCreateFlags create_flags
,
3430 VkImageTiling vk_tiling
,
3431 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3433 static inline struct isl_swizzle
3434 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3436 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3437 * RGB as RGBA for texturing
3439 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3440 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3442 /* But it doesn't matter what we render to that channel */
3443 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3449 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3452 * Subsurface of an anv_image.
3454 struct anv_surface
{
3455 /** Valid only if isl_surf::size_B > 0. */
3456 struct isl_surf isl
;
3459 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3465 VkImageType type
; /**< VkImageCreateInfo::imageType */
3466 /* The original VkFormat provided by the client. This may not match any
3467 * of the actual surface formats.
3470 const struct anv_format
*format
;
3472 VkImageAspectFlags aspects
;
3475 uint32_t array_size
;
3476 uint32_t samples
; /**< VkImageCreateInfo::samples */
3478 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3479 VkImageUsageFlags stencil_usage
;
3480 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3481 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3483 /** True if this is needs to be bound to an appropriately tiled BO.
3485 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3486 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3487 * we require a dedicated allocation so that we can know to allocate a
3490 bool needs_set_tiling
;
3493 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3494 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3496 uint64_t drm_format_mod
;
3501 /* Whether the image is made of several underlying buffer objects rather a
3502 * single one with different offsets.
3506 /* Image was created with external format. */
3507 bool external_format
;
3512 * For each foo, anv_image::planes[x].surface is valid if and only if
3513 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3514 * to figure the number associated with a given aspect.
3516 * The hardware requires that the depth buffer and stencil buffer be
3517 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3518 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3519 * allocate the depth and stencil buffers as separate surfaces in the same
3524 * -----------------------
3526 * ----------------------- |
3527 * | shadow surface0 | |
3528 * ----------------------- | Plane 0
3529 * | aux surface0 | |
3530 * ----------------------- |
3531 * | fast clear colors0 | \|/
3532 * -----------------------
3534 * ----------------------- |
3535 * | shadow surface1 | |
3536 * ----------------------- | Plane 1
3537 * | aux surface1 | |
3538 * ----------------------- |
3539 * | fast clear colors1 | \|/
3540 * -----------------------
3543 * -----------------------
3547 * Offset of the entire plane (whenever the image is disjoint this is
3555 struct anv_surface surface
;
3558 * A surface which shadows the main surface and may have different
3559 * tiling. This is used for sampling using a tiling that isn't supported
3560 * for other operations.
3562 struct anv_surface shadow_surface
;
3565 * The base aux usage for this image. For color images, this can be
3566 * either CCS_E or CCS_D depending on whether or not we can reliably
3567 * leave CCS on all the time.
3569 enum isl_aux_usage aux_usage
;
3571 struct anv_surface aux_surface
;
3574 * Offset of the fast clear state (used to compute the
3575 * fast_clear_state_offset of the following planes).
3577 uint32_t fast_clear_state_offset
;
3580 * BO associated with this plane, set when bound.
3582 struct anv_address address
;
3585 * When destroying the image, also free the bo.
3591 /* The ordering of this enum is important */
3592 enum anv_fast_clear_type
{
3593 /** Image does not have/support any fast-clear blocks */
3594 ANV_FAST_CLEAR_NONE
= 0,
3595 /** Image has/supports fast-clear but only to the default value */
3596 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3597 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3598 ANV_FAST_CLEAR_ANY
= 2,
3601 /* Returns the number of auxiliary buffer levels attached to an image. */
3602 static inline uint8_t
3603 anv_image_aux_levels(const struct anv_image
* const image
,
3604 VkImageAspectFlagBits aspect
)
3606 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3607 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3610 /* The Gen12 CCS aux surface is represented with only one level. */
3611 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3612 image
->planes
[plane
].surface
.isl
.levels
:
3613 image
->planes
[plane
].aux_surface
.isl
.levels
;
3616 /* Returns the number of auxiliary buffer layers attached to an image. */
3617 static inline uint32_t
3618 anv_image_aux_layers(const struct anv_image
* const image
,
3619 VkImageAspectFlagBits aspect
,
3620 const uint8_t miplevel
)
3624 /* The miplevel must exist in the main buffer. */
3625 assert(miplevel
< image
->levels
);
3627 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3628 /* There are no layers with auxiliary data because the miplevel has no
3633 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3635 /* The Gen12 CCS aux surface is represented with only one layer. */
3636 const struct isl_extent4d
*aux_logical_level0_px
=
3637 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3638 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3639 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3641 return MAX2(aux_logical_level0_px
->array_len
,
3642 aux_logical_level0_px
->depth
>> miplevel
);
3646 static inline struct anv_address
3647 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3648 const struct anv_image
*image
,
3649 VkImageAspectFlagBits aspect
)
3651 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3653 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3654 return anv_address_add(image
->planes
[plane
].address
,
3655 image
->planes
[plane
].fast_clear_state_offset
);
3658 static inline struct anv_address
3659 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3660 const struct anv_image
*image
,
3661 VkImageAspectFlagBits aspect
)
3663 struct anv_address addr
=
3664 anv_image_get_clear_color_addr(device
, image
, aspect
);
3666 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3667 device
->isl_dev
.ss
.clear_color_state_size
:
3668 device
->isl_dev
.ss
.clear_value_size
;
3669 return anv_address_add(addr
, clear_color_state_size
);
3672 static inline struct anv_address
3673 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3674 const struct anv_image
*image
,
3675 VkImageAspectFlagBits aspect
,
3676 uint32_t level
, uint32_t array_layer
)
3678 assert(level
< anv_image_aux_levels(image
, aspect
));
3679 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3680 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3681 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3683 struct anv_address addr
=
3684 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3685 addr
.offset
+= 4; /* Go past the fast clear type */
3687 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3688 for (uint32_t l
= 0; l
< level
; l
++)
3689 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3691 addr
.offset
+= level
* image
->array_size
* 4;
3693 addr
.offset
+= array_layer
* 4;
3695 assert(addr
.offset
<
3696 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3700 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3702 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3703 const struct anv_image
*image
)
3705 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3708 /* For Gen8-11, there are some restrictions around sampling from HiZ.
3709 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
3712 * "If this field is set to AUX_HIZ, Number of Multisamples must
3713 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
3715 if (image
->type
== VK_IMAGE_TYPE_3D
)
3718 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3719 * struct. There's documentation which suggests that this feature actually
3720 * reduces performance on BDW, but it has only been observed to help so
3721 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3722 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3724 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3727 return image
->samples
== 1;
3731 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3732 const struct anv_image
*image
,
3735 return device
->info
.has_aux_map
&&
3736 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3740 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3741 const struct anv_image
*image
,
3742 VkImageAspectFlagBits aspect
,
3743 enum isl_aux_usage aux_usage
,
3745 uint32_t base_layer
,
3746 uint32_t layer_count
);
3749 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3750 const struct anv_image
*image
,
3751 VkImageAspectFlagBits aspect
,
3752 enum isl_aux_usage aux_usage
,
3753 enum isl_format format
, struct isl_swizzle swizzle
,
3754 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3755 VkRect2D area
, union isl_color_value clear_color
);
3757 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3758 const struct anv_image
*image
,
3759 VkImageAspectFlags aspects
,
3760 enum isl_aux_usage depth_aux_usage
,
3762 uint32_t base_layer
, uint32_t layer_count
,
3764 float depth_value
, uint8_t stencil_value
);
3766 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3767 const struct anv_image
*src_image
,
3768 enum isl_aux_usage src_aux_usage
,
3769 uint32_t src_level
, uint32_t src_base_layer
,
3770 const struct anv_image
*dst_image
,
3771 enum isl_aux_usage dst_aux_usage
,
3772 uint32_t dst_level
, uint32_t dst_base_layer
,
3773 VkImageAspectFlagBits aspect
,
3774 uint32_t src_x
, uint32_t src_y
,
3775 uint32_t dst_x
, uint32_t dst_y
,
3776 uint32_t width
, uint32_t height
,
3777 uint32_t layer_count
,
3778 enum blorp_filter filter
);
3780 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3781 const struct anv_image
*image
,
3782 VkImageAspectFlagBits aspect
, uint32_t level
,
3783 uint32_t base_layer
, uint32_t layer_count
,
3784 enum isl_aux_op hiz_op
);
3786 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3787 const struct anv_image
*image
,
3788 VkImageAspectFlags aspects
,
3790 uint32_t base_layer
, uint32_t layer_count
,
3791 VkRect2D area
, uint8_t stencil_value
);
3793 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3794 const struct anv_image
*image
,
3795 enum isl_format format
, struct isl_swizzle swizzle
,
3796 VkImageAspectFlagBits aspect
,
3797 uint32_t base_layer
, uint32_t layer_count
,
3798 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3801 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3802 const struct anv_image
*image
,
3803 enum isl_format format
, struct isl_swizzle swizzle
,
3804 VkImageAspectFlagBits aspect
, uint32_t level
,
3805 uint32_t base_layer
, uint32_t layer_count
,
3806 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3810 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3811 const struct anv_image
*image
,
3812 VkImageAspectFlagBits aspect
,
3813 uint32_t base_level
, uint32_t level_count
,
3814 uint32_t base_layer
, uint32_t layer_count
);
3817 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3818 const struct anv_image
*image
,
3819 const VkImageAspectFlagBits aspect
,
3820 const VkImageLayout layout
);
3823 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3824 const struct anv_image
*image
,
3825 const VkImageAspectFlagBits aspect
,
3826 const VkImageUsageFlagBits usage
,
3827 const VkImageLayout layout
);
3829 enum anv_fast_clear_type
3830 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3831 const struct anv_image
* const image
,
3832 const VkImageAspectFlagBits aspect
,
3833 const VkImageLayout layout
);
3835 /* This is defined as a macro so that it works for both
3836 * VkImageSubresourceRange and VkImageSubresourceLayers
3838 #define anv_get_layerCount(_image, _range) \
3839 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3840 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3842 static inline uint32_t
3843 anv_get_levelCount(const struct anv_image
*image
,
3844 const VkImageSubresourceRange
*range
)
3846 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3847 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3850 static inline VkImageAspectFlags
3851 anv_image_expand_aspects(const struct anv_image
*image
,
3852 VkImageAspectFlags aspects
)
3854 /* If the underlying image has color plane aspects and
3855 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3856 * the underlying image. */
3857 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3858 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3859 return image
->aspects
;
3865 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3866 VkImageAspectFlags aspects2
)
3868 if (aspects1
== aspects2
)
3871 /* Only 1 color aspects are compatibles. */
3872 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3873 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3874 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3880 struct anv_image_view
{
3881 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3883 VkImageAspectFlags aspect_mask
;
3885 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3889 uint32_t image_plane
;
3891 struct isl_view isl
;
3894 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3895 * image layout of SHADER_READ_ONLY_OPTIMAL or
3896 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3898 struct anv_surface_state optimal_sampler_surface_state
;
3901 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3902 * image layout of GENERAL.
3904 struct anv_surface_state general_sampler_surface_state
;
3907 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3908 * states for write-only and readable, using the real format for
3909 * write-only and the lowered format for readable.
3911 struct anv_surface_state storage_surface_state
;
3912 struct anv_surface_state writeonly_storage_surface_state
;
3914 struct brw_image_param storage_image_param
;
3918 enum anv_image_view_state_flags
{
3919 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3920 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3923 void anv_image_fill_surface_state(struct anv_device
*device
,
3924 const struct anv_image
*image
,
3925 VkImageAspectFlagBits aspect
,
3926 const struct isl_view
*view
,
3927 isl_surf_usage_flags_t view_usage
,
3928 enum isl_aux_usage aux_usage
,
3929 const union isl_color_value
*clear_color
,
3930 enum anv_image_view_state_flags flags
,
3931 struct anv_surface_state
*state_inout
,
3932 struct brw_image_param
*image_param_out
);
3934 struct anv_image_create_info
{
3935 const VkImageCreateInfo
*vk_info
;
3937 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3938 isl_tiling_flags_t isl_tiling_flags
;
3940 /** These flags will be added to any derived from VkImageCreateInfo. */
3941 isl_surf_usage_flags_t isl_extra_usage_flags
;
3944 bool external_format
;
3947 VkResult
anv_image_create(VkDevice _device
,
3948 const struct anv_image_create_info
*info
,
3949 const VkAllocationCallbacks
* alloc
,
3953 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3955 static inline VkExtent3D
3956 anv_sanitize_image_extent(const VkImageType imageType
,
3957 const VkExtent3D imageExtent
)
3959 switch (imageType
) {
3960 case VK_IMAGE_TYPE_1D
:
3961 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3962 case VK_IMAGE_TYPE_2D
:
3963 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3964 case VK_IMAGE_TYPE_3D
:
3967 unreachable("invalid image type");
3971 static inline VkOffset3D
3972 anv_sanitize_image_offset(const VkImageType imageType
,
3973 const VkOffset3D imageOffset
)
3975 switch (imageType
) {
3976 case VK_IMAGE_TYPE_1D
:
3977 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3978 case VK_IMAGE_TYPE_2D
:
3979 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3980 case VK_IMAGE_TYPE_3D
:
3983 unreachable("invalid image type");
3987 VkFormatFeatureFlags
3988 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3990 const struct anv_format
*anv_format
,
3991 VkImageTiling vk_tiling
);
3993 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3994 struct anv_state state
,
3995 enum isl_format format
,
3996 struct anv_address address
,
3997 uint32_t range
, uint32_t stride
);
4000 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
4001 const struct anv_attachment_state
*att_state
,
4002 const struct anv_image_view
*iview
)
4004 const struct isl_format_layout
*view_fmtl
=
4005 isl_format_get_layout(iview
->planes
[0].isl
.format
);
4007 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
4008 if (view_fmtl->channels.c.bits) \
4009 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
4011 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
4012 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
4013 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
4014 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
4016 #undef COPY_CLEAR_COLOR_CHANNEL
4020 struct anv_ycbcr_conversion
{
4021 const struct anv_format
* format
;
4022 VkSamplerYcbcrModelConversion ycbcr_model
;
4023 VkSamplerYcbcrRange ycbcr_range
;
4024 VkComponentSwizzle mapping
[4];
4025 VkChromaLocation chroma_offsets
[2];
4026 VkFilter chroma_filter
;
4027 bool chroma_reconstruction
;
4030 struct anv_sampler
{
4031 uint32_t state
[3][4];
4033 struct anv_ycbcr_conversion
*conversion
;
4035 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
4036 * and with a 32-byte stride for use as bindless samplers.
4038 struct anv_state bindless_state
;
4041 struct anv_framebuffer
{
4046 uint32_t attachment_count
;
4047 struct anv_image_view
* attachments
[0];
4050 struct anv_subpass_attachment
{
4051 VkImageUsageFlagBits usage
;
4052 uint32_t attachment
;
4053 VkImageLayout layout
;
4055 /* Used only with attachment containing stencil data. */
4056 VkImageLayout stencil_layout
;
4059 struct anv_subpass
{
4060 uint32_t attachment_count
;
4063 * A pointer to all attachment references used in this subpass.
4064 * Only valid if ::attachment_count > 0.
4066 struct anv_subpass_attachment
* attachments
;
4067 uint32_t input_count
;
4068 struct anv_subpass_attachment
* input_attachments
;
4069 uint32_t color_count
;
4070 struct anv_subpass_attachment
* color_attachments
;
4071 struct anv_subpass_attachment
* resolve_attachments
;
4073 struct anv_subpass_attachment
* depth_stencil_attachment
;
4074 struct anv_subpass_attachment
* ds_resolve_attachment
;
4075 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4076 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4080 /** Subpass has a depth/stencil self-dependency */
4081 bool has_ds_self_dep
;
4083 /** Subpass has at least one color resolve attachment */
4084 bool has_color_resolve
;
4087 static inline unsigned
4088 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4090 return MAX2(1, util_bitcount(subpass
->view_mask
));
4093 struct anv_render_pass_attachment
{
4094 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4095 * its members individually.
4099 VkImageUsageFlags usage
;
4100 VkAttachmentLoadOp load_op
;
4101 VkAttachmentStoreOp store_op
;
4102 VkAttachmentLoadOp stencil_load_op
;
4103 VkImageLayout initial_layout
;
4104 VkImageLayout final_layout
;
4105 VkImageLayout first_subpass_layout
;
4107 VkImageLayout stencil_initial_layout
;
4108 VkImageLayout stencil_final_layout
;
4110 /* The subpass id in which the attachment will be used last. */
4111 uint32_t last_subpass_idx
;
4114 struct anv_render_pass
{
4115 uint32_t attachment_count
;
4116 uint32_t subpass_count
;
4117 /* An array of subpass_count+1 flushes, one per subpass boundary */
4118 enum anv_pipe_bits
* subpass_flushes
;
4119 struct anv_render_pass_attachment
* attachments
;
4120 struct anv_subpass subpasses
[0];
4123 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4125 struct anv_query_pool
{
4127 VkQueryPipelineStatisticFlags pipeline_statistics
;
4128 /** Stride between slots, in bytes */
4130 /** Number of slots in this query pool */
4135 int anv_get_instance_entrypoint_index(const char *name
);
4136 int anv_get_device_entrypoint_index(const char *name
);
4137 int anv_get_physical_device_entrypoint_index(const char *name
);
4139 const char *anv_get_instance_entry_name(int index
);
4140 const char *anv_get_physical_device_entry_name(int index
);
4141 const char *anv_get_device_entry_name(int index
);
4144 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4145 const struct anv_instance_extension_table
*instance
);
4147 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4148 const struct anv_instance_extension_table
*instance
);
4150 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4151 const struct anv_instance_extension_table
*instance
,
4152 const struct anv_device_extension_table
*device
);
4154 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4157 void anv_dump_image_to_ppm(struct anv_device
*device
,
4158 struct anv_image
*image
, unsigned miplevel
,
4159 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4160 const char *filename
);
4162 enum anv_dump_action
{
4163 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4166 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4167 void anv_dump_finish(void);
4169 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4171 static inline uint32_t
4172 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4174 /* This function must be called from within a subpass. */
4175 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4177 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4179 /* The id of this subpass shouldn't exceed the number of subpasses in this
4180 * render pass minus 1.
4182 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4186 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4187 void anv_device_perf_init(struct anv_device
*device
);
4189 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4191 static inline struct __anv_type * \
4192 __anv_type ## _from_handle(__VkType _handle) \
4194 return (struct __anv_type *) _handle; \
4197 static inline __VkType \
4198 __anv_type ## _to_handle(struct __anv_type *_obj) \
4200 return (__VkType) _obj; \
4203 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4205 static inline struct __anv_type * \
4206 __anv_type ## _from_handle(__VkType _handle) \
4208 return (struct __anv_type *)(uintptr_t) _handle; \
4211 static inline __VkType \
4212 __anv_type ## _to_handle(struct __anv_type *_obj) \
4214 return (__VkType)(uintptr_t) _obj; \
4217 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4218 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4220 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4221 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4222 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4223 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4224 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4226 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4227 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4228 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4229 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4230 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4231 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4232 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4233 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4234 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4235 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4236 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4237 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4238 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4239 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4240 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4241 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4242 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4243 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4244 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4245 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4246 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4247 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4248 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4250 /* Gen-specific function declarations */
4252 # include "anv_genX.h"
4254 # define genX(x) gen7_##x
4255 # include "anv_genX.h"
4257 # define genX(x) gen75_##x
4258 # include "anv_genX.h"
4260 # define genX(x) gen8_##x
4261 # include "anv_genX.h"
4263 # define genX(x) gen9_##x
4264 # include "anv_genX.h"
4266 # define genX(x) gen10_##x
4267 # include "anv_genX.h"
4269 # define genX(x) gen11_##x
4270 # include "anv_genX.h"
4272 # define genX(x) gen12_##x
4273 # include "anv_genX.h"
4277 #endif /* ANV_PRIVATE_H */