2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
33 #include "drm-uapi/i915_drm.h"
40 #define __gen_validate_value(x) VALGRIND_CHECK_MEM_IS_DEFINED(&(x), sizeof(x))
43 #define VG(x) ((void)0)
46 #include "common/gen_clflush.h"
47 #include "common/gen_decoder.h"
48 #include "common/gen_gem.h"
49 #include "common/gen_l3_config.h"
50 #include "dev/gen_device_info.h"
51 #include "blorp/blorp.h"
52 #include "compiler/brw_compiler.h"
53 #include "util/bitset.h"
54 #include "util/macros.h"
55 #include "util/hash_table.h"
56 #include "util/list.h"
57 #include "util/sparse_array.h"
58 #include "util/u_atomic.h"
59 #include "util/u_vector.h"
60 #include "util/u_math.h"
62 #include "util/xmlconfig.h"
64 #include "vk_debug_report.h"
66 /* Pre-declarations needed for WSI entrypoints */
69 typedef struct xcb_connection_t xcb_connection_t
;
70 typedef uint32_t xcb_visualid_t
;
71 typedef uint32_t xcb_window_t
;
75 struct anv_buffer_view
;
76 struct anv_image_view
;
79 struct gen_aux_map_context
;
80 struct gen_perf_config
;
82 #include <vulkan/vulkan.h>
83 #include <vulkan/vulkan_intel.h>
84 #include <vulkan/vk_icd.h>
86 #include "anv_android.h"
87 #include "anv_entrypoints.h"
88 #include "anv_extensions.h"
91 #include "dev/gen_debug.h"
92 #include "common/intel_log.h"
93 #include "wsi_common.h"
95 #define NSEC_PER_SEC 1000000000ull
97 /* anv Virtual Memory Layout
98 * =========================
100 * When the anv driver is determining the virtual graphics addresses of memory
101 * objects itself using the softpin mechanism, the following memory ranges
104 * Three special considerations to notice:
106 * (1) the dynamic state pool is located within the same 4 GiB as the low
107 * heap. This is to work around a VF cache issue described in a comment in
108 * anv_physical_device_init_heaps.
110 * (2) the binding table pool is located at lower addresses than the surface
111 * state pool, within a 4 GiB range. This allows surface state base addresses
112 * to cover both binding tables (16 bit offsets) and surface states (32 bit
115 * (3) the last 4 GiB of the address space is withheld from the high
116 * heap. Various hardware units will read past the end of an object for
117 * various reasons. This healthy margin prevents reads from wrapping around
120 #define LOW_HEAP_MIN_ADDRESS 0x000000001000ULL /* 4 KiB */
121 #define LOW_HEAP_MAX_ADDRESS 0x0000bfffffffULL
122 #define DYNAMIC_STATE_POOL_MIN_ADDRESS 0x0000c0000000ULL /* 3 GiB */
123 #define DYNAMIC_STATE_POOL_MAX_ADDRESS 0x0000ffffffffULL
124 #define BINDING_TABLE_POOL_MIN_ADDRESS 0x000100000000ULL /* 4 GiB */
125 #define BINDING_TABLE_POOL_MAX_ADDRESS 0x00013fffffffULL
126 #define SURFACE_STATE_POOL_MIN_ADDRESS 0x000140000000ULL /* 5 GiB */
127 #define SURFACE_STATE_POOL_MAX_ADDRESS 0x00017fffffffULL
128 #define INSTRUCTION_STATE_POOL_MIN_ADDRESS 0x000180000000ULL /* 6 GiB */
129 #define INSTRUCTION_STATE_POOL_MAX_ADDRESS 0x0001bfffffffULL
130 #define CLIENT_VISIBLE_HEAP_MIN_ADDRESS 0x0001c0000000ULL /* 7 GiB */
131 #define CLIENT_VISIBLE_HEAP_MAX_ADDRESS 0x0002bfffffffULL
132 #define HIGH_HEAP_MIN_ADDRESS 0x0002c0000000ULL /* 11 GiB */
134 #define LOW_HEAP_SIZE \
135 (LOW_HEAP_MAX_ADDRESS - LOW_HEAP_MIN_ADDRESS + 1)
136 #define DYNAMIC_STATE_POOL_SIZE \
137 (DYNAMIC_STATE_POOL_MAX_ADDRESS - DYNAMIC_STATE_POOL_MIN_ADDRESS + 1)
138 #define BINDING_TABLE_POOL_SIZE \
139 (BINDING_TABLE_POOL_MAX_ADDRESS - BINDING_TABLE_POOL_MIN_ADDRESS + 1)
140 #define SURFACE_STATE_POOL_SIZE \
141 (SURFACE_STATE_POOL_MAX_ADDRESS - SURFACE_STATE_POOL_MIN_ADDRESS + 1)
142 #define INSTRUCTION_STATE_POOL_SIZE \
143 (INSTRUCTION_STATE_POOL_MAX_ADDRESS - INSTRUCTION_STATE_POOL_MIN_ADDRESS + 1)
144 #define CLIENT_VISIBLE_HEAP_SIZE \
145 (CLIENT_VISIBLE_HEAP_MAX_ADDRESS - CLIENT_VISIBLE_HEAP_MIN_ADDRESS + 1)
147 /* Allowing different clear colors requires us to perform a depth resolve at
148 * the end of certain render passes. This is because while slow clears store
149 * the clear color in the HiZ buffer, fast clears (without a resolve) don't.
150 * See the PRMs for examples describing when additional resolves would be
151 * necessary. To enable fast clears without requiring extra resolves, we set
152 * the clear value to a globally-defined one. We could allow different values
153 * if the user doesn't expect coherent data during or after a render passes
154 * (VK_ATTACHMENT_STORE_OP_DONT_CARE), but such users (aside from the CTS)
155 * don't seem to exist yet. In almost all Vulkan applications tested thus far,
156 * 1.0f seems to be the only value used. The only application that doesn't set
157 * this value does so through the usage of an seemingly uninitialized clear
160 #define ANV_HZ_FC_VAL 1.0f
163 #define MAX_XFB_BUFFERS 4
164 #define MAX_XFB_STREAMS 4
167 #define MAX_VIEWPORTS 16
168 #define MAX_SCISSORS 16
169 #define MAX_PUSH_CONSTANTS_SIZE 128
170 #define MAX_DYNAMIC_BUFFERS 16
171 #define MAX_IMAGES 64
172 #define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
173 #define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
174 #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
175 #define ANV_UBO_BOUNDS_CHECK_ALIGNMENT 32
176 #define ANV_SSBO_BOUNDS_CHECK_ALIGNMENT 4
178 /* From the Skylake PRM Vol. 7 "Binding Table Surface State Model":
180 * "The surface state model is used when a Binding Table Index (specified
181 * in the message descriptor) of less than 240 is specified. In this model,
182 * the Binding Table Index is used to index into the binding table, and the
183 * binding table entry contains a pointer to the SURFACE_STATE."
185 * Binding table values above 240 are used for various things in the hardware
186 * such as stateless, stateless with incoherent cache, SLM, and bindless.
188 #define MAX_BINDING_TABLE_SIZE 240
190 /* The kernel relocation API has a limitation of a 32-bit delta value
191 * applied to the address before it is written which, in spite of it being
192 * unsigned, is treated as signed . Because of the way that this maps to
193 * the Vulkan API, we cannot handle an offset into a buffer that does not
194 * fit into a signed 32 bits. The only mechanism we have for dealing with
195 * this at the moment is to limit all VkDeviceMemory objects to a maximum
196 * of 2GB each. The Vulkan spec allows us to do this:
198 * "Some platforms may have a limit on the maximum size of a single
199 * allocation. For example, certain systems may fail to create
200 * allocations with a size greater than or equal to 4GB. Such a limit is
201 * implementation-dependent, and if such a failure occurs then the error
202 * VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned."
204 * We don't use vk_error here because it's not an error so much as an
205 * indication to the application that the allocation is too large.
207 #define MAX_MEMORY_ALLOCATION_SIZE (1ull << 31)
209 #define ANV_SVGS_VB_INDEX MAX_VBS
210 #define ANV_DRAWID_VB_INDEX (MAX_VBS + 1)
212 /* We reserve this MI ALU register for the purpose of handling predication.
213 * Other code which uses the MI ALU should leave it alone.
215 #define ANV_PREDICATE_RESULT_REG 0x2678 /* MI_ALU_REG15 */
217 /* For gen12 we set the streamout buffers using 4 separate commands
218 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout
219 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of
220 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the
221 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode.
222 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for
223 * 3DSTATE_SO_BUFFER_INDEX_0.
225 #define SO_BUFFER_INDEX_0_CMD 0x60
226 #define anv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
228 static inline uint32_t
229 align_down_npot_u32(uint32_t v
, uint32_t a
)
234 static inline uint32_t
235 align_down_u32(uint32_t v
, uint32_t a
)
237 assert(a
!= 0 && a
== (a
& -a
));
241 static inline uint32_t
242 align_u32(uint32_t v
, uint32_t a
)
244 assert(a
!= 0 && a
== (a
& -a
));
245 return align_down_u32(v
+ a
- 1, a
);
248 static inline uint64_t
249 align_down_u64(uint64_t v
, uint64_t a
)
251 assert(a
!= 0 && a
== (a
& -a
));
255 static inline uint64_t
256 align_u64(uint64_t v
, uint64_t a
)
258 return align_down_u64(v
+ a
- 1, a
);
261 static inline int32_t
262 align_i32(int32_t v
, int32_t a
)
264 assert(a
!= 0 && a
== (a
& -a
));
265 return (v
+ a
- 1) & ~(a
- 1);
268 /** Alignment must be a power of 2. */
270 anv_is_aligned(uintmax_t n
, uintmax_t a
)
272 assert(a
== (a
& -a
));
273 return (n
& (a
- 1)) == 0;
276 static inline uint32_t
277 anv_minify(uint32_t n
, uint32_t levels
)
279 if (unlikely(n
== 0))
282 return MAX2(n
>> levels
, 1);
286 anv_clamp_f(float f
, float min
, float max
)
299 anv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
301 if (*inout_mask
& clear_mask
) {
302 *inout_mask
&= ~clear_mask
;
309 static inline union isl_color_value
310 vk_to_isl_color(VkClearColorValue color
)
312 return (union isl_color_value
) {
322 static inline void *anv_unpack_ptr(uintptr_t ptr
, int bits
, int *flags
)
324 uintptr_t mask
= (1ull << bits
) - 1;
326 return (void *) (ptr
& ~mask
);
329 static inline uintptr_t anv_pack_ptr(void *ptr
, int bits
, int flags
)
331 uintptr_t value
= (uintptr_t) ptr
;
332 uintptr_t mask
= (1ull << bits
) - 1;
333 return value
| (mask
& flags
);
336 #define for_each_bit(b, dword) \
337 for (uint32_t __dword = (dword); \
338 (b) = __builtin_ffs(__dword) - 1, __dword; \
339 __dword &= ~(1 << (b)))
341 #define typed_memcpy(dest, src, count) ({ \
342 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
343 memcpy((dest), (src), (count) * sizeof(*(src))); \
346 /* Mapping from anv object to VkDebugReportObjectTypeEXT. New types need
347 * to be added here in order to utilize mapping in debug/error/perf macros.
349 #define REPORT_OBJECT_TYPE(o) \
350 __builtin_choose_expr ( \
351 __builtin_types_compatible_p (__typeof (o), struct anv_instance*), \
352 VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT, \
353 __builtin_choose_expr ( \
354 __builtin_types_compatible_p (__typeof (o), struct anv_physical_device*), \
355 VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT, \
356 __builtin_choose_expr ( \
357 __builtin_types_compatible_p (__typeof (o), struct anv_device*), \
358 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
359 __builtin_choose_expr ( \
360 __builtin_types_compatible_p (__typeof (o), const struct anv_device*), \
361 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT, \
362 __builtin_choose_expr ( \
363 __builtin_types_compatible_p (__typeof (o), struct anv_queue*), \
364 VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT, \
365 __builtin_choose_expr ( \
366 __builtin_types_compatible_p (__typeof (o), struct anv_semaphore*), \
367 VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT, \
368 __builtin_choose_expr ( \
369 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_buffer*), \
370 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT, \
371 __builtin_choose_expr ( \
372 __builtin_types_compatible_p (__typeof (o), struct anv_fence*), \
373 VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT, \
374 __builtin_choose_expr ( \
375 __builtin_types_compatible_p (__typeof (o), struct anv_device_memory*), \
376 VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT, \
377 __builtin_choose_expr ( \
378 __builtin_types_compatible_p (__typeof (o), struct anv_buffer*), \
379 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT, \
380 __builtin_choose_expr ( \
381 __builtin_types_compatible_p (__typeof (o), struct anv_image*), \
382 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
383 __builtin_choose_expr ( \
384 __builtin_types_compatible_p (__typeof (o), const struct anv_image*), \
385 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT, \
386 __builtin_choose_expr ( \
387 __builtin_types_compatible_p (__typeof (o), struct anv_event*), \
388 VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT, \
389 __builtin_choose_expr ( \
390 __builtin_types_compatible_p (__typeof (o), struct anv_query_pool*), \
391 VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT, \
392 __builtin_choose_expr ( \
393 __builtin_types_compatible_p (__typeof (o), struct anv_buffer_view*), \
394 VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT, \
395 __builtin_choose_expr ( \
396 __builtin_types_compatible_p (__typeof (o), struct anv_image_view*), \
397 VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT, \
398 __builtin_choose_expr ( \
399 __builtin_types_compatible_p (__typeof (o), struct anv_shader_module*), \
400 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT, \
401 __builtin_choose_expr ( \
402 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_cache*), \
403 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT, \
404 __builtin_choose_expr ( \
405 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline_layout*), \
406 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT, \
407 __builtin_choose_expr ( \
408 __builtin_types_compatible_p (__typeof (o), struct anv_render_pass*), \
409 VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT, \
410 __builtin_choose_expr ( \
411 __builtin_types_compatible_p (__typeof (o), struct anv_pipeline*), \
412 VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT, \
413 __builtin_choose_expr ( \
414 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set_layout*), \
415 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT, \
416 __builtin_choose_expr ( \
417 __builtin_types_compatible_p (__typeof (o), struct anv_sampler*), \
418 VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT, \
419 __builtin_choose_expr ( \
420 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_pool*), \
421 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT, \
422 __builtin_choose_expr ( \
423 __builtin_types_compatible_p (__typeof (o), struct anv_descriptor_set*), \
424 VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT, \
425 __builtin_choose_expr ( \
426 __builtin_types_compatible_p (__typeof (o), struct anv_framebuffer*), \
427 VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT, \
428 __builtin_choose_expr ( \
429 __builtin_types_compatible_p (__typeof (o), struct anv_cmd_pool*), \
430 VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT, \
431 __builtin_choose_expr ( \
432 __builtin_types_compatible_p (__typeof (o), struct anv_surface*), \
433 VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT, \
434 __builtin_choose_expr ( \
435 __builtin_types_compatible_p (__typeof (o), struct wsi_swapchain*), \
436 VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT, \
437 __builtin_choose_expr ( \
438 __builtin_types_compatible_p (__typeof (o), struct vk_debug_callback*), \
439 VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT, \
440 __builtin_choose_expr ( \
441 __builtin_types_compatible_p (__typeof (o), void*), \
442 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
443 /* The void expression results in a compile-time error \
444 when assigning the result to something. */ \
445 (void)0)))))))))))))))))))))))))))))))
447 /* Whenever we generate an error, pass it through this function. Useful for
448 * debugging, where we can break on it. Only call at error site, not when
449 * propagating errors. Might be useful to plug in a stack trace here.
452 VkResult
__vk_errorv(struct anv_instance
*instance
, const void *object
,
453 VkDebugReportObjectTypeEXT type
, VkResult error
,
454 const char *file
, int line
, const char *format
,
457 VkResult
__vk_errorf(struct anv_instance
*instance
, const void *object
,
458 VkDebugReportObjectTypeEXT type
, VkResult error
,
459 const char *file
, int line
, const char *format
, ...)
460 anv_printflike(7, 8);
463 #define vk_error(error) __vk_errorf(NULL, NULL,\
464 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
465 error, __FILE__, __LINE__, NULL)
466 #define vk_errorfi(instance, obj, error, format, ...)\
467 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
468 __FILE__, __LINE__, format, ## __VA_ARGS__)
469 #define vk_errorf(device, obj, error, format, ...)\
470 vk_errorfi(anv_device_instance_or_null(device),\
471 obj, error, format, ## __VA_ARGS__)
473 #define vk_error(error) error
474 #define vk_errorfi(instance, obj, error, format, ...) error
475 #define vk_errorf(device, obj, error, format, ...) error
479 * Warn on ignored extension structs.
481 * The Vulkan spec requires us to ignore unsupported or unknown structs in
482 * a pNext chain. In debug mode, emitting warnings for ignored structs may
483 * help us discover structs that we should not have ignored.
486 * From the Vulkan 1.0.38 spec:
488 * Any component of the implementation (the loader, any enabled layers,
489 * and drivers) must skip over, without processing (other than reading the
490 * sType and pNext members) any chained structures with sType values not
491 * defined by extensions supported by that component.
493 #define anv_debug_ignored_stype(sType) \
494 intel_logd("%s: ignored VkStructureType %u\n", __func__, (sType))
496 void __anv_perf_warn(struct anv_device
*device
, const void *object
,
497 VkDebugReportObjectTypeEXT type
, const char *file
,
498 int line
, const char *format
, ...)
499 anv_printflike(6, 7);
500 void anv_loge(const char *format
, ...) anv_printflike(1, 2);
501 void anv_loge_v(const char *format
, va_list va
);
504 * Print a FINISHME message, including its source location.
506 #define anv_finishme(format, ...) \
508 static bool reported = false; \
510 intel_logw("%s:%d: FINISHME: " format, __FILE__, __LINE__, \
517 * Print a perf warning message. Set INTEL_DEBUG=perf to see these.
519 #define anv_perf_warn(instance, obj, format, ...) \
521 static bool reported = false; \
522 if (!reported && unlikely(INTEL_DEBUG & DEBUG_PERF)) { \
523 __anv_perf_warn(instance, obj, REPORT_OBJECT_TYPE(obj), __FILE__, __LINE__,\
524 format, ##__VA_ARGS__); \
529 /* A non-fatal assert. Useful for debugging. */
531 #define anv_assert(x) ({ \
532 if (unlikely(!(x))) \
533 intel_loge("%s:%d ASSERT: %s", __FILE__, __LINE__, #x); \
536 #define anv_assert(x)
539 /* A multi-pointer allocator
541 * When copying data structures from the user (such as a render pass), it's
542 * common to need to allocate data for a bunch of different things. Instead
543 * of doing several allocations and having to handle all of the error checking
544 * that entails, it can be easier to do a single allocation. This struct
545 * helps facilitate that. The intended usage looks like this:
548 * anv_multialloc_add(&ma, &main_ptr, 1);
549 * anv_multialloc_add(&ma, &substruct1, substruct1Count);
550 * anv_multialloc_add(&ma, &substruct2, substruct2Count);
552 * if (!anv_multialloc_alloc(&ma, pAllocator, VK_ALLOCATION_SCOPE_FOO))
553 * return vk_error(VK_ERROR_OUT_OF_HOST_MEORY);
555 struct anv_multialloc
{
563 #define ANV_MULTIALLOC_INIT \
564 ((struct anv_multialloc) { 0, })
566 #define ANV_MULTIALLOC(_name) \
567 struct anv_multialloc _name = ANV_MULTIALLOC_INIT
569 __attribute__((always_inline
))
571 _anv_multialloc_add(struct anv_multialloc
*ma
,
572 void **ptr
, size_t size
, size_t align
)
574 size_t offset
= align_u64(ma
->size
, align
);
575 ma
->size
= offset
+ size
;
576 ma
->align
= MAX2(ma
->align
, align
);
578 /* Store the offset in the pointer. */
579 *ptr
= (void *)(uintptr_t)offset
;
581 assert(ma
->ptr_count
< ARRAY_SIZE(ma
->ptrs
));
582 ma
->ptrs
[ma
->ptr_count
++] = ptr
;
585 #define anv_multialloc_add_size(_ma, _ptr, _size) \
586 _anv_multialloc_add((_ma), (void **)(_ptr), (_size), __alignof__(**(_ptr)))
588 #define anv_multialloc_add(_ma, _ptr, _count) \
589 anv_multialloc_add_size(_ma, _ptr, (_count) * sizeof(**(_ptr)));
591 __attribute__((always_inline
))
593 anv_multialloc_alloc(struct anv_multialloc
*ma
,
594 const VkAllocationCallbacks
*alloc
,
595 VkSystemAllocationScope scope
)
597 void *ptr
= vk_alloc(alloc
, ma
->size
, ma
->align
, scope
);
601 /* Fill out each of the pointers with their final value.
603 * for (uint32_t i = 0; i < ma->ptr_count; i++)
604 * *ma->ptrs[i] = ptr + (uintptr_t)*ma->ptrs[i];
606 * Unfortunately, even though ma->ptr_count is basically guaranteed to be a
607 * constant, GCC is incapable of figuring this out and unrolling the loop
608 * so we have to give it a little help.
610 STATIC_ASSERT(ARRAY_SIZE(ma
->ptrs
) == 8);
611 #define _ANV_MULTIALLOC_UPDATE_POINTER(_i) \
612 if ((_i) < ma->ptr_count) \
613 *ma->ptrs[_i] = ptr + (uintptr_t)*ma->ptrs[_i]
614 _ANV_MULTIALLOC_UPDATE_POINTER(0);
615 _ANV_MULTIALLOC_UPDATE_POINTER(1);
616 _ANV_MULTIALLOC_UPDATE_POINTER(2);
617 _ANV_MULTIALLOC_UPDATE_POINTER(3);
618 _ANV_MULTIALLOC_UPDATE_POINTER(4);
619 _ANV_MULTIALLOC_UPDATE_POINTER(5);
620 _ANV_MULTIALLOC_UPDATE_POINTER(6);
621 _ANV_MULTIALLOC_UPDATE_POINTER(7);
622 #undef _ANV_MULTIALLOC_UPDATE_POINTER
627 __attribute__((always_inline
))
629 anv_multialloc_alloc2(struct anv_multialloc
*ma
,
630 const VkAllocationCallbacks
*parent_alloc
,
631 const VkAllocationCallbacks
*alloc
,
632 VkSystemAllocationScope scope
)
634 return anv_multialloc_alloc(ma
, alloc
? alloc
: parent_alloc
, scope
);
642 /* Index into the current validation list. This is used by the
643 * validation list building alrogithm to track which buffers are already
644 * in the validation list so that we can ensure uniqueness.
648 /* Index for use with util_sparse_array_free_list */
651 /* Last known offset. This value is provided by the kernel when we
652 * execbuf and is used as the presumed offset for the next bunch of
657 /** Size of the buffer not including implicit aux */
660 /* Map for internally mapped BOs.
662 * If ANV_BO_WRAPPER is set in flags, map points to the wrapped BO.
666 /** Size of the implicit CCS range at the end of the buffer
668 * On Gen12, CCS data is always a direct 1/256 scale-down. A single 64K
669 * page of main surface data maps to a 256B chunk of CCS data and that
670 * mapping is provided on TGL-LP by the AUX table which maps virtual memory
671 * addresses in the main surface to virtual memory addresses for CCS data.
673 * Because we can't change these maps around easily and because Vulkan
674 * allows two VkImages to be bound to overlapping memory regions (as long
675 * as the app is careful), it's not feasible to make this mapping part of
676 * the image. (On Gen11 and earlier, the mapping was provided via
677 * RENDER_SURFACE_STATE so each image had its own main -> CCS mapping.)
678 * Instead, we attach the CCS data directly to the buffer object and setup
679 * the AUX table mapping at BO creation time.
681 * This field is for internal tracking use by the BO allocator only and
682 * should not be touched by other parts of the code. If something wants to
683 * know if a BO has implicit CCS data, it should instead look at the
684 * has_implicit_ccs boolean below.
686 * This data is not included in maps of this buffer.
690 /** Flags to pass to the kernel through drm_i915_exec_object2::flags */
693 /** True if this BO may be shared with other processes */
696 /** True if this BO is a wrapper
698 * When set to true, none of the fields in this BO are meaningful except
699 * for anv_bo::is_wrapper and anv_bo::map which points to the actual BO.
700 * See also anv_bo_unwrap(). Wrapper BOs are not allowed when use_softpin
701 * is set in the physical device.
705 /** See also ANV_BO_ALLOC_FIXED_ADDRESS */
706 bool has_fixed_address
:1;
708 /** True if this BO wraps a host pointer */
709 bool from_host_ptr
:1;
711 /** See also ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS */
712 bool has_client_visible_address
:1;
714 /** True if this BO has implicit CCS data attached to it */
715 bool has_implicit_ccs
:1;
718 static inline struct anv_bo
*
719 anv_bo_ref(struct anv_bo
*bo
)
721 p_atomic_inc(&bo
->refcount
);
725 static inline struct anv_bo
*
726 anv_bo_unwrap(struct anv_bo
*bo
)
728 while (bo
->is_wrapper
)
733 /* Represents a lock-free linked list of "free" things. This is used by
734 * both the block pool and the state pools. Unfortunately, in order to
735 * solve the ABA problem, we can't use a single uint32_t head.
737 union anv_free_list
{
741 /* A simple count that is incremented every time the head changes. */
744 /* Make sure it's aligned to 64 bits. This will make atomic operations
745 * faster on 32 bit platforms.
747 uint64_t u64
__attribute__ ((aligned (8)));
750 #define ANV_FREE_LIST_EMPTY ((union anv_free_list) { { UINT32_MAX, 0 } })
752 struct anv_block_state
{
758 /* Make sure it's aligned to 64 bits. This will make atomic operations
759 * faster on 32 bit platforms.
761 uint64_t u64
__attribute__ ((aligned (8)));
765 #define anv_block_pool_foreach_bo(bo, pool) \
766 for (struct anv_bo **_pp_bo = (pool)->bos, *bo; \
767 _pp_bo != &(pool)->bos[(pool)->nbos] && (bo = *_pp_bo, true); \
770 #define ANV_MAX_BLOCK_POOL_BOS 20
772 struct anv_block_pool
{
773 struct anv_device
*device
;
776 /* Wrapper BO for use in relocation lists. This BO is simply a wrapper
777 * around the actual BO so that we grow the pool after the wrapper BO has
778 * been put in a relocation list. This is only used in the non-softpin
781 struct anv_bo wrapper_bo
;
783 struct anv_bo
*bos
[ANV_MAX_BLOCK_POOL_BOS
];
789 /* The address where the start of the pool is pinned. The various bos that
790 * are created as the pool grows will have addresses in the range
791 * [start_address, start_address + BLOCK_POOL_MEMFD_SIZE).
793 uint64_t start_address
;
795 /* The offset from the start of the bo to the "center" of the block
796 * pool. Pointers to allocated blocks are given by
797 * bo.map + center_bo_offset + offsets.
799 uint32_t center_bo_offset
;
801 /* Current memory map of the block pool. This pointer may or may not
802 * point to the actual beginning of the block pool memory. If
803 * anv_block_pool_alloc_back has ever been called, then this pointer
804 * will point to the "center" position of the buffer and all offsets
805 * (negative or positive) given out by the block pool alloc functions
806 * will be valid relative to this pointer.
808 * In particular, map == bo.map + center_offset
810 * DO NOT access this pointer directly. Use anv_block_pool_map() instead,
811 * since it will handle the softpin case as well, where this points to NULL.
817 * Array of mmaps and gem handles owned by the block pool, reclaimed when
818 * the block pool is destroyed.
820 struct u_vector mmap_cleanups
;
822 struct anv_block_state state
;
824 struct anv_block_state back_state
;
827 /* Block pools are backed by a fixed-size 1GB memfd */
828 #define BLOCK_POOL_MEMFD_SIZE (1ul << 30)
830 /* The center of the block pool is also the middle of the memfd. This may
831 * change in the future if we decide differently for some reason.
833 #define BLOCK_POOL_MEMFD_CENTER (BLOCK_POOL_MEMFD_SIZE / 2)
835 static inline uint32_t
836 anv_block_pool_size(struct anv_block_pool
*pool
)
838 return pool
->state
.end
+ pool
->back_state
.end
;
848 #define ANV_STATE_NULL ((struct anv_state) { .alloc_size = 0 })
850 struct anv_fixed_size_state_pool
{
851 union anv_free_list free_list
;
852 struct anv_block_state block
;
855 #define ANV_MIN_STATE_SIZE_LOG2 6
856 #define ANV_MAX_STATE_SIZE_LOG2 21
858 #define ANV_STATE_BUCKETS (ANV_MAX_STATE_SIZE_LOG2 - ANV_MIN_STATE_SIZE_LOG2 + 1)
860 struct anv_free_entry
{
862 struct anv_state state
;
865 struct anv_state_table
{
866 struct anv_device
*device
;
868 struct anv_free_entry
*map
;
870 struct anv_block_state state
;
871 struct u_vector cleanups
;
874 struct anv_state_pool
{
875 struct anv_block_pool block_pool
;
877 struct anv_state_table table
;
879 /* The size of blocks which will be allocated from the block pool */
882 /** Free list for "back" allocations */
883 union anv_free_list back_alloc_free_list
;
885 struct anv_fixed_size_state_pool buckets
[ANV_STATE_BUCKETS
];
888 struct anv_state_stream_block
;
890 struct anv_state_stream
{
891 struct anv_state_pool
*state_pool
;
893 /* The size of blocks to allocate from the state pool */
896 /* Current block we're allocating from */
897 struct anv_state block
;
899 /* Offset into the current block at which to allocate the next state */
902 /* List of all blocks allocated from this pool */
903 struct anv_state_stream_block
*block_list
;
906 /* The block_pool functions exported for testing only. The block pool should
907 * only be used via a state pool (see below).
909 VkResult
anv_block_pool_init(struct anv_block_pool
*pool
,
910 struct anv_device
*device
,
911 uint64_t start_address
,
912 uint32_t initial_size
);
913 void anv_block_pool_finish(struct anv_block_pool
*pool
);
914 int32_t anv_block_pool_alloc(struct anv_block_pool
*pool
,
915 uint32_t block_size
, uint32_t *padding
);
916 int32_t anv_block_pool_alloc_back(struct anv_block_pool
*pool
,
917 uint32_t block_size
);
918 void* anv_block_pool_map(struct anv_block_pool
*pool
, int32_t offset
, uint32_t
921 VkResult
anv_state_pool_init(struct anv_state_pool
*pool
,
922 struct anv_device
*device
,
923 uint64_t start_address
,
924 uint32_t block_size
);
925 void anv_state_pool_finish(struct anv_state_pool
*pool
);
926 struct anv_state
anv_state_pool_alloc(struct anv_state_pool
*pool
,
927 uint32_t state_size
, uint32_t alignment
);
928 struct anv_state
anv_state_pool_alloc_back(struct anv_state_pool
*pool
);
929 void anv_state_pool_free(struct anv_state_pool
*pool
, struct anv_state state
);
930 void anv_state_stream_init(struct anv_state_stream
*stream
,
931 struct anv_state_pool
*state_pool
,
932 uint32_t block_size
);
933 void anv_state_stream_finish(struct anv_state_stream
*stream
);
934 struct anv_state
anv_state_stream_alloc(struct anv_state_stream
*stream
,
935 uint32_t size
, uint32_t alignment
);
937 VkResult
anv_state_table_init(struct anv_state_table
*table
,
938 struct anv_device
*device
,
939 uint32_t initial_entries
);
940 void anv_state_table_finish(struct anv_state_table
*table
);
941 VkResult
anv_state_table_add(struct anv_state_table
*table
, uint32_t *idx
,
943 void anv_free_list_push(union anv_free_list
*list
,
944 struct anv_state_table
*table
,
945 uint32_t idx
, uint32_t count
);
946 struct anv_state
* anv_free_list_pop(union anv_free_list
*list
,
947 struct anv_state_table
*table
);
950 static inline struct anv_state
*
951 anv_state_table_get(struct anv_state_table
*table
, uint32_t idx
)
953 return &table
->map
[idx
].state
;
956 * Implements a pool of re-usable BOs. The interface is identical to that
957 * of block_pool except that each block is its own BO.
960 struct anv_device
*device
;
962 struct util_sparse_array_free_list free_list
[16];
965 void anv_bo_pool_init(struct anv_bo_pool
*pool
, struct anv_device
*device
);
966 void anv_bo_pool_finish(struct anv_bo_pool
*pool
);
967 VkResult
anv_bo_pool_alloc(struct anv_bo_pool
*pool
, uint32_t size
,
968 struct anv_bo
**bo_out
);
969 void anv_bo_pool_free(struct anv_bo_pool
*pool
, struct anv_bo
*bo
);
971 struct anv_scratch_pool
{
972 /* Indexed by Per-Thread Scratch Space number (the hardware value) and stage */
973 struct anv_bo
*bos
[16][MESA_SHADER_STAGES
];
976 void anv_scratch_pool_init(struct anv_device
*device
,
977 struct anv_scratch_pool
*pool
);
978 void anv_scratch_pool_finish(struct anv_device
*device
,
979 struct anv_scratch_pool
*pool
);
980 struct anv_bo
*anv_scratch_pool_alloc(struct anv_device
*device
,
981 struct anv_scratch_pool
*pool
,
982 gl_shader_stage stage
,
983 unsigned per_thread_scratch
);
985 /** Implements a BO cache that ensures a 1-1 mapping of GEM BOs to anv_bos */
986 struct anv_bo_cache
{
987 struct util_sparse_array bo_map
;
988 pthread_mutex_t mutex
;
991 VkResult
anv_bo_cache_init(struct anv_bo_cache
*cache
);
992 void anv_bo_cache_finish(struct anv_bo_cache
*cache
);
994 struct anv_memory_type
{
995 /* Standard bits passed on to the client */
996 VkMemoryPropertyFlags propertyFlags
;
1000 struct anv_memory_heap
{
1001 /* Standard bits passed on to the client */
1003 VkMemoryHeapFlags flags
;
1005 /* Driver-internal book-keeping */
1009 struct anv_physical_device
{
1010 VK_LOADER_DATA _loader_data
;
1012 /* Link in anv_instance::physical_devices */
1013 struct list_head link
;
1015 struct anv_instance
* instance
;
1025 struct gen_device_info info
;
1026 /** Amount of "GPU memory" we want to advertise
1028 * Clearly, this value is bogus since Intel is a UMA architecture. On
1029 * gen7 platforms, we are limited by GTT size unless we want to implement
1030 * fine-grained tracking and GTT splitting. On Broadwell and above we are
1031 * practically unlimited. However, we will never report more than 3/4 of
1032 * the total system ram to try and avoid running out of RAM.
1034 bool supports_48bit_addresses
;
1035 struct brw_compiler
* compiler
;
1036 struct isl_device isl_dev
;
1037 struct gen_perf_config
* perf
;
1038 int cmd_parser_version
;
1040 bool has_exec_async
;
1041 bool has_exec_capture
;
1042 bool has_exec_fence
;
1044 bool has_syncobj_wait
;
1045 bool has_context_priority
;
1046 bool has_context_isolation
;
1047 bool has_mem_available
;
1051 bool always_use_bindless
;
1053 /** True if we can access buffers using A64 messages */
1054 bool has_a64_buffer_access
;
1055 /** True if we can use bindless access for images */
1056 bool has_bindless_images
;
1057 /** True if we can use bindless access for samplers */
1058 bool has_bindless_samplers
;
1060 /** True if this device has implicit AUX
1062 * If true, CCS is handled as an implicit attachment to the BO rather than
1063 * as an explicitly bound surface.
1065 bool has_implicit_ccs
;
1067 bool always_flush_cache
;
1069 struct anv_device_extension_table supported_extensions
;
1072 uint32_t subslice_total
;
1075 uint32_t type_count
;
1076 struct anv_memory_type types
[VK_MAX_MEMORY_TYPES
];
1077 uint32_t heap_count
;
1078 struct anv_memory_heap heaps
[VK_MAX_MEMORY_HEAPS
];
1081 uint8_t driver_build_sha1
[20];
1082 uint8_t pipeline_cache_uuid
[VK_UUID_SIZE
];
1083 uint8_t driver_uuid
[VK_UUID_SIZE
];
1084 uint8_t device_uuid
[VK_UUID_SIZE
];
1086 struct disk_cache
* disk_cache
;
1088 struct wsi_device wsi_device
;
1093 struct anv_app_info
{
1094 const char* app_name
;
1095 uint32_t app_version
;
1096 const char* engine_name
;
1097 uint32_t engine_version
;
1098 uint32_t api_version
;
1101 struct anv_instance
{
1102 VK_LOADER_DATA _loader_data
;
1104 VkAllocationCallbacks alloc
;
1106 struct anv_app_info app_info
;
1108 struct anv_instance_extension_table enabled_extensions
;
1109 struct anv_instance_dispatch_table dispatch
;
1110 struct anv_physical_device_dispatch_table physical_device_dispatch
;
1111 struct anv_device_dispatch_table device_dispatch
;
1113 bool physical_devices_enumerated
;
1114 struct list_head physical_devices
;
1116 bool pipeline_cache_enabled
;
1118 struct vk_debug_report_instance debug_report_callbacks
;
1120 struct driOptionCache dri_options
;
1121 struct driOptionCache available_dri_options
;
1124 VkResult
anv_init_wsi(struct anv_physical_device
*physical_device
);
1125 void anv_finish_wsi(struct anv_physical_device
*physical_device
);
1127 uint32_t anv_physical_device_api_version(struct anv_physical_device
*dev
);
1128 bool anv_physical_device_extension_supported(struct anv_physical_device
*dev
,
1131 struct anv_queue_submit
{
1132 struct anv_cmd_buffer
* cmd_buffer
;
1134 uint32_t fence_count
;
1135 uint32_t fence_array_length
;
1136 struct drm_i915_gem_exec_fence
* fences
;
1138 uint32_t temporary_semaphore_count
;
1139 uint32_t temporary_semaphore_array_length
;
1140 struct anv_semaphore_impl
* temporary_semaphores
;
1142 /* Semaphores to be signaled with a SYNC_FD. */
1143 struct anv_semaphore
** sync_fd_semaphores
;
1144 uint32_t sync_fd_semaphore_count
;
1145 uint32_t sync_fd_semaphore_array_length
;
1147 /* Allocated only with non shareable timelines. */
1148 struct anv_timeline
** wait_timelines
;
1149 uint32_t wait_timeline_count
;
1150 uint32_t wait_timeline_array_length
;
1151 uint64_t * wait_timeline_values
;
1153 struct anv_timeline
** signal_timelines
;
1154 uint32_t signal_timeline_count
;
1155 uint32_t signal_timeline_array_length
;
1156 uint64_t * signal_timeline_values
;
1159 bool need_out_fence
;
1162 uint32_t fence_bo_count
;
1163 uint32_t fence_bo_array_length
;
1164 /* An array of struct anv_bo pointers with lower bit used as a flag to
1165 * signal we will wait on that BO (see anv_(un)pack_ptr).
1167 uintptr_t * fence_bos
;
1169 const VkAllocationCallbacks
* alloc
;
1170 VkSystemAllocationScope alloc_scope
;
1172 struct anv_bo
* simple_bo
;
1173 uint32_t simple_bo_size
;
1175 struct list_head link
;
1179 VK_LOADER_DATA _loader_data
;
1181 struct anv_device
* device
;
1184 * A list of struct anv_queue_submit to be submitted to i915.
1186 struct list_head queued_submits
;
1188 VkDeviceQueueCreateFlags flags
;
1191 struct anv_pipeline_cache
{
1192 struct anv_device
* device
;
1193 pthread_mutex_t mutex
;
1195 struct hash_table
* nir_cache
;
1197 struct hash_table
* cache
;
1200 struct nir_xfb_info
;
1201 struct anv_pipeline_bind_map
;
1203 void anv_pipeline_cache_init(struct anv_pipeline_cache
*cache
,
1204 struct anv_device
*device
,
1205 bool cache_enabled
);
1206 void anv_pipeline_cache_finish(struct anv_pipeline_cache
*cache
);
1208 struct anv_shader_bin
*
1209 anv_pipeline_cache_search(struct anv_pipeline_cache
*cache
,
1210 const void *key
, uint32_t key_size
);
1211 struct anv_shader_bin
*
1212 anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache
*cache
,
1213 const void *key_data
, uint32_t key_size
,
1214 const void *kernel_data
, uint32_t kernel_size
,
1215 const void *constant_data
,
1216 uint32_t constant_data_size
,
1217 const struct brw_stage_prog_data
*prog_data
,
1218 uint32_t prog_data_size
,
1219 const struct brw_compile_stats
*stats
,
1221 const struct nir_xfb_info
*xfb_info
,
1222 const struct anv_pipeline_bind_map
*bind_map
);
1224 struct anv_shader_bin
*
1225 anv_device_search_for_kernel(struct anv_device
*device
,
1226 struct anv_pipeline_cache
*cache
,
1227 const void *key_data
, uint32_t key_size
,
1228 bool *user_cache_bit
);
1230 struct anv_shader_bin
*
1231 anv_device_upload_kernel(struct anv_device
*device
,
1232 struct anv_pipeline_cache
*cache
,
1233 const void *key_data
, uint32_t key_size
,
1234 const void *kernel_data
, uint32_t kernel_size
,
1235 const void *constant_data
,
1236 uint32_t constant_data_size
,
1237 const struct brw_stage_prog_data
*prog_data
,
1238 uint32_t prog_data_size
,
1239 const struct brw_compile_stats
*stats
,
1241 const struct nir_xfb_info
*xfb_info
,
1242 const struct anv_pipeline_bind_map
*bind_map
);
1245 struct nir_shader_compiler_options
;
1248 anv_device_search_for_nir(struct anv_device
*device
,
1249 struct anv_pipeline_cache
*cache
,
1250 const struct nir_shader_compiler_options
*nir_options
,
1251 unsigned char sha1_key
[20],
1255 anv_device_upload_nir(struct anv_device
*device
,
1256 struct anv_pipeline_cache
*cache
,
1257 const struct nir_shader
*nir
,
1258 unsigned char sha1_key
[20]);
1261 VK_LOADER_DATA _loader_data
;
1263 VkAllocationCallbacks alloc
;
1265 struct anv_physical_device
* physical
;
1267 struct gen_device_info info
;
1268 struct isl_device isl_dev
;
1271 bool can_chain_batches
;
1272 bool robust_buffer_access
;
1273 struct anv_device_extension_table enabled_extensions
;
1274 struct anv_device_dispatch_table dispatch
;
1276 pthread_mutex_t vma_mutex
;
1277 struct util_vma_heap vma_lo
;
1278 struct util_vma_heap vma_cva
;
1279 struct util_vma_heap vma_hi
;
1281 /** List of all anv_device_memory objects */
1282 struct list_head memory_objects
;
1284 struct anv_bo_pool batch_bo_pool
;
1286 struct anv_bo_cache bo_cache
;
1288 struct anv_state_pool dynamic_state_pool
;
1289 struct anv_state_pool instruction_state_pool
;
1290 struct anv_state_pool binding_table_pool
;
1291 struct anv_state_pool surface_state_pool
;
1293 struct anv_bo
* workaround_bo
;
1294 struct anv_bo
* trivial_batch_bo
;
1295 struct anv_bo
* hiz_clear_bo
;
1297 struct anv_pipeline_cache default_pipeline_cache
;
1298 struct blorp_context blorp
;
1300 struct anv_state border_colors
;
1302 struct anv_state slice_hash
;
1304 struct anv_queue queue
;
1306 struct anv_scratch_pool scratch_pool
;
1308 pthread_mutex_t mutex
;
1309 pthread_cond_t queue_submit
;
1312 struct gen_batch_decode_ctx decoder_ctx
;
1314 * When decoding a anv_cmd_buffer, we might need to search for BOs through
1315 * the cmd_buffer's list.
1317 struct anv_cmd_buffer
*cmd_buffer_being_decoded
;
1319 int perf_fd
; /* -1 if no opened */
1320 uint64_t perf_metric
; /* 0 if unset */
1322 struct gen_aux_map_context
*aux_map_ctx
;
1325 static inline struct anv_instance
*
1326 anv_device_instance_or_null(const struct anv_device
*device
)
1328 return device
? device
->physical
->instance
: NULL
;
1331 static inline struct anv_state_pool
*
1332 anv_binding_table_pool(struct anv_device
*device
)
1334 if (device
->physical
->use_softpin
)
1335 return &device
->binding_table_pool
;
1337 return &device
->surface_state_pool
;
1340 static inline struct anv_state
1341 anv_binding_table_pool_alloc(struct anv_device
*device
) {
1342 if (device
->physical
->use_softpin
)
1343 return anv_state_pool_alloc(&device
->binding_table_pool
,
1344 device
->binding_table_pool
.block_size
, 0);
1346 return anv_state_pool_alloc_back(&device
->surface_state_pool
);
1350 anv_binding_table_pool_free(struct anv_device
*device
, struct anv_state state
) {
1351 anv_state_pool_free(anv_binding_table_pool(device
), state
);
1354 static inline uint32_t
1355 anv_mocs_for_bo(const struct anv_device
*device
, const struct anv_bo
*bo
)
1357 if (bo
->is_external
)
1358 return device
->isl_dev
.mocs
.external
;
1360 return device
->isl_dev
.mocs
.internal
;
1363 void anv_device_init_blorp(struct anv_device
*device
);
1364 void anv_device_finish_blorp(struct anv_device
*device
);
1366 void _anv_device_set_all_queue_lost(struct anv_device
*device
);
1367 VkResult
_anv_device_set_lost(struct anv_device
*device
,
1368 const char *file
, int line
,
1369 const char *msg
, ...)
1370 anv_printflike(4, 5);
1371 VkResult
_anv_queue_set_lost(struct anv_queue
*queue
,
1372 const char *file
, int line
,
1373 const char *msg
, ...)
1374 anv_printflike(4, 5);
1375 #define anv_device_set_lost(dev, ...) \
1376 _anv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
1377 #define anv_queue_set_lost(queue, ...) \
1378 _anv_queue_set_lost(queue, __FILE__, __LINE__, __VA_ARGS__)
1381 anv_device_is_lost(struct anv_device
*device
)
1383 return unlikely(p_atomic_read(&device
->_lost
));
1386 VkResult
anv_device_query_status(struct anv_device
*device
);
1389 enum anv_bo_alloc_flags
{
1390 /** Specifies that the BO must have a 32-bit address
1392 * This is the opposite of EXEC_OBJECT_SUPPORTS_48B_ADDRESS.
1394 ANV_BO_ALLOC_32BIT_ADDRESS
= (1 << 0),
1396 /** Specifies that the BO may be shared externally */
1397 ANV_BO_ALLOC_EXTERNAL
= (1 << 1),
1399 /** Specifies that the BO should be mapped */
1400 ANV_BO_ALLOC_MAPPED
= (1 << 2),
1402 /** Specifies that the BO should be snooped so we get coherency */
1403 ANV_BO_ALLOC_SNOOPED
= (1 << 3),
1405 /** Specifies that the BO should be captured in error states */
1406 ANV_BO_ALLOC_CAPTURE
= (1 << 4),
1408 /** Specifies that the BO will have an address assigned by the caller
1410 * Such BOs do not exist in any VMA heap.
1412 ANV_BO_ALLOC_FIXED_ADDRESS
= (1 << 5),
1414 /** Enables implicit synchronization on the BO
1416 * This is the opposite of EXEC_OBJECT_ASYNC.
1418 ANV_BO_ALLOC_IMPLICIT_SYNC
= (1 << 6),
1420 /** Enables implicit synchronization on the BO
1422 * This is equivalent to EXEC_OBJECT_WRITE.
1424 ANV_BO_ALLOC_IMPLICIT_WRITE
= (1 << 7),
1426 /** Has an address which is visible to the client */
1427 ANV_BO_ALLOC_CLIENT_VISIBLE_ADDRESS
= (1 << 8),
1429 /** This buffer has implicit CCS data attached to it */
1430 ANV_BO_ALLOC_IMPLICIT_CCS
= (1 << 9),
1433 VkResult
anv_device_alloc_bo(struct anv_device
*device
, uint64_t size
,
1434 enum anv_bo_alloc_flags alloc_flags
,
1435 uint64_t explicit_address
,
1436 struct anv_bo
**bo
);
1437 VkResult
anv_device_import_bo_from_host_ptr(struct anv_device
*device
,
1438 void *host_ptr
, uint32_t size
,
1439 enum anv_bo_alloc_flags alloc_flags
,
1440 uint64_t client_address
,
1441 struct anv_bo
**bo_out
);
1442 VkResult
anv_device_import_bo(struct anv_device
*device
, int fd
,
1443 enum anv_bo_alloc_flags alloc_flags
,
1444 uint64_t client_address
,
1445 struct anv_bo
**bo
);
1446 VkResult
anv_device_export_bo(struct anv_device
*device
,
1447 struct anv_bo
*bo
, int *fd_out
);
1448 void anv_device_release_bo(struct anv_device
*device
,
1451 static inline struct anv_bo
*
1452 anv_device_lookup_bo(struct anv_device
*device
, uint32_t gem_handle
)
1454 return util_sparse_array_get(&device
->bo_cache
.bo_map
, gem_handle
);
1457 VkResult
anv_device_bo_busy(struct anv_device
*device
, struct anv_bo
*bo
);
1458 VkResult
anv_device_wait(struct anv_device
*device
, struct anv_bo
*bo
,
1461 VkResult
anv_queue_init(struct anv_device
*device
, struct anv_queue
*queue
);
1462 void anv_queue_finish(struct anv_queue
*queue
);
1464 VkResult
anv_queue_execbuf_locked(struct anv_queue
*queue
, struct anv_queue_submit
*submit
);
1465 VkResult
anv_queue_submit_simple_batch(struct anv_queue
*queue
,
1466 struct anv_batch
*batch
);
1468 uint64_t anv_gettime_ns(void);
1469 uint64_t anv_get_absolute_timeout(uint64_t timeout
);
1471 void* anv_gem_mmap(struct anv_device
*device
,
1472 uint32_t gem_handle
, uint64_t offset
, uint64_t size
, uint32_t flags
);
1473 void anv_gem_munmap(void *p
, uint64_t size
);
1474 uint32_t anv_gem_create(struct anv_device
*device
, uint64_t size
);
1475 void anv_gem_close(struct anv_device
*device
, uint32_t gem_handle
);
1476 uint32_t anv_gem_userptr(struct anv_device
*device
, void *mem
, size_t size
);
1477 int anv_gem_busy(struct anv_device
*device
, uint32_t gem_handle
);
1478 int anv_gem_wait(struct anv_device
*device
, uint32_t gem_handle
, int64_t *timeout_ns
);
1479 int anv_gem_execbuffer(struct anv_device
*device
,
1480 struct drm_i915_gem_execbuffer2
*execbuf
);
1481 int anv_gem_set_tiling(struct anv_device
*device
, uint32_t gem_handle
,
1482 uint32_t stride
, uint32_t tiling
);
1483 int anv_gem_create_context(struct anv_device
*device
);
1484 bool anv_gem_has_context_priority(int fd
);
1485 int anv_gem_destroy_context(struct anv_device
*device
, int context
);
1486 int anv_gem_set_context_param(int fd
, int context
, uint32_t param
,
1488 int anv_gem_get_context_param(int fd
, int context
, uint32_t param
,
1490 int anv_gem_get_param(int fd
, uint32_t param
);
1491 int anv_gem_get_tiling(struct anv_device
*device
, uint32_t gem_handle
);
1492 bool anv_gem_get_bit6_swizzle(int fd
, uint32_t tiling
);
1493 int anv_gem_get_aperture(int fd
, uint64_t *size
);
1494 int anv_gem_gpu_get_reset_stats(struct anv_device
*device
,
1495 uint32_t *active
, uint32_t *pending
);
1496 int anv_gem_handle_to_fd(struct anv_device
*device
, uint32_t gem_handle
);
1497 int anv_gem_reg_read(struct anv_device
*device
,
1498 uint32_t offset
, uint64_t *result
);
1499 uint32_t anv_gem_fd_to_handle(struct anv_device
*device
, int fd
);
1500 int anv_gem_set_caching(struct anv_device
*device
, uint32_t gem_handle
, uint32_t caching
);
1501 int anv_gem_set_domain(struct anv_device
*device
, uint32_t gem_handle
,
1502 uint32_t read_domains
, uint32_t write_domain
);
1503 int anv_gem_sync_file_merge(struct anv_device
*device
, int fd1
, int fd2
);
1504 uint32_t anv_gem_syncobj_create(struct anv_device
*device
, uint32_t flags
);
1505 void anv_gem_syncobj_destroy(struct anv_device
*device
, uint32_t handle
);
1506 int anv_gem_syncobj_handle_to_fd(struct anv_device
*device
, uint32_t handle
);
1507 uint32_t anv_gem_syncobj_fd_to_handle(struct anv_device
*device
, int fd
);
1508 int anv_gem_syncobj_export_sync_file(struct anv_device
*device
,
1510 int anv_gem_syncobj_import_sync_file(struct anv_device
*device
,
1511 uint32_t handle
, int fd
);
1512 void anv_gem_syncobj_reset(struct anv_device
*device
, uint32_t handle
);
1513 bool anv_gem_supports_syncobj_wait(int fd
);
1514 int anv_gem_syncobj_wait(struct anv_device
*device
,
1515 uint32_t *handles
, uint32_t num_handles
,
1516 int64_t abs_timeout_ns
, bool wait_all
);
1518 uint64_t anv_vma_alloc(struct anv_device
*device
,
1519 uint64_t size
, uint64_t align
,
1520 enum anv_bo_alloc_flags alloc_flags
,
1521 uint64_t client_address
);
1522 void anv_vma_free(struct anv_device
*device
,
1523 uint64_t address
, uint64_t size
);
1525 struct anv_reloc_list
{
1526 uint32_t num_relocs
;
1527 uint32_t array_length
;
1528 struct drm_i915_gem_relocation_entry
* relocs
;
1529 struct anv_bo
** reloc_bos
;
1534 VkResult
anv_reloc_list_init(struct anv_reloc_list
*list
,
1535 const VkAllocationCallbacks
*alloc
);
1536 void anv_reloc_list_finish(struct anv_reloc_list
*list
,
1537 const VkAllocationCallbacks
*alloc
);
1539 VkResult
anv_reloc_list_add(struct anv_reloc_list
*list
,
1540 const VkAllocationCallbacks
*alloc
,
1541 uint32_t offset
, struct anv_bo
*target_bo
,
1542 uint32_t delta
, uint64_t *address_u64_out
);
1544 struct anv_batch_bo
{
1545 /* Link in the anv_cmd_buffer.owned_batch_bos list */
1546 struct list_head link
;
1550 /* Bytes actually consumed in this batch BO */
1553 struct anv_reloc_list relocs
;
1557 const VkAllocationCallbacks
* alloc
;
1563 struct anv_reloc_list
* relocs
;
1565 /* This callback is called (with the associated user data) in the event
1566 * that the batch runs out of space.
1568 VkResult (*extend_cb
)(struct anv_batch
*, void *);
1572 * Current error status of the command buffer. Used to track inconsistent
1573 * or incomplete command buffer states that are the consequence of run-time
1574 * errors such as out of memory scenarios. We want to track this in the
1575 * batch because the command buffer object is not visible to some parts
1581 void *anv_batch_emit_dwords(struct anv_batch
*batch
, int num_dwords
);
1582 void anv_batch_emit_batch(struct anv_batch
*batch
, struct anv_batch
*other
);
1583 uint64_t anv_batch_emit_reloc(struct anv_batch
*batch
,
1584 void *location
, struct anv_bo
*bo
, uint32_t offset
);
1586 static inline VkResult
1587 anv_batch_set_error(struct anv_batch
*batch
, VkResult error
)
1589 assert(error
!= VK_SUCCESS
);
1590 if (batch
->status
== VK_SUCCESS
)
1591 batch
->status
= error
;
1592 return batch
->status
;
1596 anv_batch_has_error(struct anv_batch
*batch
)
1598 return batch
->status
!= VK_SUCCESS
;
1601 struct anv_address
{
1606 #define ANV_NULL_ADDRESS ((struct anv_address) { NULL, 0 })
1609 anv_address_is_null(struct anv_address addr
)
1611 return addr
.bo
== NULL
&& addr
.offset
== 0;
1614 static inline uint64_t
1615 anv_address_physical(struct anv_address addr
)
1617 if (addr
.bo
&& (addr
.bo
->flags
& EXEC_OBJECT_PINNED
))
1618 return gen_canonical_address(addr
.bo
->offset
+ addr
.offset
);
1620 return gen_canonical_address(addr
.offset
);
1623 static inline struct anv_address
1624 anv_address_add(struct anv_address addr
, uint64_t offset
)
1626 addr
.offset
+= offset
;
1631 write_reloc(const struct anv_device
*device
, void *p
, uint64_t v
, bool flush
)
1633 unsigned reloc_size
= 0;
1634 if (device
->info
.gen
>= 8) {
1635 reloc_size
= sizeof(uint64_t);
1636 *(uint64_t *)p
= gen_canonical_address(v
);
1638 reloc_size
= sizeof(uint32_t);
1642 if (flush
&& !device
->info
.has_llc
)
1643 gen_flush_range(p
, reloc_size
);
1646 static inline uint64_t
1647 _anv_combine_address(struct anv_batch
*batch
, void *location
,
1648 const struct anv_address address
, uint32_t delta
)
1650 if (address
.bo
== NULL
) {
1651 return address
.offset
+ delta
;
1653 assert(batch
->start
<= location
&& location
< batch
->end
);
1655 return anv_batch_emit_reloc(batch
, location
, address
.bo
, address
.offset
+ delta
);
1659 #define __gen_address_type struct anv_address
1660 #define __gen_user_data struct anv_batch
1661 #define __gen_combine_address _anv_combine_address
1663 /* Wrapper macros needed to work around preprocessor argument issues. In
1664 * particular, arguments don't get pre-evaluated if they are concatenated.
1665 * This means that, if you pass GENX(3DSTATE_PS) into the emit macro, the
1666 * GENX macro won't get evaluated if the emit macro contains "cmd ## foo".
1667 * We can work around this easily enough with these helpers.
1669 #define __anv_cmd_length(cmd) cmd ## _length
1670 #define __anv_cmd_length_bias(cmd) cmd ## _length_bias
1671 #define __anv_cmd_header(cmd) cmd ## _header
1672 #define __anv_cmd_pack(cmd) cmd ## _pack
1673 #define __anv_reg_num(reg) reg ## _num
1675 #define anv_pack_struct(dst, struc, ...) do { \
1676 struct struc __template = { \
1679 __anv_cmd_pack(struc)(NULL, dst, &__template); \
1680 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dst, __anv_cmd_length(struc) * 4)); \
1683 #define anv_batch_emitn(batch, n, cmd, ...) ({ \
1684 void *__dst = anv_batch_emit_dwords(batch, n); \
1686 struct cmd __template = { \
1687 __anv_cmd_header(cmd), \
1688 .DWordLength = n - __anv_cmd_length_bias(cmd), \
1691 __anv_cmd_pack(cmd)(batch, __dst, &__template); \
1696 #define anv_batch_emit_merge(batch, dwords0, dwords1) \
1700 STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
1701 dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
1704 for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
1705 dw[i] = (dwords0)[i] | (dwords1)[i]; \
1706 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, ARRAY_SIZE(dwords0) * 4));\
1709 #define anv_batch_emit(batch, cmd, name) \
1710 for (struct cmd name = { __anv_cmd_header(cmd) }, \
1711 *_dst = anv_batch_emit_dwords(batch, __anv_cmd_length(cmd)); \
1712 __builtin_expect(_dst != NULL, 1); \
1713 ({ __anv_cmd_pack(cmd)(batch, _dst, &name); \
1714 VG(VALGRIND_CHECK_MEM_IS_DEFINED(_dst, __anv_cmd_length(cmd) * 4)); \
1718 struct anv_device_memory
{
1719 struct list_head link
;
1722 struct anv_memory_type
* type
;
1723 VkDeviceSize map_size
;
1726 /* If set, we are holding reference to AHardwareBuffer
1727 * which we must release when memory is freed.
1729 struct AHardwareBuffer
* ahw
;
1731 /* If set, this memory comes from a host pointer. */
1736 * Header for Vertex URB Entry (VUE)
1738 struct anv_vue_header
{
1740 uint32_t RTAIndex
; /* RenderTargetArrayIndex */
1741 uint32_t ViewportIndex
;
1745 /** Struct representing a sampled image descriptor
1747 * This descriptor layout is used for sampled images, bare sampler, and
1748 * combined image/sampler descriptors.
1750 struct anv_sampled_image_descriptor
{
1751 /** Bindless image handle
1753 * This is expected to already be shifted such that the 20-bit
1754 * SURFACE_STATE table index is in the top 20 bits.
1758 /** Bindless sampler handle
1760 * This is assumed to be a 32B-aligned SAMPLER_STATE pointer relative
1761 * to the dynamic state base address.
1766 struct anv_texture_swizzle_descriptor
{
1769 * See also nir_intrinsic_channel_select_intel
1773 /** Unused padding to ensure the struct is a multiple of 64 bits */
1777 /** Struct representing a storage image descriptor */
1778 struct anv_storage_image_descriptor
{
1779 /** Bindless image handles
1781 * These are expected to already be shifted such that the 20-bit
1782 * SURFACE_STATE table index is in the top 20 bits.
1784 uint32_t read_write
;
1785 uint32_t write_only
;
1788 /** Struct representing a address/range descriptor
1790 * The fields of this struct correspond directly to the data layout of
1791 * nir_address_format_64bit_bounded_global addresses. The last field is the
1792 * offset in the NIR address so it must be zero so that when you load the
1793 * descriptor you get a pointer to the start of the range.
1795 struct anv_address_range_descriptor
{
1801 enum anv_descriptor_data
{
1802 /** The descriptor contains a BTI reference to a surface state */
1803 ANV_DESCRIPTOR_SURFACE_STATE
= (1 << 0),
1804 /** The descriptor contains a BTI reference to a sampler state */
1805 ANV_DESCRIPTOR_SAMPLER_STATE
= (1 << 1),
1806 /** The descriptor contains an actual buffer view */
1807 ANV_DESCRIPTOR_BUFFER_VIEW
= (1 << 2),
1808 /** The descriptor contains auxiliary image layout data */
1809 ANV_DESCRIPTOR_IMAGE_PARAM
= (1 << 3),
1810 /** The descriptor contains auxiliary image layout data */
1811 ANV_DESCRIPTOR_INLINE_UNIFORM
= (1 << 4),
1812 /** anv_address_range_descriptor with a buffer address and range */
1813 ANV_DESCRIPTOR_ADDRESS_RANGE
= (1 << 5),
1814 /** Bindless surface handle */
1815 ANV_DESCRIPTOR_SAMPLED_IMAGE
= (1 << 6),
1816 /** Storage image handles */
1817 ANV_DESCRIPTOR_STORAGE_IMAGE
= (1 << 7),
1818 /** Storage image handles */
1819 ANV_DESCRIPTOR_TEXTURE_SWIZZLE
= (1 << 8),
1822 struct anv_descriptor_set_binding_layout
{
1824 /* The type of the descriptors in this binding */
1825 VkDescriptorType type
;
1828 /* Flags provided when this binding was created */
1829 VkDescriptorBindingFlagsEXT flags
;
1831 /* Bitfield representing the type of data this descriptor contains */
1832 enum anv_descriptor_data data
;
1834 /* Maximum number of YCbCr texture/sampler planes */
1835 uint8_t max_plane_count
;
1837 /* Number of array elements in this binding (or size in bytes for inline
1840 uint16_t array_size
;
1842 /* Index into the flattend descriptor set */
1843 uint16_t descriptor_index
;
1845 /* Index into the dynamic state array for a dynamic buffer */
1846 int16_t dynamic_offset_index
;
1848 /* Index into the descriptor set buffer views */
1849 int16_t buffer_view_index
;
1851 /* Offset into the descriptor buffer where this descriptor lives */
1852 uint32_t descriptor_offset
;
1854 /* Immutable samplers (or NULL if no immutable samplers) */
1855 struct anv_sampler
**immutable_samplers
;
1858 unsigned anv_descriptor_size(const struct anv_descriptor_set_binding_layout
*layout
);
1860 unsigned anv_descriptor_type_size(const struct anv_physical_device
*pdevice
,
1861 VkDescriptorType type
);
1863 bool anv_descriptor_supports_bindless(const struct anv_physical_device
*pdevice
,
1864 const struct anv_descriptor_set_binding_layout
*binding
,
1867 bool anv_descriptor_requires_bindless(const struct anv_physical_device
*pdevice
,
1868 const struct anv_descriptor_set_binding_layout
*binding
,
1871 struct anv_descriptor_set_layout
{
1872 /* Descriptor set layouts can be destroyed at almost any time */
1875 /* Number of bindings in this descriptor set */
1876 uint16_t binding_count
;
1878 /* Total size of the descriptor set with room for all array entries */
1881 /* Shader stages affected by this descriptor set */
1882 uint16_t shader_stages
;
1884 /* Number of buffer views in this descriptor set */
1885 uint16_t buffer_view_count
;
1887 /* Number of dynamic offsets used by this descriptor set */
1888 uint16_t dynamic_offset_count
;
1890 /* For each shader stage, which offsets apply to that stage */
1891 uint16_t stage_dynamic_offsets
[MESA_SHADER_STAGES
];
1893 /* Size of the descriptor buffer for this descriptor set */
1894 uint32_t descriptor_buffer_size
;
1896 /* Bindings in this descriptor set */
1897 struct anv_descriptor_set_binding_layout binding
[0];
1901 anv_descriptor_set_layout_ref(struct anv_descriptor_set_layout
*layout
)
1903 assert(layout
&& layout
->ref_cnt
>= 1);
1904 p_atomic_inc(&layout
->ref_cnt
);
1908 anv_descriptor_set_layout_unref(struct anv_device
*device
,
1909 struct anv_descriptor_set_layout
*layout
)
1911 assert(layout
&& layout
->ref_cnt
>= 1);
1912 if (p_atomic_dec_zero(&layout
->ref_cnt
))
1913 vk_free(&device
->alloc
, layout
);
1916 struct anv_descriptor
{
1917 VkDescriptorType type
;
1921 VkImageLayout layout
;
1922 struct anv_image_view
*image_view
;
1923 struct anv_sampler
*sampler
;
1927 struct anv_buffer
*buffer
;
1932 struct anv_buffer_view
*buffer_view
;
1936 struct anv_descriptor_set
{
1937 struct anv_descriptor_pool
*pool
;
1938 struct anv_descriptor_set_layout
*layout
;
1941 /* State relative to anv_descriptor_pool::bo */
1942 struct anv_state desc_mem
;
1943 /* Surface state for the descriptor buffer */
1944 struct anv_state desc_surface_state
;
1946 uint32_t buffer_view_count
;
1947 struct anv_buffer_view
*buffer_views
;
1949 /* Link to descriptor pool's desc_sets list . */
1950 struct list_head pool_link
;
1952 struct anv_descriptor descriptors
[0];
1955 struct anv_buffer_view
{
1956 enum isl_format format
; /**< VkBufferViewCreateInfo::format */
1957 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1959 struct anv_address address
;
1961 struct anv_state surface_state
;
1962 struct anv_state storage_surface_state
;
1963 struct anv_state writeonly_storage_surface_state
;
1965 struct brw_image_param storage_image_param
;
1968 struct anv_push_descriptor_set
{
1969 struct anv_descriptor_set set
;
1971 /* Put this field right behind anv_descriptor_set so it fills up the
1972 * descriptors[0] field. */
1973 struct anv_descriptor descriptors
[MAX_PUSH_DESCRIPTORS
];
1975 /** True if the descriptor set buffer has been referenced by a draw or
1978 bool set_used_on_gpu
;
1980 struct anv_buffer_view buffer_views
[MAX_PUSH_DESCRIPTORS
];
1983 struct anv_descriptor_pool
{
1989 struct util_vma_heap bo_heap
;
1991 struct anv_state_stream surface_state_stream
;
1992 void *surface_state_free_list
;
1994 struct list_head desc_sets
;
1999 enum anv_descriptor_template_entry_type
{
2000 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_IMAGE
,
2001 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER
,
2002 ANV_DESCRIPTOR_TEMPLATE_ENTRY_TYPE_BUFFER_VIEW
2005 struct anv_descriptor_template_entry
{
2006 /* The type of descriptor in this entry */
2007 VkDescriptorType type
;
2009 /* Binding in the descriptor set */
2012 /* Offset at which to write into the descriptor set binding */
2013 uint32_t array_element
;
2015 /* Number of elements to write into the descriptor set binding */
2016 uint32_t array_count
;
2018 /* Offset into the user provided data */
2021 /* Stride between elements into the user provided data */
2025 struct anv_descriptor_update_template
{
2026 VkPipelineBindPoint bind_point
;
2028 /* The descriptor set this template corresponds to. This value is only
2029 * valid if the template was created with the templateType
2030 * VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET.
2034 /* Number of entries in this template */
2035 uint32_t entry_count
;
2037 /* Entries of the template */
2038 struct anv_descriptor_template_entry entries
[0];
2042 anv_descriptor_set_layout_size(const struct anv_descriptor_set_layout
*layout
);
2045 anv_descriptor_set_write_image_view(struct anv_device
*device
,
2046 struct anv_descriptor_set
*set
,
2047 const VkDescriptorImageInfo
* const info
,
2048 VkDescriptorType type
,
2053 anv_descriptor_set_write_buffer_view(struct anv_device
*device
,
2054 struct anv_descriptor_set
*set
,
2055 VkDescriptorType type
,
2056 struct anv_buffer_view
*buffer_view
,
2061 anv_descriptor_set_write_buffer(struct anv_device
*device
,
2062 struct anv_descriptor_set
*set
,
2063 struct anv_state_stream
*alloc_stream
,
2064 VkDescriptorType type
,
2065 struct anv_buffer
*buffer
,
2068 VkDeviceSize offset
,
2069 VkDeviceSize range
);
2071 anv_descriptor_set_write_inline_uniform_data(struct anv_device
*device
,
2072 struct anv_descriptor_set
*set
,
2079 anv_descriptor_set_write_template(struct anv_device
*device
,
2080 struct anv_descriptor_set
*set
,
2081 struct anv_state_stream
*alloc_stream
,
2082 const struct anv_descriptor_update_template
*template,
2086 anv_descriptor_set_create(struct anv_device
*device
,
2087 struct anv_descriptor_pool
*pool
,
2088 struct anv_descriptor_set_layout
*layout
,
2089 struct anv_descriptor_set
**out_set
);
2092 anv_descriptor_set_destroy(struct anv_device
*device
,
2093 struct anv_descriptor_pool
*pool
,
2094 struct anv_descriptor_set
*set
);
2096 #define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5)
2097 #define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4)
2098 #define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3)
2099 #define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2)
2100 #define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1)
2101 #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
2103 struct anv_pipeline_binding
{
2104 /** Index in the descriptor set
2106 * This is a flattened index; the descriptor set layout is already taken
2111 /** The descriptor set this surface corresponds to.
2113 * The special ANV_DESCRIPTOR_SET_* values above indicates that this
2114 * binding is not a normal descriptor set but something else.
2119 /** Plane in the binding index for images */
2122 /** Input attachment index (relative to the subpass) */
2123 uint8_t input_attachment_index
;
2125 /** Dynamic offset index (for dynamic UBOs and SSBOs) */
2126 uint8_t dynamic_offset_index
;
2129 /** For a storage image, whether it is write-only */
2132 /** Pad to 64 bits so that there are no holes and we can safely memcmp
2133 * assuming POD zero-initialization.
2138 struct anv_push_range
{
2139 /** Index in the descriptor set */
2142 /** Descriptor set index */
2145 /** Dynamic offset index (for dynamic UBOs) */
2146 uint8_t dynamic_offset_index
;
2148 /** Start offset in units of 32B */
2151 /** Range in units of 32B */
2155 struct anv_pipeline_layout
{
2157 struct anv_descriptor_set_layout
*layout
;
2158 uint32_t dynamic_offset_start
;
2163 unsigned char sha1
[20];
2167 struct anv_device
* device
;
2170 VkBufferUsageFlags usage
;
2172 /* Set when bound */
2173 struct anv_address address
;
2176 static inline uint64_t
2177 anv_buffer_get_range(struct anv_buffer
*buffer
, uint64_t offset
, uint64_t range
)
2179 assert(offset
<= buffer
->size
);
2180 if (range
== VK_WHOLE_SIZE
) {
2181 return buffer
->size
- offset
;
2183 assert(range
+ offset
>= range
);
2184 assert(range
+ offset
<= buffer
->size
);
2189 enum anv_cmd_dirty_bits
{
2190 ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
2191 ANV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
2192 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
2193 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
2194 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
2195 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
2196 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
2197 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
2198 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
2199 ANV_CMD_DIRTY_PIPELINE
= 1 << 9,
2200 ANV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
2201 ANV_CMD_DIRTY_RENDER_TARGETS
= 1 << 11,
2202 ANV_CMD_DIRTY_XFB_ENABLE
= 1 << 12,
2203 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 13, /* VK_DYNAMIC_STATE_LINE_STIPPLE_EXT */
2205 typedef uint32_t anv_cmd_dirty_mask_t
;
2207 #define ANV_CMD_DIRTY_DYNAMIC_ALL \
2208 (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
2209 ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
2210 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
2211 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
2212 ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
2213 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
2214 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
2215 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
2216 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE | \
2217 ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE)
2219 static inline enum anv_cmd_dirty_bits
2220 anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state
)
2223 case VK_DYNAMIC_STATE_VIEWPORT
:
2224 return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
2225 case VK_DYNAMIC_STATE_SCISSOR
:
2226 return ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
2227 case VK_DYNAMIC_STATE_LINE_WIDTH
:
2228 return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
2229 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
2230 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2231 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
2232 return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
2233 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
2234 return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
2235 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
2236 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
2237 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
2238 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
2239 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2240 return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
2241 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
2242 return ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
2244 assert(!"Unsupported dynamic state");
2250 enum anv_pipe_bits
{
2251 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
= (1 << 0),
2252 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
= (1 << 1),
2253 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
= (1 << 2),
2254 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
= (1 << 3),
2255 ANV_PIPE_VF_CACHE_INVALIDATE_BIT
= (1 << 4),
2256 ANV_PIPE_DATA_CACHE_FLUSH_BIT
= (1 << 5),
2257 ANV_PIPE_TILE_CACHE_FLUSH_BIT
= (1 << 6),
2258 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
= (1 << 10),
2259 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
= (1 << 11),
2260 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
= (1 << 12),
2261 ANV_PIPE_DEPTH_STALL_BIT
= (1 << 13),
2262 ANV_PIPE_CS_STALL_BIT
= (1 << 20),
2263 ANV_PIPE_END_OF_PIPE_SYNC_BIT
= (1 << 21),
2265 /* This bit does not exist directly in PIPE_CONTROL. Instead it means that
2266 * a flush has happened but not a CS stall. The next time we do any sort
2267 * of invalidation we need to insert a CS stall at that time. Otherwise,
2268 * we would have to CS stall on every flush which could be bad.
2270 ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
= (1 << 22),
2272 /* This bit does not exist directly in PIPE_CONTROL. It means that render
2273 * target operations related to transfer commands with VkBuffer as
2274 * destination are ongoing. Some operations like copies on the command
2275 * streamer might need to be aware of this to trigger the appropriate stall
2276 * before they can proceed with the copy.
2278 ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
= (1 << 23),
2280 /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
2281 * AUX-TT data has changed and we need to invalidate AUX-TT data. This is
2282 * done by writing the AUX-TT register.
2284 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
= (1 << 24),
2286 /* This bit does not exist directly in PIPE_CONTROL. It means that a
2287 * PIPE_CONTROL with a post-sync operation will follow. This is used to
2288 * implement a workaround for Gen9.
2290 ANV_PIPE_POST_SYNC_BIT
= (1 << 25),
2293 #define ANV_PIPE_FLUSH_BITS ( \
2294 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
2295 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2296 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
2297 ANV_PIPE_TILE_CACHE_FLUSH_BIT)
2299 #define ANV_PIPE_STALL_BITS ( \
2300 ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
2301 ANV_PIPE_DEPTH_STALL_BIT | \
2302 ANV_PIPE_CS_STALL_BIT)
2304 #define ANV_PIPE_INVALIDATE_BITS ( \
2305 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | \
2306 ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | \
2307 ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \
2308 ANV_PIPE_DATA_CACHE_FLUSH_BIT | \
2309 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \
2310 ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
2311 ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
2313 static inline enum anv_pipe_bits
2314 anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags
)
2316 enum anv_pipe_bits pipe_bits
= 0;
2319 for_each_bit(b
, flags
) {
2320 switch ((VkAccessFlagBits
)(1 << b
)) {
2321 case VK_ACCESS_SHADER_WRITE_BIT
:
2322 /* We're transitioning a buffer that was previously used as write
2323 * destination through the data port. To make its content available
2324 * to future operations, flush the data cache.
2326 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2328 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
2329 /* We're transitioning a buffer that was previously used as render
2330 * target. To make its content available to future operations, flush
2331 * the render target cache.
2333 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2335 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
2336 /* We're transitioning a buffer that was previously used as depth
2337 * buffer. To make its content available to future operations, flush
2340 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2342 case VK_ACCESS_TRANSFER_WRITE_BIT
:
2343 /* We're transitioning a buffer that was previously used as a
2344 * transfer write destination. Generic write operations include color
2345 * & depth operations as well as buffer operations like :
2346 * - vkCmdClearColorImage()
2347 * - vkCmdClearDepthStencilImage()
2348 * - vkCmdBlitImage()
2349 * - vkCmdCopy*(), vkCmdUpdate*(), vkCmdFill*()
2351 * Most of these operations are implemented using Blorp which writes
2352 * through the render target, so flush that cache to make it visible
2353 * to future operations. And for depth related operations we also
2354 * need to flush the depth cache.
2356 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2357 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2359 case VK_ACCESS_MEMORY_WRITE_BIT
:
2360 /* We're transitioning a buffer for generic write operations. Flush
2363 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2366 break; /* Nothing to do */
2373 static inline enum anv_pipe_bits
2374 anv_pipe_invalidate_bits_for_access_flags(VkAccessFlags flags
)
2376 enum anv_pipe_bits pipe_bits
= 0;
2379 for_each_bit(b
, flags
) {
2380 switch ((VkAccessFlagBits
)(1 << b
)) {
2381 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
2382 /* Indirect draw commands take a buffer as input that we're going to
2383 * read from the command streamer to load some of the HW registers
2384 * (see genX_cmd_buffer.c:load_indirect_parameters). This requires a
2385 * command streamer stall so that all the cache flushes have
2386 * completed before the command streamer loads from memory.
2388 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2389 /* Indirect draw commands also set gl_BaseVertex & gl_BaseIndex
2390 * through a vertex buffer, so invalidate that cache.
2392 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2393 /* For CmdDipatchIndirect, we also load gl_NumWorkGroups through a
2394 * UBO from the buffer, so we need to invalidate constant cache.
2396 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2398 case VK_ACCESS_INDEX_READ_BIT
:
2399 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
2400 /* We transitioning a buffer to be used for as input for vkCmdDraw*
2401 * commands, so we invalidate the VF cache to make sure there is no
2402 * stale data when we start rendering.
2404 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2406 case VK_ACCESS_UNIFORM_READ_BIT
:
2407 /* We transitioning a buffer to be used as uniform data. Because
2408 * uniform is accessed through the data port & sampler, we need to
2409 * invalidate the texture cache (sampler) & constant cache (data
2410 * port) to avoid stale data.
2412 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2413 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2415 case VK_ACCESS_SHADER_READ_BIT
:
2416 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
2417 case VK_ACCESS_TRANSFER_READ_BIT
:
2418 /* Transitioning a buffer to be read through the sampler, so
2419 * invalidate the texture cache, we don't want any stale data.
2421 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2423 case VK_ACCESS_MEMORY_READ_BIT
:
2424 /* Transitioning a buffer for generic read, invalidate all the
2427 pipe_bits
|= ANV_PIPE_INVALIDATE_BITS
;
2429 case VK_ACCESS_MEMORY_WRITE_BIT
:
2430 /* Generic write, make sure all previously written things land in
2433 pipe_bits
|= ANV_PIPE_FLUSH_BITS
;
2435 case VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
:
2436 /* Transitioning a buffer for conditional rendering. We'll load the
2437 * content of this buffer into HW registers using the command
2438 * streamer, so we need to stall the command streamer to make sure
2439 * any in-flight flush operations have completed.
2441 pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2444 break; /* Nothing to do */
2451 #define VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV ( \
2452 VK_IMAGE_ASPECT_COLOR_BIT | \
2453 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2454 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2455 VK_IMAGE_ASPECT_PLANE_2_BIT)
2456 #define VK_IMAGE_ASPECT_PLANES_BITS_ANV ( \
2457 VK_IMAGE_ASPECT_PLANE_0_BIT | \
2458 VK_IMAGE_ASPECT_PLANE_1_BIT | \
2459 VK_IMAGE_ASPECT_PLANE_2_BIT)
2461 struct anv_vertex_binding
{
2462 struct anv_buffer
* buffer
;
2463 VkDeviceSize offset
;
2466 struct anv_xfb_binding
{
2467 struct anv_buffer
* buffer
;
2468 VkDeviceSize offset
;
2472 struct anv_push_constants
{
2473 /** Push constant data provided by the client through vkPushConstants */
2474 uint8_t client_data
[MAX_PUSH_CONSTANTS_SIZE
];
2476 /** Dynamic offsets for dynamic UBOs and SSBOs */
2477 uint32_t dynamic_offsets
[MAX_DYNAMIC_BUFFERS
];
2479 /** Pad out to a multiple of 32 bytes */
2480 uint32_t push_ubo_sizes
[4];
2483 /** Base workgroup ID
2485 * Used for vkCmdDispatchBase.
2487 uint32_t base_work_group_id
[3];
2491 * This is never set by software but is implicitly filled out when
2492 * uploading the push constants for compute shaders.
2494 uint32_t subgroup_id
;
2498 struct anv_dynamic_state
{
2501 VkViewport viewports
[MAX_VIEWPORTS
];
2506 VkRect2D scissors
[MAX_SCISSORS
];
2517 float blend_constants
[4];
2527 } stencil_compare_mask
;
2532 } stencil_write_mask
;
2537 } stencil_reference
;
2545 extern const struct anv_dynamic_state default_dynamic_state
;
2547 uint32_t anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
2548 const struct anv_dynamic_state
*src
,
2549 uint32_t copy_mask
);
2551 struct anv_surface_state
{
2552 struct anv_state state
;
2553 /** Address of the surface referred to by this state
2555 * This address is relative to the start of the BO.
2557 struct anv_address address
;
2558 /* Address of the aux surface, if any
2560 * This field is ANV_NULL_ADDRESS if and only if no aux surface exists.
2562 * With the exception of gen8, the bottom 12 bits of this address' offset
2563 * include extra aux information.
2565 struct anv_address aux_address
;
2566 /* Address of the clear color, if any
2568 * This address is relative to the start of the BO.
2570 struct anv_address clear_address
;
2574 * Attachment state when recording a renderpass instance.
2576 * The clear value is valid only if there exists a pending clear.
2578 struct anv_attachment_state
{
2579 enum isl_aux_usage aux_usage
;
2580 enum isl_aux_usage input_aux_usage
;
2581 struct anv_surface_state color
;
2582 struct anv_surface_state input
;
2584 VkImageLayout current_layout
;
2585 VkImageLayout current_stencil_layout
;
2586 VkImageAspectFlags pending_clear_aspects
;
2587 VkImageAspectFlags pending_load_aspects
;
2589 VkClearValue clear_value
;
2590 bool clear_color_is_zero_one
;
2591 bool clear_color_is_zero
;
2593 /* When multiview is active, attachments with a renderpass clear
2594 * operation have their respective layers cleared on the first
2595 * subpass that uses them, and only in that subpass. We keep track
2596 * of this using a bitfield to indicate which layers of an attachment
2597 * have not been cleared yet when multiview is active.
2599 uint32_t pending_clear_views
;
2600 struct anv_image_view
* image_view
;
2603 /** State tracking for vertex buffer flushes
2605 * On Gen8-9, the VF cache only considers the bottom 32 bits of memory
2606 * addresses. If you happen to have two vertex buffers which get placed
2607 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
2608 * collisions. In order to solve this problem, we track vertex address ranges
2609 * which are live in the cache and invalidate the cache if one ever exceeds 32
2612 struct anv_vb_cache_range
{
2613 /* Virtual address at which the live vertex buffer cache range starts for
2614 * this vertex buffer index.
2618 /* Virtual address of the byte after where vertex buffer cache range ends.
2619 * This is exclusive such that end - start is the size of the range.
2624 /** State tracking for particular pipeline bind point
2626 * This struct is the base struct for anv_cmd_graphics_state and
2627 * anv_cmd_compute_state. These are used to track state which is bound to a
2628 * particular type of pipeline. Generic state that applies per-stage such as
2629 * binding table offsets and push constants is tracked generically with a
2630 * per-stage array in anv_cmd_state.
2632 struct anv_cmd_pipeline_state
{
2633 struct anv_pipeline
*pipeline
;
2635 struct anv_descriptor_set
*descriptors
[MAX_SETS
];
2636 struct anv_push_descriptor_set
*push_descriptors
[MAX_SETS
];
2639 /** State tracking for graphics pipeline
2641 * This has anv_cmd_pipeline_state as a base struct to track things which get
2642 * bound to a graphics pipeline. Along with general pipeline bind point state
2643 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2644 * state which is graphics-specific.
2646 struct anv_cmd_graphics_state
{
2647 struct anv_cmd_pipeline_state base
;
2649 anv_cmd_dirty_mask_t dirty
;
2652 struct anv_vb_cache_range ib_bound_range
;
2653 struct anv_vb_cache_range ib_dirty_range
;
2654 struct anv_vb_cache_range vb_bound_ranges
[33];
2655 struct anv_vb_cache_range vb_dirty_ranges
[33];
2657 struct anv_dynamic_state dynamic
;
2660 struct anv_buffer
*index_buffer
;
2661 uint32_t index_type
; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
2662 uint32_t index_offset
;
2666 /** State tracking for compute pipeline
2668 * This has anv_cmd_pipeline_state as a base struct to track things which get
2669 * bound to a compute pipeline. Along with general pipeline bind point state
2670 * which is in the anv_cmd_pipeline_state base struct, it also contains other
2671 * state which is compute-specific.
2673 struct anv_cmd_compute_state
{
2674 struct anv_cmd_pipeline_state base
;
2676 bool pipeline_dirty
;
2678 struct anv_address num_workgroups
;
2681 /** State required while building cmd buffer */
2682 struct anv_cmd_state
{
2683 /* PIPELINE_SELECT.PipelineSelection */
2684 uint32_t current_pipeline
;
2685 const struct gen_l3_config
* current_l3_config
;
2686 uint32_t last_aux_map_state
;
2688 struct anv_cmd_graphics_state gfx
;
2689 struct anv_cmd_compute_state compute
;
2691 enum anv_pipe_bits pending_pipe_bits
;
2692 VkShaderStageFlags descriptors_dirty
;
2693 VkShaderStageFlags push_constants_dirty
;
2695 struct anv_framebuffer
* framebuffer
;
2696 struct anv_render_pass
* pass
;
2697 struct anv_subpass
* subpass
;
2698 VkRect2D render_area
;
2699 uint32_t restart_index
;
2700 struct anv_vertex_binding vertex_bindings
[MAX_VBS
];
2702 struct anv_xfb_binding xfb_bindings
[MAX_XFB_BUFFERS
];
2703 VkShaderStageFlags push_constant_stages
;
2704 struct anv_push_constants push_constants
[MESA_SHADER_STAGES
];
2705 struct anv_state binding_tables
[MESA_SHADER_STAGES
];
2706 struct anv_state samplers
[MESA_SHADER_STAGES
];
2708 unsigned char sampler_sha1s
[MESA_SHADER_STAGES
][20];
2709 unsigned char surface_sha1s
[MESA_SHADER_STAGES
][20];
2710 unsigned char push_sha1s
[MESA_SHADER_STAGES
][20];
2713 * Whether or not the gen8 PMA fix is enabled. We ensure that, at the top
2714 * of any command buffer it is disabled by disabling it in EndCommandBuffer
2715 * and before invoking the secondary in ExecuteCommands.
2717 bool pma_fix_enabled
;
2720 * Whether or not we know for certain that HiZ is enabled for the current
2721 * subpass. If, for whatever reason, we are unsure as to whether HiZ is
2722 * enabled or not, this will be false.
2726 bool conditional_render_enabled
;
2729 * Last rendering scale argument provided to
2730 * genX(cmd_buffer_emit_hashing_mode)().
2732 unsigned current_hash_scale
;
2735 * Array length is anv_cmd_state::pass::attachment_count. Array content is
2736 * valid only when recording a render pass instance.
2738 struct anv_attachment_state
* attachments
;
2741 * Surface states for color render targets. These are stored in a single
2742 * flat array. For depth-stencil attachments, the surface state is simply
2745 struct anv_state render_pass_states
;
2748 * A null surface state of the right size to match the framebuffer. This
2749 * is one of the states in render_pass_states.
2751 struct anv_state null_surface_state
;
2754 struct anv_cmd_pool
{
2755 VkAllocationCallbacks alloc
;
2756 struct list_head cmd_buffers
;
2759 #define ANV_CMD_BUFFER_BATCH_SIZE 8192
2761 enum anv_cmd_buffer_exec_mode
{
2762 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY
,
2763 ANV_CMD_BUFFER_EXEC_MODE_EMIT
,
2764 ANV_CMD_BUFFER_EXEC_MODE_GROW_AND_EMIT
,
2765 ANV_CMD_BUFFER_EXEC_MODE_CHAIN
,
2766 ANV_CMD_BUFFER_EXEC_MODE_COPY_AND_CHAIN
,
2769 struct anv_cmd_buffer
{
2770 VK_LOADER_DATA _loader_data
;
2772 struct anv_device
* device
;
2774 struct anv_cmd_pool
* pool
;
2775 struct list_head pool_link
;
2777 struct anv_batch batch
;
2779 /* Fields required for the actual chain of anv_batch_bo's.
2781 * These fields are initialized by anv_cmd_buffer_init_batch_bo_chain().
2783 struct list_head batch_bos
;
2784 enum anv_cmd_buffer_exec_mode exec_mode
;
2786 /* A vector of anv_batch_bo pointers for every batch or surface buffer
2787 * referenced by this command buffer
2789 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2791 struct u_vector seen_bbos
;
2793 /* A vector of int32_t's for every block of binding tables.
2795 * initialized by anv_cmd_buffer_init_batch_bo_chain()
2797 struct u_vector bt_block_states
;
2798 struct anv_state bt_next
;
2800 struct anv_reloc_list surface_relocs
;
2801 /** Last seen surface state block pool center bo offset */
2802 uint32_t last_ss_pool_center
;
2804 /* Serial for tracking buffer completion */
2807 /* Stream objects for storing temporary data */
2808 struct anv_state_stream surface_state_stream
;
2809 struct anv_state_stream dynamic_state_stream
;
2811 VkCommandBufferUsageFlags usage_flags
;
2812 VkCommandBufferLevel level
;
2814 struct anv_cmd_state state
;
2816 /* Set by SetPerformanceMarkerINTEL, written into queries by CmdBeginQuery */
2817 uint64_t intel_perf_marker
;
2820 VkResult
anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2821 void anv_cmd_buffer_fini_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2822 void anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer
*cmd_buffer
);
2823 void anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer
*cmd_buffer
);
2824 void anv_cmd_buffer_add_secondary(struct anv_cmd_buffer
*primary
,
2825 struct anv_cmd_buffer
*secondary
);
2826 void anv_cmd_buffer_prepare_execbuf(struct anv_cmd_buffer
*cmd_buffer
);
2827 VkResult
anv_cmd_buffer_execbuf(struct anv_queue
*queue
,
2828 struct anv_cmd_buffer
*cmd_buffer
,
2829 const VkSemaphore
*in_semaphores
,
2830 const uint64_t *in_wait_values
,
2831 uint32_t num_in_semaphores
,
2832 const VkSemaphore
*out_semaphores
,
2833 const uint64_t *out_signal_values
,
2834 uint32_t num_out_semaphores
,
2837 VkResult
anv_cmd_buffer_reset(struct anv_cmd_buffer
*cmd_buffer
);
2839 struct anv_state
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2840 const void *data
, uint32_t size
, uint32_t alignment
);
2841 struct anv_state
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
2842 uint32_t *a
, uint32_t *b
,
2843 uint32_t dwords
, uint32_t alignment
);
2846 anv_cmd_buffer_surface_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2848 anv_cmd_buffer_alloc_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2849 uint32_t entries
, uint32_t *state_offset
);
2851 anv_cmd_buffer_alloc_surface_state(struct anv_cmd_buffer
*cmd_buffer
);
2853 anv_cmd_buffer_alloc_dynamic_state(struct anv_cmd_buffer
*cmd_buffer
,
2854 uint32_t size
, uint32_t alignment
);
2857 anv_cmd_buffer_new_binding_table_block(struct anv_cmd_buffer
*cmd_buffer
);
2859 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer
);
2860 void gen8_cmd_buffer_emit_depth_viewport(struct anv_cmd_buffer
*cmd_buffer
,
2861 bool depth_clamp_enable
);
2862 void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer
*cmd_buffer
);
2864 void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
2865 struct anv_render_pass
*pass
,
2866 struct anv_framebuffer
*framebuffer
,
2867 const VkClearValue
*clear_values
);
2869 void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
);
2872 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2873 gl_shader_stage stage
);
2875 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
);
2877 const struct anv_image_view
*
2878 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
);
2881 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2882 uint32_t num_entries
,
2883 uint32_t *state_offset
,
2884 struct anv_state
*bt_state
);
2886 void anv_cmd_buffer_dump(struct anv_cmd_buffer
*cmd_buffer
);
2888 void anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer
*cmd_buffer
);
2890 enum anv_fence_type
{
2891 ANV_FENCE_TYPE_NONE
= 0,
2893 ANV_FENCE_TYPE_WSI_BO
,
2894 ANV_FENCE_TYPE_SYNCOBJ
,
2898 enum anv_bo_fence_state
{
2899 /** Indicates that this is a new (or newly reset fence) */
2900 ANV_BO_FENCE_STATE_RESET
,
2902 /** Indicates that this fence has been submitted to the GPU but is still
2903 * (as far as we know) in use by the GPU.
2905 ANV_BO_FENCE_STATE_SUBMITTED
,
2907 ANV_BO_FENCE_STATE_SIGNALED
,
2910 struct anv_fence_impl
{
2911 enum anv_fence_type type
;
2914 /** Fence implementation for BO fences
2916 * These fences use a BO and a set of CPU-tracked state flags. The BO
2917 * is added to the object list of the last execbuf call in a QueueSubmit
2918 * and is marked EXEC_WRITE. The state flags track when the BO has been
2919 * submitted to the kernel. We need to do this because Vulkan lets you
2920 * wait on a fence that has not yet been submitted and I915_GEM_BUSY
2921 * will say it's idle in this case.
2925 enum anv_bo_fence_state state
;
2928 /** DRM syncobj handle for syncobj-based fences */
2932 struct wsi_fence
*fence_wsi
;
2937 /* Permanent fence state. Every fence has some form of permanent state
2938 * (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on (for
2939 * cross-process fences) or it could just be a dummy for use internally.
2941 struct anv_fence_impl permanent
;
2943 /* Temporary fence state. A fence *may* have temporary state. That state
2944 * is added to the fence by an import operation and is reset back to
2945 * ANV_SEMAPHORE_TYPE_NONE when the fence is reset. A fence with temporary
2946 * state cannot be signaled because the fence must already be signaled
2947 * before the temporary state can be exported from the fence in the other
2948 * process and imported here.
2950 struct anv_fence_impl temporary
;
2953 void anv_fence_reset_temporary(struct anv_device
*device
,
2954 struct anv_fence
*fence
);
2958 struct anv_state state
;
2961 enum anv_semaphore_type
{
2962 ANV_SEMAPHORE_TYPE_NONE
= 0,
2963 ANV_SEMAPHORE_TYPE_DUMMY
,
2964 ANV_SEMAPHORE_TYPE_BO
,
2965 ANV_SEMAPHORE_TYPE_WSI_BO
,
2966 ANV_SEMAPHORE_TYPE_SYNC_FILE
,
2967 ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ
,
2968 ANV_SEMAPHORE_TYPE_TIMELINE
,
2971 struct anv_timeline_point
{
2972 struct list_head link
;
2976 /* Number of waiter on this point, when > 0 the point should not be garbage
2981 /* BO used for synchronization. */
2985 struct anv_timeline
{
2986 pthread_mutex_t mutex
;
2987 pthread_cond_t cond
;
2989 uint64_t highest_past
;
2990 uint64_t highest_pending
;
2992 struct list_head points
;
2993 struct list_head free_points
;
2996 struct anv_semaphore_impl
{
2997 enum anv_semaphore_type type
;
3000 /* A BO representing this semaphore when type == ANV_SEMAPHORE_TYPE_BO
3001 * or type == ANV_SEMAPHORE_TYPE_WSI_BO. This BO will be added to the
3002 * object list on any execbuf2 calls for which this semaphore is used as
3003 * a wait or signal fence. When used as a signal fence or when type ==
3004 * ANV_SEMAPHORE_TYPE_WSI_BO, the EXEC_OBJECT_WRITE flag will be set.
3008 /* The sync file descriptor when type == ANV_SEMAPHORE_TYPE_SYNC_FILE.
3009 * If the semaphore is in the unsignaled state due to either just being
3010 * created or because it has been used for a wait, fd will be -1.
3014 /* Sync object handle when type == ANV_SEMAPHORE_TYPE_DRM_SYNCOBJ.
3015 * Unlike GEM BOs, DRM sync objects aren't deduplicated by the kernel on
3016 * import so we don't need to bother with a userspace cache.
3020 /* Non shareable timeline semaphore
3022 * Used when kernel don't have support for timeline semaphores.
3024 struct anv_timeline timeline
;
3028 struct anv_semaphore
{
3031 /* Permanent semaphore state. Every semaphore has some form of permanent
3032 * state (type != ANV_SEMAPHORE_TYPE_NONE). This may be a BO to fence on
3033 * (for cross-process semaphores0 or it could just be a dummy for use
3036 struct anv_semaphore_impl permanent
;
3038 /* Temporary semaphore state. A semaphore *may* have temporary state.
3039 * That state is added to the semaphore by an import operation and is reset
3040 * back to ANV_SEMAPHORE_TYPE_NONE when the semaphore is waited on. A
3041 * semaphore with temporary state cannot be signaled because the semaphore
3042 * must already be signaled before the temporary state can be exported from
3043 * the semaphore in the other process and imported here.
3045 struct anv_semaphore_impl temporary
;
3048 void anv_semaphore_reset_temporary(struct anv_device
*device
,
3049 struct anv_semaphore
*semaphore
);
3051 struct anv_shader_module
{
3052 unsigned char sha1
[20];
3057 static inline gl_shader_stage
3058 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
3060 assert(__builtin_popcount(vk_stage
) == 1);
3061 return ffs(vk_stage
) - 1;
3064 static inline VkShaderStageFlagBits
3065 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
3067 return (1 << mesa_stage
);
3070 #define ANV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
3072 #define anv_foreach_stage(stage, stage_bits) \
3073 for (gl_shader_stage stage, \
3074 __tmp = (gl_shader_stage)((stage_bits) & ANV_STAGE_MASK); \
3075 stage = __builtin_ffs(__tmp) - 1, __tmp; \
3076 __tmp &= ~(1 << (stage)))
3078 struct anv_pipeline_bind_map
{
3079 unsigned char surface_sha1
[20];
3080 unsigned char sampler_sha1
[20];
3081 unsigned char push_sha1
[20];
3083 uint32_t surface_count
;
3084 uint32_t sampler_count
;
3086 struct anv_pipeline_binding
* surface_to_descriptor
;
3087 struct anv_pipeline_binding
* sampler_to_descriptor
;
3089 struct anv_push_range push_ranges
[4];
3092 struct anv_shader_bin_key
{
3097 struct anv_shader_bin
{
3100 const struct anv_shader_bin_key
*key
;
3102 struct anv_state kernel
;
3103 uint32_t kernel_size
;
3105 struct anv_state constant_data
;
3106 uint32_t constant_data_size
;
3108 const struct brw_stage_prog_data
*prog_data
;
3109 uint32_t prog_data_size
;
3111 struct brw_compile_stats stats
[3];
3114 struct nir_xfb_info
*xfb_info
;
3116 struct anv_pipeline_bind_map bind_map
;
3119 struct anv_shader_bin
*
3120 anv_shader_bin_create(struct anv_device
*device
,
3121 const void *key
, uint32_t key_size
,
3122 const void *kernel
, uint32_t kernel_size
,
3123 const void *constant_data
, uint32_t constant_data_size
,
3124 const struct brw_stage_prog_data
*prog_data
,
3125 uint32_t prog_data_size
,
3126 const struct brw_compile_stats
*stats
, uint32_t num_stats
,
3127 const struct nir_xfb_info
*xfb_info
,
3128 const struct anv_pipeline_bind_map
*bind_map
);
3131 anv_shader_bin_destroy(struct anv_device
*device
, struct anv_shader_bin
*shader
);
3134 anv_shader_bin_ref(struct anv_shader_bin
*shader
)
3136 assert(shader
&& shader
->ref_cnt
>= 1);
3137 p_atomic_inc(&shader
->ref_cnt
);
3141 anv_shader_bin_unref(struct anv_device
*device
, struct anv_shader_bin
*shader
)
3143 assert(shader
&& shader
->ref_cnt
>= 1);
3144 if (p_atomic_dec_zero(&shader
->ref_cnt
))
3145 anv_shader_bin_destroy(device
, shader
);
3148 /* 5 possible simultaneous shader stages and FS may have up to 3 binaries */
3149 #define MAX_PIPELINE_EXECUTABLES 7
3151 struct anv_pipeline_executable
{
3152 gl_shader_stage stage
;
3154 struct brw_compile_stats stats
;
3160 struct anv_pipeline
{
3161 struct anv_device
* device
;
3162 struct anv_batch batch
;
3163 uint32_t batch_data
[512];
3164 struct anv_reloc_list batch_relocs
;
3165 anv_cmd_dirty_mask_t dynamic_state_mask
;
3166 struct anv_dynamic_state dynamic_state
;
3170 VkPipelineCreateFlags flags
;
3171 struct anv_subpass
* subpass
;
3173 struct anv_shader_bin
* shaders
[MESA_SHADER_STAGES
];
3175 uint32_t num_executables
;
3176 struct anv_pipeline_executable executables
[MAX_PIPELINE_EXECUTABLES
];
3178 const struct gen_l3_config
* l3_config
;
3180 VkShaderStageFlags active_stages
;
3181 struct anv_state blend_state
;
3184 struct anv_pipeline_vertex_binding
{
3187 uint32_t instance_divisor
;
3190 bool primitive_restart
;
3193 uint32_t cs_right_mask
;
3196 bool depth_test_enable
;
3197 bool writes_stencil
;
3198 bool stencil_test_enable
;
3199 bool depth_clamp_enable
;
3200 bool depth_clip_enable
;
3201 bool sample_shading_enable
;
3203 bool depth_bounds_test_enable
;
3207 uint32_t depth_stencil_state
[3];
3213 uint32_t wm_depth_stencil
[3];
3217 uint32_t wm_depth_stencil
[4];
3220 uint32_t interface_descriptor_data
[8];
3224 anv_pipeline_has_stage(const struct anv_pipeline
*pipeline
,
3225 gl_shader_stage stage
)
3227 return (pipeline
->active_stages
& mesa_to_vk_shader_stage(stage
)) != 0;
3230 #define ANV_DECL_GET_PROG_DATA_FUNC(prefix, stage) \
3231 static inline const struct brw_##prefix##_prog_data * \
3232 get_##prefix##_prog_data(const struct anv_pipeline *pipeline) \
3234 if (anv_pipeline_has_stage(pipeline, stage)) { \
3235 return (const struct brw_##prefix##_prog_data *) \
3236 pipeline->shaders[stage]->prog_data; \
3242 ANV_DECL_GET_PROG_DATA_FUNC(vs
, MESA_SHADER_VERTEX
)
3243 ANV_DECL_GET_PROG_DATA_FUNC(tcs
, MESA_SHADER_TESS_CTRL
)
3244 ANV_DECL_GET_PROG_DATA_FUNC(tes
, MESA_SHADER_TESS_EVAL
)
3245 ANV_DECL_GET_PROG_DATA_FUNC(gs
, MESA_SHADER_GEOMETRY
)
3246 ANV_DECL_GET_PROG_DATA_FUNC(wm
, MESA_SHADER_FRAGMENT
)
3247 ANV_DECL_GET_PROG_DATA_FUNC(cs
, MESA_SHADER_COMPUTE
)
3249 static inline const struct brw_vue_prog_data
*
3250 anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline
*pipeline
)
3252 if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_GEOMETRY
))
3253 return &get_gs_prog_data(pipeline
)->base
;
3254 else if (anv_pipeline_has_stage(pipeline
, MESA_SHADER_TESS_EVAL
))
3255 return &get_tes_prog_data(pipeline
)->base
;
3257 return &get_vs_prog_data(pipeline
)->base
;
3261 anv_pipeline_init(struct anv_pipeline
*pipeline
, struct anv_device
*device
,
3262 struct anv_pipeline_cache
*cache
,
3263 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3264 const VkAllocationCallbacks
*alloc
);
3267 anv_pipeline_compile_cs(struct anv_pipeline
*pipeline
,
3268 struct anv_pipeline_cache
*cache
,
3269 const VkComputePipelineCreateInfo
*info
,
3270 const struct anv_shader_module
*module
,
3271 const char *entrypoint
,
3272 const VkSpecializationInfo
*spec_info
);
3274 struct anv_format_plane
{
3275 enum isl_format isl_format
:16;
3276 struct isl_swizzle swizzle
;
3278 /* Whether this plane contains chroma channels */
3281 /* For downscaling of YUV planes */
3282 uint8_t denominator_scales
[2];
3284 /* How to map sampled ycbcr planes to a single 4 component element. */
3285 struct isl_swizzle ycbcr_swizzle
;
3287 /* What aspect is associated to this plane */
3288 VkImageAspectFlags aspect
;
3293 struct anv_format_plane planes
[3];
3300 * Return the aspect's _format_ plane, not its _memory_ plane (using the
3301 * vocabulary of VK_EXT_image_drm_format_modifier). As a consequence, \a
3302 * aspect_mask may contain VK_IMAGE_ASPECT_PLANE_*, but must not contain
3303 * VK_IMAGE_ASPECT_MEMORY_PLANE_* .
3305 static inline uint32_t
3306 anv_image_aspect_to_plane(VkImageAspectFlags image_aspects
,
3307 VkImageAspectFlags aspect_mask
)
3309 switch (aspect_mask
) {
3310 case VK_IMAGE_ASPECT_COLOR_BIT
:
3311 case VK_IMAGE_ASPECT_DEPTH_BIT
:
3312 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
3314 case VK_IMAGE_ASPECT_STENCIL_BIT
:
3315 if ((image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) == 0)
3318 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
3320 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
3323 /* Purposefully assert with depth/stencil aspects. */
3324 unreachable("invalid image aspect");
3328 static inline VkImageAspectFlags
3329 anv_plane_to_aspect(VkImageAspectFlags image_aspects
,
3332 if (image_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3333 if (util_bitcount(image_aspects
) > 1)
3334 return VK_IMAGE_ASPECT_PLANE_0_BIT
<< plane
;
3335 return VK_IMAGE_ASPECT_COLOR_BIT
;
3337 if (image_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
3338 return VK_IMAGE_ASPECT_DEPTH_BIT
<< plane
;
3339 assert(image_aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
3340 return VK_IMAGE_ASPECT_STENCIL_BIT
;
3343 #define anv_foreach_image_aspect_bit(b, image, aspects) \
3344 for_each_bit(b, anv_image_expand_aspects(image, aspects))
3346 const struct anv_format
*
3347 anv_get_format(VkFormat format
);
3349 static inline uint32_t
3350 anv_get_format_planes(VkFormat vk_format
)
3352 const struct anv_format
*format
= anv_get_format(vk_format
);
3354 return format
!= NULL
? format
->n_planes
: 0;
3357 struct anv_format_plane
3358 anv_get_format_plane(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3359 VkImageAspectFlagBits aspect
, VkImageTiling tiling
);
3361 static inline enum isl_format
3362 anv_get_isl_format(const struct gen_device_info
*devinfo
, VkFormat vk_format
,
3363 VkImageAspectFlags aspect
, VkImageTiling tiling
)
3365 return anv_get_format_plane(devinfo
, vk_format
, aspect
, tiling
).isl_format
;
3368 bool anv_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
3369 VkImageCreateFlags create_flags
,
3371 VkImageTiling vk_tiling
,
3372 const VkImageFormatListCreateInfoKHR
*fmt_list
);
3374 static inline struct isl_swizzle
3375 anv_swizzle_for_render(struct isl_swizzle swizzle
)
3377 /* Sometimes the swizzle will have alpha map to one. We do this to fake
3378 * RGB as RGBA for texturing
3380 assert(swizzle
.a
== ISL_CHANNEL_SELECT_ONE
||
3381 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
3383 /* But it doesn't matter what we render to that channel */
3384 swizzle
.a
= ISL_CHANNEL_SELECT_ALPHA
;
3390 anv_pipeline_setup_l3_config(struct anv_pipeline
*pipeline
, bool needs_slm
);
3393 * Subsurface of an anv_image.
3395 struct anv_surface
{
3396 /** Valid only if isl_surf::size_B > 0. */
3397 struct isl_surf isl
;
3400 * Offset from VkImage's base address, as bound by vkBindImageMemory().
3406 VkImageType type
; /**< VkImageCreateInfo::imageType */
3407 /* The original VkFormat provided by the client. This may not match any
3408 * of the actual surface formats.
3411 const struct anv_format
*format
;
3413 VkImageAspectFlags aspects
;
3416 uint32_t array_size
;
3417 uint32_t samples
; /**< VkImageCreateInfo::samples */
3419 VkImageUsageFlags usage
; /**< VkImageCreateInfo::usage. */
3420 VkImageUsageFlags stencil_usage
;
3421 VkImageCreateFlags create_flags
; /* Flags used when creating image. */
3422 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
3424 /** True if this is needs to be bound to an appropriately tiled BO.
3426 * When not using modifiers, consumers such as X11, Wayland, and KMS need
3427 * the tiling passed via I915_GEM_SET_TILING. When exporting these buffers
3428 * we require a dedicated allocation so that we can know to allocate a
3431 bool needs_set_tiling
;
3434 * Must be DRM_FORMAT_MOD_INVALID unless tiling is
3435 * VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.
3437 uint64_t drm_format_mod
;
3442 /* Whether the image is made of several underlying buffer objects rather a
3443 * single one with different offsets.
3447 /* Image was created with external format. */
3448 bool external_format
;
3453 * For each foo, anv_image::planes[x].surface is valid if and only if
3454 * anv_image::aspects has a x aspect. Refer to anv_image_aspect_to_plane()
3455 * to figure the number associated with a given aspect.
3457 * The hardware requires that the depth buffer and stencil buffer be
3458 * separate surfaces. From Vulkan's perspective, though, depth and stencil
3459 * reside in the same VkImage. To satisfy both the hardware and Vulkan, we
3460 * allocate the depth and stencil buffers as separate surfaces in the same
3465 * -----------------------
3467 * ----------------------- |
3468 * | shadow surface0 | |
3469 * ----------------------- | Plane 0
3470 * | aux surface0 | |
3471 * ----------------------- |
3472 * | fast clear colors0 | \|/
3473 * -----------------------
3475 * ----------------------- |
3476 * | shadow surface1 | |
3477 * ----------------------- | Plane 1
3478 * | aux surface1 | |
3479 * ----------------------- |
3480 * | fast clear colors1 | \|/
3481 * -----------------------
3484 * -----------------------
3488 * Offset of the entire plane (whenever the image is disjoint this is
3496 struct anv_surface surface
;
3499 * A surface which shadows the main surface and may have different
3500 * tiling. This is used for sampling using a tiling that isn't supported
3501 * for other operations.
3503 struct anv_surface shadow_surface
;
3506 * The base aux usage for this image. For color images, this can be
3507 * either CCS_E or CCS_D depending on whether or not we can reliably
3508 * leave CCS on all the time.
3510 enum isl_aux_usage aux_usage
;
3512 struct anv_surface aux_surface
;
3515 * Offset of the fast clear state (used to compute the
3516 * fast_clear_state_offset of the following planes).
3518 uint32_t fast_clear_state_offset
;
3521 * BO associated with this plane, set when bound.
3523 struct anv_address address
;
3526 * When destroying the image, also free the bo.
3532 /* The ordering of this enum is important */
3533 enum anv_fast_clear_type
{
3534 /** Image does not have/support any fast-clear blocks */
3535 ANV_FAST_CLEAR_NONE
= 0,
3536 /** Image has/supports fast-clear but only to the default value */
3537 ANV_FAST_CLEAR_DEFAULT_VALUE
= 1,
3538 /** Image has/supports fast-clear with an arbitrary fast-clear value */
3539 ANV_FAST_CLEAR_ANY
= 2,
3542 /* Returns the number of auxiliary buffer levels attached to an image. */
3543 static inline uint8_t
3544 anv_image_aux_levels(const struct anv_image
* const image
,
3545 VkImageAspectFlagBits aspect
)
3547 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3548 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
3551 /* The Gen12 CCS aux surface is represented with only one level. */
3552 return image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3553 image
->planes
[plane
].surface
.isl
.levels
:
3554 image
->planes
[plane
].aux_surface
.isl
.levels
;
3557 /* Returns the number of auxiliary buffer layers attached to an image. */
3558 static inline uint32_t
3559 anv_image_aux_layers(const struct anv_image
* const image
,
3560 VkImageAspectFlagBits aspect
,
3561 const uint8_t miplevel
)
3565 /* The miplevel must exist in the main buffer. */
3566 assert(miplevel
< image
->levels
);
3568 if (miplevel
>= anv_image_aux_levels(image
, aspect
)) {
3569 /* There are no layers with auxiliary data because the miplevel has no
3574 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3576 /* The Gen12 CCS aux surface is represented with only one layer. */
3577 const struct isl_extent4d
*aux_logical_level0_px
=
3578 image
->planes
[plane
].aux_surface
.isl
.tiling
== ISL_TILING_GEN12_CCS
?
3579 &image
->planes
[plane
].surface
.isl
.logical_level0_px
:
3580 &image
->planes
[plane
].aux_surface
.isl
.logical_level0_px
;
3582 return MAX2(aux_logical_level0_px
->array_len
,
3583 aux_logical_level0_px
->depth
>> miplevel
);
3587 static inline struct anv_address
3588 anv_image_get_clear_color_addr(const struct anv_device
*device
,
3589 const struct anv_image
*image
,
3590 VkImageAspectFlagBits aspect
)
3592 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
3594 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3595 return anv_address_add(image
->planes
[plane
].address
,
3596 image
->planes
[plane
].fast_clear_state_offset
);
3599 static inline struct anv_address
3600 anv_image_get_fast_clear_type_addr(const struct anv_device
*device
,
3601 const struct anv_image
*image
,
3602 VkImageAspectFlagBits aspect
)
3604 struct anv_address addr
=
3605 anv_image_get_clear_color_addr(device
, image
, aspect
);
3607 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
3608 device
->isl_dev
.ss
.clear_color_state_size
:
3609 device
->isl_dev
.ss
.clear_value_size
;
3610 return anv_address_add(addr
, clear_color_state_size
);
3613 static inline struct anv_address
3614 anv_image_get_compression_state_addr(const struct anv_device
*device
,
3615 const struct anv_image
*image
,
3616 VkImageAspectFlagBits aspect
,
3617 uint32_t level
, uint32_t array_layer
)
3619 assert(level
< anv_image_aux_levels(image
, aspect
));
3620 assert(array_layer
< anv_image_aux_layers(image
, aspect
, level
));
3621 UNUSED
uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
3622 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
);
3624 struct anv_address addr
=
3625 anv_image_get_fast_clear_type_addr(device
, image
, aspect
);
3626 addr
.offset
+= 4; /* Go past the fast clear type */
3628 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3629 for (uint32_t l
= 0; l
< level
; l
++)
3630 addr
.offset
+= anv_minify(image
->extent
.depth
, l
) * 4;
3632 addr
.offset
+= level
* image
->array_size
* 4;
3634 addr
.offset
+= array_layer
* 4;
3636 assert(addr
.offset
<
3637 image
->planes
[plane
].address
.offset
+ image
->planes
[plane
].size
);
3641 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
3643 anv_can_sample_with_hiz(const struct gen_device_info
* const devinfo
,
3644 const struct anv_image
*image
)
3646 if (!(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
3649 /* Allow this feature on BDW even though it is disabled in the BDW devinfo
3650 * struct. There's documentation which suggests that this feature actually
3651 * reduces performance on BDW, but it has only been observed to help so
3652 * far. Sampling fast-cleared blocks on BDW must also be handled with care
3653 * (see depth_stencil_attachment_compute_aux_usage() for more info).
3655 if (devinfo
->gen
!= 8 && !devinfo
->has_sample_with_hiz
)
3658 return image
->samples
== 1;
3662 anv_image_plane_uses_aux_map(const struct anv_device
*device
,
3663 const struct anv_image
*image
,
3666 return device
->info
.has_aux_map
&&
3667 isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
);
3671 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer
*cmd_buffer
,
3672 const struct anv_image
*image
,
3673 VkImageAspectFlagBits aspect
,
3674 enum isl_aux_usage aux_usage
,
3676 uint32_t base_layer
,
3677 uint32_t layer_count
);
3680 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
3681 const struct anv_image
*image
,
3682 VkImageAspectFlagBits aspect
,
3683 enum isl_aux_usage aux_usage
,
3684 enum isl_format format
, struct isl_swizzle swizzle
,
3685 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
3686 VkRect2D area
, union isl_color_value clear_color
);
3688 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
3689 const struct anv_image
*image
,
3690 VkImageAspectFlags aspects
,
3691 enum isl_aux_usage depth_aux_usage
,
3693 uint32_t base_layer
, uint32_t layer_count
,
3695 float depth_value
, uint8_t stencil_value
);
3697 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
3698 const struct anv_image
*src_image
,
3699 enum isl_aux_usage src_aux_usage
,
3700 uint32_t src_level
, uint32_t src_base_layer
,
3701 const struct anv_image
*dst_image
,
3702 enum isl_aux_usage dst_aux_usage
,
3703 uint32_t dst_level
, uint32_t dst_base_layer
,
3704 VkImageAspectFlagBits aspect
,
3705 uint32_t src_x
, uint32_t src_y
,
3706 uint32_t dst_x
, uint32_t dst_y
,
3707 uint32_t width
, uint32_t height
,
3708 uint32_t layer_count
,
3709 enum blorp_filter filter
);
3711 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
3712 const struct anv_image
*image
,
3713 VkImageAspectFlagBits aspect
, uint32_t level
,
3714 uint32_t base_layer
, uint32_t layer_count
,
3715 enum isl_aux_op hiz_op
);
3717 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
3718 const struct anv_image
*image
,
3719 VkImageAspectFlags aspects
,
3721 uint32_t base_layer
, uint32_t layer_count
,
3722 VkRect2D area
, uint8_t stencil_value
);
3724 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
3725 const struct anv_image
*image
,
3726 enum isl_format format
,
3727 VkImageAspectFlagBits aspect
,
3728 uint32_t base_layer
, uint32_t layer_count
,
3729 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
3732 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
3733 const struct anv_image
*image
,
3734 enum isl_format format
,
3735 VkImageAspectFlagBits aspect
, uint32_t level
,
3736 uint32_t base_layer
, uint32_t layer_count
,
3737 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
3741 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
3742 const struct anv_image
*image
,
3743 VkImageAspectFlagBits aspect
,
3744 uint32_t base_level
, uint32_t level_count
,
3745 uint32_t base_layer
, uint32_t layer_count
);
3748 anv_layout_to_aux_state(const struct gen_device_info
* const devinfo
,
3749 const struct anv_image
*image
,
3750 const VkImageAspectFlagBits aspect
,
3751 const VkImageLayout layout
);
3754 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
3755 const struct anv_image
*image
,
3756 const VkImageAspectFlagBits aspect
,
3757 const VkImageUsageFlagBits usage
,
3758 const VkImageLayout layout
);
3760 enum anv_fast_clear_type
3761 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
3762 const struct anv_image
* const image
,
3763 const VkImageAspectFlagBits aspect
,
3764 const VkImageLayout layout
);
3766 /* This is defined as a macro so that it works for both
3767 * VkImageSubresourceRange and VkImageSubresourceLayers
3769 #define anv_get_layerCount(_image, _range) \
3770 ((_range)->layerCount == VK_REMAINING_ARRAY_LAYERS ? \
3771 (_image)->array_size - (_range)->baseArrayLayer : (_range)->layerCount)
3773 static inline uint32_t
3774 anv_get_levelCount(const struct anv_image
*image
,
3775 const VkImageSubresourceRange
*range
)
3777 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
3778 image
->levels
- range
->baseMipLevel
: range
->levelCount
;
3781 static inline VkImageAspectFlags
3782 anv_image_expand_aspects(const struct anv_image
*image
,
3783 VkImageAspectFlags aspects
)
3785 /* If the underlying image has color plane aspects and
3786 * VK_IMAGE_ASPECT_COLOR_BIT has been requested, then return the aspects of
3787 * the underlying image. */
3788 if ((image
->aspects
& VK_IMAGE_ASPECT_PLANES_BITS_ANV
) != 0 &&
3789 aspects
== VK_IMAGE_ASPECT_COLOR_BIT
)
3790 return image
->aspects
;
3796 anv_image_aspects_compatible(VkImageAspectFlags aspects1
,
3797 VkImageAspectFlags aspects2
)
3799 if (aspects1
== aspects2
)
3802 /* Only 1 color aspects are compatibles. */
3803 if ((aspects1
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3804 (aspects2
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) != 0 &&
3805 util_bitcount(aspects1
) == util_bitcount(aspects2
))
3811 struct anv_image_view
{
3812 const struct anv_image
*image
; /**< VkImageViewCreateInfo::image */
3814 VkImageAspectFlags aspect_mask
;
3816 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
3820 uint32_t image_plane
;
3822 struct isl_view isl
;
3825 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3826 * image layout of SHADER_READ_ONLY_OPTIMAL or
3827 * DEPTH_STENCIL_READ_ONLY_OPTIMAL.
3829 struct anv_surface_state optimal_sampler_surface_state
;
3832 * RENDER_SURFACE_STATE when using image as a sampler surface with an
3833 * image layout of GENERAL.
3835 struct anv_surface_state general_sampler_surface_state
;
3838 * RENDER_SURFACE_STATE when using image as a storage image. Separate
3839 * states for write-only and readable, using the real format for
3840 * write-only and the lowered format for readable.
3842 struct anv_surface_state storage_surface_state
;
3843 struct anv_surface_state writeonly_storage_surface_state
;
3845 struct brw_image_param storage_image_param
;
3849 enum anv_image_view_state_flags
{
3850 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
= (1 << 0),
3851 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
= (1 << 1),
3854 void anv_image_fill_surface_state(struct anv_device
*device
,
3855 const struct anv_image
*image
,
3856 VkImageAspectFlagBits aspect
,
3857 const struct isl_view
*view
,
3858 isl_surf_usage_flags_t view_usage
,
3859 enum isl_aux_usage aux_usage
,
3860 const union isl_color_value
*clear_color
,
3861 enum anv_image_view_state_flags flags
,
3862 struct anv_surface_state
*state_inout
,
3863 struct brw_image_param
*image_param_out
);
3865 struct anv_image_create_info
{
3866 const VkImageCreateInfo
*vk_info
;
3868 /** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
3869 isl_tiling_flags_t isl_tiling_flags
;
3871 /** These flags will be added to any derived from VkImageCreateInfo. */
3872 isl_surf_usage_flags_t isl_extra_usage_flags
;
3875 bool external_format
;
3878 VkResult
anv_image_create(VkDevice _device
,
3879 const struct anv_image_create_info
*info
,
3880 const VkAllocationCallbacks
* alloc
,
3884 anv_isl_format_for_descriptor_type(VkDescriptorType type
);
3886 static inline VkExtent3D
3887 anv_sanitize_image_extent(const VkImageType imageType
,
3888 const VkExtent3D imageExtent
)
3890 switch (imageType
) {
3891 case VK_IMAGE_TYPE_1D
:
3892 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
3893 case VK_IMAGE_TYPE_2D
:
3894 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
3895 case VK_IMAGE_TYPE_3D
:
3898 unreachable("invalid image type");
3902 static inline VkOffset3D
3903 anv_sanitize_image_offset(const VkImageType imageType
,
3904 const VkOffset3D imageOffset
)
3906 switch (imageType
) {
3907 case VK_IMAGE_TYPE_1D
:
3908 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
3909 case VK_IMAGE_TYPE_2D
:
3910 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
3911 case VK_IMAGE_TYPE_3D
:
3914 unreachable("invalid image type");
3918 VkFormatFeatureFlags
3919 anv_get_image_format_features(const struct gen_device_info
*devinfo
,
3921 const struct anv_format
*anv_format
,
3922 VkImageTiling vk_tiling
);
3924 void anv_fill_buffer_surface_state(struct anv_device
*device
,
3925 struct anv_state state
,
3926 enum isl_format format
,
3927 struct anv_address address
,
3928 uint32_t range
, uint32_t stride
);
3931 anv_clear_color_from_att_state(union isl_color_value
*clear_color
,
3932 const struct anv_attachment_state
*att_state
,
3933 const struct anv_image_view
*iview
)
3935 const struct isl_format_layout
*view_fmtl
=
3936 isl_format_get_layout(iview
->planes
[0].isl
.format
);
3938 #define COPY_CLEAR_COLOR_CHANNEL(c, i) \
3939 if (view_fmtl->channels.c.bits) \
3940 clear_color->u32[i] = att_state->clear_value.color.uint32[i]
3942 COPY_CLEAR_COLOR_CHANNEL(r
, 0);
3943 COPY_CLEAR_COLOR_CHANNEL(g
, 1);
3944 COPY_CLEAR_COLOR_CHANNEL(b
, 2);
3945 COPY_CLEAR_COLOR_CHANNEL(a
, 3);
3947 #undef COPY_CLEAR_COLOR_CHANNEL
3951 struct anv_ycbcr_conversion
{
3952 const struct anv_format
* format
;
3953 VkSamplerYcbcrModelConversion ycbcr_model
;
3954 VkSamplerYcbcrRange ycbcr_range
;
3955 VkComponentSwizzle mapping
[4];
3956 VkChromaLocation chroma_offsets
[2];
3957 VkFilter chroma_filter
;
3958 bool chroma_reconstruction
;
3961 struct anv_sampler
{
3962 uint32_t state
[3][4];
3964 struct anv_ycbcr_conversion
*conversion
;
3966 /* Blob of sampler state data which is guaranteed to be 32-byte aligned
3967 * and with a 32-byte stride for use as bindless samplers.
3969 struct anv_state bindless_state
;
3972 struct anv_framebuffer
{
3977 uint32_t attachment_count
;
3978 struct anv_image_view
* attachments
[0];
3981 struct anv_subpass_attachment
{
3982 VkImageUsageFlagBits usage
;
3983 uint32_t attachment
;
3984 VkImageLayout layout
;
3986 /* Used only with attachment containing stencil data. */
3987 VkImageLayout stencil_layout
;
3990 struct anv_subpass
{
3991 uint32_t attachment_count
;
3994 * A pointer to all attachment references used in this subpass.
3995 * Only valid if ::attachment_count > 0.
3997 struct anv_subpass_attachment
* attachments
;
3998 uint32_t input_count
;
3999 struct anv_subpass_attachment
* input_attachments
;
4000 uint32_t color_count
;
4001 struct anv_subpass_attachment
* color_attachments
;
4002 struct anv_subpass_attachment
* resolve_attachments
;
4004 struct anv_subpass_attachment
* depth_stencil_attachment
;
4005 struct anv_subpass_attachment
* ds_resolve_attachment
;
4006 VkResolveModeFlagBitsKHR depth_resolve_mode
;
4007 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
4011 /** Subpass has a depth/stencil self-dependency */
4012 bool has_ds_self_dep
;
4014 /** Subpass has at least one color resolve attachment */
4015 bool has_color_resolve
;
4018 static inline unsigned
4019 anv_subpass_view_count(const struct anv_subpass
*subpass
)
4021 return MAX2(1, util_bitcount(subpass
->view_mask
));
4024 struct anv_render_pass_attachment
{
4025 /* TODO: Consider using VkAttachmentDescription instead of storing each of
4026 * its members individually.
4030 VkImageUsageFlags usage
;
4031 VkAttachmentLoadOp load_op
;
4032 VkAttachmentStoreOp store_op
;
4033 VkAttachmentLoadOp stencil_load_op
;
4034 VkImageLayout initial_layout
;
4035 VkImageLayout final_layout
;
4036 VkImageLayout first_subpass_layout
;
4038 VkImageLayout stencil_initial_layout
;
4039 VkImageLayout stencil_final_layout
;
4041 /* The subpass id in which the attachment will be used last. */
4042 uint32_t last_subpass_idx
;
4045 struct anv_render_pass
{
4046 uint32_t attachment_count
;
4047 uint32_t subpass_count
;
4048 /* An array of subpass_count+1 flushes, one per subpass boundary */
4049 enum anv_pipe_bits
* subpass_flushes
;
4050 struct anv_render_pass_attachment
* attachments
;
4051 struct anv_subpass subpasses
[0];
4054 #define ANV_PIPELINE_STATISTICS_MASK 0x000007ff
4056 struct anv_query_pool
{
4058 VkQueryPipelineStatisticFlags pipeline_statistics
;
4059 /** Stride between slots, in bytes */
4061 /** Number of slots in this query pool */
4066 int anv_get_instance_entrypoint_index(const char *name
);
4067 int anv_get_device_entrypoint_index(const char *name
);
4068 int anv_get_physical_device_entrypoint_index(const char *name
);
4070 const char *anv_get_instance_entry_name(int index
);
4071 const char *anv_get_physical_device_entry_name(int index
);
4072 const char *anv_get_device_entry_name(int index
);
4075 anv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
4076 const struct anv_instance_extension_table
*instance
);
4078 anv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4079 const struct anv_instance_extension_table
*instance
);
4081 anv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
4082 const struct anv_instance_extension_table
*instance
,
4083 const struct anv_device_extension_table
*device
);
4085 void *anv_lookup_entrypoint(const struct gen_device_info
*devinfo
,
4088 void anv_dump_image_to_ppm(struct anv_device
*device
,
4089 struct anv_image
*image
, unsigned miplevel
,
4090 unsigned array_layer
, VkImageAspectFlagBits aspect
,
4091 const char *filename
);
4093 enum anv_dump_action
{
4094 ANV_DUMP_FRAMEBUFFERS_BIT
= 0x1,
4097 void anv_dump_start(struct anv_device
*device
, enum anv_dump_action actions
);
4098 void anv_dump_finish(void);
4100 void anv_dump_add_attachments(struct anv_cmd_buffer
*cmd_buffer
);
4102 static inline uint32_t
4103 anv_get_subpass_id(const struct anv_cmd_state
* const cmd_state
)
4105 /* This function must be called from within a subpass. */
4106 assert(cmd_state
->pass
&& cmd_state
->subpass
);
4108 const uint32_t subpass_id
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
4110 /* The id of this subpass shouldn't exceed the number of subpasses in this
4111 * render pass minus 1.
4113 assert(subpass_id
< cmd_state
->pass
->subpass_count
);
4117 struct gen_perf_config
*anv_get_perf(const struct gen_device_info
*devinfo
, int fd
);
4118 void anv_device_perf_init(struct anv_device
*device
);
4120 #define ANV_DEFINE_HANDLE_CASTS(__anv_type, __VkType) \
4122 static inline struct __anv_type * \
4123 __anv_type ## _from_handle(__VkType _handle) \
4125 return (struct __anv_type *) _handle; \
4128 static inline __VkType \
4129 __anv_type ## _to_handle(struct __anv_type *_obj) \
4131 return (__VkType) _obj; \
4134 #define ANV_DEFINE_NONDISP_HANDLE_CASTS(__anv_type, __VkType) \
4136 static inline struct __anv_type * \
4137 __anv_type ## _from_handle(__VkType _handle) \
4139 return (struct __anv_type *)(uintptr_t) _handle; \
4142 static inline __VkType \
4143 __anv_type ## _to_handle(struct __anv_type *_obj) \
4145 return (__VkType)(uintptr_t) _obj; \
4148 #define ANV_FROM_HANDLE(__anv_type, __name, __handle) \
4149 struct __anv_type *__name = __anv_type ## _from_handle(__handle)
4151 ANV_DEFINE_HANDLE_CASTS(anv_cmd_buffer
, VkCommandBuffer
)
4152 ANV_DEFINE_HANDLE_CASTS(anv_device
, VkDevice
)
4153 ANV_DEFINE_HANDLE_CASTS(anv_instance
, VkInstance
)
4154 ANV_DEFINE_HANDLE_CASTS(anv_physical_device
, VkPhysicalDevice
)
4155 ANV_DEFINE_HANDLE_CASTS(anv_queue
, VkQueue
)
4157 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool
, VkCommandPool
)
4158 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer
, VkBuffer
)
4159 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view
, VkBufferView
)
4160 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool
, VkDescriptorPool
)
4161 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set
, VkDescriptorSet
)
4162 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout
, VkDescriptorSetLayout
)
4163 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
4164 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory
, VkDeviceMemory
)
4165 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_fence
, VkFence
)
4166 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_event
, VkEvent
)
4167 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_framebuffer
, VkFramebuffer
)
4168 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image
, VkImage
)
4169 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view
, VkImageView
);
4170 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_cache
, VkPipelineCache
)
4171 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline
, VkPipeline
)
4172 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline_layout
, VkPipelineLayout
)
4173 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool
, VkQueryPool
)
4174 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_render_pass
, VkRenderPass
)
4175 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler
, VkSampler
)
4176 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_semaphore
, VkSemaphore
)
4177 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_shader_module
, VkShaderModule
)
4178 ANV_DEFINE_NONDISP_HANDLE_CASTS(vk_debug_report_callback
, VkDebugReportCallbackEXT
)
4179 ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_ycbcr_conversion
, VkSamplerYcbcrConversion
)
4181 /* Gen-specific function declarations */
4183 # include "anv_genX.h"
4185 # define genX(x) gen7_##x
4186 # include "anv_genX.h"
4188 # define genX(x) gen75_##x
4189 # include "anv_genX.h"
4191 # define genX(x) gen8_##x
4192 # include "anv_genX.h"
4194 # define genX(x) gen9_##x
4195 # include "anv_genX.h"
4197 # define genX(x) gen10_##x
4198 # include "anv_genX.h"
4200 # define genX(x) gen11_##x
4201 # include "anv_genX.h"
4203 # define genX(x) gen12_##x
4204 # include "anv_genX.h"
4208 #endif /* ANV_PRIVATE_H */